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25#include <core/object.h>
26#include <core/parent.h>
27#include <core/handle.h>
28#include <core/class.h>
29
30#include <engine/disp.h>
31
32#include <subdev/bios.h>
33#include <subdev/bios/dcb.h>
34#include <subdev/bios/disp.h>
35#include <subdev/bios/init.h>
36#include <subdev/bios/pll.h>
37#include <subdev/devinit.h>
38#include <subdev/fb.h>
39#include <subdev/timer.h>
40
41#include "nv50.h"
42
43
44
45
46
47static int
48nvd0_disp_dmac_object_attach(struct nouveau_object *parent,
49 struct nouveau_object *object, u32 name)
50{
51 struct nv50_disp_base *base = (void *)parent->parent;
52 struct nv50_disp_chan *chan = (void *)parent;
53 u32 addr = nv_gpuobj(object)->node->offset;
54 u32 data = (chan->chid << 27) | (addr << 9) | 0x00000001;
55 return nouveau_ramht_insert(base->ramht, chan->chid, name, data);
56}
57
58static void
59nvd0_disp_dmac_object_detach(struct nouveau_object *parent, int cookie)
60{
61 struct nv50_disp_base *base = (void *)parent->parent;
62 nouveau_ramht_remove(base->ramht, cookie);
63}
64
65static int
66nvd0_disp_dmac_init(struct nouveau_object *object)
67{
68 struct nv50_disp_priv *priv = (void *)object->engine;
69 struct nv50_disp_dmac *dmac = (void *)object;
70 int chid = dmac->base.chid;
71 int ret;
72
73 ret = nv50_disp_chan_init(&dmac->base);
74 if (ret)
75 return ret;
76
77
78 nv_mask(priv, 0x610090, 0x00000001 << chid, 0x00000001 << chid);
79 nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000001 << chid);
80
81
82 nv_wr32(priv, 0x610494 + (chid * 0x0010), dmac->push);
83 nv_wr32(priv, 0x610498 + (chid * 0x0010), 0x00010000);
84 nv_wr32(priv, 0x61049c + (chid * 0x0010), 0x00000001);
85 nv_mask(priv, 0x610490 + (chid * 0x0010), 0x00000010, 0x00000010);
86 nv_wr32(priv, 0x640000 + (chid * 0x1000), 0x00000000);
87 nv_wr32(priv, 0x610490 + (chid * 0x0010), 0x00000013);
88
89
90 if (!nv_wait(priv, 0x610490 + (chid * 0x10), 0x80000000, 0x00000000)) {
91 nv_error(dmac, "init: 0x%08x\n",
92 nv_rd32(priv, 0x610490 + (chid * 0x10)));
93 return -EBUSY;
94 }
95
96 return 0;
97}
98
99static int
100nvd0_disp_dmac_fini(struct nouveau_object *object, bool suspend)
101{
102 struct nv50_disp_priv *priv = (void *)object->engine;
103 struct nv50_disp_dmac *dmac = (void *)object;
104 int chid = dmac->base.chid;
105
106
107 nv_mask(priv, 0x610490 + (chid * 0x0010), 0x00001010, 0x00001000);
108 nv_mask(priv, 0x610490 + (chid * 0x0010), 0x00000003, 0x00000000);
109 if (!nv_wait(priv, 0x610490 + (chid * 0x10), 0x001e0000, 0x00000000)) {
110 nv_error(dmac, "fini: 0x%08x\n",
111 nv_rd32(priv, 0x610490 + (chid * 0x10)));
112 if (suspend)
113 return -EBUSY;
114 }
115
116
117 nv_mask(priv, 0x610090, 0x00000001 << chid, 0x00000000);
118 nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000000);
119
120 return nv50_disp_chan_fini(&dmac->base, suspend);
121}
122
123
124
125
126
127static int
128nvd0_disp_mast_ctor(struct nouveau_object *parent,
129 struct nouveau_object *engine,
130 struct nouveau_oclass *oclass, void *data, u32 size,
131 struct nouveau_object **pobject)
132{
133 struct nv50_display_mast_class *args = data;
134 struct nv50_disp_dmac *mast;
135 int ret;
136
137 if (size < sizeof(*args))
138 return -EINVAL;
139
140 ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf,
141 0, sizeof(*mast), (void **)&mast);
142 *pobject = nv_object(mast);
143 if (ret)
144 return ret;
145
146 nv_parent(mast)->object_attach = nvd0_disp_dmac_object_attach;
147 nv_parent(mast)->object_detach = nvd0_disp_dmac_object_detach;
148 return 0;
149}
150
151static int
152nvd0_disp_mast_init(struct nouveau_object *object)
153{
154 struct nv50_disp_priv *priv = (void *)object->engine;
155 struct nv50_disp_dmac *mast = (void *)object;
156 int ret;
157
158 ret = nv50_disp_chan_init(&mast->base);
159 if (ret)
160 return ret;
161
162
163 nv_mask(priv, 0x610090, 0x00000001, 0x00000001);
164 nv_mask(priv, 0x6100a0, 0x00000001, 0x00000001);
165
166
167 nv_wr32(priv, 0x610494, mast->push);
168 nv_wr32(priv, 0x610498, 0x00010000);
169 nv_wr32(priv, 0x61049c, 0x00000001);
170 nv_mask(priv, 0x610490, 0x00000010, 0x00000010);
171 nv_wr32(priv, 0x640000, 0x00000000);
172 nv_wr32(priv, 0x610490, 0x01000013);
173
174
175 if (!nv_wait(priv, 0x610490, 0x80000000, 0x00000000)) {
176 nv_error(mast, "init: 0x%08x\n", nv_rd32(priv, 0x610490));
177 return -EBUSY;
178 }
179
180 return 0;
181}
182
183static int
184nvd0_disp_mast_fini(struct nouveau_object *object, bool suspend)
185{
186 struct nv50_disp_priv *priv = (void *)object->engine;
187 struct nv50_disp_dmac *mast = (void *)object;
188
189
190 nv_mask(priv, 0x610490, 0x00000010, 0x00000000);
191 nv_mask(priv, 0x610490, 0x00000003, 0x00000000);
192 if (!nv_wait(priv, 0x610490, 0x001e0000, 0x00000000)) {
193 nv_error(mast, "fini: 0x%08x\n", nv_rd32(priv, 0x610490));
194 if (suspend)
195 return -EBUSY;
196 }
197
198
199 nv_mask(priv, 0x610090, 0x00000001, 0x00000000);
200 nv_mask(priv, 0x6100a0, 0x00000001, 0x00000000);
201
202 return nv50_disp_chan_fini(&mast->base, suspend);
203}
204
205struct nouveau_ofuncs
206nvd0_disp_mast_ofuncs = {
207 .ctor = nvd0_disp_mast_ctor,
208 .dtor = nv50_disp_dmac_dtor,
209 .init = nvd0_disp_mast_init,
210 .fini = nvd0_disp_mast_fini,
211 .rd32 = nv50_disp_chan_rd32,
212 .wr32 = nv50_disp_chan_wr32,
213};
214
215
216
217
218
219static int
220nvd0_disp_sync_ctor(struct nouveau_object *parent,
221 struct nouveau_object *engine,
222 struct nouveau_oclass *oclass, void *data, u32 size,
223 struct nouveau_object **pobject)
224{
225 struct nv50_display_sync_class *args = data;
226 struct nv50_disp_priv *priv = (void *)engine;
227 struct nv50_disp_dmac *dmac;
228 int ret;
229
230 if (size < sizeof(*args) || args->head >= priv->head.nr)
231 return -EINVAL;
232
233 ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf,
234 1 + args->head, sizeof(*dmac),
235 (void **)&dmac);
236 *pobject = nv_object(dmac);
237 if (ret)
238 return ret;
239
240 nv_parent(dmac)->object_attach = nvd0_disp_dmac_object_attach;
241 nv_parent(dmac)->object_detach = nvd0_disp_dmac_object_detach;
242 return 0;
243}
244
245struct nouveau_ofuncs
246nvd0_disp_sync_ofuncs = {
247 .ctor = nvd0_disp_sync_ctor,
248 .dtor = nv50_disp_dmac_dtor,
249 .init = nvd0_disp_dmac_init,
250 .fini = nvd0_disp_dmac_fini,
251 .rd32 = nv50_disp_chan_rd32,
252 .wr32 = nv50_disp_chan_wr32,
253};
254
255
256
257
258
259static int
260nvd0_disp_ovly_ctor(struct nouveau_object *parent,
261 struct nouveau_object *engine,
262 struct nouveau_oclass *oclass, void *data, u32 size,
263 struct nouveau_object **pobject)
264{
265 struct nv50_display_ovly_class *args = data;
266 struct nv50_disp_priv *priv = (void *)engine;
267 struct nv50_disp_dmac *dmac;
268 int ret;
269
270 if (size < sizeof(*args) || args->head >= priv->head.nr)
271 return -EINVAL;
272
273 ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf,
274 5 + args->head, sizeof(*dmac),
275 (void **)&dmac);
276 *pobject = nv_object(dmac);
277 if (ret)
278 return ret;
279
280 nv_parent(dmac)->object_attach = nvd0_disp_dmac_object_attach;
281 nv_parent(dmac)->object_detach = nvd0_disp_dmac_object_detach;
282 return 0;
283}
284
285struct nouveau_ofuncs
286nvd0_disp_ovly_ofuncs = {
287 .ctor = nvd0_disp_ovly_ctor,
288 .dtor = nv50_disp_dmac_dtor,
289 .init = nvd0_disp_dmac_init,
290 .fini = nvd0_disp_dmac_fini,
291 .rd32 = nv50_disp_chan_rd32,
292 .wr32 = nv50_disp_chan_wr32,
293};
294
295
296
297
298
299static int
300nvd0_disp_pioc_create_(struct nouveau_object *parent,
301 struct nouveau_object *engine,
302 struct nouveau_oclass *oclass, int chid,
303 int length, void **pobject)
304{
305 return nv50_disp_chan_create_(parent, engine, oclass, chid,
306 length, pobject);
307}
308
309static void
310nvd0_disp_pioc_dtor(struct nouveau_object *object)
311{
312 struct nv50_disp_pioc *pioc = (void *)object;
313 nv50_disp_chan_destroy(&pioc->base);
314}
315
316static int
317nvd0_disp_pioc_init(struct nouveau_object *object)
318{
319 struct nv50_disp_priv *priv = (void *)object->engine;
320 struct nv50_disp_pioc *pioc = (void *)object;
321 int chid = pioc->base.chid;
322 int ret;
323
324 ret = nv50_disp_chan_init(&pioc->base);
325 if (ret)
326 return ret;
327
328
329 nv_mask(priv, 0x610090, 0x00000001 << chid, 0x00000001 << chid);
330 nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000001 << chid);
331
332
333 nv_wr32(priv, 0x610490 + (chid * 0x10), 0x00000001);
334 if (!nv_wait(priv, 0x610490 + (chid * 0x10), 0x00030000, 0x00010000)) {
335 nv_error(pioc, "init: 0x%08x\n",
336 nv_rd32(priv, 0x610490 + (chid * 0x10)));
337 return -EBUSY;
338 }
339
340 return 0;
341}
342
343static int
344nvd0_disp_pioc_fini(struct nouveau_object *object, bool suspend)
345{
346 struct nv50_disp_priv *priv = (void *)object->engine;
347 struct nv50_disp_pioc *pioc = (void *)object;
348 int chid = pioc->base.chid;
349
350 nv_mask(priv, 0x610490 + (chid * 0x10), 0x00000001, 0x00000000);
351 if (!nv_wait(priv, 0x610490 + (chid * 0x10), 0x00030000, 0x00000000)) {
352 nv_error(pioc, "timeout: 0x%08x\n",
353 nv_rd32(priv, 0x610490 + (chid * 0x10)));
354 if (suspend)
355 return -EBUSY;
356 }
357
358
359 nv_mask(priv, 0x610090, 0x00000001 << chid, 0x00000000);
360 nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000000);
361
362 return nv50_disp_chan_fini(&pioc->base, suspend);
363}
364
365
366
367
368
369static int
370nvd0_disp_oimm_ctor(struct nouveau_object *parent,
371 struct nouveau_object *engine,
372 struct nouveau_oclass *oclass, void *data, u32 size,
373 struct nouveau_object **pobject)
374{
375 struct nv50_display_oimm_class *args = data;
376 struct nv50_disp_priv *priv = (void *)engine;
377 struct nv50_disp_pioc *pioc;
378 int ret;
379
380 if (size < sizeof(*args) || args->head >= priv->head.nr)
381 return -EINVAL;
382
383 ret = nvd0_disp_pioc_create_(parent, engine, oclass, 9 + args->head,
384 sizeof(*pioc), (void **)&pioc);
385 *pobject = nv_object(pioc);
386 if (ret)
387 return ret;
388
389 return 0;
390}
391
392struct nouveau_ofuncs
393nvd0_disp_oimm_ofuncs = {
394 .ctor = nvd0_disp_oimm_ctor,
395 .dtor = nvd0_disp_pioc_dtor,
396 .init = nvd0_disp_pioc_init,
397 .fini = nvd0_disp_pioc_fini,
398 .rd32 = nv50_disp_chan_rd32,
399 .wr32 = nv50_disp_chan_wr32,
400};
401
402
403
404
405
406static int
407nvd0_disp_curs_ctor(struct nouveau_object *parent,
408 struct nouveau_object *engine,
409 struct nouveau_oclass *oclass, void *data, u32 size,
410 struct nouveau_object **pobject)
411{
412 struct nv50_display_curs_class *args = data;
413 struct nv50_disp_priv *priv = (void *)engine;
414 struct nv50_disp_pioc *pioc;
415 int ret;
416
417 if (size < sizeof(*args) || args->head >= priv->head.nr)
418 return -EINVAL;
419
420 ret = nvd0_disp_pioc_create_(parent, engine, oclass, 13 + args->head,
421 sizeof(*pioc), (void **)&pioc);
422 *pobject = nv_object(pioc);
423 if (ret)
424 return ret;
425
426 return 0;
427}
428
429struct nouveau_ofuncs
430nvd0_disp_curs_ofuncs = {
431 .ctor = nvd0_disp_curs_ctor,
432 .dtor = nvd0_disp_pioc_dtor,
433 .init = nvd0_disp_pioc_init,
434 .fini = nvd0_disp_pioc_fini,
435 .rd32 = nv50_disp_chan_rd32,
436 .wr32 = nv50_disp_chan_wr32,
437};
438
439
440
441
442
443static void
444nvd0_disp_base_vblank_enable(struct nouveau_event *event, int head)
445{
446 nv_mask(event->priv, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000001);
447}
448
449static void
450nvd0_disp_base_vblank_disable(struct nouveau_event *event, int head)
451{
452 nv_mask(event->priv, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000000);
453}
454
455static int
456nvd0_disp_base_ctor(struct nouveau_object *parent,
457 struct nouveau_object *engine,
458 struct nouveau_oclass *oclass, void *data, u32 size,
459 struct nouveau_object **pobject)
460{
461 struct nv50_disp_priv *priv = (void *)engine;
462 struct nv50_disp_base *base;
463 int ret;
464
465 ret = nouveau_parent_create(parent, engine, oclass, 0,
466 priv->sclass, 0, &base);
467 *pobject = nv_object(base);
468 if (ret)
469 return ret;
470
471 priv->base.vblank->priv = priv;
472 priv->base.vblank->enable = nvd0_disp_base_vblank_enable;
473 priv->base.vblank->disable = nvd0_disp_base_vblank_disable;
474
475 return nouveau_ramht_new(nv_object(base), nv_object(base), 0x1000, 0,
476 &base->ramht);
477}
478
479static void
480nvd0_disp_base_dtor(struct nouveau_object *object)
481{
482 struct nv50_disp_base *base = (void *)object;
483 nouveau_ramht_ref(NULL, &base->ramht);
484 nouveau_parent_destroy(&base->base);
485}
486
487static int
488nvd0_disp_base_init(struct nouveau_object *object)
489{
490 struct nv50_disp_priv *priv = (void *)object->engine;
491 struct nv50_disp_base *base = (void *)object;
492 int ret, i;
493 u32 tmp;
494
495 ret = nouveau_parent_init(&base->base);
496 if (ret)
497 return ret;
498
499
500
501
502
503
504
505 for (i = 0; i < priv->head.nr; i++) {
506 tmp = nv_rd32(priv, 0x616104 + (i * 0x800));
507 nv_wr32(priv, 0x6101b4 + (i * 0x800), tmp);
508 tmp = nv_rd32(priv, 0x616108 + (i * 0x800));
509 nv_wr32(priv, 0x6101b8 + (i * 0x800), tmp);
510 tmp = nv_rd32(priv, 0x61610c + (i * 0x800));
511 nv_wr32(priv, 0x6101bc + (i * 0x800), tmp);
512 }
513
514
515 for (i = 0; i < priv->dac.nr; i++) {
516 tmp = nv_rd32(priv, 0x61a000 + (i * 0x800));
517 nv_wr32(priv, 0x6101c0 + (i * 0x800), tmp);
518 }
519
520
521 for (i = 0; i < priv->sor.nr; i++) {
522 tmp = nv_rd32(priv, 0x61c000 + (i * 0x800));
523 nv_wr32(priv, 0x6301c4 + (i * 0x800), tmp);
524 }
525
526
527 if (nv_rd32(priv, 0x6100ac) & 0x00000100) {
528 nv_wr32(priv, 0x6100ac, 0x00000100);
529 nv_mask(priv, 0x6194e8, 0x00000001, 0x00000000);
530 if (!nv_wait(priv, 0x6194e8, 0x00000002, 0x00000000)) {
531 nv_error(priv, "timeout acquiring display\n");
532 return -EBUSY;
533 }
534 }
535
536
537 nv_wr32(priv, 0x610010, (nv_gpuobj(object->parent)->addr >> 8) | 9);
538
539
540 nv_wr32(priv, 0x610090, 0x00000000);
541 nv_wr32(priv, 0x6100a0, 0x00000000);
542 nv_wr32(priv, 0x6100b0, 0x00000307);
543
544 return 0;
545}
546
547static int
548nvd0_disp_base_fini(struct nouveau_object *object, bool suspend)
549{
550 struct nv50_disp_priv *priv = (void *)object->engine;
551 struct nv50_disp_base *base = (void *)object;
552
553
554 nv_wr32(priv, 0x6100b0, 0x00000000);
555
556 return nouveau_parent_fini(&base->base, suspend);
557}
558
559struct nouveau_ofuncs
560nvd0_disp_base_ofuncs = {
561 .ctor = nvd0_disp_base_ctor,
562 .dtor = nvd0_disp_base_dtor,
563 .init = nvd0_disp_base_init,
564 .fini = nvd0_disp_base_fini,
565};
566
567static struct nouveau_oclass
568nvd0_disp_base_oclass[] = {
569 { NVD0_DISP_CLASS, &nvd0_disp_base_ofuncs, nva3_disp_base_omthds },
570 {}
571};
572
573static struct nouveau_oclass
574nvd0_disp_sclass[] = {
575 { NVD0_DISP_MAST_CLASS, &nvd0_disp_mast_ofuncs },
576 { NVD0_DISP_SYNC_CLASS, &nvd0_disp_sync_ofuncs },
577 { NVD0_DISP_OVLY_CLASS, &nvd0_disp_ovly_ofuncs },
578 { NVD0_DISP_OIMM_CLASS, &nvd0_disp_oimm_ofuncs },
579 { NVD0_DISP_CURS_CLASS, &nvd0_disp_curs_ofuncs },
580 {}
581};
582
583
584
585
586
587static u16
588exec_lookup(struct nv50_disp_priv *priv, int head, int outp, u32 ctrl,
589 struct dcb_output *dcb, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
590 struct nvbios_outp *info)
591{
592 struct nouveau_bios *bios = nouveau_bios(priv);
593 u16 mask, type, data;
594
595 if (outp < 4) {
596 type = DCB_OUTPUT_ANALOG;
597 mask = 0;
598 } else {
599 outp -= 4;
600 switch (ctrl & 0x00000f00) {
601 case 0x00000000: type = DCB_OUTPUT_LVDS; mask = 1; break;
602 case 0x00000100: type = DCB_OUTPUT_TMDS; mask = 1; break;
603 case 0x00000200: type = DCB_OUTPUT_TMDS; mask = 2; break;
604 case 0x00000500: type = DCB_OUTPUT_TMDS; mask = 3; break;
605 case 0x00000800: type = DCB_OUTPUT_DP; mask = 1; break;
606 case 0x00000900: type = DCB_OUTPUT_DP; mask = 2; break;
607 default:
608 nv_error(priv, "unknown SOR mc 0x%08x\n", ctrl);
609 return 0x0000;
610 }
611 dcb->sorconf.link = mask;
612 }
613
614 mask = 0x00c0 & (mask << 6);
615 mask |= 0x0001 << outp;
616 mask |= 0x0100 << head;
617
618 data = dcb_outp_match(bios, type, mask, ver, hdr, dcb);
619 if (!data)
620 return 0x0000;
621
622 return nvbios_outp_match(bios, type, mask, ver, hdr, cnt, len, info);
623}
624
625static bool
626exec_script(struct nv50_disp_priv *priv, int head, int id)
627{
628 struct nouveau_bios *bios = nouveau_bios(priv);
629 struct nvbios_outp info;
630 struct dcb_output dcb;
631 u8 ver, hdr, cnt, len;
632 u32 ctrl = 0x00000000;
633 u16 data;
634 int outp;
635
636 for (outp = 0; !(ctrl & (1 << head)) && outp < 8; outp++) {
637 ctrl = nv_rd32(priv, 0x640180 + (outp * 0x20));
638 if (ctrl & (1 << head))
639 break;
640 }
641
642 if (outp == 8)
643 return false;
644
645 data = exec_lookup(priv, head, outp, ctrl, &dcb, &ver, &hdr, &cnt, &len, &info);
646 if (data) {
647 struct nvbios_init init = {
648 .subdev = nv_subdev(priv),
649 .bios = bios,
650 .offset = info.script[id],
651 .outp = &dcb,
652 .crtc = head,
653 .execute = 1,
654 };
655
656 return nvbios_exec(&init) == 0;
657 }
658
659 return false;
660}
661
662static u32
663exec_clkcmp(struct nv50_disp_priv *priv, int head, int id,
664 u32 pclk, struct dcb_output *dcb)
665{
666 struct nouveau_bios *bios = nouveau_bios(priv);
667 struct nvbios_outp info1;
668 struct nvbios_ocfg info2;
669 u8 ver, hdr, cnt, len;
670 u32 ctrl = 0x00000000;
671 u32 data, conf = ~0;
672 int outp;
673
674 for (outp = 0; !(ctrl & (1 << head)) && outp < 8; outp++) {
675 ctrl = nv_rd32(priv, 0x660180 + (outp * 0x20));
676 if (ctrl & (1 << head))
677 break;
678 }
679
680 if (outp == 8)
681 return false;
682
683 data = exec_lookup(priv, head, outp, ctrl, dcb, &ver, &hdr, &cnt, &len, &info1);
684 if (data == 0x0000)
685 return conf;
686
687 switch (dcb->type) {
688 case DCB_OUTPUT_TMDS:
689 conf = (ctrl & 0x00000f00) >> 8;
690 if (pclk >= 165000)
691 conf |= 0x0100;
692 break;
693 case DCB_OUTPUT_LVDS:
694 conf = priv->sor.lvdsconf;
695 break;
696 case DCB_OUTPUT_DP:
697 conf = (ctrl & 0x00000f00) >> 8;
698 break;
699 case DCB_OUTPUT_ANALOG:
700 default:
701 conf = 0x00ff;
702 break;
703 }
704
705 data = nvbios_ocfg_match(bios, data, conf, &ver, &hdr, &cnt, &len, &info2);
706 if (data && id < 0xff) {
707 data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk);
708 if (data) {
709 struct nvbios_init init = {
710 .subdev = nv_subdev(priv),
711 .bios = bios,
712 .offset = data,
713 .outp = dcb,
714 .crtc = head,
715 .execute = 1,
716 };
717
718 nvbios_exec(&init);
719 }
720 }
721
722 return conf;
723}
724
725static void
726nvd0_disp_intr_unk1_0(struct nv50_disp_priv *priv, int head)
727{
728 exec_script(priv, head, 1);
729}
730
731static void
732nvd0_disp_intr_unk2_0(struct nv50_disp_priv *priv, int head)
733{
734 exec_script(priv, head, 2);
735}
736
737static void
738nvd0_disp_intr_unk2_1(struct nv50_disp_priv *priv, int head)
739{
740 struct nouveau_devinit *devinit = nouveau_devinit(priv);
741 u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000;
742 if (pclk)
743 devinit->pll_set(devinit, PLL_VPLL0 + head, pclk);
744 nv_wr32(priv, 0x612200 + (head * 0x800), 0x00000000);
745}
746
747static void
748nvd0_disp_intr_unk2_2_tu(struct nv50_disp_priv *priv, int head,
749 struct dcb_output *outp)
750{
751 const int or = ffs(outp->or) - 1;
752 const u32 ctrl = nv_rd32(priv, 0x660200 + (or * 0x020));
753 const u32 conf = nv_rd32(priv, 0x660404 + (head * 0x300));
754 const u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000;
755 const u32 link = ((ctrl & 0xf00) == 0x800) ? 0 : 1;
756 const u32 hoff = (head * 0x800);
757 const u32 soff = ( or * 0x800);
758 const u32 loff = (link * 0x080) + soff;
759 const u32 symbol = 100000;
760 const u32 TU = 64;
761 u32 dpctrl = nv_rd32(priv, 0x61c10c + loff) & 0x000f0000;
762 u32 clksor = nv_rd32(priv, 0x612300 + soff);
763 u32 datarate, link_nr, link_bw, bits;
764 u64 ratio, value;
765
766 if ((conf & 0x3c0) == 0x180) bits = 30;
767 else if ((conf & 0x3c0) == 0x140) bits = 24;
768 else bits = 18;
769 datarate = (pclk * bits) / 8;
770
771 if (dpctrl > 0x00030000) link_nr = 4;
772 else if (dpctrl > 0x00010000) link_nr = 2;
773 else link_nr = 1;
774
775 link_bw = (clksor & 0x007c0000) >> 18;
776 link_bw *= 27000;
777
778 ratio = datarate;
779 ratio *= symbol;
780 do_div(ratio, link_nr * link_bw);
781
782 value = (symbol - ratio) * TU;
783 value *= ratio;
784 do_div(value, symbol);
785 do_div(value, symbol);
786
787 value += 5;
788 value |= 0x08000000;
789
790 nv_wr32(priv, 0x616610 + hoff, value);
791}
792
793static void
794nvd0_disp_intr_unk2_2(struct nv50_disp_priv *priv, int head)
795{
796 struct dcb_output outp;
797 u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000;
798 u32 conf = exec_clkcmp(priv, head, 0xff, pclk, &outp);
799 if (conf != ~0) {
800 u32 addr, data;
801
802 if (outp.type == DCB_OUTPUT_DP) {
803 u32 sync = nv_rd32(priv, 0x660404 + (head * 0x300));
804 switch ((sync & 0x000003c0) >> 6) {
805 case 6: pclk = pclk * 30 / 8; break;
806 case 5: pclk = pclk * 24 / 8; break;
807 case 2:
808 default:
809 pclk = pclk * 18 / 8;
810 break;
811 }
812
813 nouveau_dp_train(&priv->base, priv->sor.dp,
814 &outp, head, pclk);
815 }
816
817 exec_clkcmp(priv, head, 0, pclk, &outp);
818
819 if (outp.type == DCB_OUTPUT_ANALOG) {
820 addr = 0x612280 + (ffs(outp.or) - 1) * 0x800;
821 data = 0x00000000;
822 } else {
823 if (outp.type == DCB_OUTPUT_DP)
824 nvd0_disp_intr_unk2_2_tu(priv, head, &outp);
825 addr = 0x612300 + (ffs(outp.or) - 1) * 0x800;
826 data = (conf & 0x0100) ? 0x00000101 : 0x00000000;
827 }
828
829 nv_mask(priv, addr, 0x00000707, data);
830 }
831}
832
833static void
834nvd0_disp_intr_unk4_0(struct nv50_disp_priv *priv, int head)
835{
836 struct dcb_output outp;
837 u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000;
838 exec_clkcmp(priv, head, 1, pclk, &outp);
839}
840
841void
842nvd0_disp_intr_supervisor(struct work_struct *work)
843{
844 struct nv50_disp_priv *priv =
845 container_of(work, struct nv50_disp_priv, supervisor);
846 u32 mask[4];
847 int head;
848
849 nv_debug(priv, "supervisor %08x\n", priv->super);
850 for (head = 0; head < priv->head.nr; head++) {
851 mask[head] = nv_rd32(priv, 0x6101d4 + (head * 0x800));
852 nv_debug(priv, "head %d: 0x%08x\n", head, mask[head]);
853 }
854
855 if (priv->super & 0x00000001) {
856 for (head = 0; head < priv->head.nr; head++) {
857 if (!(mask[head] & 0x00001000))
858 continue;
859 nvd0_disp_intr_unk1_0(priv, head);
860 }
861 } else
862 if (priv->super & 0x00000002) {
863 for (head = 0; head < priv->head.nr; head++) {
864 if (!(mask[head] & 0x00001000))
865 continue;
866 nvd0_disp_intr_unk2_0(priv, head);
867 }
868 for (head = 0; head < priv->head.nr; head++) {
869 if (!(mask[head] & 0x00010000))
870 continue;
871 nvd0_disp_intr_unk2_1(priv, head);
872 }
873 for (head = 0; head < priv->head.nr; head++) {
874 if (!(mask[head] & 0x00001000))
875 continue;
876 nvd0_disp_intr_unk2_2(priv, head);
877 }
878 } else
879 if (priv->super & 0x00000004) {
880 for (head = 0; head < priv->head.nr; head++) {
881 if (!(mask[head] & 0x00001000))
882 continue;
883 nvd0_disp_intr_unk4_0(priv, head);
884 }
885 }
886
887 for (head = 0; head < priv->head.nr; head++)
888 nv_wr32(priv, 0x6101d4 + (head * 0x800), 0x00000000);
889 nv_wr32(priv, 0x6101d0, 0x80000000);
890}
891
892void
893nvd0_disp_intr(struct nouveau_subdev *subdev)
894{
895 struct nv50_disp_priv *priv = (void *)subdev;
896 u32 intr = nv_rd32(priv, 0x610088);
897 int i;
898
899 if (intr & 0x00000001) {
900 u32 stat = nv_rd32(priv, 0x61008c);
901 nv_wr32(priv, 0x61008c, stat);
902 intr &= ~0x00000001;
903 }
904
905 if (intr & 0x00000002) {
906 u32 stat = nv_rd32(priv, 0x61009c);
907 int chid = ffs(stat) - 1;
908 if (chid >= 0) {
909 u32 mthd = nv_rd32(priv, 0x6101f0 + (chid * 12));
910 u32 data = nv_rd32(priv, 0x6101f4 + (chid * 12));
911 u32 unkn = nv_rd32(priv, 0x6101f8 + (chid * 12));
912
913 nv_error(priv, "chid %d mthd 0x%04x data 0x%08x "
914 "0x%08x 0x%08x\n",
915 chid, (mthd & 0x0000ffc), data, mthd, unkn);
916 nv_wr32(priv, 0x61009c, (1 << chid));
917 nv_wr32(priv, 0x6101f0 + (chid * 12), 0x90000000);
918 }
919
920 intr &= ~0x00000002;
921 }
922
923 if (intr & 0x00100000) {
924 u32 stat = nv_rd32(priv, 0x6100ac);
925 if (stat & 0x00000007) {
926 priv->super = (stat & 0x00000007);
927 schedule_work(&priv->supervisor);
928 nv_wr32(priv, 0x6100ac, priv->super);
929 stat &= ~0x00000007;
930 }
931
932 if (stat) {
933 nv_info(priv, "unknown intr24 0x%08x\n", stat);
934 nv_wr32(priv, 0x6100ac, stat);
935 }
936
937 intr &= ~0x00100000;
938 }
939
940 for (i = 0; i < priv->head.nr; i++) {
941 u32 mask = 0x01000000 << i;
942 if (mask & intr) {
943 u32 stat = nv_rd32(priv, 0x6100bc + (i * 0x800));
944 if (stat & 0x00000001)
945 nouveau_event_trigger(priv->base.vblank, i);
946 nv_mask(priv, 0x6100bc + (i * 0x800), 0, 0);
947 nv_rd32(priv, 0x6100c0 + (i * 0x800));
948 }
949 }
950}
951
952static int
953nvd0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
954 struct nouveau_oclass *oclass, void *data, u32 size,
955 struct nouveau_object **pobject)
956{
957 struct nv50_disp_priv *priv;
958 int heads = nv_rd32(parent, 0x022448);
959 int ret;
960
961 if (nv_rd32(parent, 0x022500) & 0x00000001)
962 return -ENODEV;
963
964 ret = nouveau_disp_create(parent, engine, oclass, heads,
965 "PDISP", "display", &priv);
966 *pobject = nv_object(priv);
967 if (ret)
968 return ret;
969
970 nv_engine(priv)->sclass = nvd0_disp_base_oclass;
971 nv_engine(priv)->cclass = &nv50_disp_cclass;
972 nv_subdev(priv)->intr = nvd0_disp_intr;
973 INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
974 priv->sclass = nvd0_disp_sclass;
975 priv->head.nr = heads;
976 priv->dac.nr = 3;
977 priv->sor.nr = 4;
978 priv->dac.power = nv50_dac_power;
979 priv->dac.sense = nv50_dac_sense;
980 priv->sor.power = nv50_sor_power;
981 priv->sor.hda_eld = nvd0_hda_eld;
982 priv->sor.hdmi = nvd0_hdmi_ctrl;
983 priv->sor.dp = &nvd0_sor_dp_func;
984 return 0;
985}
986
987struct nouveau_oclass
988nvd0_disp_oclass = {
989 .handle = NV_ENGINE(DISP, 0x90),
990 .ofuncs = &(struct nouveau_ofuncs) {
991 .ctor = nvd0_disp_ctor,
992 .dtor = _nouveau_disp_dtor,
993 .init = _nouveau_disp_init,
994 .fini = _nouveau_disp_fini,
995 },
996};
997
