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25#include <core/os.h>
26#include <core/client.h>
27#include <core/engctx.h>
28#include <core/ramht.h>
29#include <core/event.h>
30#include <core/class.h>
31
32#include <subdev/timer.h>
33#include <subdev/bar.h>
34
35#include <engine/dmaobj.h>
36#include <engine/fifo.h>
37
38#include "nv50.h"
39
40
41
42
43
44static int
45nv84_fifo_context_attach(struct nouveau_object *parent,
46 struct nouveau_object *object)
47{
48 struct nouveau_bar *bar = nouveau_bar(parent);
49 struct nv50_fifo_base *base = (void *)parent->parent;
50 struct nouveau_gpuobj *ectx = (void *)object;
51 u64 limit = ectx->addr + ectx->size - 1;
52 u64 start = ectx->addr;
53 u32 addr;
54
55 switch (nv_engidx(object->engine)) {
56 case NVDEV_ENGINE_SW : return 0;
57 case NVDEV_ENGINE_GR : addr = 0x0020; break;
58 case NVDEV_ENGINE_VP : addr = 0x0040; break;
59 case NVDEV_ENGINE_PPP :
60 case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
61 case NVDEV_ENGINE_BSP : addr = 0x0080; break;
62 case NVDEV_ENGINE_CRYPT: addr = 0x00a0; break;
63 case NVDEV_ENGINE_COPY0: addr = 0x00c0; break;
64 default:
65 return -EINVAL;
66 }
67
68 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
69 nv_wo32(base->eng, addr + 0x00, 0x00190000);
70 nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit));
71 nv_wo32(base->eng, addr + 0x08, lower_32_bits(start));
72 nv_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 |
73 upper_32_bits(start));
74 nv_wo32(base->eng, addr + 0x10, 0x00000000);
75 nv_wo32(base->eng, addr + 0x14, 0x00000000);
76 bar->flush(bar);
77 return 0;
78}
79
80static int
81nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend,
82 struct nouveau_object *object)
83{
84 struct nouveau_bar *bar = nouveau_bar(parent);
85 struct nv50_fifo_priv *priv = (void *)parent->engine;
86 struct nv50_fifo_base *base = (void *)parent->parent;
87 struct nv50_fifo_chan *chan = (void *)parent;
88 u32 addr, save, engn;
89 bool done;
90
91 switch (nv_engidx(object->engine)) {
92 case NVDEV_ENGINE_SW : return 0;
93 case NVDEV_ENGINE_GR : engn = 0; addr = 0x0020; break;
94 case NVDEV_ENGINE_VP : engn = 3; addr = 0x0040; break;
95 case NVDEV_ENGINE_PPP :
96 case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break;
97 case NVDEV_ENGINE_BSP : engn = 5; addr = 0x0080; break;
98 case NVDEV_ENGINE_CRYPT: engn = 4; addr = 0x00a0; break;
99 case NVDEV_ENGINE_COPY0: engn = 2; addr = 0x00c0; break;
100 default:
101 return -EINVAL;
102 }
103
104 save = nv_mask(priv, 0x002520, 0x0000003f, 1 << engn);
105 nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12);
106 done = nv_wait_ne(priv, 0x0032fc, 0xffffffff, 0xffffffff);
107 nv_wr32(priv, 0x002520, save);
108 if (!done) {
109 nv_error(priv, "channel %d [%s] unload timeout\n",
110 chan->base.chid, nouveau_client_name(chan));
111 if (suspend)
112 return -EBUSY;
113 }
114
115 nv_wo32(base->eng, addr + 0x00, 0x00000000);
116 nv_wo32(base->eng, addr + 0x04, 0x00000000);
117 nv_wo32(base->eng, addr + 0x08, 0x00000000);
118 nv_wo32(base->eng, addr + 0x0c, 0x00000000);
119 nv_wo32(base->eng, addr + 0x10, 0x00000000);
120 nv_wo32(base->eng, addr + 0x14, 0x00000000);
121 bar->flush(bar);
122 return 0;
123}
124
125static int
126nv84_fifo_object_attach(struct nouveau_object *parent,
127 struct nouveau_object *object, u32 handle)
128{
129 struct nv50_fifo_chan *chan = (void *)parent;
130 u32 context;
131
132 if (nv_iclass(object, NV_GPUOBJ_CLASS))
133 context = nv_gpuobj(object)->node->offset >> 4;
134 else
135 context = 0x00000004;
136
137 switch (nv_engidx(object->engine)) {
138 case NVDEV_ENGINE_DMAOBJ:
139 case NVDEV_ENGINE_SW : context |= 0x00000000; break;
140 case NVDEV_ENGINE_GR : context |= 0x00100000; break;
141 case NVDEV_ENGINE_MPEG :
142 case NVDEV_ENGINE_PPP : context |= 0x00200000; break;
143 case NVDEV_ENGINE_ME :
144 case NVDEV_ENGINE_COPY0 : context |= 0x00300000; break;
145 case NVDEV_ENGINE_VP : context |= 0x00400000; break;
146 case NVDEV_ENGINE_CRYPT :
147 case NVDEV_ENGINE_UNK1C1: context |= 0x00500000; break;
148 case NVDEV_ENGINE_BSP : context |= 0x00600000; break;
149 default:
150 return -EINVAL;
151 }
152
153 return nouveau_ramht_insert(chan->ramht, 0, handle, context);
154}
155
156static int
157nv84_fifo_chan_ctor_dma(struct nouveau_object *parent,
158 struct nouveau_object *engine,
159 struct nouveau_oclass *oclass, void *data, u32 size,
160 struct nouveau_object **pobject)
161{
162 struct nouveau_bar *bar = nouveau_bar(parent);
163 struct nv50_fifo_base *base = (void *)parent;
164 struct nv50_fifo_chan *chan;
165 struct nv03_channel_dma_class *args = data;
166 int ret;
167
168 if (size < sizeof(*args))
169 return -EINVAL;
170
171 ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
172 0x2000, args->pushbuf,
173 (1ULL << NVDEV_ENGINE_DMAOBJ) |
174 (1ULL << NVDEV_ENGINE_SW) |
175 (1ULL << NVDEV_ENGINE_GR) |
176 (1ULL << NVDEV_ENGINE_MPEG) |
177 (1ULL << NVDEV_ENGINE_ME) |
178 (1ULL << NVDEV_ENGINE_VP) |
179 (1ULL << NVDEV_ENGINE_CRYPT) |
180 (1ULL << NVDEV_ENGINE_BSP) |
181 (1ULL << NVDEV_ENGINE_PPP) |
182 (1ULL << NVDEV_ENGINE_COPY0) |
183 (1ULL << NVDEV_ENGINE_UNK1C1), &chan);
184 *pobject = nv_object(chan);
185 if (ret)
186 return ret;
187
188 ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
189 &chan->ramht);
190 if (ret)
191 return ret;
192
193 nv_parent(chan)->context_attach = nv84_fifo_context_attach;
194 nv_parent(chan)->context_detach = nv84_fifo_context_detach;
195 nv_parent(chan)->object_attach = nv84_fifo_object_attach;
196 nv_parent(chan)->object_detach = nv50_fifo_object_detach;
197
198 nv_wo32(base->ramfc, 0x08, lower_32_bits(args->offset));
199 nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->offset));
200 nv_wo32(base->ramfc, 0x10, lower_32_bits(args->offset));
201 nv_wo32(base->ramfc, 0x14, upper_32_bits(args->offset));
202 nv_wo32(base->ramfc, 0x3c, 0x003f6078);
203 nv_wo32(base->ramfc, 0x44, 0x01003fff);
204 nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
205 nv_wo32(base->ramfc, 0x4c, 0xffffffff);
206 nv_wo32(base->ramfc, 0x60, 0x7fffffff);
207 nv_wo32(base->ramfc, 0x78, 0x00000000);
208 nv_wo32(base->ramfc, 0x7c, 0x30000001);
209 nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
210 (4 << 24) |
211 (chan->ramht->base.node->offset >> 4));
212 nv_wo32(base->ramfc, 0x88, base->cache->addr >> 10);
213 nv_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12);
214 bar->flush(bar);
215 return 0;
216}
217
218static int
219nv84_fifo_chan_ctor_ind(struct nouveau_object *parent,
220 struct nouveau_object *engine,
221 struct nouveau_oclass *oclass, void *data, u32 size,
222 struct nouveau_object **pobject)
223{
224 struct nouveau_bar *bar = nouveau_bar(parent);
225 struct nv50_fifo_base *base = (void *)parent;
226 struct nv50_fifo_chan *chan;
227 struct nv50_channel_ind_class *args = data;
228 u64 ioffset, ilength;
229 int ret;
230
231 if (size < sizeof(*args))
232 return -EINVAL;
233
234 ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
235 0x2000, args->pushbuf,
236 (1ULL << NVDEV_ENGINE_DMAOBJ) |
237 (1ULL << NVDEV_ENGINE_SW) |
238 (1ULL << NVDEV_ENGINE_GR) |
239 (1ULL << NVDEV_ENGINE_MPEG) |
240 (1ULL << NVDEV_ENGINE_ME) |
241 (1ULL << NVDEV_ENGINE_VP) |
242 (1ULL << NVDEV_ENGINE_CRYPT) |
243 (1ULL << NVDEV_ENGINE_BSP) |
244 (1ULL << NVDEV_ENGINE_PPP) |
245 (1ULL << NVDEV_ENGINE_COPY0) |
246 (1ULL << NVDEV_ENGINE_UNK1C1), &chan);
247 *pobject = nv_object(chan);
248 if (ret)
249 return ret;
250
251 ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
252 &chan->ramht);
253 if (ret)
254 return ret;
255
256 nv_parent(chan)->context_attach = nv84_fifo_context_attach;
257 nv_parent(chan)->context_detach = nv84_fifo_context_detach;
258 nv_parent(chan)->object_attach = nv84_fifo_object_attach;
259 nv_parent(chan)->object_detach = nv50_fifo_object_detach;
260
261 ioffset = args->ioffset;
262 ilength = order_base_2(args->ilength / 8);
263
264 nv_wo32(base->ramfc, 0x3c, 0x403f6078);
265 nv_wo32(base->ramfc, 0x44, 0x01003fff);
266 nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
267 nv_wo32(base->ramfc, 0x50, lower_32_bits(ioffset));
268 nv_wo32(base->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16));
269 nv_wo32(base->ramfc, 0x60, 0x7fffffff);
270 nv_wo32(base->ramfc, 0x78, 0x00000000);
271 nv_wo32(base->ramfc, 0x7c, 0x30000001);
272 nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
273 (4 << 24) |
274 (chan->ramht->base.node->offset >> 4));
275 nv_wo32(base->ramfc, 0x88, base->cache->addr >> 10);
276 nv_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12);
277 bar->flush(bar);
278 return 0;
279}
280
281static int
282nv84_fifo_chan_init(struct nouveau_object *object)
283{
284 struct nv50_fifo_priv *priv = (void *)object->engine;
285 struct nv50_fifo_base *base = (void *)object->parent;
286 struct nv50_fifo_chan *chan = (void *)object;
287 struct nouveau_gpuobj *ramfc = base->ramfc;
288 u32 chid = chan->base.chid;
289 int ret;
290
291 ret = nouveau_fifo_channel_init(&chan->base);
292 if (ret)
293 return ret;
294
295 nv_wr32(priv, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 8);
296 nv50_fifo_playlist_update(priv);
297 return 0;
298}
299
300static struct nouveau_ofuncs
301nv84_fifo_ofuncs_dma = {
302 .ctor = nv84_fifo_chan_ctor_dma,
303 .dtor = nv50_fifo_chan_dtor,
304 .init = nv84_fifo_chan_init,
305 .fini = nv50_fifo_chan_fini,
306 .rd32 = _nouveau_fifo_channel_rd32,
307 .wr32 = _nouveau_fifo_channel_wr32,
308};
309
310static struct nouveau_ofuncs
311nv84_fifo_ofuncs_ind = {
312 .ctor = nv84_fifo_chan_ctor_ind,
313 .dtor = nv50_fifo_chan_dtor,
314 .init = nv84_fifo_chan_init,
315 .fini = nv50_fifo_chan_fini,
316 .rd32 = _nouveau_fifo_channel_rd32,
317 .wr32 = _nouveau_fifo_channel_wr32,
318};
319
320static struct nouveau_oclass
321nv84_fifo_sclass[] = {
322 { NV84_CHANNEL_DMA_CLASS, &nv84_fifo_ofuncs_dma },
323 { NV84_CHANNEL_IND_CLASS, &nv84_fifo_ofuncs_ind },
324 {}
325};
326
327
328
329
330
331static int
332nv84_fifo_context_ctor(struct nouveau_object *parent,
333 struct nouveau_object *engine,
334 struct nouveau_oclass *oclass, void *data, u32 size,
335 struct nouveau_object **pobject)
336{
337 struct nv50_fifo_base *base;
338 int ret;
339
340 ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x10000,
341 0x1000, NVOBJ_FLAG_HEAP, &base);
342 *pobject = nv_object(base);
343 if (ret)
344 return ret;
345
346 ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x0200, 0,
347 NVOBJ_FLAG_ZERO_ALLOC, &base->eng);
348 if (ret)
349 return ret;
350
351 ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x4000, 0,
352 0, &base->pgd);
353 if (ret)
354 return ret;
355
356 ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
357 if (ret)
358 return ret;
359
360 ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x1000,
361 0x400, NVOBJ_FLAG_ZERO_ALLOC, &base->cache);
362 if (ret)
363 return ret;
364
365 ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x0100,
366 0x100, NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc);
367 if (ret)
368 return ret;
369
370 return 0;
371}
372
373static struct nouveau_oclass
374nv84_fifo_cclass = {
375 .handle = NV_ENGCTX(FIFO, 0x84),
376 .ofuncs = &(struct nouveau_ofuncs) {
377 .ctor = nv84_fifo_context_ctor,
378 .dtor = nv50_fifo_context_dtor,
379 .init = _nouveau_fifo_context_init,
380 .fini = _nouveau_fifo_context_fini,
381 .rd32 = _nouveau_fifo_context_rd32,
382 .wr32 = _nouveau_fifo_context_wr32,
383 },
384};
385
386
387
388
389
390static void
391nv84_fifo_uevent_enable(struct nouveau_event *event, int index)
392{
393 struct nv84_fifo_priv *priv = event->priv;
394 nv_mask(priv, 0x002140, 0x40000000, 0x40000000);
395}
396
397static void
398nv84_fifo_uevent_disable(struct nouveau_event *event, int index)
399{
400 struct nv84_fifo_priv *priv = event->priv;
401 nv_mask(priv, 0x002140, 0x40000000, 0x00000000);
402}
403
404static int
405nv84_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
406 struct nouveau_oclass *oclass, void *data, u32 size,
407 struct nouveau_object **pobject)
408{
409 struct nv50_fifo_priv *priv;
410 int ret;
411
412 ret = nouveau_fifo_create(parent, engine, oclass, 1, 127, &priv);
413 *pobject = nv_object(priv);
414 if (ret)
415 return ret;
416
417 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0,
418 &priv->playlist[0]);
419 if (ret)
420 return ret;
421
422 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0,
423 &priv->playlist[1]);
424 if (ret)
425 return ret;
426
427 priv->base.uevent->enable = nv84_fifo_uevent_enable;
428 priv->base.uevent->disable = nv84_fifo_uevent_disable;
429 priv->base.uevent->priv = priv;
430
431 nv_subdev(priv)->unit = 0x00000100;
432 nv_subdev(priv)->intr = nv04_fifo_intr;
433 nv_engine(priv)->cclass = &nv84_fifo_cclass;
434 nv_engine(priv)->sclass = nv84_fifo_sclass;
435 return 0;
436}
437
438struct nouveau_oclass
439nv84_fifo_oclass = {
440 .handle = NV_ENGINE(FIFO, 0x84),
441 .ofuncs = &(struct nouveau_ofuncs) {
442 .ctor = nv84_fifo_ctor,
443 .dtor = nv50_fifo_dtor,
444 .init = nv50_fifo_init,
445 .fini = _nouveau_fifo_fini,
446 },
447};
448
