1#include <core/engine.h>
2#include <core/device.h>
3
4#include <subdev/bios.h>
5#include <subdev/bios/bmp.h>
6#include <subdev/bios/bit.h>
7#include <subdev/bios/conn.h>
8#include <subdev/bios/dcb.h>
9#include <subdev/bios/dp.h>
10#include <subdev/bios/gpio.h>
11#include <subdev/bios/init.h>
12#include <subdev/devinit.h>
13#include <subdev/i2c.h>
14#include <subdev/vga.h>
15#include <subdev/gpio.h>
16
17#define bioslog(lvl, fmt, args...) do { \
18 nv_printk(init->bios, lvl, "0x%04x[%c]: "fmt, init->offset, \
19 init_exec(init) ? '0' + (init->nested - 1) : ' ', ##args); \
20} while(0)
21#define cont(fmt, args...) do { \
22 if (nv_subdev(init->bios)->debug >= NV_DBG_TRACE) \
23 printk(fmt, ##args); \
24} while(0)
25#define trace(fmt, args...) bioslog(TRACE, fmt, ##args)
26#define warn(fmt, args...) bioslog(WARN, fmt, ##args)
27#define error(fmt, args...) bioslog(ERROR, fmt, ##args)
28
29
30
31
32
33static inline bool
34init_exec(struct nvbios_init *init)
35{
36 return (init->execute == 1) || ((init->execute & 5) == 5);
37}
38
39static inline void
40init_exec_set(struct nvbios_init *init, bool exec)
41{
42 if (exec) init->execute &= 0xfd;
43 else init->execute |= 0x02;
44}
45
46static inline void
47init_exec_inv(struct nvbios_init *init)
48{
49 init->execute ^= 0x02;
50}
51
52static inline void
53init_exec_force(struct nvbios_init *init, bool exec)
54{
55 if (exec) init->execute |= 0x04;
56 else init->execute &= 0xfb;
57}
58
59
60
61
62
63static inline int
64init_or(struct nvbios_init *init)
65{
66 if (init_exec(init)) {
67 if (init->outp)
68 return ffs(init->outp->or) - 1;
69 error("script needs OR!!\n");
70 }
71 return 0;
72}
73
74static inline int
75init_link(struct nvbios_init *init)
76{
77 if (init_exec(init)) {
78 if (init->outp)
79 return !(init->outp->sorconf.link & 1);
80 error("script needs OR link\n");
81 }
82 return 0;
83}
84
85static inline int
86init_crtc(struct nvbios_init *init)
87{
88 if (init_exec(init)) {
89 if (init->crtc >= 0)
90 return init->crtc;
91 error("script needs crtc\n");
92 }
93 return 0;
94}
95
96static u8
97init_conn(struct nvbios_init *init)
98{
99 struct nouveau_bios *bios = init->bios;
100 u8 ver, len;
101 u16 conn;
102
103 if (init_exec(init)) {
104 if (init->outp) {
105 conn = init->outp->connector;
106 conn = dcb_conn(bios, conn, &ver, &len);
107 if (conn)
108 return nv_ro08(bios, conn);
109 }
110
111 error("script needs connector type\n");
112 }
113
114 return 0xff;
115}
116
117static inline u32
118init_nvreg(struct nvbios_init *init, u32 reg)
119{
120
121
122
123
124
125
126 reg &= ~0x00000003;
127
128
129
130
131 if (nv_device(init->bios)->card_type >= NV_50) {
132 if (reg & 0x80000000) {
133 reg += init_crtc(init) * 0x800;
134 reg &= ~0x80000000;
135 }
136
137 if (reg & 0x40000000) {
138 reg += init_or(init) * 0x800;
139 reg &= ~0x40000000;
140 if (reg & 0x20000000) {
141 reg += init_link(init) * 0x80;
142 reg &= ~0x20000000;
143 }
144 }
145 }
146
147 if (reg & ~0x00fffffc)
148 warn("unknown bits in register 0x%08x\n", reg);
149 return reg;
150}
151
152static u32
153init_rd32(struct nvbios_init *init, u32 reg)
154{
155 reg = init_nvreg(init, reg);
156 if (init_exec(init))
157 return nv_rd32(init->subdev, reg);
158 return 0x00000000;
159}
160
161static void
162init_wr32(struct nvbios_init *init, u32 reg, u32 val)
163{
164 reg = init_nvreg(init, reg);
165 if (init_exec(init))
166 nv_wr32(init->subdev, reg, val);
167}
168
169static u32
170init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val)
171{
172 reg = init_nvreg(init, reg);
173 if (init_exec(init)) {
174 u32 tmp = nv_rd32(init->subdev, reg);
175 nv_wr32(init->subdev, reg, (tmp & ~mask) | val);
176 return tmp;
177 }
178 return 0x00000000;
179}
180
181static u8
182init_rdport(struct nvbios_init *init, u16 port)
183{
184 if (init_exec(init))
185 return nv_rdport(init->subdev, init->crtc, port);
186 return 0x00;
187}
188
189static void
190init_wrport(struct nvbios_init *init, u16 port, u8 value)
191{
192 if (init_exec(init))
193 nv_wrport(init->subdev, init->crtc, port, value);
194}
195
196static u8
197init_rdvgai(struct nvbios_init *init, u16 port, u8 index)
198{
199 struct nouveau_subdev *subdev = init->subdev;
200 if (init_exec(init)) {
201 int head = init->crtc < 0 ? 0 : init->crtc;
202 return nv_rdvgai(subdev, head, port, index);
203 }
204 return 0x00;
205}
206
207static void
208init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value)
209{
210
211 if (nv_device(init->subdev)->card_type < NV_50) {
212 if (port == 0x03d4 && index == 0x44)
213 init->crtc = 0;
214 }
215
216 if (init_exec(init)) {
217 int head = init->crtc < 0 ? 0 : init->crtc;
218 nv_wrvgai(init->subdev, head, port, index, value);
219 }
220
221
222 if (nv_device(init->subdev)->card_type < NV_50) {
223 if (port == 0x03d4 && index == 0x44 && value == 3)
224 init->crtc = 1;
225 }
226}
227
228static struct nouveau_i2c_port *
229init_i2c(struct nvbios_init *init, int index)
230{
231 struct nouveau_i2c *i2c = nouveau_i2c(init->bios);
232
233 if (index == 0xff) {
234 index = NV_I2C_DEFAULT(0);
235 if (init->outp && init->outp->i2c_upper_default)
236 index = NV_I2C_DEFAULT(1);
237 } else
238 if (index < 0) {
239 if (!init->outp) {
240 if (init_exec(init))
241 error("script needs output for i2c\n");
242 return NULL;
243 }
244
245 if (index == -2 && init->outp->location) {
246 index = NV_I2C_TYPE_EXTAUX(init->outp->extdev);
247 return i2c->find_type(i2c, index);
248 }
249
250 index = init->outp->i2c_index;
251 }
252
253 return i2c->find(i2c, index);
254}
255
256static int
257init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg)
258{
259 struct nouveau_i2c_port *port = init_i2c(init, index);
260 if (port && init_exec(init))
261 return nv_rdi2cr(port, addr, reg);
262 return -ENODEV;
263}
264
265static int
266init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val)
267{
268 struct nouveau_i2c_port *port = init_i2c(init, index);
269 if (port && init_exec(init))
270 return nv_wri2cr(port, addr, reg, val);
271 return -ENODEV;
272}
273
274static int
275init_rdauxr(struct nvbios_init *init, u32 addr)
276{
277 struct nouveau_i2c_port *port = init_i2c(init, -2);
278 u8 data;
279
280 if (port && init_exec(init)) {
281 int ret = nv_rdaux(port, addr, &data, 1);
282 if (ret)
283 return ret;
284 return data;
285 }
286
287 return -ENODEV;
288}
289
290static int
291init_wrauxr(struct nvbios_init *init, u32 addr, u8 data)
292{
293 struct nouveau_i2c_port *port = init_i2c(init, -2);
294 if (port && init_exec(init))
295 return nv_wraux(port, addr, &data, 1);
296 return -ENODEV;
297}
298
299static void
300init_prog_pll(struct nvbios_init *init, u32 id, u32 freq)
301{
302 struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
303 if (devinit->pll_set && init_exec(init)) {
304 int ret = devinit->pll_set(devinit, id, freq);
305 if (ret)
306 warn("failed to prog pll 0x%08x to %dkHz\n", id, freq);
307 }
308}
309
310
311
312
313
314static u16
315init_table(struct nouveau_bios *bios, u16 *len)
316{
317 struct bit_entry bit_I;
318
319 if (!bit_entry(bios, 'I', &bit_I)) {
320 *len = bit_I.length;
321 return bit_I.offset;
322 }
323
324 if (bmp_version(bios) >= 0x0510) {
325 *len = 14;
326 return bios->bmp_offset + 75;
327 }
328
329 return 0x0000;
330}
331
332static u16
333init_table_(struct nvbios_init *init, u16 offset, const char *name)
334{
335 struct nouveau_bios *bios = init->bios;
336 u16 len, data = init_table(bios, &len);
337 if (data) {
338 if (len >= offset + 2) {
339 data = nv_ro16(bios, data + offset);
340 if (data)
341 return data;
342
343 warn("%s pointer invalid\n", name);
344 return 0x0000;
345 }
346
347 warn("init data too short for %s pointer", name);
348 return 0x0000;
349 }
350
351 warn("init data not found\n");
352 return 0x0000;
353}
354
355#define init_script_table(b) init_table_((b), 0x00, "script table")
356#define init_macro_index_table(b) init_table_((b), 0x02, "macro index table")
357#define init_macro_table(b) init_table_((b), 0x04, "macro table")
358#define init_condition_table(b) init_table_((b), 0x06, "condition table")
359#define init_io_condition_table(b) init_table_((b), 0x08, "io condition table")
360#define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table")
361#define init_function_table(b) init_table_((b), 0x0c, "function table")
362#define init_xlat_table(b) init_table_((b), 0x10, "xlat table");
363
364static u16
365init_script(struct nouveau_bios *bios, int index)
366{
367 struct nvbios_init init = { .bios = bios };
368 u16 data;
369
370 if (bmp_version(bios) && bmp_version(bios) < 0x0510) {
371 if (index > 1)
372 return 0x0000;
373
374 data = bios->bmp_offset + (bios->version.major < 2 ? 14 : 18);
375 return nv_ro16(bios, data + (index * 2));
376 }
377
378 data = init_script_table(&init);
379 if (data)
380 return nv_ro16(bios, data + (index * 2));
381
382 return 0x0000;
383}
384
385static u16
386init_unknown_script(struct nouveau_bios *bios)
387{
388 u16 len, data = init_table(bios, &len);
389 if (data && len >= 16)
390 return nv_ro16(bios, data + 14);
391 return 0x0000;
392}
393
394static u16
395init_ram_restrict_table(struct nvbios_init *init)
396{
397 struct nouveau_bios *bios = init->bios;
398 struct bit_entry bit_M;
399 u16 data = 0x0000;
400
401 if (!bit_entry(bios, 'M', &bit_M)) {
402 if (bit_M.version == 1 && bit_M.length >= 5)
403 data = nv_ro16(bios, bit_M.offset + 3);
404 if (bit_M.version == 2 && bit_M.length >= 3)
405 data = nv_ro16(bios, bit_M.offset + 1);
406 }
407
408 if (data == 0x0000)
409 warn("ram restrict table not found\n");
410 return data;
411}
412
413static u8
414init_ram_restrict_group_count(struct nvbios_init *init)
415{
416 struct nouveau_bios *bios = init->bios;
417 struct bit_entry bit_M;
418
419 if (!bit_entry(bios, 'M', &bit_M)) {
420 if (bit_M.version == 1 && bit_M.length >= 5)
421 return nv_ro08(bios, bit_M.offset + 2);
422 if (bit_M.version == 2 && bit_M.length >= 3)
423 return nv_ro08(bios, bit_M.offset + 0);
424 }
425
426 return 0x00;
427}
428
429static u8
430init_ram_restrict_strap(struct nvbios_init *init)
431{
432
433
434
435
436
437
438
439
440 if (!init->ramcfg || init->bios->version.major < 0x70)
441 init->ramcfg = init_rd32(init, 0x101000);
442 return (init->ramcfg & 0x00000003c) >> 2;
443}
444
445static u8
446init_ram_restrict(struct nvbios_init *init)
447{
448 u8 strap = init_ram_restrict_strap(init);
449 u16 table = init_ram_restrict_table(init);
450 if (table)
451 return nv_ro08(init->bios, table + strap);
452 return 0x00;
453}
454
455static u8
456init_xlat_(struct nvbios_init *init, u8 index, u8 offset)
457{
458 struct nouveau_bios *bios = init->bios;
459 u16 table = init_xlat_table(init);
460 if (table) {
461 u16 data = nv_ro16(bios, table + (index * 2));
462 if (data)
463 return nv_ro08(bios, data + offset);
464 warn("xlat table pointer %d invalid\n", index);
465 }
466 return 0x00;
467}
468
469
470
471
472
473static bool
474init_condition_met(struct nvbios_init *init, u8 cond)
475{
476 struct nouveau_bios *bios = init->bios;
477 u16 table = init_condition_table(init);
478 if (table) {
479 u32 reg = nv_ro32(bios, table + (cond * 12) + 0);
480 u32 msk = nv_ro32(bios, table + (cond * 12) + 4);
481 u32 val = nv_ro32(bios, table + (cond * 12) + 8);
482 trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n",
483 cond, reg, msk, val);
484 return (init_rd32(init, reg) & msk) == val;
485 }
486 return false;
487}
488
489static bool
490init_io_condition_met(struct nvbios_init *init, u8 cond)
491{
492 struct nouveau_bios *bios = init->bios;
493 u16 table = init_io_condition_table(init);
494 if (table) {
495 u16 port = nv_ro16(bios, table + (cond * 5) + 0);
496 u8 index = nv_ro08(bios, table + (cond * 5) + 2);
497 u8 mask = nv_ro08(bios, table + (cond * 5) + 3);
498 u8 value = nv_ro08(bios, table + (cond * 5) + 4);
499 trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n",
500 cond, port, index, mask, value);
501 return (init_rdvgai(init, port, index) & mask) == value;
502 }
503 return false;
504}
505
506static bool
507init_io_flag_condition_met(struct nvbios_init *init, u8 cond)
508{
509 struct nouveau_bios *bios = init->bios;
510 u16 table = init_io_flag_condition_table(init);
511 if (table) {
512 u16 port = nv_ro16(bios, table + (cond * 9) + 0);
513 u8 index = nv_ro08(bios, table + (cond * 9) + 2);
514 u8 mask = nv_ro08(bios, table + (cond * 9) + 3);
515 u8 shift = nv_ro08(bios, table + (cond * 9) + 4);
516 u16 data = nv_ro16(bios, table + (cond * 9) + 5);
517 u8 dmask = nv_ro08(bios, table + (cond * 9) + 7);
518 u8 value = nv_ro08(bios, table + (cond * 9) + 8);
519 u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift;
520 return (nv_ro08(bios, data + ioval) & dmask) == value;
521 }
522 return false;
523}
524
525static inline u32
526init_shift(u32 data, u8 shift)
527{
528 if (shift < 0x80)
529 return data >> shift;
530 return data << (0x100 - shift);
531}
532
533static u32
534init_tmds_reg(struct nvbios_init *init, u8 tmds)
535{
536
537
538
539
540
541
542
543
544
545 const int pramdac_offset[13] = {
546 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
547 const u32 pramdac_table[4] = {
548 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
549
550 if (tmds >= 0x80) {
551 if (init->outp) {
552 u32 dacoffset = pramdac_offset[init->outp->or];
553 if (tmds == 0x81)
554 dacoffset ^= 8;
555 return 0x6808b0 + dacoffset;
556 }
557
558 if (init_exec(init))
559 error("tmds opcodes need dcb\n");
560 } else {
561 if (tmds < ARRAY_SIZE(pramdac_table))
562 return pramdac_table[tmds];
563
564 error("tmds selector 0x%02x unknown\n", tmds);
565 }
566
567 return 0;
568}
569
570
571
572
573
574
575
576
577
578static void
579init_reserved(struct nvbios_init *init)
580{
581 u8 opcode = nv_ro08(init->bios, init->offset);
582 u8 length, i;
583
584 switch (opcode) {
585 case 0xaa:
586 length = 4;
587 break;
588 default:
589 length = 1;
590 break;
591 }
592
593 trace("RESERVED 0x%02x\t", opcode);
594 for (i = 1; i < length; i++)
595 cont(" 0x%02x", nv_ro08(init->bios, init->offset + i));
596 cont("\n");
597 init->offset += length;
598}
599
600
601
602
603
604static void
605init_done(struct nvbios_init *init)
606{
607 trace("DONE\n");
608 init->offset = 0x0000;
609}
610
611
612
613
614
615static void
616init_io_restrict_prog(struct nvbios_init *init)
617{
618 struct nouveau_bios *bios = init->bios;
619 u16 port = nv_ro16(bios, init->offset + 1);
620 u8 index = nv_ro08(bios, init->offset + 3);
621 u8 mask = nv_ro08(bios, init->offset + 4);
622 u8 shift = nv_ro08(bios, init->offset + 5);
623 u8 count = nv_ro08(bios, init->offset + 6);
624 u32 reg = nv_ro32(bios, init->offset + 7);
625 u8 conf, i;
626
627 trace("IO_RESTRICT_PROG\tR[0x%06x] = "
628 "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n",
629 reg, port, index, mask, shift);
630 init->offset += 11;
631
632 conf = (init_rdvgai(init, port, index) & mask) >> shift;
633 for (i = 0; i < count; i++) {
634 u32 data = nv_ro32(bios, init->offset);
635
636 if (i == conf) {
637 trace("\t0x%08x *\n", data);
638 init_wr32(init, reg, data);
639 } else {
640 trace("\t0x%08x\n", data);
641 }
642
643 init->offset += 4;
644 }
645 trace("}]\n");
646}
647
648
649
650
651
652static void
653init_repeat(struct nvbios_init *init)
654{
655 struct nouveau_bios *bios = init->bios;
656 u8 count = nv_ro08(bios, init->offset + 1);
657 u16 repeat = init->repeat;
658
659 trace("REPEAT\t0x%02x\n", count);
660 init->offset += 2;
661
662 init->repeat = init->offset;
663 init->repend = init->offset;
664 while (count--) {
665 init->offset = init->repeat;
666 nvbios_exec(init);
667 if (count)
668 trace("REPEAT\t0x%02x\n", count);
669 }
670 init->offset = init->repend;
671 init->repeat = repeat;
672}
673
674
675
676
677
678static void
679init_io_restrict_pll(struct nvbios_init *init)
680{
681 struct nouveau_bios *bios = init->bios;
682 u16 port = nv_ro16(bios, init->offset + 1);
683 u8 index = nv_ro08(bios, init->offset + 3);
684 u8 mask = nv_ro08(bios, init->offset + 4);
685 u8 shift = nv_ro08(bios, init->offset + 5);
686 s8 iofc = nv_ro08(bios, init->offset + 6);
687 u8 count = nv_ro08(bios, init->offset + 7);
688 u32 reg = nv_ro32(bios, init->offset + 8);
689 u8 conf, i;
690
691 trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= "
692 "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n",
693 reg, port, index, mask, shift, iofc);
694 init->offset += 12;
695
696 conf = (init_rdvgai(init, port, index) & mask) >> shift;
697 for (i = 0; i < count; i++) {
698 u32 freq = nv_ro16(bios, init->offset) * 10;
699
700 if (i == conf) {
701 trace("\t%dkHz *\n", freq);
702 if (iofc > 0 && init_io_flag_condition_met(init, iofc))
703 freq *= 2;
704 init_prog_pll(init, reg, freq);
705 } else {
706 trace("\t%dkHz\n", freq);
707 }
708
709 init->offset += 2;
710 }
711 trace("}]\n");
712}
713
714
715
716
717
718static void
719init_end_repeat(struct nvbios_init *init)
720{
721 trace("END_REPEAT\n");
722 init->offset += 1;
723
724 if (init->repeat) {
725 init->repend = init->offset;
726 init->offset = 0;
727 }
728}
729
730
731
732
733
734static void
735init_copy(struct nvbios_init *init)
736{
737 struct nouveau_bios *bios = init->bios;
738 u32 reg = nv_ro32(bios, init->offset + 1);
739 u8 shift = nv_ro08(bios, init->offset + 5);
740 u8 smask = nv_ro08(bios, init->offset + 6);
741 u16 port = nv_ro16(bios, init->offset + 7);
742 u8 index = nv_ro08(bios, init->offset + 9);
743 u8 mask = nv_ro08(bios, init->offset + 10);
744 u8 data;
745
746 trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= "
747 "((R[0x%06x] %s 0x%02x) & 0x%02x)\n",
748 port, index, mask, reg, (shift & 0x80) ? "<<" : ">>",
749 (shift & 0x80) ? (0x100 - shift) : shift, smask);
750 init->offset += 11;
751
752 data = init_rdvgai(init, port, index) & mask;
753 data |= init_shift(init_rd32(init, reg), shift) & smask;
754 init_wrvgai(init, port, index, data);
755}
756
757
758
759
760
761static void
762init_not(struct nvbios_init *init)
763{
764 trace("NOT\n");
765 init->offset += 1;
766 init_exec_inv(init);
767}
768
769
770
771
772
773static void
774init_io_flag_condition(struct nvbios_init *init)
775{
776 struct nouveau_bios *bios = init->bios;
777 u8 cond = nv_ro08(bios, init->offset + 1);
778
779 trace("IO_FLAG_CONDITION\t0x%02x\n", cond);
780 init->offset += 2;
781
782 if (!init_io_flag_condition_met(init, cond))
783 init_exec_set(init, false);
784}
785
786
787
788
789
790static void
791init_dp_condition(struct nvbios_init *init)
792{
793 struct nouveau_bios *bios = init->bios;
794 struct nvbios_dpout info;
795 u8 cond = nv_ro08(bios, init->offset + 1);
796 u8 unkn = nv_ro08(bios, init->offset + 2);
797 u8 ver, hdr, cnt, len;
798 u16 data;
799
800 trace("DP_CONDITION\t0x%02x 0x%02x\n", cond, unkn);
801 init->offset += 3;
802
803 switch (cond) {
804 case 0:
805 if (init_conn(init) != DCB_CONNECTOR_eDP)
806 init_exec_set(init, false);
807 break;
808 case 1:
809 case 2:
810 if ( init->outp &&
811 (data = nvbios_dpout_match(bios, DCB_OUTPUT_DP,
812 (init->outp->or << 0) |
813 (init->outp->sorconf.link << 6),
814 &ver, &hdr, &cnt, &len, &info)))
815 {
816 if (!(info.flags & cond))
817 init_exec_set(init, false);
818 break;
819 }
820
821 if (init_exec(init))
822 warn("script needs dp output table data\n");
823 break;
824 case 5:
825 if (!(init_rdauxr(init, 0x0d) & 1))
826 init_exec_set(init, false);
827 break;
828 default:
829 warn("unknown dp condition 0x%02x\n", cond);
830 break;
831 }
832}
833
834
835
836
837
838static void
839init_io_mask_or(struct nvbios_init *init)
840{
841 struct nouveau_bios *bios = init->bios;
842 u8 index = nv_ro08(bios, init->offset + 1);
843 u8 or = init_or(init);
844 u8 data;
845
846 trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)\n", index, or);
847 init->offset += 2;
848
849 data = init_rdvgai(init, 0x03d4, index);
850 init_wrvgai(init, 0x03d4, index, data &= ~(1 << or));
851}
852
853
854
855
856
857static void
858init_io_or(struct nvbios_init *init)
859{
860 struct nouveau_bios *bios = init->bios;
861 u8 index = nv_ro08(bios, init->offset + 1);
862 u8 or = init_or(init);
863 u8 data;
864
865 trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)\n", index, or);
866 init->offset += 2;
867
868 data = init_rdvgai(init, 0x03d4, index);
869 init_wrvgai(init, 0x03d4, index, data | (1 << or));
870}
871
872
873
874
875
876static void
877init_idx_addr_latched(struct nvbios_init *init)
878{
879 struct nouveau_bios *bios = init->bios;
880 u32 creg = nv_ro32(bios, init->offset + 1);
881 u32 dreg = nv_ro32(bios, init->offset + 5);
882 u32 mask = nv_ro32(bios, init->offset + 9);
883 u32 data = nv_ro32(bios, init->offset + 13);
884 u8 count = nv_ro08(bios, init->offset + 17);
885
886 trace("INDEX_ADDRESS_LATCHED\t"
887 "R[0x%06x] : R[0x%06x]\n\tCTRL &= 0x%08x |= 0x%08x\n",
888 creg, dreg, mask, data);
889 init->offset += 18;
890
891 while (count--) {
892 u8 iaddr = nv_ro08(bios, init->offset + 0);
893 u8 idata = nv_ro08(bios, init->offset + 1);
894
895 trace("\t[0x%02x] = 0x%02x\n", iaddr, idata);
896 init->offset += 2;
897
898 init_wr32(init, dreg, idata);
899 init_mask(init, creg, ~mask, data | iaddr);
900 }
901}
902
903
904
905
906
907static void
908init_io_restrict_pll2(struct nvbios_init *init)
909{
910 struct nouveau_bios *bios = init->bios;
911 u16 port = nv_ro16(bios, init->offset + 1);
912 u8 index = nv_ro08(bios, init->offset + 3);
913 u8 mask = nv_ro08(bios, init->offset + 4);
914 u8 shift = nv_ro08(bios, init->offset + 5);
915 u8 count = nv_ro08(bios, init->offset + 6);
916 u32 reg = nv_ro32(bios, init->offset + 7);
917 u8 conf, i;
918
919 trace("IO_RESTRICT_PLL2\t"
920 "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n",
921 reg, port, index, mask, shift);
922 init->offset += 11;
923
924 conf = (init_rdvgai(init, port, index) & mask) >> shift;
925 for (i = 0; i < count; i++) {
926 u32 freq = nv_ro32(bios, init->offset);
927 if (i == conf) {
928 trace("\t%dkHz *\n", freq);
929 init_prog_pll(init, reg, freq);
930 } else {
931 trace("\t%dkHz\n", freq);
932 }
933 init->offset += 4;
934 }
935 trace("}]\n");
936}
937
938
939
940
941
942static void
943init_pll2(struct nvbios_init *init)
944{
945 struct nouveau_bios *bios = init->bios;
946 u32 reg = nv_ro32(bios, init->offset + 1);
947 u32 freq = nv_ro32(bios, init->offset + 5);
948
949 trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
950 init->offset += 9;
951
952 init_prog_pll(init, reg, freq);
953}
954
955
956
957
958
959static void
960init_i2c_byte(struct nvbios_init *init)
961{
962 struct nouveau_bios *bios = init->bios;
963 u8 index = nv_ro08(bios, init->offset + 1);
964 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
965 u8 count = nv_ro08(bios, init->offset + 3);
966
967 trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
968 init->offset += 4;
969
970 while (count--) {
971 u8 reg = nv_ro08(bios, init->offset + 0);
972 u8 mask = nv_ro08(bios, init->offset + 1);
973 u8 data = nv_ro08(bios, init->offset + 2);
974 int val;
975
976 trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data);
977 init->offset += 3;
978
979 val = init_rdi2cr(init, index, addr, reg);
980 if (val < 0)
981 continue;
982 init_wri2cr(init, index, addr, reg, (val & mask) | data);
983 }
984}
985
986
987
988
989
990static void
991init_zm_i2c_byte(struct nvbios_init *init)
992{
993 struct nouveau_bios *bios = init->bios;
994 u8 index = nv_ro08(bios, init->offset + 1);
995 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
996 u8 count = nv_ro08(bios, init->offset + 3);
997
998 trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
999 init->offset += 4;
1000
1001 while (count--) {
1002 u8 reg = nv_ro08(bios, init->offset + 0);
1003 u8 data = nv_ro08(bios, init->offset + 1);
1004
1005 trace("\t[0x%02x] = 0x%02x\n", reg, data);
1006 init->offset += 2;
1007
1008 init_wri2cr(init, index, addr, reg, data);
1009 }
1010
1011}
1012
1013
1014
1015
1016
1017static void
1018init_zm_i2c(struct nvbios_init *init)
1019{
1020 struct nouveau_bios *bios = init->bios;
1021 u8 index = nv_ro08(bios, init->offset + 1);
1022 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
1023 u8 count = nv_ro08(bios, init->offset + 3);
1024 u8 data[256], i;
1025
1026 trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr);
1027 init->offset += 4;
1028
1029 for (i = 0; i < count; i++) {
1030 data[i] = nv_ro08(bios, init->offset);
1031 trace("\t0x%02x\n", data[i]);
1032 init->offset++;
1033 }
1034
1035 if (init_exec(init)) {
1036 struct nouveau_i2c_port *port = init_i2c(init, index);
1037 struct i2c_msg msg = {
1038 .addr = addr, .flags = 0, .len = count, .buf = data,
1039 };
1040 int ret;
1041
1042 if (port && (ret = i2c_transfer(&port->adapter, &msg, 1)) != 1)
1043 warn("i2c wr failed, %d\n", ret);
1044 }
1045}
1046
1047
1048
1049
1050
1051static void
1052init_tmds(struct nvbios_init *init)
1053{
1054 struct nouveau_bios *bios = init->bios;
1055 u8 tmds = nv_ro08(bios, init->offset + 1);
1056 u8 addr = nv_ro08(bios, init->offset + 2);
1057 u8 mask = nv_ro08(bios, init->offset + 3);
1058 u8 data = nv_ro08(bios, init->offset + 4);
1059 u32 reg = init_tmds_reg(init, tmds);
1060
1061 trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n",
1062 tmds, addr, mask, data);
1063 init->offset += 5;
1064
1065 if (reg == 0)
1066 return;
1067
1068 init_wr32(init, reg + 0, addr | 0x00010000);
1069 init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask));
1070 init_wr32(init, reg + 0, addr);
1071}
1072
1073
1074
1075
1076
1077static void
1078init_zm_tmds_group(struct nvbios_init *init)
1079{
1080 struct nouveau_bios *bios = init->bios;
1081 u8 tmds = nv_ro08(bios, init->offset + 1);
1082 u8 count = nv_ro08(bios, init->offset + 2);
1083 u32 reg = init_tmds_reg(init, tmds);
1084
1085 trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds);
1086 init->offset += 3;
1087
1088 while (count--) {
1089 u8 addr = nv_ro08(bios, init->offset + 0);
1090 u8 data = nv_ro08(bios, init->offset + 1);
1091
1092 trace("\t[0x%02x] = 0x%02x\n", addr, data);
1093 init->offset += 2;
1094
1095 init_wr32(init, reg + 4, data);
1096 init_wr32(init, reg + 0, addr);
1097 }
1098}
1099
1100
1101
1102
1103
1104static void
1105init_cr_idx_adr_latch(struct nvbios_init *init)
1106{
1107 struct nouveau_bios *bios = init->bios;
1108 u8 addr0 = nv_ro08(bios, init->offset + 1);
1109 u8 addr1 = nv_ro08(bios, init->offset + 2);
1110 u8 base = nv_ro08(bios, init->offset + 3);
1111 u8 count = nv_ro08(bios, init->offset + 4);
1112 u8 save0;
1113
1114 trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0, addr1);
1115 init->offset += 5;
1116
1117 save0 = init_rdvgai(init, 0x03d4, addr0);
1118 while (count--) {
1119 u8 data = nv_ro08(bios, init->offset);
1120
1121 trace("\t\t[0x%02x] = 0x%02x\n", base, data);
1122 init->offset += 1;
1123
1124 init_wrvgai(init, 0x03d4, addr0, base++);
1125 init_wrvgai(init, 0x03d4, addr1, data);
1126 }
1127 init_wrvgai(init, 0x03d4, addr0, save0);
1128}
1129
1130
1131
1132
1133
1134static void
1135init_cr(struct nvbios_init *init)
1136{
1137 struct nouveau_bios *bios = init->bios;
1138 u8 addr = nv_ro08(bios, init->offset + 1);
1139 u8 mask = nv_ro08(bios, init->offset + 2);
1140 u8 data = nv_ro08(bios, init->offset + 3);
1141 u8 val;
1142
1143 trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1144 init->offset += 4;
1145
1146 val = init_rdvgai(init, 0x03d4, addr) & mask;
1147 init_wrvgai(init, 0x03d4, addr, val | data);
1148}
1149
1150
1151
1152
1153
1154static void
1155init_zm_cr(struct nvbios_init *init)
1156{
1157 struct nouveau_bios *bios = init->bios;
1158 u8 addr = nv_ro08(bios, init->offset + 1);
1159 u8 data = nv_ro08(bios, init->offset + 2);
1160
1161 trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr, data);
1162 init->offset += 3;
1163
1164 init_wrvgai(init, 0x03d4, addr, data);
1165}
1166
1167
1168
1169
1170
1171static void
1172init_zm_cr_group(struct nvbios_init *init)
1173{
1174 struct nouveau_bios *bios = init->bios;
1175 u8 count = nv_ro08(bios, init->offset + 1);
1176
1177 trace("ZM_CR_GROUP\n");
1178 init->offset += 2;
1179
1180 while (count--) {
1181 u8 addr = nv_ro08(bios, init->offset + 0);
1182 u8 data = nv_ro08(bios, init->offset + 1);
1183
1184 trace("\t\tC[0x%02x] = 0x%02x\n", addr, data);
1185 init->offset += 2;
1186
1187 init_wrvgai(init, 0x03d4, addr, data);
1188 }
1189}
1190
1191
1192
1193
1194
1195static void
1196init_condition_time(struct nvbios_init *init)
1197{
1198 struct nouveau_bios *bios = init->bios;
1199 u8 cond = nv_ro08(bios, init->offset + 1);
1200 u8 retry = nv_ro08(bios, init->offset + 2);
1201 u8 wait = min((u16)retry * 50, 100);
1202
1203 trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry);
1204 init->offset += 3;
1205
1206 if (!init_exec(init))
1207 return;
1208
1209 while (wait--) {
1210 if (init_condition_met(init, cond))
1211 return;
1212 mdelay(20);
1213 }
1214
1215 init_exec_set(init, false);
1216}
1217
1218
1219
1220
1221
1222static void
1223init_ltime(struct nvbios_init *init)
1224{
1225 struct nouveau_bios *bios = init->bios;
1226 u16 msec = nv_ro16(bios, init->offset + 1);
1227
1228 trace("LTIME\t0x%04x\n", msec);
1229 init->offset += 3;
1230
1231 if (init_exec(init))
1232 mdelay(msec);
1233}
1234
1235
1236
1237
1238
1239static void
1240init_zm_reg_sequence(struct nvbios_init *init)
1241{
1242 struct nouveau_bios *bios = init->bios;
1243 u32 base = nv_ro32(bios, init->offset + 1);
1244 u8 count = nv_ro08(bios, init->offset + 5);
1245
1246 trace("ZM_REG_SEQUENCE\t0x%02x\n", count);
1247 init->offset += 6;
1248
1249 while (count--) {
1250 u32 data = nv_ro32(bios, init->offset);
1251
1252 trace("\t\tR[0x%06x] = 0x%08x\n", base, data);
1253 init->offset += 4;
1254
1255 init_wr32(init, base, data);
1256 base += 4;
1257 }
1258}
1259
1260
1261
1262
1263
1264static void
1265init_sub_direct(struct nvbios_init *init)
1266{
1267 struct nouveau_bios *bios = init->bios;
1268 u16 addr = nv_ro16(bios, init->offset + 1);
1269 u16 save;
1270
1271 trace("SUB_DIRECT\t0x%04x\n", addr);
1272
1273 if (init_exec(init)) {
1274 save = init->offset;
1275 init->offset = addr;
1276 if (nvbios_exec(init)) {
1277 error("error parsing sub-table\n");
1278 return;
1279 }
1280 init->offset = save;
1281 }
1282
1283 init->offset += 3;
1284}
1285
1286
1287
1288
1289
1290static void
1291init_jump(struct nvbios_init *init)
1292{
1293 struct nouveau_bios *bios = init->bios;
1294 u16 offset = nv_ro16(bios, init->offset + 1);
1295
1296 trace("JUMP\t0x%04x\n", offset);
1297 init->offset = offset;
1298}
1299
1300
1301
1302
1303
1304static void
1305init_i2c_if(struct nvbios_init *init)
1306{
1307 struct nouveau_bios *bios = init->bios;
1308 u8 index = nv_ro08(bios, init->offset + 1);
1309 u8 addr = nv_ro08(bios, init->offset + 2);
1310 u8 reg = nv_ro08(bios, init->offset + 3);
1311 u8 mask = nv_ro08(bios, init->offset + 4);
1312 u8 data = nv_ro08(bios, init->offset + 5);
1313 u8 value;
1314
1315 trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n",
1316 index, addr, reg, mask, data);
1317 init->offset += 6;
1318 init_exec_force(init, true);
1319
1320 value = init_rdi2cr(init, index, addr, reg);
1321 if ((value & mask) != data)
1322 init_exec_set(init, false);
1323
1324 init_exec_force(init, false);
1325}
1326
1327
1328
1329
1330
1331static void
1332init_copy_nv_reg(struct nvbios_init *init)
1333{
1334 struct nouveau_bios *bios = init->bios;
1335 u32 sreg = nv_ro32(bios, init->offset + 1);
1336 u8 shift = nv_ro08(bios, init->offset + 5);
1337 u32 smask = nv_ro32(bios, init->offset + 6);
1338 u32 sxor = nv_ro32(bios, init->offset + 10);
1339 u32 dreg = nv_ro32(bios, init->offset + 14);
1340 u32 dmask = nv_ro32(bios, init->offset + 18);
1341 u32 data;
1342
1343 trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= "
1344 "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n",
1345 dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>",
1346 (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor);
1347 init->offset += 22;
1348
1349 data = init_shift(init_rd32(init, sreg), shift);
1350 init_mask(init, dreg, ~dmask, (data & smask) ^ sxor);
1351}
1352
1353
1354
1355
1356
1357static void
1358init_zm_index_io(struct nvbios_init *init)
1359{
1360 struct nouveau_bios *bios = init->bios;
1361 u16 port = nv_ro16(bios, init->offset + 1);
1362 u8 index = nv_ro08(bios, init->offset + 3);
1363 u8 data = nv_ro08(bios, init->offset + 4);
1364
1365 trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data);
1366 init->offset += 5;
1367
1368 init_wrvgai(init, port, index, data);
1369}
1370
1371
1372
1373
1374
1375static void
1376init_compute_mem(struct nvbios_init *init)
1377{
1378 struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
1379
1380 trace("COMPUTE_MEM\n");
1381 init->offset += 1;
1382
1383 init_exec_force(init, true);
1384 if (init_exec(init) && devinit->meminit)
1385 devinit->meminit(devinit);
1386 init_exec_force(init, false);
1387}
1388
1389
1390
1391
1392
1393static void
1394init_reset(struct nvbios_init *init)
1395{
1396 struct nouveau_bios *bios = init->bios;
1397 u32 reg = nv_ro32(bios, init->offset + 1);
1398 u32 data1 = nv_ro32(bios, init->offset + 5);
1399 u32 data2 = nv_ro32(bios, init->offset + 9);
1400 u32 savepci19;
1401
1402 trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2);
1403 init->offset += 13;
1404 init_exec_force(init, true);
1405
1406 savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000);
1407 init_wr32(init, reg, data1);
1408 udelay(10);
1409 init_wr32(init, reg, data2);
1410 init_wr32(init, 0x00184c, savepci19);
1411 init_mask(init, 0x001850, 0x00000001, 0x00000000);
1412
1413 init_exec_force(init, false);
1414}
1415
1416
1417
1418
1419
1420static u16
1421init_configure_mem_clk(struct nvbios_init *init)
1422{
1423 u16 mdata = bmp_mem_init_table(init->bios);
1424 if (mdata)
1425 mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66;
1426 return mdata;
1427}
1428
1429static void
1430init_configure_mem(struct nvbios_init *init)
1431{
1432 struct nouveau_bios *bios = init->bios;
1433 u16 mdata, sdata;
1434 u32 addr, data;
1435
1436 trace("CONFIGURE_MEM\n");
1437 init->offset += 1;
1438
1439 if (bios->version.major > 2) {
1440 init_done(init);
1441 return;
1442 }
1443 init_exec_force(init, true);
1444
1445 mdata = init_configure_mem_clk(init);
1446 sdata = bmp_sdr_seq_table(bios);
1447 if (nv_ro08(bios, mdata) & 0x01)
1448 sdata = bmp_ddr_seq_table(bios);
1449 mdata += 6;
1450
1451 data = init_rdvgai(init, 0x03c4, 0x01);
1452 init_wrvgai(init, 0x03c4, 0x01, data | 0x20);
1453
1454 for (; (addr = nv_ro32(bios, sdata)) != 0xffffffff; sdata += 4) {
1455 switch (addr) {
1456 case 0x10021c:
1457 case 0x1002d0:
1458 case 0x1002d4:
1459 data = 0x00000001;
1460 break;
1461 default:
1462 data = nv_ro32(bios, mdata);
1463 mdata += 4;
1464 if (data == 0xffffffff)
1465 continue;
1466 break;
1467 }
1468
1469 init_wr32(init, addr, data);
1470 }
1471
1472 init_exec_force(init, false);
1473}
1474
1475
1476
1477
1478
1479static void
1480init_configure_clk(struct nvbios_init *init)
1481{
1482 struct nouveau_bios *bios = init->bios;
1483 u16 mdata, clock;
1484
1485 trace("CONFIGURE_CLK\n");
1486 init->offset += 1;
1487
1488 if (bios->version.major > 2) {
1489 init_done(init);
1490 return;
1491 }
1492 init_exec_force(init, true);
1493
1494 mdata = init_configure_mem_clk(init);
1495
1496
1497 clock = nv_ro16(bios, mdata + 4) * 10;
1498 init_prog_pll(init, 0x680500, clock);
1499
1500
1501 clock = nv_ro16(bios, mdata + 2) * 10;
1502 if (nv_ro08(bios, mdata) & 0x01)
1503 clock *= 2;
1504 init_prog_pll(init, 0x680504, clock);
1505
1506 init_exec_force(init, false);
1507}
1508
1509
1510
1511
1512
1513static void
1514init_configure_preinit(struct nvbios_init *init)
1515{
1516 struct nouveau_bios *bios = init->bios;
1517 u32 strap;
1518
1519 trace("CONFIGURE_PREINIT\n");
1520 init->offset += 1;
1521
1522 if (bios->version.major > 2) {
1523 init_done(init);
1524 return;
1525 }
1526 init_exec_force(init, true);
1527
1528 strap = init_rd32(init, 0x101000);
1529 strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6);
1530 init_wrvgai(init, 0x03d4, 0x3c, strap);
1531
1532 init_exec_force(init, false);
1533}
1534
1535
1536
1537
1538
1539static void
1540init_io(struct nvbios_init *init)
1541{
1542 struct nouveau_bios *bios = init->bios;
1543 u16 port = nv_ro16(bios, init->offset + 1);
1544 u8 mask = nv_ro16(bios, init->offset + 3);
1545 u8 data = nv_ro16(bios, init->offset + 4);
1546 u8 value;
1547
1548 trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data);
1549 init->offset += 5;
1550
1551
1552
1553
1554
1555 if (nv_device(init->bios)->card_type >= NV_50 &&
1556 port == 0x03c3 && data == 0x01) {
1557 init_mask(init, 0x614100, 0xf0800000, 0x00800000);
1558 init_mask(init, 0x00e18c, 0x00020000, 0x00020000);
1559 init_mask(init, 0x614900, 0xf0800000, 0x00800000);
1560 init_mask(init, 0x000200, 0x40000000, 0x00000000);
1561 mdelay(10);
1562 init_mask(init, 0x00e18c, 0x00020000, 0x00000000);
1563 init_mask(init, 0x000200, 0x40000000, 0x40000000);
1564 init_wr32(init, 0x614100, 0x00800018);
1565 init_wr32(init, 0x614900, 0x00800018);
1566 mdelay(10);
1567 init_wr32(init, 0x614100, 0x10000018);
1568 init_wr32(init, 0x614900, 0x10000018);
1569 }
1570
1571 value = init_rdport(init, port) & mask;
1572 init_wrport(init, port, data | value);
1573}
1574
1575
1576
1577
1578
1579static void
1580init_sub(struct nvbios_init *init)
1581{
1582 struct nouveau_bios *bios = init->bios;
1583 u8 index = nv_ro08(bios, init->offset + 1);
1584 u16 addr, save;
1585
1586 trace("SUB\t0x%02x\n", index);
1587
1588 addr = init_script(bios, index);
1589 if (addr && init_exec(init)) {
1590 save = init->offset;
1591 init->offset = addr;
1592 if (nvbios_exec(init)) {
1593 error("error parsing sub-table\n");
1594 return;
1595 }
1596 init->offset = save;
1597 }
1598
1599 init->offset += 2;
1600}
1601
1602
1603
1604
1605
1606static void
1607init_ram_condition(struct nvbios_init *init)
1608{
1609 struct nouveau_bios *bios = init->bios;
1610 u8 mask = nv_ro08(bios, init->offset + 1);
1611 u8 value = nv_ro08(bios, init->offset + 2);
1612
1613 trace("RAM_CONDITION\t"
1614 "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value);
1615 init->offset += 3;
1616
1617 if ((init_rd32(init, 0x100000) & mask) != value)
1618 init_exec_set(init, false);
1619}
1620
1621
1622
1623
1624
1625static void
1626init_nv_reg(struct nvbios_init *init)
1627{
1628 struct nouveau_bios *bios = init->bios;
1629 u32 reg = nv_ro32(bios, init->offset + 1);
1630 u32 mask = nv_ro32(bios, init->offset + 5);
1631 u32 data = nv_ro32(bios, init->offset + 9);
1632
1633 trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data);
1634 init->offset += 13;
1635
1636 init_mask(init, reg, ~mask, data);
1637}
1638
1639
1640
1641
1642
1643static void
1644init_macro(struct nvbios_init *init)
1645{
1646 struct nouveau_bios *bios = init->bios;
1647 u8 macro = nv_ro08(bios, init->offset + 1);
1648 u16 table;
1649
1650 trace("MACRO\t0x%02x\n", macro);
1651
1652 table = init_macro_table(init);
1653 if (table) {
1654 u32 addr = nv_ro32(bios, table + (macro * 8) + 0);
1655 u32 data = nv_ro32(bios, table + (macro * 8) + 4);
1656 trace("\t\tR[0x%06x] = 0x%08x\n", addr, data);
1657 init_wr32(init, addr, data);
1658 }
1659
1660 init->offset += 2;
1661}
1662
1663
1664
1665
1666
1667static void
1668init_resume(struct nvbios_init *init)
1669{
1670 trace("RESUME\n");
1671 init->offset += 1;
1672 init_exec_set(init, true);
1673}
1674
1675
1676
1677
1678
1679static void
1680init_time(struct nvbios_init *init)
1681{
1682 struct nouveau_bios *bios = init->bios;
1683 u16 usec = nv_ro16(bios, init->offset + 1);
1684
1685 trace("TIME\t0x%04x\n", usec);
1686 init->offset += 3;
1687
1688 if (init_exec(init)) {
1689 if (usec < 1000)
1690 udelay(usec);
1691 else
1692 mdelay((usec + 900) / 1000);
1693 }
1694}
1695
1696
1697
1698
1699
1700static void
1701init_condition(struct nvbios_init *init)
1702{
1703 struct nouveau_bios *bios = init->bios;
1704 u8 cond = nv_ro08(bios, init->offset + 1);
1705
1706 trace("CONDITION\t0x%02x\n", cond);
1707 init->offset += 2;
1708
1709 if (!init_condition_met(init, cond))
1710 init_exec_set(init, false);
1711}
1712
1713
1714
1715
1716
1717static void
1718init_io_condition(struct nvbios_init *init)
1719{
1720 struct nouveau_bios *bios = init->bios;
1721 u8 cond = nv_ro08(bios, init->offset + 1);
1722
1723 trace("IO_CONDITION\t0x%02x\n", cond);
1724 init->offset += 2;
1725
1726 if (!init_io_condition_met(init, cond))
1727 init_exec_set(init, false);
1728}
1729
1730
1731
1732
1733
1734static void
1735init_index_io(struct nvbios_init *init)
1736{
1737 struct nouveau_bios *bios = init->bios;
1738 u16 port = nv_ro16(bios, init->offset + 1);
1739 u8 index = nv_ro16(bios, init->offset + 3);
1740 u8 mask = nv_ro08(bios, init->offset + 4);
1741 u8 data = nv_ro08(bios, init->offset + 5);
1742 u8 value;
1743
1744 trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n",
1745 port, index, mask, data);
1746 init->offset += 6;
1747
1748 value = init_rdvgai(init, port, index) & mask;
1749 init_wrvgai(init, port, index, data | value);
1750}
1751
1752
1753
1754
1755
1756static void
1757init_pll(struct nvbios_init *init)
1758{
1759 struct nouveau_bios *bios = init->bios;
1760 u32 reg = nv_ro32(bios, init->offset + 1);
1761 u32 freq = nv_ro16(bios, init->offset + 5) * 10;
1762
1763 trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
1764 init->offset += 7;
1765
1766 init_prog_pll(init, reg, freq);
1767}
1768
1769
1770
1771
1772
1773static void
1774init_zm_reg(struct nvbios_init *init)
1775{
1776 struct nouveau_bios *bios = init->bios;
1777 u32 addr = nv_ro32(bios, init->offset + 1);
1778 u32 data = nv_ro32(bios, init->offset + 5);
1779
1780 trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data);
1781 init->offset += 9;
1782
1783 if (addr == 0x000200)
1784 data |= 0x00000001;
1785
1786 init_wr32(init, addr, data);
1787}
1788
1789
1790
1791
1792
1793static void
1794init_ram_restrict_pll(struct nvbios_init *init)
1795{
1796 struct nouveau_bios *bios = init->bios;
1797 u8 type = nv_ro08(bios, init->offset + 1);
1798 u8 count = init_ram_restrict_group_count(init);
1799 u8 strap = init_ram_restrict(init);
1800 u8 cconf;
1801
1802 trace("RAM_RESTRICT_PLL\t0x%02x\n", type);
1803 init->offset += 2;
1804
1805 for (cconf = 0; cconf < count; cconf++) {
1806 u32 freq = nv_ro32(bios, init->offset);
1807
1808 if (cconf == strap) {
1809 trace("%dkHz *\n", freq);
1810 init_prog_pll(init, type, freq);
1811 } else {
1812 trace("%dkHz\n", freq);
1813 }
1814
1815 init->offset += 4;
1816 }
1817}
1818
1819
1820
1821
1822
1823static void
1824init_gpio(struct nvbios_init *init)
1825{
1826 struct nouveau_gpio *gpio = nouveau_gpio(init->bios);
1827
1828 trace("GPIO\n");
1829 init->offset += 1;
1830
1831 if (init_exec(init) && gpio && gpio->reset)
1832 gpio->reset(gpio, DCB_GPIO_UNUSED);
1833}
1834
1835
1836
1837
1838
1839static void
1840init_ram_restrict_zm_reg_group(struct nvbios_init *init)
1841{
1842 struct nouveau_bios *bios = init->bios;
1843 u32 addr = nv_ro32(bios, init->offset + 1);
1844 u8 incr = nv_ro08(bios, init->offset + 5);
1845 u8 num = nv_ro08(bios, init->offset + 6);
1846 u8 count = init_ram_restrict_group_count(init);
1847 u8 index = init_ram_restrict(init);
1848 u8 i, j;
1849
1850 trace("RAM_RESTRICT_ZM_REG_GROUP\t"
1851 "R[0x%08x] 0x%02x 0x%02x\n", addr, incr, num);
1852 init->offset += 7;
1853
1854 for (i = 0; i < num; i++) {
1855 trace("\tR[0x%06x] = {\n", addr);
1856 for (j = 0; j < count; j++) {
1857 u32 data = nv_ro32(bios, init->offset);
1858
1859 if (j == index) {
1860 trace("\t\t0x%08x *\n", data);
1861 init_wr32(init, addr, data);
1862 } else {
1863 trace("\t\t0x%08x\n", data);
1864 }
1865
1866 init->offset += 4;
1867 }
1868 trace("\t}\n");
1869 addr += incr;
1870 }
1871}
1872
1873
1874
1875
1876
1877static void
1878init_copy_zm_reg(struct nvbios_init *init)
1879{
1880 struct nouveau_bios *bios = init->bios;
1881 u32 sreg = nv_ro32(bios, init->offset + 1);
1882 u32 dreg = nv_ro32(bios, init->offset + 5);
1883
1884 trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", dreg, sreg);
1885 init->offset += 9;
1886
1887 init_wr32(init, dreg, init_rd32(init, sreg));
1888}
1889
1890
1891
1892
1893
1894static void
1895init_zm_reg_group(struct nvbios_init *init)
1896{
1897 struct nouveau_bios *bios = init->bios;
1898 u32 addr = nv_ro32(bios, init->offset + 1);
1899 u8 count = nv_ro08(bios, init->offset + 5);
1900
1901 trace("ZM_REG_GROUP\tR[0x%06x] =\n", addr);
1902 init->offset += 6;
1903
1904 while (count--) {
1905 u32 data = nv_ro32(bios, init->offset);
1906 trace("\t0x%08x\n", data);
1907 init_wr32(init, addr, data);
1908 init->offset += 4;
1909 }
1910}
1911
1912
1913
1914
1915
1916static void
1917init_xlat(struct nvbios_init *init)
1918{
1919 struct nouveau_bios *bios = init->bios;
1920 u32 saddr = nv_ro32(bios, init->offset + 1);
1921 u8 sshift = nv_ro08(bios, init->offset + 5);
1922 u8 smask = nv_ro08(bios, init->offset + 6);
1923 u8 index = nv_ro08(bios, init->offset + 7);
1924 u32 daddr = nv_ro32(bios, init->offset + 8);
1925 u32 dmask = nv_ro32(bios, init->offset + 12);
1926 u8 shift = nv_ro08(bios, init->offset + 16);
1927 u32 data;
1928
1929 trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= "
1930 "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n",
1931 daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>",
1932 (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift);
1933 init->offset += 17;
1934
1935 data = init_shift(init_rd32(init, saddr), sshift) & smask;
1936 data = init_xlat_(init, index, data) << shift;
1937 init_mask(init, daddr, ~dmask, data);
1938}
1939
1940
1941
1942
1943
1944static void
1945init_zm_mask_add(struct nvbios_init *init)
1946{
1947 struct nouveau_bios *bios = init->bios;
1948 u32 addr = nv_ro32(bios, init->offset + 1);
1949 u32 mask = nv_ro32(bios, init->offset + 5);
1950 u32 add = nv_ro32(bios, init->offset + 9);
1951 u32 data;
1952
1953 trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add);
1954 init->offset += 13;
1955
1956 data = init_rd32(init, addr);
1957 data = (data & mask) | ((data + add) & ~mask);
1958 init_wr32(init, addr, data);
1959}
1960
1961
1962
1963
1964
1965static void
1966init_auxch(struct nvbios_init *init)
1967{
1968 struct nouveau_bios *bios = init->bios;
1969 u32 addr = nv_ro32(bios, init->offset + 1);
1970 u8 count = nv_ro08(bios, init->offset + 5);
1971
1972 trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
1973 init->offset += 6;
1974
1975 while (count--) {
1976 u8 mask = nv_ro08(bios, init->offset + 0);
1977 u8 data = nv_ro08(bios, init->offset + 1);
1978 trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1979 mask = init_rdauxr(init, addr) & mask;
1980 init_wrauxr(init, addr, mask | data);
1981 init->offset += 2;
1982 }
1983}
1984
1985
1986
1987
1988
1989static void
1990init_zm_auxch(struct nvbios_init *init)
1991{
1992 struct nouveau_bios *bios = init->bios;
1993 u32 addr = nv_ro32(bios, init->offset + 1);
1994 u8 count = nv_ro08(bios, init->offset + 5);
1995
1996 trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
1997 init->offset += 6;
1998
1999 while (count--) {
2000 u8 data = nv_ro08(bios, init->offset + 0);
2001 trace("\tAUX[0x%08x] = 0x%02x\n", addr, data);
2002 init_wrauxr(init, addr, data);
2003 init->offset += 1;
2004 }
2005}
2006
2007
2008
2009
2010
2011static void
2012init_i2c_long_if(struct nvbios_init *init)
2013{
2014 struct nouveau_bios *bios = init->bios;
2015 u8 index = nv_ro08(bios, init->offset + 1);
2016 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
2017 u8 reglo = nv_ro08(bios, init->offset + 3);
2018 u8 reghi = nv_ro08(bios, init->offset + 4);
2019 u8 mask = nv_ro08(bios, init->offset + 5);
2020 u8 data = nv_ro08(bios, init->offset + 6);
2021 struct nouveau_i2c_port *port;
2022
2023 trace("I2C_LONG_IF\t"
2024 "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n",
2025 index, addr, reglo, reghi, mask, data);
2026 init->offset += 7;
2027
2028 port = init_i2c(init, index);
2029 if (port) {
2030 u8 i[2] = { reghi, reglo };
2031 u8 o[1] = {};
2032 struct i2c_msg msg[] = {
2033 { .addr = addr, .flags = 0, .len = 2, .buf = i },
2034 { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o }
2035 };
2036 int ret;
2037
2038 ret = i2c_transfer(&port->adapter, msg, 2);
2039 if (ret == 2 && ((o[0] & mask) == data))
2040 return;
2041 }
2042
2043 init_exec_set(init, false);
2044}
2045
2046
2047
2048
2049
2050static void
2051init_gpio_ne(struct nvbios_init *init)
2052{
2053 struct nouveau_bios *bios = init->bios;
2054 struct nouveau_gpio *gpio = nouveau_gpio(bios);
2055 struct dcb_gpio_func func;
2056 u8 count = nv_ro08(bios, init->offset + 1);
2057 u8 idx = 0, ver, len;
2058 u16 data, i;
2059
2060 trace("GPIO_NE\t");
2061 init->offset += 2;
2062
2063 for (i = init->offset; i < init->offset + count; i++)
2064 cont("0x%02x ", nv_ro08(bios, i));
2065 cont("\n");
2066
2067 while ((data = dcb_gpio_parse(bios, 0, idx++, &ver, &len, &func))) {
2068 if (func.func != DCB_GPIO_UNUSED) {
2069 for (i = init->offset; i < init->offset + count; i++) {
2070 if (func.func == nv_ro08(bios, i))
2071 break;
2072 }
2073
2074 trace("\tFUNC[0x%02x]", func.func);
2075 if (i == (init->offset + count)) {
2076 cont(" *");
2077 if (init_exec(init) && gpio && gpio->reset)
2078 gpio->reset(gpio, func.func);
2079 }
2080 cont("\n");
2081 }
2082 }
2083
2084 init->offset += count;
2085}
2086
2087static struct nvbios_init_opcode {
2088 void (*exec)(struct nvbios_init *);
2089} init_opcode[] = {
2090 [0x32] = { init_io_restrict_prog },
2091 [0x33] = { init_repeat },
2092 [0x34] = { init_io_restrict_pll },
2093 [0x36] = { init_end_repeat },
2094 [0x37] = { init_copy },
2095 [0x38] = { init_not },
2096 [0x39] = { init_io_flag_condition },
2097 [0x3a] = { init_dp_condition },
2098 [0x3b] = { init_io_mask_or },
2099 [0x3c] = { init_io_or },
2100 [0x49] = { init_idx_addr_latched },
2101 [0x4a] = { init_io_restrict_pll2 },
2102 [0x4b] = { init_pll2 },
2103 [0x4c] = { init_i2c_byte },
2104 [0x4d] = { init_zm_i2c_byte },
2105 [0x4e] = { init_zm_i2c },
2106 [0x4f] = { init_tmds },
2107 [0x50] = { init_zm_tmds_group },
2108 [0x51] = { init_cr_idx_adr_latch },
2109 [0x52] = { init_cr },
2110 [0x53] = { init_zm_cr },
2111 [0x54] = { init_zm_cr_group },
2112 [0x56] = { init_condition_time },
2113 [0x57] = { init_ltime },
2114 [0x58] = { init_zm_reg_sequence },
2115 [0x5b] = { init_sub_direct },
2116 [0x5c] = { init_jump },
2117 [0x5e] = { init_i2c_if },
2118 [0x5f] = { init_copy_nv_reg },
2119 [0x62] = { init_zm_index_io },
2120 [0x63] = { init_compute_mem },
2121 [0x65] = { init_reset },
2122 [0x66] = { init_configure_mem },
2123 [0x67] = { init_configure_clk },
2124 [0x68] = { init_configure_preinit },
2125 [0x69] = { init_io },
2126 [0x6b] = { init_sub },
2127 [0x6d] = { init_ram_condition },
2128 [0x6e] = { init_nv_reg },
2129 [0x6f] = { init_macro },
2130 [0x71] = { init_done },
2131 [0x72] = { init_resume },
2132 [0x74] = { init_time },
2133 [0x75] = { init_condition },
2134 [0x76] = { init_io_condition },
2135 [0x78] = { init_index_io },
2136 [0x79] = { init_pll },
2137 [0x7a] = { init_zm_reg },
2138 [0x87] = { init_ram_restrict_pll },
2139 [0x8c] = { init_reserved },
2140 [0x8d] = { init_reserved },
2141 [0x8e] = { init_gpio },
2142 [0x8f] = { init_ram_restrict_zm_reg_group },
2143 [0x90] = { init_copy_zm_reg },
2144 [0x91] = { init_zm_reg_group },
2145 [0x92] = { init_reserved },
2146 [0x96] = { init_xlat },
2147 [0x97] = { init_zm_mask_add },
2148 [0x98] = { init_auxch },
2149 [0x99] = { init_zm_auxch },
2150 [0x9a] = { init_i2c_long_if },
2151 [0xa9] = { init_gpio_ne },
2152 [0xaa] = { init_reserved },
2153};
2154
2155#define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0]))
2156
2157int
2158nvbios_exec(struct nvbios_init *init)
2159{
2160 init->nested++;
2161 while (init->offset) {
2162 u8 opcode = nv_ro08(init->bios, init->offset);
2163 if (opcode >= init_opcode_nr || !init_opcode[opcode].exec) {
2164 error("unknown opcode 0x%02x\n", opcode);
2165 return -EINVAL;
2166 }
2167
2168 init_opcode[opcode].exec(init);
2169 }
2170 init->nested--;
2171 return 0;
2172}
2173
2174int
2175nvbios_init(struct nouveau_subdev *subdev, bool execute)
2176{
2177 struct nouveau_bios *bios = nouveau_bios(subdev);
2178 int ret = 0;
2179 int i = -1;
2180 u16 data;
2181
2182 if (execute)
2183 nv_suspend(bios, "running init tables\n");
2184 while (!ret && (data = (init_script(bios, ++i)))) {
2185 struct nvbios_init init = {
2186 .subdev = subdev,
2187 .bios = bios,
2188 .offset = data,
2189 .outp = NULL,
2190 .crtc = -1,
2191 .execute = execute ? 1 : 0,
2192 };
2193
2194 ret = nvbios_exec(&init);
2195 }
2196
2197
2198
2199
2200 if (!ret && (data = init_unknown_script(bios))) {
2201 struct nvbios_init init = {
2202 .subdev = subdev,
2203 .bios = bios,
2204 .offset = data,
2205 .outp = NULL,
2206 .crtc = -1,
2207 .execute = execute ? 1 : 0,
2208 };
2209
2210 ret = nvbios_exec(&init);
2211 }
2212
2213 return 0;
2214}
2215
