1/* 2 * Copyright 2006-2007 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 24/****************************************************************************/ 25/*Portion I: Definitions shared between VBIOS and Driver */ 26/****************************************************************************/ 27 28 29#ifndef _ATOMBIOS_H 30#define _ATOMBIOS_H 31 32#define ATOM_VERSION_MAJOR 0x00020000 33#define ATOM_VERSION_MINOR 0x00000002 34 35#define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR) 36 37/* Endianness should be specified before inclusion, 38 * default to little endian 39 */ 40#ifndef ATOM_BIG_ENDIAN 41#error Endian not specified 42#endif 43 44#ifdef _H2INC 45 #ifndef ULONG 46 typedef unsigned long ULONG; 47 #endif 48 49 #ifndef UCHAR 50 typedef unsigned char UCHAR; 51 #endif 52 53 #ifndef USHORT 54 typedef unsigned short USHORT; 55 #endif 56#endif 57 58#define ATOM_DAC_A 0 59#define ATOM_DAC_B 1 60#define ATOM_EXT_DAC 2 61 62#define ATOM_CRTC1 0 63#define ATOM_CRTC2 1 64#define ATOM_CRTC3 2 65#define ATOM_CRTC4 3 66#define ATOM_CRTC5 4 67#define ATOM_CRTC6 5 68#define ATOM_CRTC_INVALID 0xFF 69 70#define ATOM_DIGA 0 71#define ATOM_DIGB 1 72 73#define ATOM_PPLL1 0 74#define ATOM_PPLL2 1 75#define ATOM_DCPLL 2 76#define ATOM_PPLL0 2 77#define ATOM_PPLL3 3 78 79#define ATOM_EXT_PLL1 8 80#define ATOM_EXT_PLL2 9 81#define ATOM_EXT_CLOCK 10 82#define ATOM_PPLL_INVALID 0xFF 83 84#define ENCODER_REFCLK_SRC_P1PLL 0 85#define ENCODER_REFCLK_SRC_P2PLL 1 86#define ENCODER_REFCLK_SRC_DCPLL 2 87#define ENCODER_REFCLK_SRC_EXTCLK 3 88#define ENCODER_REFCLK_SRC_INVALID 0xFF 89 90#define ATOM_SCALER1 0 91#define ATOM_SCALER2 1 92 93#define ATOM_SCALER_DISABLE 0 94#define ATOM_SCALER_CENTER 1 95#define ATOM_SCALER_EXPANSION 2 96#define ATOM_SCALER_MULTI_EX 3 97 98#define ATOM_DISABLE 0 99#define ATOM_ENABLE 1 100#define ATOM_LCD_BLOFF (ATOM_DISABLE+2) 101#define ATOM_LCD_BLON (ATOM_ENABLE+2) 102#define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3) 103#define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5) 104#define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5) 105#define ATOM_ENCODER_INIT (ATOM_DISABLE+7) 106#define ATOM_INIT (ATOM_DISABLE+7) 107#define ATOM_GET_STATUS (ATOM_DISABLE+8) 108 109#define ATOM_BLANKING 1 110#define ATOM_BLANKING_OFF 0 111 112#define ATOM_CURSOR1 0 113#define ATOM_CURSOR2 1 114 115#define ATOM_ICON1 0 116#define ATOM_ICON2 1 117 118#define ATOM_CRT1 0 119#define ATOM_CRT2 1 120 121#define ATOM_TV_NTSC 1 122#define ATOM_TV_NTSCJ 2 123#define ATOM_TV_PAL 3 124#define ATOM_TV_PALM 4 125#define ATOM_TV_PALCN 5 126#define ATOM_TV_PALN 6 127#define ATOM_TV_PAL60 7 128#define ATOM_TV_SECAM 8 129#define ATOM_TV_CV 16 130 131#define ATOM_DAC1_PS2 1 132#define ATOM_DAC1_CV 2 133#define ATOM_DAC1_NTSC 3 134#define ATOM_DAC1_PAL 4 135 136#define ATOM_DAC2_PS2 ATOM_DAC1_PS2 137#define ATOM_DAC2_CV ATOM_DAC1_CV 138#define ATOM_DAC2_NTSC ATOM_DAC1_NTSC 139#define ATOM_DAC2_PAL ATOM_DAC1_PAL 140 141#define ATOM_PM_ON 0 142#define ATOM_PM_STANDBY 1 143#define ATOM_PM_SUSPEND 2 144#define ATOM_PM_OFF 3 145 146/* Bit0:{=0:single, =1:dual}, 147 Bit1 {=0:666RGB, =1:888RGB}, 148 Bit2:3:{Grey level} 149 Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/ 150 151#define ATOM_PANEL_MISC_DUAL 0x00000001 152#define ATOM_PANEL_MISC_888RGB 0x00000002 153#define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C 154#define ATOM_PANEL_MISC_FPDI 0x00000010 155#define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2 156#define ATOM_PANEL_MISC_SPATIAL 0x00000020 157#define ATOM_PANEL_MISC_TEMPORAL 0x00000040 158#define ATOM_PANEL_MISC_API_ENABLED 0x00000080 159 160 161#define MEMTYPE_DDR1 "DDR1" 162#define MEMTYPE_DDR2 "DDR2" 163#define MEMTYPE_DDR3 "DDR3" 164#define MEMTYPE_DDR4 "DDR4" 165 166#define ASIC_BUS_TYPE_PCI "PCI" 167#define ASIC_BUS_TYPE_AGP "AGP" 168#define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS" 169 170/* Maximum size of that FireGL flag string */ 171 172#define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support 173#define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING ) 174 175#define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop 176#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 177 178#define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support 179#define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING ) 180 181#define HW_ASSISTED_I2C_STATUS_FAILURE 2 182#define HW_ASSISTED_I2C_STATUS_SUCCESS 1 183 184#pragma pack(1) /* BIOS data must use byte aligment */ 185 186/* Define offset to location of ROM header. */ 187 188#define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L 189#define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L 190 191#define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94 192#define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 /* including the terminator 0x0! */ 193#define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f 194#define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e 195 196/* Common header for all ROM Data tables. 197 Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. 198 And the pointer actually points to this header. */ 199 200typedef struct _ATOM_COMMON_TABLE_HEADER 201{ 202 USHORT usStructureSize; 203 UCHAR ucTableFormatRevision; /*Change it when the Parser is not backward compatible */ 204 UCHAR ucTableContentRevision; /*Change it only when the table needs to change but the firmware */ 205 /*Image can't be updated, while Driver needs to carry the new table! */ 206}ATOM_COMMON_TABLE_HEADER; 207 208/****************************************************************************/ 209// Structure stores the ROM header. 210/****************************************************************************/ 211typedef struct _ATOM_ROM_HEADER 212{ 213 ATOM_COMMON_TABLE_HEADER sHeader; 214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios, 215 atombios should init it as "ATOM", don't change the position */ 216 USHORT usBiosRuntimeSegmentAddress; 217 USHORT usProtectedModeInfoOffset; 218 USHORT usConfigFilenameOffset; 219 USHORT usCRC_BlockOffset; 220 USHORT usBIOS_BootupMessageOffset; 221 USHORT usInt10Offset; 222 USHORT usPciBusDevInitCode; 223 USHORT usIoBaseAddress; 224 USHORT usSubsystemVendorID; 225 USHORT usSubsystemID; 226 USHORT usPCI_InfoOffset; 227 USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */ 228 USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */ 229 UCHAR ucExtendedFunctionCode; 230 UCHAR ucReserved; 231}ATOM_ROM_HEADER; 232 233/*==============================Command Table Portion==================================== */ 234 235#ifdef UEFI_BUILD 236 #define UTEMP USHORT 237 #define USHORT void* 238#endif 239 240/****************************************************************************/ 241// Structures used in Command.mtb 242/****************************************************************************/ 243typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ 244 USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1 245 USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON 246 USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 247 USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios 248 USHORT DIGxEncoderControl; //Only used by Bios 249 USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 250 USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1 251 USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed 252 USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2 253 USHORT GPIOPinControl; //Atomic Table, only used by Bios 254 USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1 255 USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1 256 USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2 257 USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 258 USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 259 USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 260 USHORT MemoryPLLInit; //Atomic Table, used only by Bios 261 USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes. 262 USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 263 USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios 264 USHORT SetUniphyInstance; //Atomic Table, only used by Bios 265 USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2 266 USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3 267 USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW components,latest version 1.1 268 USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 269 USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 270 USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 271 USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead 272 USHORT GetConditionalGoldenSetting; //Only used by Bios 273 USHORT TVEncoderControl; //Function Table,directly used by various SW components,latest version 1.1 274 USHORT PatchMCSetting; //only used by BIOS 275 USHORT MC_SEQ_Control; //only used by BIOS 276 USHORT Gfx_Harvesting; //Atomic Table, Obsolete from Ry6xx, Now only used by BIOS for GFX harvesting 277 USHORT EnableScaler; //Atomic Table, used only by Bios 278 USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 279 USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 280 USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1 281 USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1 282 USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios 283 USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1 284 USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1 285 USHORT SetCRTC_Replication; //Atomic Table, used only by Bios 286 USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1 287 USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios 288 USHORT UpdateCRTC_DoubleBufferRegisters; //Atomic Table, used only by Bios 289 USHORT LUT_AutoFill; //Atomic Table, only used by Bios 290 USHORT EnableHW_IconCursor; //Atomic Table, only used by Bios 291 USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1 292 USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1 293 USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1 294 USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1 295 USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 296 USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios 297 USHORT MemoryCleanUp; //Atomic Table, only used by Bios 298 USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios 299 USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components 300 USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components 301 USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init 302 USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1 303 USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 304 USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock 305 USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock 306 USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios 307 USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 308 USHORT MemoryTraining; //Atomic Table, used only by Bios 309 USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2 310 USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 311 USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1 312 USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 313 USHORT DAC2OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 314 USHORT ComputeMemoryClockParam; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C" 315 USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 316 USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 317 USHORT GetDispObjectInfo; //Atomic Table, indirectly used by various SW components,called from EnableVGARender 318 USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 319 USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 320 USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 321 USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 322 USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios 323 USHORT DPEncoderService; //Function Table,only used by Bios 324 USHORT GetVoltageInfo; //Function Table,only used by Bios since SI 325}ATOM_MASTER_LIST_OF_COMMAND_TABLES; 326 327// For backward compatible 328#define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction 329#define DPTranslatorControl DIG2EncoderControl 330#define UNIPHYTransmitterControl DIG1TransmitterControl 331#define LVTMATransmitterControl DIG2TransmitterControl 332#define SetCRTC_DPM_State GetConditionalGoldenSetting 333#define ASIC_StaticPwrMgtStatusChange SetUniphyInstance 334#define HPDInterruptService ReadHWAssistedI2CStatus 335#define EnableVGA_Access GetSCLKOverMCLKRatio 336#define EnableYUV GetDispObjectInfo 337#define DynamicClockGating EnableDispPowerGating 338#define SetupHWAssistedI2CStatus ComputeMemoryClockParam 339 340#define TMDSAEncoderControl PatchMCSetting 341#define LVDSEncoderControl MC_SEQ_Control 342#define LCD1OutputControl HW_Misc_Operation 343#define TV1OutputControl Gfx_Harvesting 344 345typedef struct _ATOM_MASTER_COMMAND_TABLE 346{ 347 ATOM_COMMON_TABLE_HEADER sHeader; 348 ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables; 349}ATOM_MASTER_COMMAND_TABLE; 350 351/****************************************************************************/ 352// Structures used in every command table 353/****************************************************************************/ 354typedef struct _ATOM_TABLE_ATTRIBUTE 355{ 356#if ATOM_BIG_ENDIAN 357 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag 358 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 359 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 360#else 361 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 362 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 363 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag 364#endif 365}ATOM_TABLE_ATTRIBUTE; 366 367typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS 368{ 369 ATOM_TABLE_ATTRIBUTE sbfAccess; 370 USHORT susAccess; 371}ATOM_TABLE_ATTRIBUTE_ACCESS; 372 373/****************************************************************************/ 374// Common header for all command tables. 375// Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. 376// And the pointer actually points to this header. 377/****************************************************************************/ 378typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER 379{ 380 ATOM_COMMON_TABLE_HEADER CommonHeader; 381 ATOM_TABLE_ATTRIBUTE TableAttribute; 382}ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; 383 384/****************************************************************************/ 385// Structures used by ComputeMemoryEnginePLLTable 386/****************************************************************************/ 387#define COMPUTE_MEMORY_PLL_PARAM 1 388#define COMPUTE_ENGINE_PLL_PARAM 2 389#define ADJUST_MC_SETTING_PARAM 3 390 391/****************************************************************************/ 392// Structures used by AdjustMemoryControllerTable 393/****************************************************************************/ 394typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ 395{ 396#if ATOM_BIG_ENDIAN 397 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block 398 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] 399 ULONG ulClockFreq:24; 400#else 401 ULONG ulClockFreq:24; 402 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] 403 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block 404#endif 405}ATOM_ADJUST_MEMORY_CLOCK_FREQ; 406#define POINTER_RETURN_FLAG 0x80 407 408typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS 409{ 410 ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div 411 UCHAR ucAction; //0:reserved //1:Memory //2:Engine 412 UCHAR ucReserved; //may expand to return larger Fbdiv later 413 UCHAR ucFbDiv; //return value 414 UCHAR ucPostDiv; //return value 415}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS; 416 417typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 418{ 419 ULONG ulClock; //When return, [23:0] return real clock 420 UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register 421 USHORT usFbDiv; //return Feedback value to be written to register 422 UCHAR ucPostDiv; //return post div to be written to register 423}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2; 424#define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS 425 426 427#define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value 428#define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) 429#define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition 430#define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change 431#define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup 432#define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL 433#define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK 434 435#define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) 436#define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition 437#define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change 438#define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup 439#define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL 440 441typedef struct _ATOM_COMPUTE_CLOCK_FREQ 442{ 443#if ATOM_BIG_ENDIAN 444 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM 445 ULONG ulClockFreq:24; // in unit of 10kHz 446#else 447 ULONG ulClockFreq:24; // in unit of 10kHz 448 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM 449#endif 450}ATOM_COMPUTE_CLOCK_FREQ; 451 452typedef struct _ATOM_S_MPLL_FB_DIVIDER 453{ 454 USHORT usFbDivFrac; 455 USHORT usFbDiv; 456}ATOM_S_MPLL_FB_DIVIDER; 457 458typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 459{ 460 union 461 { 462 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 463 ULONG ulClockParams; //ULONG access for BE 464 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter 465 }; 466 UCHAR ucRefDiv; //Output Parameter 467 UCHAR ucPostDiv; //Output Parameter 468 UCHAR ucCntlFlag; //Output Parameter 469 UCHAR ucReserved; 470}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3; 471 472// ucCntlFlag 473#define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1 474#define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2 475#define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4 476#define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8 477 478 479// V4 are only used for APU which PLL outside GPU 480typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 481{ 482#if ATOM_BIG_ENDIAN 483 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly 484 ULONG ulClock:24; //Input= target clock, output = actual clock 485#else 486 ULONG ulClock:24; //Input= target clock, output = actual clock 487 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly 488#endif 489}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4; 490 491typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 492{ 493 union 494 { 495 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 496 ULONG ulClockParams; //ULONG access for BE 497 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter 498 }; 499 UCHAR ucRefDiv; //Output Parameter 500 UCHAR ucPostDiv; //Output Parameter 501 union 502 { 503 UCHAR ucCntlFlag; //Output Flags 504 UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode 505 }; 506 UCHAR ucReserved; 507}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5; 508 509 510typedef struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 511{ 512 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 513 ULONG ulReserved[2]; 514}COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6; 515 516//ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag 517#define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK 0x0f 518#define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK 0x00 519#define COMPUTE_GPUCLK_INPUT_FLAG_SCLK 0x01 520 521typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 522{ 523 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider 524 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter: PLL FB divider 525 UCHAR ucPllRefDiv; //Output Parameter: PLL ref divider 526 UCHAR ucPllPostDiv; //Output Parameter: PLL post divider 527 UCHAR ucPllCntlFlag; //Output Flags: control flag 528 UCHAR ucReserved; 529}COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6; 530 531//ucPllCntlFlag 532#define SPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 533 534 535// ucInputFlag 536#define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode 537 538// use for ComputeMemoryClockParamTable 539typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 540{ 541 union 542 { 543 ULONG ulClock; 544 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS) 545 }; 546 UCHAR ucDllSpeed; //Output 547 UCHAR ucPostDiv; //Output 548 union{ 549 UCHAR ucInputFlag; //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode 550 UCHAR ucPllCntlFlag; //Output: 551 }; 552 UCHAR ucBWCntl; 553}COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1; 554 555// definition of ucInputFlag 556#define MPLL_INPUT_FLAG_STROBE_MODE_EN 0x01 557// definition of ucPllCntlFlag 558#define MPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 559#define MPLL_CNTL_FLAG_BYPASS_DQ_PLL 0x04 560#define MPLL_CNTL_FLAG_QDR_ENABLE 0x08 561#define MPLL_CNTL_FLAG_AD_HALF_RATE 0x10 562 563//MPLL_CNTL_FLAG_BYPASS_AD_PLL has a wrong name, should be BYPASS_DQ_PLL 564#define MPLL_CNTL_FLAG_BYPASS_AD_PLL 0x04 565 566typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER 567{ 568 ATOM_COMPUTE_CLOCK_FREQ ulClock; 569 ULONG ulReserved[2]; 570}DYNAMICE_MEMORY_SETTINGS_PARAMETER; 571 572typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER 573{ 574 ATOM_COMPUTE_CLOCK_FREQ ulClock; 575 ULONG ulMemoryClock; 576 ULONG ulReserved; 577}DYNAMICE_ENGINE_SETTINGS_PARAMETER; 578 579/****************************************************************************/ 580// Structures used by SetEngineClockTable 581/****************************************************************************/ 582typedef struct _SET_ENGINE_CLOCK_PARAMETERS 583{ 584 ULONG ulTargetEngineClock; //In 10Khz unit 585}SET_ENGINE_CLOCK_PARAMETERS; 586 587typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION 588{ 589 ULONG ulTargetEngineClock; //In 10Khz unit 590 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; 591}SET_ENGINE_CLOCK_PS_ALLOCATION; 592 593/****************************************************************************/ 594// Structures used by SetMemoryClockTable 595/****************************************************************************/ 596typedef struct _SET_MEMORY_CLOCK_PARAMETERS 597{ 598 ULONG ulTargetMemoryClock; //In 10Khz unit 599}SET_MEMORY_CLOCK_PARAMETERS; 600 601typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION 602{ 603 ULONG ulTargetMemoryClock; //In 10Khz unit 604 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; 605}SET_MEMORY_CLOCK_PS_ALLOCATION; 606 607/****************************************************************************/ 608// Structures used by ASIC_Init.ctb 609/****************************************************************************/ 610typedef struct _ASIC_INIT_PARAMETERS 611{ 612 ULONG ulDefaultEngineClock; //In 10Khz unit 613 ULONG ulDefaultMemoryClock; //In 10Khz unit 614}ASIC_INIT_PARAMETERS; 615 616typedef struct _ASIC_INIT_PS_ALLOCATION 617{ 618 ASIC_INIT_PARAMETERS sASICInitClocks; 619 SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure 620}ASIC_INIT_PS_ALLOCATION; 621 622/****************************************************************************/ 623// Structure used by DynamicClockGatingTable.ctb 624/****************************************************************************/ 625typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS 626{ 627 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 628 UCHAR ucPadding[3]; 629}DYNAMIC_CLOCK_GATING_PARAMETERS; 630#define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS 631 632/****************************************************************************/ 633// Structure used by EnableDispPowerGatingTable.ctb 634/****************************************************************************/ 635typedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 636{ 637 UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ... 638 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 639 UCHAR ucPadding[2]; 640}ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1; 641 642/****************************************************************************/ 643// Structure used by EnableASIC_StaticPwrMgtTable.ctb 644/****************************************************************************/ 645typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS 646{ 647 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 648 UCHAR ucPadding[3]; 649}ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS; 650#define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS 651 652/****************************************************************************/ 653// Structures used by DAC_LoadDetectionTable.ctb 654/****************************************************************************/ 655typedef struct _DAC_LOAD_DETECTION_PARAMETERS 656{ 657 USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT} 658 UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC} 659 UCHAR ucMisc; //Valid only when table revision =1.3 and above 660}DAC_LOAD_DETECTION_PARAMETERS; 661 662// DAC_LOAD_DETECTION_PARAMETERS.ucMisc 663#define DAC_LOAD_MISC_YPrPb 0x01 664 665typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION 666{ 667 DAC_LOAD_DETECTION_PARAMETERS sDacload; 668 ULONG Reserved[2];// Don't set this one, allocation for EXT DAC 669}DAC_LOAD_DETECTION_PS_ALLOCATION; 670 671/****************************************************************************/ 672// Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb 673/****************************************************************************/ 674typedef struct _DAC_ENCODER_CONTROL_PARAMETERS 675{ 676 USHORT usPixelClock; // in 10KHz; for bios convenient 677 UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0) 678 UCHAR ucAction; // 0: turn off encoder 679 // 1: setup and turn on encoder 680 // 7: ATOM_ENCODER_INIT Initialize DAC 681}DAC_ENCODER_CONTROL_PARAMETERS; 682 683#define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS 684 685/****************************************************************************/ 686// Structures used by DIG1EncoderControlTable 687// DIG2EncoderControlTable 688// ExternalEncoderControlTable 689/****************************************************************************/ 690typedef struct _DIG_ENCODER_CONTROL_PARAMETERS 691{ 692 USHORT usPixelClock; // in 10KHz; for bios convenient 693 UCHAR ucConfig; 694 // [2] Link Select: 695 // =0: PHY linkA if bfLane<3 696 // =1: PHY linkB if bfLanes<3 697 // =0: PHY linkA+B if bfLanes=3 698 // [3] Transmitter Sel 699 // =0: UNIPHY or PCIEPHY 700 // =1: LVTMA 701 UCHAR ucAction; // =0: turn off encoder 702 // =1: turn on encoder 703 UCHAR ucEncoderMode; 704 // =0: DP encoder 705 // =1: LVDS encoder 706 // =2: DVI encoder 707 // =3: HDMI encoder 708 // =4: SDVO encoder 709 UCHAR ucLaneNum; // how many lanes to enable 710 UCHAR ucReserved[2]; 711}DIG_ENCODER_CONTROL_PARAMETERS; 712#define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS 713#define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS 714 715//ucConfig 716#define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01 717#define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00 718#define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01 719#define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ 0x02 720#define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04 721#define ATOM_ENCODER_CONFIG_LINKA 0x00 722#define ATOM_ENCODER_CONFIG_LINKB 0x04 723#define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA 724#define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB 725#define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08 726#define ATOM_ENCODER_CONFIG_UNIPHY 0x00 727#define ATOM_ENCODER_CONFIG_LVTMA 0x08 728#define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00 729#define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08 730#define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0 731// ucAction 732// ATOM_ENABLE: Enable Encoder 733// ATOM_DISABLE: Disable Encoder 734 735//ucEncoderMode 736#define ATOM_ENCODER_MODE_DP 0 737#define ATOM_ENCODER_MODE_LVDS 1 738#define ATOM_ENCODER_MODE_DVI 2 739#define ATOM_ENCODER_MODE_HDMI 3 740#define ATOM_ENCODER_MODE_SDVO 4 741#define ATOM_ENCODER_MODE_DP_AUDIO 5 742#define ATOM_ENCODER_MODE_TV 13 743#define ATOM_ENCODER_MODE_CV 14 744#define ATOM_ENCODER_MODE_CRT 15 745#define ATOM_ENCODER_MODE_DVO 16 746#define ATOM_ENCODER_MODE_DP_SST ATOM_ENCODER_MODE_DP // For DP1.2 747#define ATOM_ENCODER_MODE_DP_MST 5 // For DP1.2 748 749typedef struct _ATOM_DIG_ENCODER_CONFIG_V2 750{ 751#if ATOM_BIG_ENDIAN 752 UCHAR ucReserved1:2; 753 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF 754 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F 755 UCHAR ucReserved:1; 756 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 757#else 758 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 759 UCHAR ucReserved:1; 760 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F 761 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF 762 UCHAR ucReserved1:2; 763#endif 764}ATOM_DIG_ENCODER_CONFIG_V2; 765 766 767typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 768{ 769 USHORT usPixelClock; // in 10KHz; for bios convenient 770 ATOM_DIG_ENCODER_CONFIG_V2 acConfig; 771 UCHAR ucAction; 772 UCHAR ucEncoderMode; 773 // =0: DP encoder 774 // =1: LVDS encoder 775 // =2: DVI encoder 776 // =3: HDMI encoder 777 // =4: SDVO encoder 778 UCHAR ucLaneNum; // how many lanes to enable 779 UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 780 UCHAR ucReserved; 781}DIG_ENCODER_CONTROL_PARAMETERS_V2; 782 783//ucConfig 784#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01 785#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00 786#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01 787#define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK 0x04 788#define ATOM_ENCODER_CONFIG_V2_LINKA 0x00 789#define ATOM_ENCODER_CONFIG_V2_LINKB 0x04 790#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK 0x18 791#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 0x00 792#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08 793#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10 794 795// ucAction: 796// ATOM_DISABLE 797// ATOM_ENABLE 798#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08 799#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09 800#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a 801#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 0x13 802#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b 803#define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c 804#define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d 805#define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e 806#define ATOM_ENCODER_CMD_SETUP 0x0f 807#define ATOM_ENCODER_CMD_SETUP_PANEL_MODE 0x10 808 809// ucStatus 810#define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10 811#define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00 812 813//ucTableFormatRevision=1 814//ucTableContentRevision=3 815// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver 816typedef struct _ATOM_DIG_ENCODER_CONFIG_V3 817{ 818#if ATOM_BIG_ENDIAN 819 UCHAR ucReserved1:1; 820 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 821 UCHAR ucReserved:3; 822 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 823#else 824 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 825 UCHAR ucReserved:3; 826 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 827 UCHAR ucReserved1:1; 828#endif 829}ATOM_DIG_ENCODER_CONFIG_V3; 830 831#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 832#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 833#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 834#define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70 835#define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER 0x00 836#define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER 0x10 837#define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER 0x20 838#define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER 0x30 839#define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER 0x40 840#define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER 0x50 841 842typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3 843{ 844 USHORT usPixelClock; // in 10KHz; for bios convenient 845 ATOM_DIG_ENCODER_CONFIG_V3 acConfig; 846 UCHAR ucAction; 847 union { 848 UCHAR ucEncoderMode; 849 // =0: DP encoder 850 // =1: LVDS encoder 851 // =2: DVI encoder 852 // =3: HDMI encoder 853 // =4: SDVO encoder 854 // =5: DP audio 855 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE 856 // =0: external DP 857 // =1: internal DP2 858 // =0x11: internal DP1 for NutMeg/Travis DP translator 859 }; 860 UCHAR ucLaneNum; // how many lanes to enable 861 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP 862 UCHAR ucReserved; 863}DIG_ENCODER_CONTROL_PARAMETERS_V3; 864 865//ucTableFormatRevision=1 866//ucTableContentRevision=4 867// start from NI 868// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver 869typedef struct _ATOM_DIG_ENCODER_CONFIG_V4 870{ 871#if ATOM_BIG_ENDIAN 872 UCHAR ucReserved1:1; 873 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 874 UCHAR ucReserved:2; 875 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version 876#else 877 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version 878 UCHAR ucReserved:2; 879 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 880 UCHAR ucReserved1:1; 881#endif 882}ATOM_DIG_ENCODER_CONFIG_V4; 883 884#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK 0x03 885#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ 0x00 886#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ 0x01 887#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ 0x02 888#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ 0x03 889#define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL 0x70 890#define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER 0x00 891#define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER 0x10 892#define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER 0x20 893#define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER 0x30 894#define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER 0x40 895#define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER 0x50 896#define ATOM_ENCODER_CONFIG_V4_DIG6_ENCODER 0x60 897 898typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4 899{ 900 USHORT usPixelClock; // in 10KHz; for bios convenient 901 union{ 902 ATOM_DIG_ENCODER_CONFIG_V4 acConfig; 903 UCHAR ucConfig; 904 }; 905 UCHAR ucAction; 906 union { 907 UCHAR ucEncoderMode; 908 // =0: DP encoder 909 // =1: LVDS encoder 910 // =2: DVI encoder 911 // =3: HDMI encoder 912 // =4: SDVO encoder 913 // =5: DP audio 914 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE 915 // =0: external DP 916 // =1: internal DP2 917 // =0x11: internal DP1 for NutMeg/Travis DP translator 918 }; 919 UCHAR ucLaneNum; // how many lanes to enable 920 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP 921 UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version 922}DIG_ENCODER_CONTROL_PARAMETERS_V4; 923 924// define ucBitPerColor: 925#define PANEL_BPC_UNDEFINE 0x00 926#define PANEL_6BIT_PER_COLOR 0x01 927#define PANEL_8BIT_PER_COLOR 0x02 928#define PANEL_10BIT_PER_COLOR 0x03 929#define PANEL_12BIT_PER_COLOR 0x04 930#define PANEL_16BIT_PER_COLOR 0x05 931 932//define ucPanelMode 933#define DP_PANEL_MODE_EXTERNAL_DP_MODE 0x00 934#define DP_PANEL_MODE_INTERNAL_DP2_MODE 0x01 935#define DP_PANEL_MODE_INTERNAL_DP1_MODE 0x11 936 937/****************************************************************************/ 938// Structures used by UNIPHYTransmitterControlTable 939// LVTMATransmitterControlTable 940// DVOOutputControlTable 941/****************************************************************************/ 942typedef struct _ATOM_DP_VS_MODE 943{ 944 UCHAR ucLaneSel; 945 UCHAR ucLaneSet; 946}ATOM_DP_VS_MODE; 947 948typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS 949{ 950 union 951 { 952 USHORT usPixelClock; // in 10KHz; for bios convenient 953 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 954 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 955 }; 956 UCHAR ucConfig; 957 // [0]=0: 4 lane Link, 958 // =1: 8 lane Link ( Dual Links TMDS ) 959 // [1]=0: InCoherent mode 960 // =1: Coherent Mode 961 // [2] Link Select: 962 // =0: PHY linkA if bfLane<3 963 // =1: PHY linkB if bfLanes<3 964 // =0: PHY linkA+B if bfLanes=3 965 // [5:4]PCIE lane Sel 966 // =0: lane 0~3 or 0~7 967 // =1: lane 4~7 968 // =2: lane 8~11 or 8~15 969 // =3: lane 12~15 970 UCHAR ucAction; // =0: turn off encoder 971 // =1: turn on encoder 972 UCHAR ucReserved[4]; 973}DIG_TRANSMITTER_CONTROL_PARAMETERS; 974 975#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS 976 977//ucInitInfo 978#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff 979 980//ucConfig 981#define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01 982#define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02 983#define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04 984#define ATOM_TRANSMITTER_CONFIG_LINKA 0x00 985#define ATOM_TRANSMITTER_CONFIG_LINKB 0x04 986#define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00 987#define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04 988 989#define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 990#define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 991#define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 992 993#define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30 994#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00 995#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20 996#define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30 997#define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0 998#define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00 999#define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00 1000#define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40
1001#define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80 1002#define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80 1003#define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0 1004 1005//ucAction 1006#define ATOM_TRANSMITTER_ACTION_DISABLE 0 1007#define ATOM_TRANSMITTER_ACTION_ENABLE 1 1008#define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2 1009#define ATOM_TRANSMITTER_ACTION_LCD_BLON 3 1010#define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4 1011#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5 1012#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6 1013#define ATOM_TRANSMITTER_ACTION_INIT 7 1014#define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8 1015#define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9 1016#define ATOM_TRANSMITTER_ACTION_SETUP 10 1017#define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11 1018#define ATOM_TRANSMITTER_ACTION_POWER_ON 12 1019#define ATOM_TRANSMITTER_ACTION_POWER_OFF 13 1020 1021// Following are used for DigTransmitterControlTable ver1.2 1022typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2 1023{ 1024#if ATOM_BIG_ENDIAN 1025 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1026 // =1 Dig Transmitter 2 ( Uniphy CD ) 1027 // =2 Dig Transmitter 3 ( Uniphy EF ) 1028 UCHAR ucReserved:1; 1029 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector 1030 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) 1031 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1032 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1033 1034 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1035 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1036#else 1037 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1038 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1039 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1040 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1041 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) 1042 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector 1043 UCHAR ucReserved:1; 1044 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1045 // =1 Dig Transmitter 2 ( Uniphy CD ) 1046 // =2 Dig Transmitter 3 ( Uniphy EF ) 1047#endif 1048}ATOM_DIG_TRANSMITTER_CONFIG_V2; 1049 1050//ucConfig 1051//Bit0 1052#define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01 1053 1054//Bit1 1055#define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02 1056 1057//Bit2 1058#define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04 1059#define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00 1060#define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04 1061 1062// Bit3 1063#define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08 1064#define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP 1065#define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP 1066 1067// Bit4 1068#define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10 1069 1070// Bit7:6 1071#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0 1072#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 //AB 1073#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 //CD 1074#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 //EF 1075 1076typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 1077{ 1078 union 1079 { 1080 USHORT usPixelClock; // in 10KHz; for bios convenient 1081 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1082 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 1083 }; 1084 ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig; 1085 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1086 UCHAR ucReserved[4]; 1087}DIG_TRANSMITTER_CONTROL_PARAMETERS_V2; 1088 1089typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3 1090{ 1091#if ATOM_BIG_ENDIAN 1092 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1093 // =1 Dig Transmitter 2 ( Uniphy CD ) 1094 // =2 Dig Transmitter 3 ( Uniphy EF ) 1095 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 1096 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1097 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1098 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1099 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1100 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1101#else 1102 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1103 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1104 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1105 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1106 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1107 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 1108 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1109 // =1 Dig Transmitter 2 ( Uniphy CD ) 1110 // =2 Dig Transmitter 3 ( Uniphy EF ) 1111#endif 1112}ATOM_DIG_TRANSMITTER_CONFIG_V3; 1113 1114 1115typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 1116{ 1117 union 1118 { 1119 USHORT usPixelClock; // in 10KHz; for bios convenient 1120 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1121 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 1122 }; 1123 ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig; 1124 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1125 UCHAR ucLaneNum; 1126 UCHAR ucReserved[3]; 1127}DIG_TRANSMITTER_CONTROL_PARAMETERS_V3; 1128 1129//ucConfig 1130//Bit0 1131#define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x01 1132 1133//Bit1 1134#define ATOM_TRANSMITTER_CONFIG_V3_COHERENT 0x02 1135 1136//Bit2 1137#define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK 0x04 1138#define ATOM_TRANSMITTER_CONFIG_V3_LINKA 0x00 1139#define ATOM_TRANSMITTER_CONFIG_V3_LINKB 0x04 1140 1141// Bit3 1142#define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK 0x08 1143#define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER 0x00 1144#define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER 0x08 1145 1146// Bit5:4 1147#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK 0x30 1148#define ATOM_TRASMITTER_CONFIG_V3_P1PLL 0x00 1149#define ATOM_TRASMITTER_CONFIG_V3_P2PLL 0x10 1150#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT 0x20 1151 1152// Bit7:6 1153#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC0 1154#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB 1155#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD 1156#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF 1157 1158 1159/****************************************************************************/ 1160// Structures used by UNIPHYTransmitterControlTable V1.4 1161// ASIC Families: NI 1162// ucTableFormatRevision=1 1163// ucTableContentRevision=4 1164/****************************************************************************/ 1165typedef struct _ATOM_DP_VS_MODE_V4 1166{ 1167 UCHAR ucLaneSel; 1168 union 1169 { 1170 UCHAR ucLaneSet; 1171 struct { 1172#if ATOM_BIG_ENDIAN 1173 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 1174 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level 1175 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level 1176#else 1177 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level 1178 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level 1179 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 1180#endif 1181 }; 1182 }; 1183}ATOM_DP_VS_MODE_V4; 1184 1185typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4 1186{ 1187#if ATOM_BIG_ENDIAN 1188 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1189 // =1 Dig Transmitter 2 ( Uniphy CD ) 1190 // =2 Dig Transmitter 3 ( Uniphy EF ) 1191 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New 1192 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1193 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1194 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1195 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1196 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1197#else 1198 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1199 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1200 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1201 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1202 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1203 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New 1204 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1205 // =1 Dig Transmitter 2 ( Uniphy CD ) 1206 // =2 Dig Transmitter 3 ( Uniphy EF ) 1207#endif 1208}ATOM_DIG_TRANSMITTER_CONFIG_V4; 1209 1210typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 1211{ 1212 union 1213 { 1214 USHORT usPixelClock; // in 10KHz; for bios convenient 1215 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1216 ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode Redefined comparing to previous version 1217 }; 1218 union 1219 { 1220 ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig; 1221 UCHAR ucConfig; 1222 }; 1223 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1224 UCHAR ucLaneNum; 1225 UCHAR ucReserved[3]; 1226}DIG_TRANSMITTER_CONTROL_PARAMETERS_V4; 1227 1228//ucConfig 1229//Bit0 1230#define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR 0x01 1231//Bit1 1232#define ATOM_TRANSMITTER_CONFIG_V4_COHERENT 0x02 1233//Bit2 1234#define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK 0x04 1235#define ATOM_TRANSMITTER_CONFIG_V4_LINKA 0x00 1236#define ATOM_TRANSMITTER_CONFIG_V4_LINKB 0x04 1237// Bit3 1238#define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK 0x08 1239#define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER 0x00 1240#define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER 0x08 1241// Bit5:4 1242#define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK 0x30 1243#define ATOM_TRANSMITTER_CONFIG_V4_P1PLL 0x00 1244#define ATOM_TRANSMITTER_CONFIG_V4_P2PLL 0x10 1245#define ATOM_TRANSMITTER_CONFIG_V4_DCPLL 0x20 // New in _V4 1246#define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT 0x30 // Changed comparing to V3 1247// Bit7:6 1248#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK 0xC0 1249#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1 0x00 //AB 1250#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2 0x40 //CD 1251#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3 0x80 //EF 1252 1253 1254typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V5 1255{ 1256#if ATOM_BIG_ENDIAN 1257 UCHAR ucReservd1:1; 1258 UCHAR ucHPDSel:3; 1259 UCHAR ucPhyClkSrcId:2; 1260 UCHAR ucCoherentMode:1; 1261 UCHAR ucReserved:1; 1262#else 1263 UCHAR ucReserved:1; 1264 UCHAR ucCoherentMode:1; 1265 UCHAR ucPhyClkSrcId:2; 1266 UCHAR ucHPDSel:3; 1267 UCHAR ucReservd1:1; 1268#endif 1269}ATOM_DIG_TRANSMITTER_CONFIG_V5; 1270 1271typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 1272{ 1273 USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= pixel clock, (HDMI deep color), =pixel clock * deep_color_ratio 1274 UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF 1275 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx 1276 UCHAR ucLaneNum; // indicate lane number 1-8 1277 UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h 1278 UCHAR ucDigMode; // indicate DIG mode 1279 union{ 1280 ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; 1281 UCHAR ucConfig; 1282 }; 1283 UCHAR ucDigEncoderSel; // indicate DIG front end encoder 1284 UCHAR ucDPLaneSet; 1285 UCHAR ucReserved; 1286 UCHAR ucReserved1; 1287}DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5; 1288 1289//ucPhyId 1290#define ATOM_PHY_ID_UNIPHYA 0 1291#define ATOM_PHY_ID_UNIPHYB 1 1292#define ATOM_PHY_ID_UNIPHYC 2 1293#define ATOM_PHY_ID_UNIPHYD 3 1294#define ATOM_PHY_ID_UNIPHYE 4 1295#define ATOM_PHY_ID_UNIPHYF 5 1296#define ATOM_PHY_ID_UNIPHYG 6 1297 1298// ucDigEncoderSel 1299#define ATOM_TRANMSITTER_V5__DIGA_SEL 0x01 1300#define ATOM_TRANMSITTER_V5__DIGB_SEL 0x02 1301#define ATOM_TRANMSITTER_V5__DIGC_SEL 0x04 1302#define ATOM_TRANMSITTER_V5__DIGD_SEL 0x08 1303#define ATOM_TRANMSITTER_V5__DIGE_SEL 0x10 1304#define ATOM_TRANMSITTER_V5__DIGF_SEL 0x20 1305#define ATOM_TRANMSITTER_V5__DIGG_SEL 0x40 1306 1307// ucDigMode 1308#define ATOM_TRANSMITTER_DIGMODE_V5_DP 0 1309#define ATOM_TRANSMITTER_DIGMODE_V5_LVDS 1 1310#define ATOM_TRANSMITTER_DIGMODE_V5_DVI 2 1311#define ATOM_TRANSMITTER_DIGMODE_V5_HDMI 3 1312#define ATOM_TRANSMITTER_DIGMODE_V5_SDVO 4 1313#define ATOM_TRANSMITTER_DIGMODE_V5_DP_MST 5 1314 1315// ucDPLaneSet 1316#define DP_LANE_SET__0DB_0_4V 0x00 1317#define DP_LANE_SET__0DB_0_6V 0x01 1318#define DP_LANE_SET__0DB_0_8V 0x02 1319#define DP_LANE_SET__0DB_1_2V 0x03 1320#define DP_LANE_SET__3_5DB_0_4V 0x08 1321#define DP_LANE_SET__3_5DB_0_6V 0x09 1322#define DP_LANE_SET__3_5DB_0_8V 0x0a 1323#define DP_LANE_SET__6DB_0_4V 0x10 1324#define DP_LANE_SET__6DB_0_6V 0x11 1325#define DP_LANE_SET__9_5DB_0_4V 0x18 1326 1327// ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; 1328// Bit1 1329#define ATOM_TRANSMITTER_CONFIG_V5_COHERENT 0x02 1330 1331// Bit3:2 1332#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_MASK 0x0c 1333#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_SHIFT 0x02 1334 1335#define ATOM_TRANSMITTER_CONFIG_V5_P1PLL 0x00 1336#define ATOM_TRANSMITTER_CONFIG_V5_P2PLL 0x04 1337#define ATOM_TRANSMITTER_CONFIG_V5_P0PLL 0x08 1338#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT 0x0c 1339// Bit6:4 1340#define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK 0x70 1341#define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_SHIFT 0x04 1342 1343#define ATOM_TRANSMITTER_CONFIG_V5_NO_HPD_SEL 0x00 1344#define ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL 0x10 1345#define ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL 0x20 1346#define ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL 0x30 1347#define ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL 0x40 1348#define ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL 0x50 1349#define ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL 0x60 1350 1351#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 1352 1353 1354/****************************************************************************/ 1355// Structures used by ExternalEncoderControlTable V1.3 1356// ASIC Families: Evergreen, Llano, NI 1357// ucTableFormatRevision=1 1358// ucTableContentRevision=3 1359/****************************************************************************/ 1360 1361typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 1362{ 1363 union{ 1364 USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT 1365 USHORT usConnectorId; // connector id, valid when ucAction = INIT 1366 }; 1367 UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT 1368 UCHAR ucAction; // 1369 UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT 1370 UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT 1371 UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP 1372 UCHAR ucReserved; 1373}EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3; 1374 1375// ucAction 1376#define EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT 0x00 1377#define EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT 0x01 1378#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT 0x07 1379#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP 0x0f 1380#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10 1381#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11 1382#define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12 1383#define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP 0x14 1384 1385// ucConfig 1386#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 1387#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 1388#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 1389#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ 0x02 1390#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MASK 0x70 1391#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 0x00 1392#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 0x10 1393#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 0x20 1394 1395typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 1396{ 1397 EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder; 1398 ULONG ulReserved[2]; 1399}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3; 1400 1401 1402/****************************************************************************/ 1403// Structures used by DAC1OuputControlTable 1404// DAC2OuputControlTable 1405// LVTMAOutputControlTable (Before DEC30) 1406// TMDSAOutputControlTable (Before DEC30) 1407/****************************************************************************/ 1408typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1409{ 1410 UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE 1411 // When the display is LCD, in addition to above: 1412 // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START|| 1413 // ATOM_LCD_SELFTEST_STOP 1414 1415 UCHAR aucPadding[3]; // padding to DWORD aligned 1416}DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS; 1417 1418#define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1419 1420 1421#define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1422#define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1423 1424#define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1425#define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1426 1427#define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1428#define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1429 1430#define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1431#define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1432 1433#define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1434#define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1435 1436#define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1437#define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1438 1439#define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1440#define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1441 1442#define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1443#define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION 1444#define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS 1445 1446/****************************************************************************/ 1447// Structures used by BlankCRTCTable 1448/****************************************************************************/ 1449typedef struct _BLANK_CRTC_PARAMETERS 1450{ 1451 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1452 UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF 1453 USHORT usBlackColorRCr; 1454 USHORT usBlackColorGY; 1455 USHORT usBlackColorBCb; 1456}BLANK_CRTC_PARAMETERS; 1457#define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS 1458 1459/****************************************************************************/ 1460// Structures used by EnableCRTCTable 1461// EnableCRTCMemReqTable 1462// UpdateCRTC_DoubleBufferRegistersTable 1463/****************************************************************************/ 1464typedef struct _ENABLE_CRTC_PARAMETERS 1465{ 1466 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1467 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1468 UCHAR ucPadding[2]; 1469}ENABLE_CRTC_PARAMETERS; 1470#define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS 1471 1472/****************************************************************************/ 1473// Structures used by SetCRTC_OverScanTable 1474/****************************************************************************/ 1475typedef struct _SET_CRTC_OVERSCAN_PARAMETERS 1476{ 1477 USHORT usOverscanRight; // right 1478 USHORT usOverscanLeft; // left 1479 USHORT usOverscanBottom; // bottom 1480 USHORT usOverscanTop; // top 1481 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1482 UCHAR ucPadding[3]; 1483}SET_CRTC_OVERSCAN_PARAMETERS; 1484#define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS 1485 1486/****************************************************************************/ 1487// Structures used by SetCRTC_ReplicationTable 1488/****************************************************************************/ 1489typedef struct _SET_CRTC_REPLICATION_PARAMETERS 1490{ 1491 UCHAR ucH_Replication; // horizontal replication 1492 UCHAR ucV_Replication; // vertical replication 1493 UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1494 UCHAR ucPadding; 1495}SET_CRTC_REPLICATION_PARAMETERS; 1496#define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS 1497 1498/****************************************************************************/ 1499// Structures used by SelectCRTC_SourceTable 1500/****************************************************************************/ 1501typedef struct _SELECT_CRTC_SOURCE_PARAMETERS 1502{ 1503 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1504 UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|.... 1505 UCHAR ucPadding[2]; 1506}SELECT_CRTC_SOURCE_PARAMETERS; 1507#define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS 1508 1509typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 1510{ 1511 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1512 UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO 1513 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO 1514 UCHAR ucPadding; 1515}SELECT_CRTC_SOURCE_PARAMETERS_V2; 1516 1517//ucEncoderID 1518//#define ASIC_INT_DAC1_ENCODER_ID 0x00 1519//#define ASIC_INT_TV_ENCODER_ID 0x02 1520//#define ASIC_INT_DIG1_ENCODER_ID 0x03 1521//#define ASIC_INT_DAC2_ENCODER_ID 0x04 1522//#define ASIC_EXT_TV_ENCODER_ID 0x06 1523//#define ASIC_INT_DVO_ENCODER_ID 0x07 1524//#define ASIC_INT_DIG2_ENCODER_ID 0x09 1525//#define ASIC_EXT_DIG_ENCODER_ID 0x05 1526 1527//ucEncodeMode 1528//#define ATOM_ENCODER_MODE_DP 0 1529//#define ATOM_ENCODER_MODE_LVDS 1 1530//#define ATOM_ENCODER_MODE_DVI 2 1531//#define ATOM_ENCODER_MODE_HDMI 3 1532//#define ATOM_ENCODER_MODE_SDVO 4 1533//#define ATOM_ENCODER_MODE_TV 13 1534//#define ATOM_ENCODER_MODE_CV 14 1535//#define ATOM_ENCODER_MODE_CRT 15 1536 1537/****************************************************************************/ 1538// Structures used by SetPixelClockTable 1539// GetPixelClockTable 1540/****************************************************************************/ 1541//Major revision=1., Minor revision=1 1542typedef struct _PIXEL_CLOCK_PARAMETERS 1543{ 1544 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1545 // 0 means disable PPLL 1546 USHORT usRefDiv; // Reference divider 1547 USHORT usFbDiv; // feedback divider 1548 UCHAR ucPostDiv; // post divider 1549 UCHAR ucFracFbDiv; // fractional feedback divider 1550 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1551 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER 1552 UCHAR ucCRTC; // Which CRTC uses this Ppll 1553 UCHAR ucPadding; 1554}PIXEL_CLOCK_PARAMETERS; 1555 1556//Major revision=1., Minor revision=2, add ucMiscIfno 1557//ucMiscInfo: 1558#define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1 1559#define MISC_DEVICE_INDEX_MASK 0xF0 1560#define MISC_DEVICE_INDEX_SHIFT 4 1561 1562typedef struct _PIXEL_CLOCK_PARAMETERS_V2 1563{ 1564 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1565 // 0 means disable PPLL 1566 USHORT usRefDiv; // Reference divider 1567 USHORT usFbDiv; // feedback divider 1568 UCHAR ucPostDiv; // post divider 1569 UCHAR ucFracFbDiv; // fractional feedback divider 1570 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1571 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER 1572 UCHAR ucCRTC; // Which CRTC uses this Ppll 1573 UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog 1574}PIXEL_CLOCK_PARAMETERS_V2; 1575 1576//Major revision=1., Minor revision=3, structure/definition change 1577//ucEncoderMode: 1578//ATOM_ENCODER_MODE_DP 1579//ATOM_ENOCDER_MODE_LVDS 1580//ATOM_ENOCDER_MODE_DVI 1581//ATOM_ENOCDER_MODE_HDMI 1582//ATOM_ENOCDER_MODE_SDVO 1583//ATOM_ENCODER_MODE_TV 13 1584//ATOM_ENCODER_MODE_CV 14 1585//ATOM_ENCODER_MODE_CRT 15 1586 1587//ucDVOConfig 1588//#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 1589//#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 1590//#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 1591//#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c 1592//#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 1593//#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 1594//#define DVO_ENCODER_CONFIG_24BIT 0x08 1595 1596//ucMiscInfo: also changed, see below 1597#define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01 1598#define PIXEL_CLOCK_MISC_VGA_MODE 0x02 1599#define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04 1600#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00 1601#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04 1602#define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08 1603#define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x10 1604// V1.4 for RoadRunner 1605#define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10 1606#define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20 1607 1608 1609typedef struct _PIXEL_CLOCK_PARAMETERS_V3 1610{ 1611 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1612 // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0. 1613 USHORT usRefDiv; // Reference divider 1614 USHORT usFbDiv; // feedback divider 1615 UCHAR ucPostDiv; // post divider 1616 UCHAR ucFracFbDiv; // fractional feedback divider 1617 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1618 UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h 1619 union 1620 { 1621 UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/ 1622 UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit 1623 }; 1624 UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel 1625 // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source 1626 // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider 1627}PIXEL_CLOCK_PARAMETERS_V3; 1628 1629#define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2 1630#define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST 1631 1632typedef struct _PIXEL_CLOCK_PARAMETERS_V5 1633{ 1634 UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to 1635 // drive the pixel clock. not used for DCPLL case. 1636 union{ 1637 UCHAR ucReserved; 1638 UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed. 1639 }; 1640 USHORT usPixelClock; // target the pixel clock to drive the CRTC timing 1641 // 0 means disable PPLL/DCPLL. 1642 USHORT usFbDiv; // feedback divider integer part. 1643 UCHAR ucPostDiv; // post divider. 1644 UCHAR ucRefDiv; // Reference divider 1645 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL 1646 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, 1647 // indicate which graphic encoder will be used. 1648 UCHAR ucEncoderMode; // Encoder mode: 1649 UCHAR ucMiscInfo; // bit[0]= Force program PPLL 1650 // bit[1]= when VGA timing is used. 1651 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp 1652 // bit[4]= RefClock source for PPLL. 1653 // =0: XTLAIN( default mode ) 1654 // =1: other external clock source, which is pre-defined 1655 // by VBIOS depend on the feature required. 1656 // bit[7:5]: reserved. 1657 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) 1658 1659}PIXEL_CLOCK_PARAMETERS_V5; 1660 1661#define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL 0x01 1662#define PIXEL_CLOCK_V5_MISC_VGA_MODE 0x02 1663#define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK 0x0c 1664#define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x00 1665#define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x04 1666#define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08 1667#define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10 1668 1669typedef struct _CRTC_PIXEL_CLOCK_FREQ 1670{ 1671#if ATOM_BIG_ENDIAN 1672 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to 1673 // drive the pixel clock. not used for DCPLL case. 1674 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. 1675 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. 1676#else 1677 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. 1678 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. 1679 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to 1680 // drive the pixel clock. not used for DCPLL case. 1681#endif 1682}CRTC_PIXEL_CLOCK_FREQ; 1683 1684typedef struct _PIXEL_CLOCK_PARAMETERS_V6 1685{ 1686 union{ 1687 CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency 1688 ULONG ulDispEngClkFreq; // dispclk frequency 1689 }; 1690 USHORT usFbDiv; // feedback divider integer part. 1691 UCHAR ucPostDiv; // post divider. 1692 UCHAR ucRefDiv; // Reference divider 1693 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL 1694 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, 1695 // indicate which graphic encoder will be used. 1696 UCHAR ucEncoderMode; // Encoder mode: 1697 UCHAR ucMiscInfo; // bit[0]= Force program PPLL 1698 // bit[1]= when VGA timing is used. 1699 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp 1700 // bit[4]= RefClock source for PPLL. 1701 // =0: XTLAIN( default mode ) 1702 // =1: other external clock source, which is pre-defined 1703 // by VBIOS depend on the feature required. 1704 // bit[7:5]: reserved. 1705 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) 1706 1707}PIXEL_CLOCK_PARAMETERS_V6; 1708 1709#define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL 0x01 1710#define PIXEL_CLOCK_V6_MISC_VGA_MODE 0x02 1711#define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c 1712#define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00 1713#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04 1714#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08 1715#define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c 1716#define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10 1717#define PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK 0x40 1718 1719typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2 1720{ 1721 PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput; 1722}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2; 1723 1724typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2 1725{ 1726 UCHAR ucStatus; 1727 UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock 1728 UCHAR ucReserved[2]; 1729}GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2; 1730 1731typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3 1732{ 1733 PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput; 1734}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3; 1735 1736/****************************************************************************/ 1737// Structures used by AdjustDisplayPllTable 1738/****************************************************************************/ 1739typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS 1740{ 1741 USHORT usPixelClock; 1742 UCHAR ucTransmitterID; 1743 UCHAR ucEncodeMode; 1744 union 1745 { 1746 UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit 1747 UCHAR ucConfig; //if none DVO, not defined yet 1748 }; 1749 UCHAR ucReserved[3]; 1750}ADJUST_DISPLAY_PLL_PARAMETERS; 1751 1752#define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10 1753#define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS 1754 1755typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 1756{ 1757 USHORT usPixelClock; // target pixel clock 1758 UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h 1759 UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI 1760 UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX 1761 UCHAR ucExtTransmitterID; // external encoder id. 1762 UCHAR ucReserved[2]; 1763}ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3; 1764 1765// usDispPllConfig v1.2 for RoadRunner 1766#define DISPPLL_CONFIG_DVO_RATE_SEL 0x0001 // need only when ucTransmitterID = DVO 1767#define DISPPLL_CONFIG_DVO_DDR_SPEED 0x0000 // need only when ucTransmitterID = DVO 1768#define DISPPLL_CONFIG_DVO_SDR_SPEED 0x0001 // need only when ucTransmitterID = DVO 1769#define DISPPLL_CONFIG_DVO_OUTPUT_SEL 0x000c // need only when ucTransmitterID = DVO 1770#define DISPPLL_CONFIG_DVO_LOW12BIT 0x0000 // need only when ucTransmitterID = DVO 1771#define DISPPLL_CONFIG_DVO_UPPER12BIT 0x0004 // need only when ucTransmitterID = DVO 1772#define DISPPLL_CONFIG_DVO_24BIT 0x0008 // need only when ucTransmitterID = DVO 1773#define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS 1774#define DISPPLL_CONFIG_COHERENT_MODE 0x0020 // Only used when ucEncoderMode = TMDS or HDMI 1775#define DISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS 1776 1777 1778typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 1779{ 1780 ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc 1781 UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given ) 1782 UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider 1783 UCHAR ucReserved[2]; 1784}ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3; 1785 1786typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 1787{ 1788 union 1789 { 1790 ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 sInput; 1791 ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput; 1792 }; 1793} ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3; 1794 1795/****************************************************************************/ 1796// Structures used by EnableYUVTable 1797/****************************************************************************/ 1798typedef struct _ENABLE_YUV_PARAMETERS 1799{ 1800 UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB) 1801 UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format 1802 UCHAR ucPadding[2]; 1803}ENABLE_YUV_PARAMETERS; 1804#define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS 1805 1806/****************************************************************************/ 1807// Structures used by GetMemoryClockTable 1808/****************************************************************************/ 1809typedef struct _GET_MEMORY_CLOCK_PARAMETERS 1810{ 1811 ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit 1812} GET_MEMORY_CLOCK_PARAMETERS; 1813#define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS 1814 1815/****************************************************************************/ 1816// Structures used by GetEngineClockTable 1817/****************************************************************************/ 1818typedef struct _GET_ENGINE_CLOCK_PARAMETERS 1819{ 1820 ULONG ulReturnEngineClock; // current engine speed in 10KHz unit 1821} GET_ENGINE_CLOCK_PARAMETERS; 1822#define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS 1823 1824/****************************************************************************/ 1825// Following Structures and constant may be obsolete 1826/****************************************************************************/ 1827//Maxium 8 bytes,the data read in will be placed in the parameter space. 1828//Read operaion successeful when the paramter space is non-zero, otherwise read operation failed 1829typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS 1830{ 1831 USHORT usPrescale; //Ratio between Engine clock and I2C clock 1832 USHORT usVRAMAddress; //Address in Frame Buffer where to pace raw EDID 1833 USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status 1834 //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte 1835 UCHAR ucSlaveAddr; //Read from which slave 1836 UCHAR ucLineNumber; //Read from which HW assisted line 1837}READ_EDID_FROM_HW_I2C_DATA_PARAMETERS; 1838#define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS 1839 1840 1841#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0 1842#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1 1843#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2 1844#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3 1845#define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4 1846 1847typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 1848{ 1849 USHORT usPrescale; //Ratio between Engine clock and I2C clock 1850 USHORT usByteOffset; //Write to which byte 1851 //Upper portion of usByteOffset is Format of data 1852 //1bytePS+offsetPS 1853 //2bytesPS+offsetPS 1854 //blockID+offsetPS 1855 //blockID+offsetID 1856 //blockID+counterID+offsetID 1857 UCHAR ucData; //PS data1 1858 UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2 1859 UCHAR ucSlaveAddr; //Write to which slave 1860 UCHAR ucLineNumber; //Write from which HW assisted line 1861}WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS; 1862 1863#define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 1864 1865typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS 1866{ 1867 USHORT usPrescale; //Ratio between Engine clock and I2C clock 1868 UCHAR ucSlaveAddr; //Write to which slave 1869 UCHAR ucLineNumber; //Write from which HW assisted line 1870}SET_UP_HW_I2C_DATA_PARAMETERS; 1871 1872 1873/**************************************************************************/ 1874#define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 1875 1876 1877/****************************************************************************/ 1878// Structures used by PowerConnectorDetectionTable 1879/****************************************************************************/ 1880typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS 1881{ 1882 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected 1883 UCHAR ucPwrBehaviorId; 1884 USHORT usPwrBudget; //how much power currently boot to in unit of watt 1885}POWER_CONNECTOR_DETECTION_PARAMETERS; 1886 1887typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION 1888{ 1889 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected 1890 UCHAR ucReserved; 1891 USHORT usPwrBudget; //how much power currently boot to in unit of watt 1892 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 1893}POWER_CONNECTOR_DETECTION_PS_ALLOCATION; 1894 1895/****************************LVDS SS Command Table Definitions**********************/ 1896 1897/****************************************************************************/ 1898// Structures used by EnableSpreadSpectrumOnPPLLTable 1899/****************************************************************************/ 1900typedef struct _ENABLE_LVDS_SS_PARAMETERS 1901{ 1902 USHORT usSpreadSpectrumPercentage; 1903 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 1904 UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY 1905 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE 1906 UCHAR ucPadding[3]; 1907}ENABLE_LVDS_SS_PARAMETERS; 1908 1909//ucTableFormatRevision=1,ucTableContentRevision=2 1910typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2 1911{ 1912 USHORT usSpreadSpectrumPercentage; 1913 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 1914 UCHAR ucSpreadSpectrumStep; // 1915 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE 1916 UCHAR ucSpreadSpectrumDelay; 1917 UCHAR ucSpreadSpectrumRange; 1918 UCHAR ucPadding; 1919}ENABLE_LVDS_SS_PARAMETERS_V2; 1920 1921//This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS. 1922typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL 1923{ 1924 USHORT usSpreadSpectrumPercentage; 1925 UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 1926 UCHAR ucSpreadSpectrumStep; // 1927 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1928 UCHAR ucSpreadSpectrumDelay; 1929 UCHAR ucSpreadSpectrumRange; 1930 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2 1931}ENABLE_SPREAD_SPECTRUM_ON_PPLL; 1932 1933typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 1934{ 1935 USHORT usSpreadSpectrumPercentage; 1936 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. 1937 // Bit[1]: 1-Ext. 0-Int. 1938 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL 1939 // Bits[7:4] reserved 1940 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1941 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] 1942 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC 1943}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2; 1944 1945#define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD 0x00 1946#define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD 0x01 1947#define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD 0x02 1948#define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK 0x0c 1949#define ATOM_PPLL_SS_TYPE_V2_P1PLL 0x00 1950#define ATOM_PPLL_SS_TYPE_V2_P2PLL 0x04 1951#define ATOM_PPLL_SS_TYPE_V2_DCPLL 0x08 1952#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF 1953#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 0 1954#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00 1955#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8 1956 1957// Used by DCE5.0 1958 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 1959{ 1960 USHORT usSpreadSpectrumAmountFrac; // SS_AMOUNT_DSFRAC New in DCE5.0 1961 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. 1962 // Bit[1]: 1-Ext. 0-Int. 1963 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL 1964 // Bits[7:4] reserved 1965 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1966 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] 1967 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC 1968}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3; 1969 1970#define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD 0x00 1971#define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD 0x01 1972#define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD 0x02 1973#define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK 0x0c 1974#define ATOM_PPLL_SS_TYPE_V3_P1PLL 0x00 1975#define ATOM_PPLL_SS_TYPE_V3_P2PLL 0x04 1976#define ATOM_PPLL_SS_TYPE_V3_DCPLL 0x08 1977#define ATOM_PPLL_SS_TYPE_V3_P0PLL ATOM_PPLL_SS_TYPE_V3_DCPLL 1978#define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK 0x00FF 1979#define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT 0 1980#define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK 0x0F00 1981#define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT 8 1982 1983#define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL 1984 1985/**************************************************************************/ 1986 1987typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION 1988{ 1989 PIXEL_CLOCK_PARAMETERS sPCLKInput; 1990 ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion 1991}SET_PIXEL_CLOCK_PS_ALLOCATION; 1992 1993#define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION 1994 1995/****************************************************************************/ 1996// Structures used by ### 1997/****************************************************************************/ 1998typedef struct _MEMORY_TRAINING_PARAMETERS 1999{ 2000 ULONG ulTargetMemoryClock; //In 10Khz unit
2001}MEMORY_TRAINING_PARAMETERS; 2002#define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS 2003 2004 2005/****************************LVDS and other encoder command table definitions **********************/ 2006 2007 2008/****************************************************************************/ 2009// Structures used by LVDSEncoderControlTable (Before DCE30) 2010// LVTMAEncoderControlTable (Before DCE30) 2011// TMDSAEncoderControlTable (Before DCE30) 2012/****************************************************************************/ 2013typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS 2014{ 2015 USHORT usPixelClock; // in 10KHz; for bios convenient 2016 UCHAR ucMisc; // bit0=0: Enable single link 2017 // =1: Enable dual link 2018 // Bit1=0: 666RGB 2019 // =1: 888RGB 2020 UCHAR ucAction; // 0: turn off encoder 2021 // 1: setup and turn on encoder 2022}LVDS_ENCODER_CONTROL_PARAMETERS; 2023 2024#define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS 2025 2026#define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS 2027#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS 2028 2029#define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS 2030#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS 2031 2032 2033//ucTableFormatRevision=1,ucTableContentRevision=2 2034typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 2035{ 2036 USHORT usPixelClock; // in 10KHz; for bios convenient 2037 UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below 2038 UCHAR ucAction; // 0: turn off encoder 2039 // 1: setup and turn on encoder 2040 UCHAR ucTruncate; // bit0=0: Disable truncate 2041 // =1: Enable truncate 2042 // bit4=0: 666RGB 2043 // =1: 888RGB 2044 UCHAR ucSpatial; // bit0=0: Disable spatial dithering 2045 // =1: Enable spatial dithering 2046 // bit4=0: 666RGB 2047 // =1: 888RGB 2048 UCHAR ucTemporal; // bit0=0: Disable temporal dithering 2049 // =1: Enable temporal dithering 2050 // bit4=0: 666RGB 2051 // =1: 888RGB 2052 // bit5=0: Gray level 2 2053 // =1: Gray level 4 2054 UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E 2055 // =1: 25FRC_SEL pattern F 2056 // bit6:5=0: 50FRC_SEL pattern A 2057 // =1: 50FRC_SEL pattern B 2058 // =2: 50FRC_SEL pattern C 2059 // =3: 50FRC_SEL pattern D 2060 // bit7=0: 75FRC_SEL pattern E 2061 // =1: 75FRC_SEL pattern F 2062}LVDS_ENCODER_CONTROL_PARAMETERS_V2; 2063 2064#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2065 2066#define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2067#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 2068 2069#define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 2070#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2 2071 2072#define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2073#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2074 2075#define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2076#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3 2077 2078#define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2079#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3 2080 2081/****************************************************************************/ 2082// Structures used by ### 2083/****************************************************************************/ 2084typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS 2085{ 2086 UCHAR ucEnable; // Enable or Disable External TMDS encoder 2087 UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB} 2088 UCHAR ucPadding[2]; 2089}ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS; 2090 2091typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION 2092{ 2093 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder; 2094 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 2095}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION; 2096 2097#define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2098 2099typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 2100{ 2101 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder; 2102 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 2103}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2; 2104 2105typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION 2106{ 2107 DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder; 2108 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 2109}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION; 2110 2111/****************************************************************************/ 2112// Structures used by DVOEncoderControlTable 2113/****************************************************************************/ 2114//ucTableFormatRevision=1,ucTableContentRevision=3 2115 2116//ucDVOConfig: 2117#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 2118#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 2119#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 2120#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c 2121#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 2122#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 2123#define DVO_ENCODER_CONFIG_24BIT 0x08 2124 2125typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 2126{ 2127 USHORT usPixelClock; 2128 UCHAR ucDVOConfig; 2129 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 2130 UCHAR ucReseved[4]; 2131}DVO_ENCODER_CONTROL_PARAMETERS_V3; 2132#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3 2133 2134typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V1_4 2135{ 2136 USHORT usPixelClock; 2137 UCHAR ucDVOConfig; 2138 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 2139 UCHAR ucBitPerColor; //please refer to definition of PANEL_xBIT_PER_COLOR 2140 UCHAR ucReseved[3]; 2141}DVO_ENCODER_CONTROL_PARAMETERS_V1_4; 2142#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 DVO_ENCODER_CONTROL_PARAMETERS_V1_4 2143 2144 2145//ucTableFormatRevision=1 2146//ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for 2147// bit1=0: non-coherent mode 2148// =1: coherent mode 2149 2150//========================================================================================== 2151//Only change is here next time when changing encoder parameter definitions again! 2152#define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2153#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST 2154 2155#define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2156#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST 2157 2158#define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2159#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST 2160 2161#define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS 2162#define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION 2163 2164//========================================================================================== 2165#define PANEL_ENCODER_MISC_DUAL 0x01 2166#define PANEL_ENCODER_MISC_COHERENT 0x02 2167#define PANEL_ENCODER_MISC_TMDS_LINKB 0x04 2168#define PANEL_ENCODER_MISC_HDMI_TYPE 0x08 2169 2170#define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE 2171#define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE 2172#define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1) 2173 2174#define PANEL_ENCODER_TRUNCATE_EN 0x01 2175#define PANEL_ENCODER_TRUNCATE_DEPTH 0x10 2176#define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01 2177#define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10 2178#define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01 2179#define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10 2180#define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20 2181#define PANEL_ENCODER_25FRC_MASK 0x10 2182#define PANEL_ENCODER_25FRC_E 0x00 2183#define PANEL_ENCODER_25FRC_F 0x10 2184#define PANEL_ENCODER_50FRC_MASK 0x60 2185#define PANEL_ENCODER_50FRC_A 0x00 2186#define PANEL_ENCODER_50FRC_B 0x20 2187#define PANEL_ENCODER_50FRC_C 0x40 2188#define PANEL_ENCODER_50FRC_D 0x60 2189#define PANEL_ENCODER_75FRC_MASK 0x80 2190#define PANEL_ENCODER_75FRC_E 0x00 2191#define PANEL_ENCODER_75FRC_F 0x80 2192 2193/****************************************************************************/ 2194// Structures used by SetVoltageTable 2195/****************************************************************************/ 2196#define SET_VOLTAGE_TYPE_ASIC_VDDC 1 2197#define SET_VOLTAGE_TYPE_ASIC_MVDDC 2 2198#define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3 2199#define SET_VOLTAGE_TYPE_ASIC_VDDCI 4 2200#define SET_VOLTAGE_INIT_MODE 5 2201#define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic 2202 2203#define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1 2204#define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2 2205#define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4 2206 2207#define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0 2208#define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1 2209#define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2 2210 2211typedef struct _SET_VOLTAGE_PARAMETERS 2212{ 2213 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ 2214 UCHAR ucVoltageMode; // To set all, to set source A or source B or ... 2215 UCHAR ucVoltageIndex; // An index to tell which voltage level 2216 UCHAR ucReserved; 2217}SET_VOLTAGE_PARAMETERS; 2218 2219typedef struct _SET_VOLTAGE_PARAMETERS_V2 2220{ 2221 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ 2222 UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode 2223 USHORT usVoltageLevel; // real voltage level 2224}SET_VOLTAGE_PARAMETERS_V2; 2225 2226 2227typedef struct _SET_VOLTAGE_PARAMETERS_V1_3 2228{ 2229 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2230 UCHAR ucVoltageMode; // Indicate action: Set voltage level 2231 USHORT usVoltageLevel; // real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) 2232}SET_VOLTAGE_PARAMETERS_V1_3; 2233 2234//ucVoltageType 2235#define VOLTAGE_TYPE_VDDC 1 2236#define VOLTAGE_TYPE_MVDDC 2 2237#define VOLTAGE_TYPE_MVDDQ 3 2238#define VOLTAGE_TYPE_VDDCI 4 2239 2240//SET_VOLTAGE_PARAMETERS_V3.ucVoltageMode 2241#define ATOM_SET_VOLTAGE 0 //Set voltage Level 2242#define ATOM_INIT_VOLTAGE_REGULATOR 3 //Init Regulator 2243#define ATOM_SET_VOLTAGE_PHASE 4 //Set Vregulator Phase, only for SVID/PVID regulator 2244#define ATOM_GET_MAX_VOLTAGE 6 //Get Max Voltage, not used from SetVoltageTable v1.3 2245#define ATOM_GET_VOLTAGE_LEVEL 6 //Get Voltage level from vitual voltage ID, not used for SetVoltage v1.4 2246#define ATOM_GET_LEAKAGE_ID 8 //Get Leakage Voltage Id ( starting from SMU7x IP ), SetVoltage v1.4 2247 2248// define vitual voltage id in usVoltageLevel 2249#define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01 2250#define ATOM_VIRTUAL_VOLTAGE_ID1 0xff02 2251#define ATOM_VIRTUAL_VOLTAGE_ID2 0xff03 2252#define ATOM_VIRTUAL_VOLTAGE_ID3 0xff04 2253#define ATOM_VIRTUAL_VOLTAGE_ID4 0xff05 2254#define ATOM_VIRTUAL_VOLTAGE_ID5 0xff06 2255#define ATOM_VIRTUAL_VOLTAGE_ID6 0xff07 2256#define ATOM_VIRTUAL_VOLTAGE_ID7 0xff08 2257 2258typedef struct _SET_VOLTAGE_PS_ALLOCATION 2259{ 2260 SET_VOLTAGE_PARAMETERS sASICSetVoltage; 2261 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 2262}SET_VOLTAGE_PS_ALLOCATION; 2263 2264// New Added from SI for GetVoltageInfoTable, input parameter structure 2265typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1 2266{ 2267 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2268 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info 2269 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id 2270 ULONG ulReserved; 2271}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1; 2272 2273// New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_VID 2274typedef struct _GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 2275{ 2276 ULONG ulVotlageGpioState; 2277 ULONG ulVoltageGPioMask; 2278}GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1; 2279 2280// New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_STATEx_LEAKAGE_VID 2281typedef struct _GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 2282{ 2283 USHORT usVoltageLevel; 2284 USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator 2285 ULONG ulReseved; 2286}GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1; 2287 2288 2289// GetVoltageInfo v1.1 ucVoltageMode 2290#define ATOM_GET_VOLTAGE_VID 0x00 2291#define ATOM_GET_VOTLAGE_INIT_SEQ 0x03 2292#define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID 0x04 2293// for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state 2294#define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10 2295 2296// for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state 2297#define ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11 2298// undefined power state 2299#define ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x12 2300#define ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13 2301 2302/****************************************************************************/ 2303// Structures used by TVEncoderControlTable 2304/****************************************************************************/ 2305typedef struct _TV_ENCODER_CONTROL_PARAMETERS 2306{ 2307 USHORT usPixelClock; // in 10KHz; for bios convenient 2308 UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..." 2309 UCHAR ucAction; // 0: turn off encoder 2310 // 1: setup and turn on encoder 2311}TV_ENCODER_CONTROL_PARAMETERS; 2312 2313typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION 2314{ 2315 TV_ENCODER_CONTROL_PARAMETERS sTVEncoder; 2316 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one 2317}TV_ENCODER_CONTROL_PS_ALLOCATION; 2318 2319//==============================Data Table Portion==================================== 2320 2321/****************************************************************************/ 2322// Structure used in Data.mtb 2323/****************************************************************************/ 2324typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES 2325{ 2326 USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position! 2327 USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios 2328 USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios 2329 USHORT StandardVESA_Timing; // Only used by Bios 2330 USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4 2331 USHORT PaletteData; // Only used by BIOS 2332 USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info 2333 USHORT DIGTransmitterInfo; // Internal used by VBIOS only version 3.1 2334 USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1 2335 USHORT SupportedDevicesInfo; // Will be obsolete from R600 2336 USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600 2337 USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600 2338 USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1 2339 USHORT VESA_ToInternalModeLUT; // Only used by Bios 2340 USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will be used from R600 2341 USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600 2342 USHORT CompassionateData; // Will be obsolete from R600 2343 USHORT SaveRestoreInfo; // Only used by Bios 2344 USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info 2345 USHORT OemInfo; // Defined and used by external SW, should be obsolete soon 2346 USHORT XTMDS_Info; // Will be obsolete from R600 2347 USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used 2348 USHORT Object_Header; // Shared by various SW components,latest version 1.1 2349 USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!! 2350 USHORT MC_InitParameter; // Only used by command table 2351 USHORT ASIC_VDDC_Info; // Will be obsolete from R600 2352 USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info" 2353 USHORT TV_VideoMode; // Only used by command table 2354 USHORT VRAM_Info; // Only used by command table, latest version 1.3 2355 USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1 2356 USHORT IntegratedSystemInfo; // Shared by various SW components 2357 USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600 2358 USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1 2359 USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1 2360}ATOM_MASTER_LIST_OF_DATA_TABLES; 2361 2362typedef struct _ATOM_MASTER_DATA_TABLE 2363{ 2364 ATOM_COMMON_TABLE_HEADER sHeader; 2365 ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; 2366}ATOM_MASTER_DATA_TABLE; 2367 2368// For backward compatible 2369#define LVDS_Info LCD_Info 2370#define DAC_Info PaletteData 2371#define TMDS_Info DIGTransmitterInfo 2372 2373/****************************************************************************/ 2374// Structure used in MultimediaCapabilityInfoTable 2375/****************************************************************************/ 2376typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO 2377{ 2378 ATOM_COMMON_TABLE_HEADER sHeader; 2379 ULONG ulSignature; // HW info table signature string "$ATI" 2380 UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc) 2381 UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7) 2382 UCHAR ucVideoPortInfo; // Provides the video port capabilities 2383 UCHAR ucHostPortInfo; // Provides host port configuration information 2384}ATOM_MULTIMEDIA_CAPABILITY_INFO; 2385 2386/****************************************************************************/ 2387// Structure used in MultimediaConfigInfoTable 2388/****************************************************************************/ 2389typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO 2390{ 2391 ATOM_COMMON_TABLE_HEADER sHeader; 2392 ULONG ulSignature; // MM info table signature sting "$MMT" 2393 UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5) 2394 UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5) 2395 UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting 2396 UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7) 2397 UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6) 2398 UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4) 2399 UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3) 2400 UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2401 UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2402 UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2403 UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2404 UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2405}ATOM_MULTIMEDIA_CONFIG_INFO; 2406 2407 2408/****************************************************************************/ 2409// Structures used in FirmwareInfoTable 2410/****************************************************************************/ 2411 2412// usBIOSCapability Definition: 2413// Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; 2414// Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; 2415// Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; 2416// Others: Reserved 2417#define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001 2418#define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002 2419#define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004 2420#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable. 2421#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable. 2422#define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020 2423#define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040 2424#define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080 2425#define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100 2426#define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00 2427#define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000 2428#define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000 2429#define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss chip 2430#define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss chip 2431 2432#ifndef _H2INC 2433 2434//Please don't add or expand this bitfield structure below, this one will retire soon.! 2435typedef struct _ATOM_FIRMWARE_CAPABILITY 2436{ 2437#if ATOM_BIG_ENDIAN 2438 USHORT Reserved:1; 2439 USHORT SCL2Redefined:1; 2440 USHORT PostWithoutModeSet:1; 2441 USHORT HyperMemory_Size:4; 2442 USHORT HyperMemory_Support:1; 2443 USHORT PPMode_Assigned:1; 2444 USHORT WMI_SUPPORT:1; 2445 USHORT GPUControlsBL:1; 2446 USHORT EngineClockSS_Support:1; 2447 USHORT MemoryClockSS_Support:1; 2448 USHORT ExtendedDesktopSupport:1; 2449 USHORT DualCRTC_Support:1; 2450 USHORT FirmwarePosted:1; 2451#else 2452 USHORT FirmwarePosted:1; 2453 USHORT DualCRTC_Support:1; 2454 USHORT ExtendedDesktopSupport:1; 2455 USHORT MemoryClockSS_Support:1; 2456 USHORT EngineClockSS_Support:1; 2457 USHORT GPUControlsBL:1; 2458 USHORT WMI_SUPPORT:1; 2459 USHORT PPMode_Assigned:1; 2460 USHORT HyperMemory_Support:1; 2461 USHORT HyperMemory_Size:4; 2462 USHORT PostWithoutModeSet:1; 2463 USHORT SCL2Redefined:1; 2464 USHORT Reserved:1; 2465#endif 2466}ATOM_FIRMWARE_CAPABILITY; 2467 2468typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS 2469{ 2470 ATOM_FIRMWARE_CAPABILITY sbfAccess; 2471 USHORT susAccess; 2472}ATOM_FIRMWARE_CAPABILITY_ACCESS; 2473 2474#else 2475 2476typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS 2477{ 2478 USHORT susAccess; 2479}ATOM_FIRMWARE_CAPABILITY_ACCESS; 2480 2481#endif 2482 2483typedef struct _ATOM_FIRMWARE_INFO 2484{ 2485 ATOM_COMMON_TABLE_HEADER sHeader; 2486 ULONG ulFirmwareRevision; 2487 ULONG ulDefaultEngineClock; //In 10Khz unit 2488 ULONG ulDefaultMemoryClock; //In 10Khz unit 2489 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2490 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2491 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2492 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2493 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2494 ULONG ulASICMaxEngineClock; //In 10Khz unit 2495 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2496 UCHAR ucASICMaxTemperature; 2497 UCHAR ucPadding[3]; //Don't use them 2498 ULONG aulReservedForBIOS[3]; //Don't use them 2499 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2500 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2501 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2502 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2503 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2504 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2505 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2506 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2507 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2508 USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!! 2509 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2510 USHORT usReferenceClock; //In 10Khz unit 2511 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2512 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2513 UCHAR ucDesign_ID; //Indicate what is the board design 2514 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2515}ATOM_FIRMWARE_INFO; 2516 2517typedef struct _ATOM_FIRMWARE_INFO_V1_2 2518{ 2519 ATOM_COMMON_TABLE_HEADER sHeader; 2520 ULONG ulFirmwareRevision; 2521 ULONG ulDefaultEngineClock; //In 10Khz unit 2522 ULONG ulDefaultMemoryClock; //In 10Khz unit 2523 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2524 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2525 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2526 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2527 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2528 ULONG ulASICMaxEngineClock; //In 10Khz unit 2529 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2530 UCHAR ucASICMaxTemperature; 2531 UCHAR ucMinAllowedBL_Level; 2532 UCHAR ucPadding[2]; //Don't use them 2533 ULONG aulReservedForBIOS[2]; //Don't use them 2534 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2535 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2536 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2537 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2538 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2539 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2540 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2541 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2542 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2543 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2544 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2545 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2546 USHORT usReferenceClock; //In 10Khz unit 2547 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2548 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2549 UCHAR ucDesign_ID; //Indicate what is the board design 2550 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2551}ATOM_FIRMWARE_INFO_V1_2; 2552 2553typedef struct _ATOM_FIRMWARE_INFO_V1_3 2554{ 2555 ATOM_COMMON_TABLE_HEADER sHeader; 2556 ULONG ulFirmwareRevision; 2557 ULONG ulDefaultEngineClock; //In 10Khz unit 2558 ULONG ulDefaultMemoryClock; //In 10Khz unit 2559 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2560 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2561 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2562 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2563 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2564 ULONG ulASICMaxEngineClock; //In 10Khz unit 2565 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2566 UCHAR ucASICMaxTemperature; 2567 UCHAR ucMinAllowedBL_Level; 2568 UCHAR ucPadding[2]; //Don't use them 2569 ULONG aulReservedForBIOS; //Don't use them 2570 ULONG ul3DAccelerationEngineClock;//In 10Khz unit 2571 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2572 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2573 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2574 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2575 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2576 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2577 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2578 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2579 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2580 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2581 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2582 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2583 USHORT usReferenceClock; //In 10Khz unit 2584 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2585 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2586 UCHAR ucDesign_ID; //Indicate what is the board design 2587 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2588}ATOM_FIRMWARE_INFO_V1_3; 2589 2590typedef struct _ATOM_FIRMWARE_INFO_V1_4 2591{ 2592 ATOM_COMMON_TABLE_HEADER sHeader; 2593 ULONG ulFirmwareRevision; 2594 ULONG ulDefaultEngineClock; //In 10Khz unit 2595 ULONG ulDefaultMemoryClock; //In 10Khz unit 2596 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2597 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2598 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2599 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2600 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2601 ULONG ulASICMaxEngineClock; //In 10Khz unit 2602 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2603 UCHAR ucASICMaxTemperature; 2604 UCHAR ucMinAllowedBL_Level; 2605 USHORT usBootUpVDDCVoltage; //In MV unit 2606 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 2607 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 2608 ULONG ul3DAccelerationEngineClock;//In 10Khz unit 2609 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2610 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2611 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2612 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2613 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2614 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2615 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2616 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2617 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2618 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2619 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2620 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2621 USHORT usReferenceClock; //In 10Khz unit 2622 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2623 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2624 UCHAR ucDesign_ID; //Indicate what is the board design 2625 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2626}ATOM_FIRMWARE_INFO_V1_4; 2627 2628//the structure below to be used from Cypress 2629typedef struct _ATOM_FIRMWARE_INFO_V2_1 2630{ 2631 ATOM_COMMON_TABLE_HEADER sHeader; 2632 ULONG ulFirmwareRevision; 2633 ULONG ulDefaultEngineClock; //In 10Khz unit 2634 ULONG ulDefaultMemoryClock; //In 10Khz unit 2635 ULONG ulReserved1; 2636 ULONG ulReserved2; 2637 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2638 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2639 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2640 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock 2641 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit 2642 UCHAR ucReserved1; //Was ucASICMaxTemperature; 2643 UCHAR ucMinAllowedBL_Level; 2644 USHORT usBootUpVDDCVoltage; //In MV unit 2645 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 2646 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 2647 ULONG ulReserved4; //Was ulAsicMaximumVoltage 2648 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2649 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2650 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2651 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2652 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2653 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2654 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2655 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2656 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2657 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2658 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2659 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2660 USHORT usCoreReferenceClock; //In 10Khz unit 2661 USHORT usMemoryReferenceClock; //In 10Khz unit 2662 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock 2663 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2664 UCHAR ucReserved4[3]; 2665}ATOM_FIRMWARE_INFO_V2_1; 2666 2667//the structure below to be used from NI 2668//ucTableFormatRevision=2 2669//ucTableContentRevision=2 2670typedef struct _ATOM_FIRMWARE_INFO_V2_2 2671{ 2672 ATOM_COMMON_TABLE_HEADER sHeader; 2673 ULONG ulFirmwareRevision; 2674 ULONG ulDefaultEngineClock; //In 10Khz unit 2675 ULONG ulDefaultMemoryClock; //In 10Khz unit 2676 ULONG ulSPLL_OutputFreq; //In 10Khz unit 2677 ULONG ulGPUPLL_OutputFreq; //In 10Khz unit 2678 ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit* 2679 ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit* 2680 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2681 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ? 2682 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage. 2683 UCHAR ucReserved3; //Was ucASICMaxTemperature; 2684 UCHAR ucMinAllowedBL_Level; 2685 USHORT usBootUpVDDCVoltage; //In MV unit 2686 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 2687 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 2688 ULONG ulReserved4; //Was ulAsicMaximumVoltage 2689 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2690 UCHAR ucRemoteDisplayConfig; 2691 UCHAR ucReserved5[3]; //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input 2692 ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input 2693 ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output 2694 USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz unit, Max. Pclk used only for DAC 2695 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2696 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2697 USHORT usBootUpVDDCIVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; 2698 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2699 USHORT usCoreReferenceClock; //In 10Khz unit 2700 USHORT usMemoryReferenceClock; //In 10Khz unit 2701 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock 2702 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2703 UCHAR ucReserved9[3]; 2704 USHORT usBootUpMVDDCVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; 2705 USHORT usReserved12; 2706 ULONG ulReserved10[3]; // New added comparing to previous version 2707}ATOM_FIRMWARE_INFO_V2_2; 2708 2709#define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_2 2710 2711 2712// definition of ucRemoteDisplayConfig 2713#define REMOTE_DISPLAY_DISABLE 0x00 2714#define REMOTE_DISPLAY_ENABLE 0x01 2715 2716/****************************************************************************/ 2717// Structures used in IntegratedSystemInfoTable 2718/****************************************************************************/ 2719#define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2 2720#define IGP_CAP_FLAG_AC_CARD 0x4 2721#define IGP_CAP_FLAG_SDVO_CARD 0x8 2722#define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10 2723 2724typedef struct _ATOM_INTEGRATED_SYSTEM_INFO 2725{ 2726 ATOM_COMMON_TABLE_HEADER sHeader; 2727 ULONG ulBootUpEngineClock; //in 10kHz unit 2728 ULONG ulBootUpMemoryClock; //in 10kHz unit 2729 ULONG ulMaxSystemMemoryClock; //in 10kHz unit 2730 ULONG ulMinSystemMemoryClock; //in 10kHz unit 2731 UCHAR ucNumberOfCyclesInPeriodHi; 2732 UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID. 2733 USHORT usReserved1; 2734 USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage 2735 USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage 2736 ULONG ulReserved[2]; 2737 2738 USHORT usFSBClock; //In MHz unit 2739 USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable 2740 //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card 2741 //Bit[4]==1: P/2 mode, ==0: P/1 mode 2742 USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal 2743 USHORT usK8MemoryClock; //in MHz unit 2744 USHORT usK8SyncStartDelay; //in 0.01 us unit 2745 USHORT usK8DataReturnTime; //in 0.01 us unit 2746 UCHAR ucMaxNBVoltage; 2747 UCHAR ucMinNBVoltage; 2748 UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved 2749 UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod 2750 UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime 2751 UCHAR ucHTLinkWidth; //16 bit vs. 8 bit 2752 UCHAR ucMaxNBVoltageHigh; 2753 UCHAR ucMinNBVoltageHigh; 2754}ATOM_INTEGRATED_SYSTEM_INFO; 2755 2756/* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO 2757ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock 2758 For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock 2759ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 2760 For AMD IGP,for now this can be 0 2761ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 2762 For AMD IGP,for now this can be 0 2763 2764usFSBClock: For Intel IGP,it's FSB Freq 2765 For AMD IGP,it's HT Link Speed 2766 2767usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200 2768usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation 2769usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation 2770 2771VC:Voltage Control 2772ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. 2773ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. 2774 2775ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. 2776ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 2777 2778ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. 2779ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. 2780 2781 2782usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all. 2783usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all. 2784*/ 2785 2786 2787/* 2788The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST; 2789Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. 2790The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries. 2791 2792SW components can access the IGP system infor structure in the same way as before 2793*/ 2794 2795 2796typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 2797{ 2798 ATOM_COMMON_TABLE_HEADER sHeader; 2799 ULONG ulBootUpEngineClock; //in 10kHz unit 2800 ULONG ulReserved1[2]; //must be 0x0 for the reserved 2801 ULONG ulBootUpUMAClock; //in 10kHz unit 2802 ULONG ulBootUpSidePortClock; //in 10kHz unit 2803 ULONG ulMinSidePortClock; //in 10kHz unit 2804 ULONG ulReserved2[6]; //must be 0x0 for the reserved 2805 ULONG ulSystemConfig; //see explanation below 2806 ULONG ulBootUpReqDisplayVector; 2807 ULONG ulOtherDisplayMisc; 2808 ULONG ulDDISlot1Config; 2809 ULONG ulDDISlot2Config; 2810 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved 2811 UCHAR ucUMAChannelNumber; 2812 UCHAR ucDockingPinBit; 2813 UCHAR ucDockingPinPolarity; 2814 ULONG ulDockingPinCFGInfo; 2815 ULONG ulCPUCapInfo; 2816 USHORT usNumberOfCyclesInPeriod; 2817 USHORT usMaxNBVoltage; 2818 USHORT usMinNBVoltage; 2819 USHORT usBootUpNBVoltage; 2820 ULONG ulHTLinkFreq; //in 10Khz 2821 USHORT usMinHTLinkWidth; 2822 USHORT usMaxHTLinkWidth; 2823 USHORT usUMASyncStartDelay; 2824 USHORT usUMADataReturnTime; 2825 USHORT usLinkStatusZeroTime; 2826 USHORT usDACEfuse; //for storing badgap value (for RS880 only) 2827 ULONG ulHighVoltageHTLinkFreq; // in 10Khz 2828 ULONG ulLowVoltageHTLinkFreq; // in 10Khz 2829 USHORT usMaxUpStreamHTLinkWidth; 2830 USHORT usMaxDownStreamHTLinkWidth; 2831 USHORT usMinUpStreamHTLinkWidth; 2832 USHORT usMinDownStreamHTLinkWidth; 2833 USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW. 2834 USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us. 2835 ULONG ulReserved3[96]; //must be 0x0 2836}ATOM_INTEGRATED_SYSTEM_INFO_V2; 2837 2838/* 2839ulBootUpEngineClock: Boot-up Engine Clock in 10Khz; 2840ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present 2841ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock 2842 2843ulSystemConfig: 2844Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode; 2845Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state 2846 =0: system boots up at driver control state. Power state depends on PowerPlay table. 2847Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used. 2848Bit[3]=1: Only one power state(Performance) will be supported. 2849 =0: Multiple power states supported from PowerPlay table. 2850Bit[4]=1: CLMC is supported and enabled on current system. 2851 =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface. 2852Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement. 2853 =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied. 2854Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored. 2855 =0: Voltage settings is determined by powerplay table. 2856Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue. 2857 =0: Enable CLMC as regular mode, CDLD and CILR will be enabled. 2858Bit[8]=1: CDLF is supported and enabled on current system. 2859 =0: CDLF is not supported or enabled on current system. 2860Bit[9]=1: DLL Shut Down feature is enabled on current system. 2861 =0: DLL Shut Down feature is not enabled or supported on current system. 2862 2863ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions. 2864 2865ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion; 2866 [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSupportedStd definition; 2867 2868ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design). 2869 [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) 2870 [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12) 2871 When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time. 2872 in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example: 2873 one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2. 2874 2875 [15:8] - Lane configuration attribute; 2876 [23:16]- Connector type, possible value: 2877 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 2878 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D 2879 CONNECTOR_OBJECT_ID_HDMI_TYPE_A 2880 CONNECTOR_OBJECT_ID_DISPLAYPORT 2881 CONNECTOR_OBJECT_ID_eDP 2882 [31:24]- Reserved 2883 2884ulDDISlot2Config: Same as Slot1. 2885ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC. 2886For IGP, Hypermemory is the only memory type showed in CCC. 2887 2888ucUMAChannelNumber: how many channels for the UMA; 2889 2890ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin 2891ucDockingPinBit: which bit in this register to read the pin status; 2892ucDockingPinPolarity:Polarity of the pin when docked; 2893 2894ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0 2895 2896usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%. 2897 2898usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode. 2899usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode. 2900 GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0 2901 PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1 2902 GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 2903 2904usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value. 2905 2906ulHTLinkFreq: Bootup HT link Frequency in 10Khz. 2907usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth. 2908 If CDLW enabled, both upstream and downstream width should be the same during bootup. 2909usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth. 2910 If CDLW enabled, both upstream and downstream width should be the same during bootup. 2911 2912usUMASyncStartDelay: Memory access latency, required for watermark calculation 2913usUMADataReturnTime: Memory access latency, required for watermark calculation 2914usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us 2915for Griffin or Greyhound. SBIOS needs to convert to actual time by: 2916 if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us) 2917 if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us) 2918 if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us) 2919 if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us) 2920 2921ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0. 2922 This must be less than or equal to ulHTLinkFreq(bootup frequency). 2923ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0. 2924 This must be less than or equal to ulHighVoltageHTLinkFreq. 2925 2926usMaxUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now. 2927usMaxDownStreamHTLinkWidth: same as above. 2928usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now. 2929usMinDownStreamHTLinkWidth: same as above. 2930*/ 2931 2932// ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition 2933#define INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU 0 2934#define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN 1 2935#define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND 2 2936#define INTEGRATED_SYSTEM_INFO__AMD_CPU__K8 3 2937#define INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH 4 2938#define INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI 5 2939 2940#define INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI // this deff reflects max defined CPU code 2941 2942#define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001 2943#define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002 2944#define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004 2945#define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008 2946#define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010 2947#define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020 2948#define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x00000040 2949#define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x00000080 2950#define SYSTEM_CONFIG_CDLF_ENABLED 0x00000100 2951#define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED 0x00000200 2952 2953#define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF 2954 2955#define b0IGP_DDI_SLOT_LANE_MAP_MASK 0x0F 2956#define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK 0xF0 2957#define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 0x01 2958#define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 0x02 2959#define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 0x04 2960#define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 0x08 2961 2962#define IGP_DDI_SLOT_ATTRIBUTE_MASK 0x0000FF00 2963#define IGP_DDI_SLOT_CONFIG_REVERSED 0x00000100 2964#define b1IGP_DDI_SLOT_CONFIG_REVERSED 0x01 2965 2966#define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000 2967 2968// IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR 2969typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 2970{ 2971 ATOM_COMMON_TABLE_HEADER sHeader; 2972 ULONG ulBootUpEngineClock; //in 10kHz unit 2973 ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK. 2974 ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge 2975 ULONG ulBootUpUMAClock; //in 10kHz unit 2976 ULONG ulReserved1[8]; //must be 0x0 for the reserved 2977 ULONG ulBootUpReqDisplayVector; 2978 ULONG ulOtherDisplayMisc; 2979 ULONG ulReserved2[4]; //must be 0x0 for the reserved 2980 ULONG ulSystemConfig; //TBD 2981 ULONG ulCPUCapInfo; //TBD 2982 USHORT usMaxNBVoltage; //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; 2983 USHORT usMinNBVoltage; //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; 2984 USHORT usBootUpNBVoltage; //boot up NB voltage 2985 UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD 2986 UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD 2987 ULONG ulReserved3[4]; //must be 0x0 for the reserved 2988 ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition 2989 ULONG ulDDISlot2Config; 2990 ULONG ulDDISlot3Config; 2991 ULONG ulDDISlot4Config; 2992 ULONG ulReserved4[4]; //must be 0x0 for the reserved 2993 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved 2994 UCHAR ucUMAChannelNumber; 2995 USHORT usReserved; 2996 ULONG ulReserved5[4]; //must be 0x0 for the reserved 2997 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default 2998 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback 2999 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications 3000 ULONG ulReserved6[61]; //must be 0x0
3001}ATOM_INTEGRATED_SYSTEM_INFO_V5; 3002 3003#define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000 3004#define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001 3005#define ATOM_TV_INT_ENCODER1_INDEX 0x00000002 3006#define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003 3007#define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004 3008#define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005 3009#define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006 3010#define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007 3011#define ATOM_CV_INT_ENCODER1_INDEX 0x00000008 3012#define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009 3013#define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A 3014#define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B 3015#define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C 3016#define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D 3017 3018// define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable 3019#define ASIC_INT_DAC1_ENCODER_ID 0x00 3020#define ASIC_INT_TV_ENCODER_ID 0x02 3021#define ASIC_INT_DIG1_ENCODER_ID 0x03 3022#define ASIC_INT_DAC2_ENCODER_ID 0x04 3023#define ASIC_EXT_TV_ENCODER_ID 0x06 3024#define ASIC_INT_DVO_ENCODER_ID 0x07 3025#define ASIC_INT_DIG2_ENCODER_ID 0x09 3026#define ASIC_EXT_DIG_ENCODER_ID 0x05 3027#define ASIC_EXT_DIG2_ENCODER_ID 0x08 3028#define ASIC_INT_DIG3_ENCODER_ID 0x0a 3029#define ASIC_INT_DIG4_ENCODER_ID 0x0b 3030#define ASIC_INT_DIG5_ENCODER_ID 0x0c 3031#define ASIC_INT_DIG6_ENCODER_ID 0x0d 3032#define ASIC_INT_DIG7_ENCODER_ID 0x0e 3033 3034//define Encoder attribute 3035#define ATOM_ANALOG_ENCODER 0 3036#define ATOM_DIGITAL_ENCODER 1 3037#define ATOM_DP_ENCODER 2 3038 3039#define ATOM_ENCODER_ENUM_MASK 0x70 3040#define ATOM_ENCODER_ENUM_ID1 0x00 3041#define ATOM_ENCODER_ENUM_ID2 0x10 3042#define ATOM_ENCODER_ENUM_ID3 0x20 3043#define ATOM_ENCODER_ENUM_ID4 0x30 3044#define ATOM_ENCODER_ENUM_ID5 0x40 3045#define ATOM_ENCODER_ENUM_ID6 0x50 3046 3047#define ATOM_DEVICE_CRT1_INDEX 0x00000000 3048#define ATOM_DEVICE_LCD1_INDEX 0x00000001 3049#define ATOM_DEVICE_TV1_INDEX 0x00000002 3050#define ATOM_DEVICE_DFP1_INDEX 0x00000003 3051#define ATOM_DEVICE_CRT2_INDEX 0x00000004 3052#define ATOM_DEVICE_LCD2_INDEX 0x00000005 3053#define ATOM_DEVICE_DFP6_INDEX 0x00000006 3054#define ATOM_DEVICE_DFP2_INDEX 0x00000007 3055#define ATOM_DEVICE_CV_INDEX 0x00000008 3056#define ATOM_DEVICE_DFP3_INDEX 0x00000009 3057#define ATOM_DEVICE_DFP4_INDEX 0x0000000A 3058#define ATOM_DEVICE_DFP5_INDEX 0x0000000B 3059 3060#define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C 3061#define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D 3062#define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E 3063#define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F 3064#define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1) 3065#define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO 3066#define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1 ) 3067 3068#define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1) 3069 3070#define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX ) 3071#define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX ) 3072#define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX ) 3073#define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX ) 3074#define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX ) 3075#define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX ) 3076#define ATOM_DEVICE_DFP6_SUPPORT (0x1L << ATOM_DEVICE_DFP6_INDEX ) 3077#define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX ) 3078#define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX ) 3079#define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX ) 3080#define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX ) 3081#define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX ) 3082 3083#define ATOM_DEVICE_CRT_SUPPORT (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT) 3084#define ATOM_DEVICE_DFP_SUPPORT (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT) 3085#define ATOM_DEVICE_TV_SUPPORT (ATOM_DEVICE_TV1_SUPPORT) 3086#define ATOM_DEVICE_LCD_SUPPORT (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT) 3087 3088#define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0 3089#define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004 3090#define ATOM_DEVICE_CONNECTOR_VGA 0x00000001 3091#define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002 3092#define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003 3093#define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004 3094#define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005 3095#define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006 3096#define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007 3097#define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008 3098#define ATOM_DEVICE_CONNECTOR_SCART 0x00000009 3099#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A 3100#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B 3101#define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E 3102#define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F 3103 3104 3105#define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F 3106#define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000 3107#define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000 3108#define ATOM_DEVICE_DAC_INFO_DACA 0x00000001 3109#define ATOM_DEVICE_DAC_INFO_DACB 0x00000002 3110#define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003 3111 3112#define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000 3113 3114#define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F 3115#define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000 3116 3117#define ATOM_DEVICE_I2C_ID_MASK 0x00000070 3118#define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004 3119#define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001 3120#define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002 3121#define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600 3122#define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690 3123 3124#define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080 3125#define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007 3126#define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000 3127#define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001 3128 3129// usDeviceSupport: 3130// Bits0 = 0 - no CRT1 support= 1- CRT1 is supported 3131// Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported 3132// Bit 2 = 0 - no TV1 support= 1- TV1 is supported 3133// Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported 3134// Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported 3135// Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported 3136// Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported 3137// Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported 3138// Bit 8 = 0 - no CV support= 1- CV is supported 3139// Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported 3140// Bit 10 = 0 - no DFP4 support= 1- DFP4 is supported 3141// Bit 11 = 0 - no DFP5 support= 1- DFP5 is supported 3142// 3143// 3144 3145/****************************************************************************/ 3146/* Structure used in MclkSS_InfoTable */ 3147/****************************************************************************/ 3148// ucI2C_ConfigID 3149// [7:0] - I2C LINE Associate ID 3150// = 0 - no I2C 3151// [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection) 3152// = 0, [6:0]=SW assisted I2C ID 3153// [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use 3154// = 2, HW engine for Multimedia use 3155// = 3-7 Reserved for future I2C engines 3156// [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C 3157 3158typedef struct _ATOM_I2C_ID_CONFIG 3159{ 3160#if ATOM_BIG_ENDIAN 3161 UCHAR bfHW_Capable:1; 3162 UCHAR bfHW_EngineID:3; 3163 UCHAR bfI2C_LineMux:4; 3164#else 3165 UCHAR bfI2C_LineMux:4; 3166 UCHAR bfHW_EngineID:3; 3167 UCHAR bfHW_Capable:1; 3168#endif 3169}ATOM_I2C_ID_CONFIG; 3170 3171typedef union _ATOM_I2C_ID_CONFIG_ACCESS 3172{ 3173 ATOM_I2C_ID_CONFIG sbfAccess; 3174 UCHAR ucAccess; 3175}ATOM_I2C_ID_CONFIG_ACCESS; 3176 3177 3178/****************************************************************************/ 3179// Structure used in GPIO_I2C_InfoTable 3180/****************************************************************************/ 3181typedef struct _ATOM_GPIO_I2C_ASSIGMENT 3182{ 3183 USHORT usClkMaskRegisterIndex; 3184 USHORT usClkEnRegisterIndex; 3185 USHORT usClkY_RegisterIndex; 3186 USHORT usClkA_RegisterIndex; 3187 USHORT usDataMaskRegisterIndex; 3188 USHORT usDataEnRegisterIndex; 3189 USHORT usDataY_RegisterIndex; 3190 USHORT usDataA_RegisterIndex; 3191 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 3192 UCHAR ucClkMaskShift; 3193 UCHAR ucClkEnShift; 3194 UCHAR ucClkY_Shift; 3195 UCHAR ucClkA_Shift; 3196 UCHAR ucDataMaskShift; 3197 UCHAR ucDataEnShift; 3198 UCHAR ucDataY_Shift; 3199 UCHAR ucDataA_Shift; 3200 UCHAR ucReserved1; 3201 UCHAR ucReserved2; 3202}ATOM_GPIO_I2C_ASSIGMENT; 3203 3204typedef struct _ATOM_GPIO_I2C_INFO 3205{ 3206 ATOM_COMMON_TABLE_HEADER sHeader; 3207 ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE]; 3208}ATOM_GPIO_I2C_INFO; 3209 3210/****************************************************************************/ 3211// Common Structure used in other structures 3212/****************************************************************************/ 3213 3214#ifndef _H2INC 3215 3216//Please don't add or expand this bitfield structure below, this one will retire soon.! 3217typedef struct _ATOM_MODE_MISC_INFO 3218{ 3219#if ATOM_BIG_ENDIAN 3220 USHORT Reserved:6; 3221 USHORT RGB888:1; 3222 USHORT DoubleClock:1; 3223 USHORT Interlace:1; 3224 USHORT CompositeSync:1; 3225 USHORT V_ReplicationBy2:1; 3226 USHORT H_ReplicationBy2:1; 3227 USHORT VerticalCutOff:1; 3228 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low 3229 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low 3230 USHORT HorizontalCutOff:1; 3231#else 3232 USHORT HorizontalCutOff:1; 3233 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low 3234 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low 3235 USHORT VerticalCutOff:1; 3236 USHORT H_ReplicationBy2:1; 3237 USHORT V_ReplicationBy2:1; 3238 USHORT CompositeSync:1; 3239 USHORT Interlace:1; 3240 USHORT DoubleClock:1; 3241 USHORT RGB888:1; 3242 USHORT Reserved:6; 3243#endif 3244}ATOM_MODE_MISC_INFO; 3245 3246typedef union _ATOM_MODE_MISC_INFO_ACCESS 3247{ 3248 ATOM_MODE_MISC_INFO sbfAccess; 3249 USHORT usAccess; 3250}ATOM_MODE_MISC_INFO_ACCESS; 3251 3252#else 3253 3254typedef union _ATOM_MODE_MISC_INFO_ACCESS 3255{ 3256 USHORT usAccess; 3257}ATOM_MODE_MISC_INFO_ACCESS; 3258 3259#endif 3260 3261// usModeMiscInfo- 3262#define ATOM_H_CUTOFF 0x01 3263#define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low 3264#define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low 3265#define ATOM_V_CUTOFF 0x08 3266#define ATOM_H_REPLICATIONBY2 0x10 3267#define ATOM_V_REPLICATIONBY2 0x20 3268#define ATOM_COMPOSITESYNC 0x40 3269#define ATOM_INTERLACE 0x80 3270#define ATOM_DOUBLE_CLOCK_MODE 0x100 3271#define ATOM_RGB888_MODE 0x200 3272 3273//usRefreshRate- 3274#define ATOM_REFRESH_43 43 3275#define ATOM_REFRESH_47 47 3276#define ATOM_REFRESH_56 56 3277#define ATOM_REFRESH_60 60 3278#define ATOM_REFRESH_65 65 3279#define ATOM_REFRESH_70 70 3280#define ATOM_REFRESH_72 72 3281#define ATOM_REFRESH_75 75 3282#define ATOM_REFRESH_85 85 3283 3284// ATOM_MODE_TIMING data are exactly the same as VESA timing data. 3285// Translation from EDID to ATOM_MODE_TIMING, use the following formula. 3286// 3287// VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK 3288// = EDID_HA + EDID_HBL 3289// VESA_HDISP = VESA_ACTIVE = EDID_HA 3290// VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH 3291// = EDID_HA + EDID_HSO 3292// VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW 3293// VESA_BORDER = EDID_BORDER 3294 3295/****************************************************************************/ 3296// Structure used in SetCRTC_UsingDTDTimingTable 3297/****************************************************************************/ 3298typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS 3299{ 3300 USHORT usH_Size; 3301 USHORT usH_Blanking_Time; 3302 USHORT usV_Size; 3303 USHORT usV_Blanking_Time; 3304 USHORT usH_SyncOffset; 3305 USHORT usH_SyncWidth; 3306 USHORT usV_SyncOffset; 3307 USHORT usV_SyncWidth; 3308 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3309 UCHAR ucH_Border; // From DFP EDID 3310 UCHAR ucV_Border; 3311 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 3312 UCHAR ucPadding[3]; 3313}SET_CRTC_USING_DTD_TIMING_PARAMETERS; 3314 3315/****************************************************************************/ 3316// Structure used in SetCRTC_TimingTable 3317/****************************************************************************/ 3318typedef struct _SET_CRTC_TIMING_PARAMETERS 3319{ 3320 USHORT usH_Total; // horizontal total 3321 USHORT usH_Disp; // horizontal display 3322 USHORT usH_SyncStart; // horozontal Sync start 3323 USHORT usH_SyncWidth; // horizontal Sync width 3324 USHORT usV_Total; // vertical total 3325 USHORT usV_Disp; // vertical display 3326 USHORT usV_SyncStart; // vertical Sync start 3327 USHORT usV_SyncWidth; // vertical Sync width 3328 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3329 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 3330 UCHAR ucOverscanRight; // right 3331 UCHAR ucOverscanLeft; // left 3332 UCHAR ucOverscanBottom; // bottom 3333 UCHAR ucOverscanTop; // top 3334 UCHAR ucReserved; 3335}SET_CRTC_TIMING_PARAMETERS; 3336#define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS 3337 3338/****************************************************************************/ 3339// Structure used in StandardVESA_TimingTable 3340// AnalogTV_InfoTable 3341// ComponentVideoInfoTable 3342/****************************************************************************/ 3343typedef struct _ATOM_MODE_TIMING 3344{ 3345 USHORT usCRTC_H_Total; 3346 USHORT usCRTC_H_Disp; 3347 USHORT usCRTC_H_SyncStart; 3348 USHORT usCRTC_H_SyncWidth; 3349 USHORT usCRTC_V_Total; 3350 USHORT usCRTC_V_Disp; 3351 USHORT usCRTC_V_SyncStart; 3352 USHORT usCRTC_V_SyncWidth; 3353 USHORT usPixelClock; //in 10Khz unit 3354 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3355 USHORT usCRTC_OverscanRight; 3356 USHORT usCRTC_OverscanLeft; 3357 USHORT usCRTC_OverscanBottom; 3358 USHORT usCRTC_OverscanTop; 3359 USHORT usReserve; 3360 UCHAR ucInternalModeNumber; 3361 UCHAR ucRefreshRate; 3362}ATOM_MODE_TIMING; 3363 3364typedef struct _ATOM_DTD_FORMAT 3365{ 3366 USHORT usPixClk; 3367 USHORT usHActive; 3368 USHORT usHBlanking_Time; 3369 USHORT usVActive; 3370 USHORT usVBlanking_Time; 3371 USHORT usHSyncOffset; 3372 USHORT usHSyncWidth; 3373 USHORT usVSyncOffset; 3374 USHORT usVSyncWidth; 3375 USHORT usImageHSize; 3376 USHORT usImageVSize; 3377 UCHAR ucHBorder; 3378 UCHAR ucVBorder; 3379 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3380 UCHAR ucInternalModeNumber; 3381 UCHAR ucRefreshRate; 3382}ATOM_DTD_FORMAT; 3383 3384/****************************************************************************/ 3385// Structure used in LVDS_InfoTable 3386// * Need a document to describe this table 3387/****************************************************************************/ 3388#define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 3389#define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 3390#define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 3391#define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 3392 3393//ucTableFormatRevision=1 3394//ucTableContentRevision=1 3395typedef struct _ATOM_LVDS_INFO 3396{ 3397 ATOM_COMMON_TABLE_HEADER sHeader; 3398 ATOM_DTD_FORMAT sLCDTiming; 3399 USHORT usModePatchTableOffset; 3400 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3401 USHORT usOffDelayInMs; 3402 UCHAR ucPowerSequenceDigOntoDEin10Ms; 3403 UCHAR ucPowerSequenceDEtoBLOnin10Ms; 3404 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} 3405 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 3406 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} 3407 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} 3408 UCHAR ucPanelDefaultRefreshRate; 3409 UCHAR ucPanelIdentification; 3410 UCHAR ucSS_Id; 3411}ATOM_LVDS_INFO; 3412 3413//ucTableFormatRevision=1 3414//ucTableContentRevision=2 3415typedef struct _ATOM_LVDS_INFO_V12 3416{ 3417 ATOM_COMMON_TABLE_HEADER sHeader; 3418 ATOM_DTD_FORMAT sLCDTiming; 3419 USHORT usExtInfoTableOffset; 3420 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3421 USHORT usOffDelayInMs; 3422 UCHAR ucPowerSequenceDigOntoDEin10Ms; 3423 UCHAR ucPowerSequenceDEtoBLOnin10Ms; 3424 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} 3425 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 3426 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} 3427 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} 3428 UCHAR ucPanelDefaultRefreshRate; 3429 UCHAR ucPanelIdentification; 3430 UCHAR ucSS_Id; 3431 USHORT usLCDVenderID; 3432 USHORT usLCDProductID; 3433 UCHAR ucLCDPanel_SpecialHandlingCap; 3434 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable 3435 UCHAR ucReserved[2]; 3436}ATOM_LVDS_INFO_V12; 3437 3438//Definitions for ucLCDPanel_SpecialHandlingCap: 3439 3440//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. 3441//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL 3442#define LCDPANEL_CAP_READ_EDID 0x1 3443 3444//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together 3445//with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static 3446//refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 3447#define LCDPANEL_CAP_DRR_SUPPORTED 0x2 3448 3449//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. 3450#define LCDPANEL_CAP_eDP 0x4 3451 3452 3453//Color Bit Depth definition in EDID V1.4 @BYTE 14h 3454//Bit 6 5 4 3455 // 0 0 0 - Color bit depth is undefined 3456 // 0 0 1 - 6 Bits per Primary Color 3457 // 0 1 0 - 8 Bits per Primary Color 3458 // 0 1 1 - 10 Bits per Primary Color 3459 // 1 0 0 - 12 Bits per Primary Color 3460 // 1 0 1 - 14 Bits per Primary Color 3461 // 1 1 0 - 16 Bits per Primary Color 3462 // 1 1 1 - Reserved 3463 3464#define PANEL_COLOR_BIT_DEPTH_MASK 0x70 3465 3466// Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled} 3467#define PANEL_RANDOM_DITHER 0x80 3468#define PANEL_RANDOM_DITHER_MASK 0x80 3469 3470#define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 // no need to change this 3471 3472/****************************************************************************/ 3473// Structures used by LCD_InfoTable V1.3 Note: previous version was called ATOM_LVDS_INFO_V12 3474// ASIC Families: NI 3475// ucTableFormatRevision=1 3476// ucTableContentRevision=3 3477/****************************************************************************/ 3478typedef struct _ATOM_LCD_INFO_V13 3479{ 3480 ATOM_COMMON_TABLE_HEADER sHeader; 3481 ATOM_DTD_FORMAT sLCDTiming; 3482 USHORT usExtInfoTableOffset; 3483 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3484 ULONG ulReserved0; 3485 UCHAR ucLCD_Misc; // Reorganized in V13 3486 // Bit0: {=0:single, =1:dual}, 3487 // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888} // was {=0:666RGB, =1:888RGB}, 3488 // Bit3:2: {Grey level} 3489 // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h) 3490 // Bit7 Reserved. was for ATOM_PANEL_MISC_API_ENABLED, still need it? 3491 UCHAR ucPanelDefaultRefreshRate; 3492 UCHAR ucPanelIdentification; 3493 UCHAR ucSS_Id; 3494 USHORT usLCDVenderID; 3495 USHORT usLCDProductID; 3496 UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13 3497 // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own 3498 // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED 3499 // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1) 3500 // Bit7-3: Reserved 3501 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable 3502 USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13 3503 3504 UCHAR ucPowerSequenceDIGONtoDE_in4Ms; 3505 UCHAR ucPowerSequenceDEtoVARY_BL_in4Ms; 3506 UCHAR ucPowerSequenceVARY_BLtoDE_in4Ms; 3507 UCHAR ucPowerSequenceDEtoDIGON_in4Ms; 3508 3509 UCHAR ucOffDelay_in4Ms; 3510 UCHAR ucPowerSequenceVARY_BLtoBLON_in4Ms; 3511 UCHAR ucPowerSequenceBLONtoVARY_BL_in4Ms; 3512 UCHAR ucReserved1; 3513 3514 UCHAR ucDPCD_eDP_CONFIGURATION_CAP; // dpcd 0dh 3515 UCHAR ucDPCD_MAX_LINK_RATE; // dpcd 01h 3516 UCHAR ucDPCD_MAX_LANE_COUNT; // dpcd 02h 3517 UCHAR ucDPCD_MAX_DOWNSPREAD; // dpcd 03h 3518 3519 USHORT usMaxPclkFreqInSingleLink; // Max PixelClock frequency in single link mode. 3520 UCHAR uceDPToLVDSRxId; 3521 UCHAR ucLcdReservd; 3522 ULONG ulReserved[2]; 3523}ATOM_LCD_INFO_V13; 3524 3525#define ATOM_LCD_INFO_LAST ATOM_LCD_INFO_V13 3526 3527//Definitions for ucLCD_Misc 3528#define ATOM_PANEL_MISC_V13_DUAL 0x00000001 3529#define ATOM_PANEL_MISC_V13_FPDI 0x00000002 3530#define ATOM_PANEL_MISC_V13_GREY_LEVEL 0x0000000C 3531#define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT 2 3532#define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK 0x70 3533#define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR 0x10 3534#define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR 0x20 3535 3536//Color Bit Depth definition in EDID V1.4 @BYTE 14h 3537//Bit 6 5 4 3538 // 0 0 0 - Color bit depth is undefined 3539 // 0 0 1 - 6 Bits per Primary Color 3540 // 0 1 0 - 8 Bits per Primary Color 3541 // 0 1 1 - 10 Bits per Primary Color 3542 // 1 0 0 - 12 Bits per Primary Color 3543 // 1 0 1 - 14 Bits per Primary Color 3544 // 1 1 0 - 16 Bits per Primary Color 3545 // 1 1 1 - Reserved 3546 3547//Definitions for ucLCDPanel_SpecialHandlingCap: 3548 3549//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. 3550//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL 3551#define LCDPANEL_CAP_V13_READ_EDID 0x1 // = LCDPANEL_CAP_READ_EDID no change comparing to previous version 3552 3553//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together 3554//with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static 3555//refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 3556#define LCDPANEL_CAP_V13_DRR_SUPPORTED 0x2 // = LCDPANEL_CAP_DRR_SUPPORTED no change comparing to previous version 3557 3558//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. 3559#define LCDPANEL_CAP_V13_eDP 0x4 // = LCDPANEL_CAP_eDP no change comparing to previous version 3560 3561//uceDPToLVDSRxId 3562#define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip 3563#define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip without AMD SW init 3564#define eDP_TO_LVDS_RT_ID 0x02 // RT tanslator which require AMD SW init 3565 3566typedef struct _ATOM_PATCH_RECORD_MODE 3567{ 3568 UCHAR ucRecordType; 3569 USHORT usHDisp; 3570 USHORT usVDisp; 3571}ATOM_PATCH_RECORD_MODE; 3572 3573typedef struct _ATOM_LCD_RTS_RECORD 3574{ 3575 UCHAR ucRecordType; 3576 UCHAR ucRTSValue; 3577}ATOM_LCD_RTS_RECORD; 3578 3579//!! If the record below exits, it shoud always be the first record for easy use in command table!!! 3580// The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead. 3581typedef struct _ATOM_LCD_MODE_CONTROL_CAP 3582{ 3583 UCHAR ucRecordType; 3584 USHORT usLCDCap; 3585}ATOM_LCD_MODE_CONTROL_CAP; 3586 3587#define LCD_MODE_CAP_BL_OFF 1 3588#define LCD_MODE_CAP_CRTC_OFF 2 3589#define LCD_MODE_CAP_PANEL_OFF 4 3590 3591typedef struct _ATOM_FAKE_EDID_PATCH_RECORD 3592{ 3593 UCHAR ucRecordType; 3594 UCHAR ucFakeEDIDLength; 3595 UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements. 3596} ATOM_FAKE_EDID_PATCH_RECORD; 3597 3598typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD 3599{ 3600 UCHAR ucRecordType; 3601 USHORT usHSize; 3602 USHORT usVSize; 3603}ATOM_PANEL_RESOLUTION_PATCH_RECORD; 3604 3605#define LCD_MODE_PATCH_RECORD_MODE_TYPE 1 3606#define LCD_RTS_RECORD_TYPE 2 3607#define LCD_CAP_RECORD_TYPE 3 3608#define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4 3609#define LCD_PANEL_RESOLUTION_RECORD_TYPE 5 3610#define LCD_EDID_OFFSET_PATCH_RECORD_TYPE 6 3611#define ATOM_RECORD_END_TYPE 0xFF 3612 3613/****************************Spread Spectrum Info Table Definitions **********************/ 3614 3615//ucTableFormatRevision=1 3616//ucTableContentRevision=2 3617typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT 3618{ 3619 USHORT usSpreadSpectrumPercentage; 3620 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD 3621 UCHAR ucSS_Step; 3622 UCHAR ucSS_Delay; 3623 UCHAR ucSS_Id; 3624 UCHAR ucRecommendedRef_Div; 3625 UCHAR ucSS_Range; //it was reserved for V11 3626}ATOM_SPREAD_SPECTRUM_ASSIGNMENT; 3627 3628#define ATOM_MAX_SS_ENTRY 16 3629#define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well. 3630#define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable. 3631#define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz 3632#define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz 3633 3634 3635#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 3636#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 3637#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 3638#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 3639#define ATOM_INTERNAL_SS_MASK 0x00000000 3640#define ATOM_EXTERNAL_SS_MASK 0x00000002 3641#define EXEC_SS_STEP_SIZE_SHIFT 2 3642#define EXEC_SS_DELAY_SHIFT 4 3643#define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4 3644 3645typedef struct _ATOM_SPREAD_SPECTRUM_INFO 3646{ 3647 ATOM_COMMON_TABLE_HEADER sHeader; 3648 ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY]; 3649}ATOM_SPREAD_SPECTRUM_INFO; 3650 3651/****************************************************************************/ 3652// Structure used in AnalogTV_InfoTable (Top level) 3653/****************************************************************************/ 3654//ucTVBootUpDefaultStd definition: 3655 3656//ATOM_TV_NTSC 1 3657//ATOM_TV_NTSCJ 2 3658//ATOM_TV_PAL 3 3659//ATOM_TV_PALM 4 3660//ATOM_TV_PALCN 5 3661//ATOM_TV_PALN 6 3662//ATOM_TV_PAL60 7 3663//ATOM_TV_SECAM 8 3664 3665//ucTVSupportedStd definition: 3666#define NTSC_SUPPORT 0x1 3667#define NTSCJ_SUPPORT 0x2 3668 3669#define PAL_SUPPORT 0x4 3670#define PALM_SUPPORT 0x8 3671#define PALCN_SUPPORT 0x10 3672#define PALN_SUPPORT 0x20 3673#define PAL60_SUPPORT 0x40 3674#define SECAM_SUPPORT 0x80 3675 3676#define MAX_SUPPORTED_TV_TIMING 2 3677 3678typedef struct _ATOM_ANALOG_TV_INFO 3679{ 3680 ATOM_COMMON_TABLE_HEADER sHeader; 3681 UCHAR ucTV_SupportedStandard; 3682 UCHAR ucTV_BootUpDefaultStandard; 3683 UCHAR ucExt_TV_ASIC_ID; 3684 UCHAR ucExt_TV_ASIC_SlaveAddr; 3685 /*ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING];*/ 3686 ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING]; 3687}ATOM_ANALOG_TV_INFO; 3688 3689#define MAX_SUPPORTED_TV_TIMING_V1_2 3 3690 3691typedef struct _ATOM_ANALOG_TV_INFO_V1_2 3692{ 3693 ATOM_COMMON_TABLE_HEADER sHeader; 3694 UCHAR ucTV_SupportedStandard; 3695 UCHAR ucTV_BootUpDefaultStandard; 3696 UCHAR ucExt_TV_ASIC_ID; 3697 UCHAR ucExt_TV_ASIC_SlaveAddr; 3698 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING_V1_2]; 3699}ATOM_ANALOG_TV_INFO_V1_2; 3700 3701typedef struct _ATOM_DPCD_INFO 3702{ 3703 UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1 3704 UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane 3705 UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP 3706 UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec) 3707}ATOM_DPCD_INFO; 3708 3709#define ATOM_DPCD_MAX_LANE_MASK 0x1F 3710 3711/**************************************************************************/ 3712// VRAM usage and their defintions 3713 3714// One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. 3715// Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. 3716// All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned! 3717// To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR 3718// To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX 3719 3720#ifndef VESA_MEMORY_IN_64K_BLOCK 3721#define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!) 3722#endif 3723 3724#define ATOM_EDID_RAW_DATASIZE 256 //In Bytes 3725#define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes 3726#define ATOM_HWICON_INFOTABLE_SIZE 32 3727#define MAX_DTD_MODE_IN_VRAM 6 3728#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) 3729#define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) 3730//20 bytes for Encoder Type and DPCD in STD EDID area 3731#define DFP_ENCODER_TYPE_OFFSET (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20) 3732#define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 ) 3733 3734#define ATOM_HWICON1_SURFACE_ADDR 0 3735#define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) 3736#define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) 3737#define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE) 3738#define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3739#define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3740 3741#define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3742#define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3743#define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3744 3745#define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3746 3747#define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3748#define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3749#define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3750 3751#define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3752#define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3753#define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3754 3755#define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3756#define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3757#define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3758 3759#define ATOM_DFP6_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3760#define ATOM_DFP6_DTD_MODE_TBL_ADDR (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3761#define ATOM_DFP6_STD_MODE_TBL_ADDR (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3762 3763#define ATOM_DFP2_EDID_ADDR (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3764#define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3765#define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3766 3767#define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3768#define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3769#define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3770 3771#define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3772#define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3773#define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3774 3775#define ATOM_DFP4_EDID_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3776#define ATOM_DFP4_DTD_MODE_TBL_ADDR (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3777#define ATOM_DFP4_STD_MODE_TBL_ADDR (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3778 3779#define ATOM_DFP5_EDID_ADDR (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3780#define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3781#define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3782 3783#define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3784 3785#define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 1024) 3786#define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START + 512 3787 3788//The size below is in Kb! 3789#define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC) 3790 3791#define ATOM_VRAM_RESERVE_V2_SIZE 32 3792 3793#define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L 3794#define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30 3795#define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1 3796#define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0 3797 3798/***********************************************************************************/ 3799// Structure used in VRAM_UsageByFirmwareTable 3800// Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm 3801// at running time. 3802// note2: From RV770, the memory is more than 32bit addressable, so we will change 3803// ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains 3804// exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware 3805// (in offset to start of memory address) is KB aligned instead of byte aligend. 3806/***********************************************************************************/ 3807// Note3: 3808/* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged constant across VGA or non VGA adapter, 3809for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have: 3810 3811If (ulStartAddrUsedByFirmware!=0) 3812FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB; 3813Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose 3814else //Non VGA case 3815 if (FB_Size<=2Gb) 3816 FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB; 3817 else 3818 FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB 3819 3820CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/ 3821 3822/***********************************************************************************/ 3823#define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1 3824 3825typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO 3826{ 3827 ULONG ulStartAddrUsedByFirmware; 3828 USHORT usFirmwareUseInKb; 3829 USHORT usReserved; 3830}ATOM_FIRMWARE_VRAM_RESERVE_INFO; 3831 3832typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE 3833{ 3834 ATOM_COMMON_TABLE_HEADER sHeader; 3835 ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; 3836}ATOM_VRAM_USAGE_BY_FIRMWARE; 3837 3838// change verion to 1.5, when allow driver to allocate the vram area for command table access. 3839typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 3840{ 3841 ULONG ulStartAddrUsedByFirmware; 3842 USHORT usFirmwareUseInKb; 3843 USHORT usFBUsedByDrvInKb; 3844}ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5; 3845 3846typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5 3847{ 3848 ATOM_COMMON_TABLE_HEADER sHeader; 3849 ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; 3850}ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5; 3851 3852/****************************************************************************/ 3853// Structure used in GPIO_Pin_LUTTable 3854/****************************************************************************/ 3855typedef struct _ATOM_GPIO_PIN_ASSIGNMENT 3856{ 3857 USHORT usGpioPin_AIndex; 3858 UCHAR ucGpioPinBitShift; 3859 UCHAR ucGPIO_ID; 3860}ATOM_GPIO_PIN_ASSIGNMENT; 3861 3862//ucGPIO_ID pre-define id for multiple usage 3863//from SMU7.x, if ucGPIO_ID=PP_AC_DC_SWITCH_GPIO_PINID in GPIO_LUTTable, AC/DC swithing feature is enable 3864#define PP_AC_DC_SWITCH_GPIO_PINID 60 3865//from SMU7.x, if ucGPIO_ID=VDDC_REGULATOR_VRHOT_GPIO_PINID in GPIO_LUTable, VRHot feature is enable 3866#define VDDC_VRHOT_GPIO_PINID 61 3867 3868typedef struct _ATOM_GPIO_PIN_LUT 3869{ 3870 ATOM_COMMON_TABLE_HEADER sHeader; 3871 ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1]; 3872}ATOM_GPIO_PIN_LUT; 3873 3874/****************************************************************************/ 3875// Structure used in ComponentVideoInfoTable 3876/****************************************************************************/ 3877#define GPIO_PIN_ACTIVE_HIGH 0x1 3878 3879#define MAX_SUPPORTED_CV_STANDARDS 5 3880 3881// definitions for ATOM_D_INFO.ucSettings 3882#define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0] 3883#define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out 3884#define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7] 3885 3886typedef struct _ATOM_GPIO_INFO 3887{ 3888 USHORT usAOffset; 3889 UCHAR ucSettings; 3890 UCHAR ucReserved; 3891}ATOM_GPIO_INFO; 3892 3893// definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector) 3894#define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2 3895 3896// definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i 3897#define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7]; 3898#define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0] 3899 3900// definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode 3901//Line 3 out put 5V. 3902#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9 3903#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9 3904#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0 3905 3906//Line 3 out put 2.2V 3907#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box 3908#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box 3909#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2 3910 3911//Line 3 out put 0V 3912#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3 3913#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3 3914#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4 3915 3916#define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0] 3917 3918#define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7 3919 3920//GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks. 3921#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. 3922#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. 3923 3924 3925typedef struct _ATOM_COMPONENT_VIDEO_INFO 3926{ 3927 ATOM_COMMON_TABLE_HEADER sHeader; 3928 USHORT usMask_PinRegisterIndex; 3929 USHORT usEN_PinRegisterIndex; 3930 USHORT usY_PinRegisterIndex; 3931 USHORT usA_PinRegisterIndex; 3932 UCHAR ucBitShift; 3933 UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low 3934 ATOM_DTD_FORMAT sReserved; // must be zeroed out 3935 UCHAR ucMiscInfo; 3936 UCHAR uc480i; 3937 UCHAR uc480p; 3938 UCHAR uc720p; 3939 UCHAR uc1080i; 3940 UCHAR ucLetterBoxMode; 3941 UCHAR ucReserved[3]; 3942 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector 3943 ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; 3944 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; 3945}ATOM_COMPONENT_VIDEO_INFO; 3946 3947//ucTableFormatRevision=2 3948//ucTableContentRevision=1 3949typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21 3950{ 3951 ATOM_COMMON_TABLE_HEADER sHeader; 3952 UCHAR ucMiscInfo; 3953 UCHAR uc480i; 3954 UCHAR uc480p; 3955 UCHAR uc720p; 3956 UCHAR uc1080i; 3957 UCHAR ucReserved; 3958 UCHAR ucLetterBoxMode; 3959 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector 3960 ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; 3961 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; 3962}ATOM_COMPONENT_VIDEO_INFO_V21; 3963 3964#define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21 3965 3966/****************************************************************************/ 3967// Structure used in object_InfoTable 3968/****************************************************************************/ 3969typedef struct _ATOM_OBJECT_HEADER 3970{ 3971 ATOM_COMMON_TABLE_HEADER sHeader; 3972 USHORT usDeviceSupport; 3973 USHORT usConnectorObjectTableOffset; 3974 USHORT usRouterObjectTableOffset; 3975 USHORT usEncoderObjectTableOffset; 3976 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. 3977 USHORT usDisplayPathTableOffset; 3978}ATOM_OBJECT_HEADER; 3979 3980typedef struct _ATOM_OBJECT_HEADER_V3 3981{ 3982 ATOM_COMMON_TABLE_HEADER sHeader; 3983 USHORT usDeviceSupport; 3984 USHORT usConnectorObjectTableOffset; 3985 USHORT usRouterObjectTableOffset; 3986 USHORT usEncoderObjectTableOffset; 3987 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. 3988 USHORT usDisplayPathTableOffset; 3989 USHORT usMiscObjectTableOffset; 3990}ATOM_OBJECT_HEADER_V3; 3991 3992typedef struct _ATOM_DISPLAY_OBJECT_PATH 3993{ 3994 USHORT usDeviceTag; //supported device 3995 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH 3996 USHORT usConnObjectId; //Connector Object ID 3997 USHORT usGPUObjectId; //GPU ID 3998 USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. 3999}ATOM_DISPLAY_OBJECT_PATH; 4000
4001typedef struct _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH 4002{ 4003 USHORT usDeviceTag; //supported device 4004 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH 4005 USHORT usConnObjectId; //Connector Object ID 4006 USHORT usGPUObjectId; //GPU ID 4007 USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder 4008}ATOM_DISPLAY_EXTERNAL_OBJECT_PATH; 4009 4010typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE 4011{ 4012 UCHAR ucNumOfDispPath; 4013 UCHAR ucVersion; 4014 UCHAR ucPadding[2]; 4015 ATOM_DISPLAY_OBJECT_PATH asDispPath[1]; 4016}ATOM_DISPLAY_OBJECT_PATH_TABLE; 4017 4018 4019typedef struct _ATOM_OBJECT //each object has this structure 4020{ 4021 USHORT usObjectID; 4022 USHORT usSrcDstTableOffset; 4023 USHORT usRecordOffset; //this pointing to a bunch of records defined below 4024 USHORT usReserved; 4025}ATOM_OBJECT; 4026 4027typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure 4028{ 4029 UCHAR ucNumberOfObjects; 4030 UCHAR ucPadding[3]; 4031 ATOM_OBJECT asObjects[1]; 4032}ATOM_OBJECT_TABLE; 4033 4034typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure 4035{ 4036 UCHAR ucNumberOfSrc; 4037 USHORT usSrcObjectID[1]; 4038 UCHAR ucNumberOfDst; 4039 USHORT usDstObjectID[1]; 4040}ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT; 4041 4042 4043//Two definitions below are for OPM on MXM module designs 4044 4045#define EXT_HPDPIN_LUTINDEX_0 0 4046#define EXT_HPDPIN_LUTINDEX_1 1 4047#define EXT_HPDPIN_LUTINDEX_2 2 4048#define EXT_HPDPIN_LUTINDEX_3 3 4049#define EXT_HPDPIN_LUTINDEX_4 4 4050#define EXT_HPDPIN_LUTINDEX_5 5 4051#define EXT_HPDPIN_LUTINDEX_6 6 4052#define EXT_HPDPIN_LUTINDEX_7 7 4053#define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES (EXT_HPDPIN_LUTINDEX_7+1) 4054 4055#define EXT_AUXDDC_LUTINDEX_0 0 4056#define EXT_AUXDDC_LUTINDEX_1 1 4057#define EXT_AUXDDC_LUTINDEX_2 2 4058#define EXT_AUXDDC_LUTINDEX_3 3 4059#define EXT_AUXDDC_LUTINDEX_4 4 4060#define EXT_AUXDDC_LUTINDEX_5 5 4061#define EXT_AUXDDC_LUTINDEX_6 6 4062#define EXT_AUXDDC_LUTINDEX_7 7 4063#define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1) 4064 4065//ucChannelMapping are defined as following 4066//for DP connector, eDP, DP to VGA/LVDS 4067//Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4068//Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4069//Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4070//Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4071typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING 4072{ 4073#if ATOM_BIG_ENDIAN 4074 UCHAR ucDP_Lane3_Source:2; 4075 UCHAR ucDP_Lane2_Source:2; 4076 UCHAR ucDP_Lane1_Source:2; 4077 UCHAR ucDP_Lane0_Source:2; 4078#else 4079 UCHAR ucDP_Lane0_Source:2; 4080 UCHAR ucDP_Lane1_Source:2; 4081 UCHAR ucDP_Lane2_Source:2; 4082 UCHAR ucDP_Lane3_Source:2; 4083#endif 4084}ATOM_DP_CONN_CHANNEL_MAPPING; 4085 4086//for DVI/HDMI, in dual link case, both links have to have same mapping. 4087//Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4088//Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4089//Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4090//Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4091typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING 4092{ 4093#if ATOM_BIG_ENDIAN 4094 UCHAR ucDVI_CLK_Source:2; 4095 UCHAR ucDVI_DATA0_Source:2; 4096 UCHAR ucDVI_DATA1_Source:2; 4097 UCHAR ucDVI_DATA2_Source:2; 4098#else 4099 UCHAR ucDVI_DATA2_Source:2; 4100 UCHAR ucDVI_DATA1_Source:2; 4101 UCHAR ucDVI_DATA0_Source:2; 4102 UCHAR ucDVI_CLK_Source:2; 4103#endif 4104}ATOM_DVI_CONN_CHANNEL_MAPPING; 4105 4106typedef struct _EXT_DISPLAY_PATH 4107{ 4108 USHORT usDeviceTag; //A bit vector to show what devices are supported 4109 USHORT usDeviceACPIEnum; //16bit device ACPI id. 4110 USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions 4111 UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT 4112 UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT 4113 USHORT usExtEncoderObjId; //external encoder object id 4114 union{ 4115 UCHAR ucChannelMapping; // if ucChannelMapping=0, using default one to one mapping 4116 ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping; 4117 ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping; 4118 }; 4119 UCHAR ucChPNInvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted 4120 USHORT usCaps; 4121 USHORT usReserved; 4122}EXT_DISPLAY_PATH; 4123 4124#define NUMBER_OF_UCHAR_FOR_GUID 16 4125#define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7 4126 4127//usCaps 4128#define EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE 0x01 4129#define EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN 0x02 4130 4131typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO 4132{ 4133 ATOM_COMMON_TABLE_HEADER sHeader; 4134 UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string 4135 EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries. 4136 UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0. 4137 UCHAR uc3DStereoPinId; // use for eDP panel 4138 UCHAR ucRemoteDisplayConfig; 4139 UCHAR uceDPToLVDSRxId; 4140 UCHAR ucFixDPVoltageSwing; // usCaps[1]=1, this indicate DP_LANE_SET value 4141 UCHAR Reserved[3]; // for potential expansion 4142}ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; 4143 4144//Related definitions, all records are different but they have a commond header 4145typedef struct _ATOM_COMMON_RECORD_HEADER 4146{ 4147 UCHAR ucRecordType; //An emun to indicate the record type 4148 UCHAR ucRecordSize; //The size of the whole record in byte 4149}ATOM_COMMON_RECORD_HEADER; 4150 4151 4152#define ATOM_I2C_RECORD_TYPE 1 4153#define ATOM_HPD_INT_RECORD_TYPE 2 4154#define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3 4155#define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4 4156#define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4157#define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4158#define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7 4159#define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4160#define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9 4161#define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10 4162#define ATOM_CONNECTOR_CF_RECORD_TYPE 11 4163#define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12 4164#define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13 4165#define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14 4166#define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15 4167#define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 16 //This is for the case when connectors are not known to object table 4168#define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table 4169#define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record 4170#define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19 4171#define ATOM_ENCODER_CAP_RECORD_TYPE 20 4172 4173 4174//Must be updated when new record type is added,equal to that record definition! 4175#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_ENCODER_CAP_RECORD_TYPE 4176 4177typedef struct _ATOM_I2C_RECORD 4178{ 4179 ATOM_COMMON_RECORD_HEADER sheader; 4180 ATOM_I2C_ID_CONFIG sucI2cId; 4181 UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC 4182}ATOM_I2C_RECORD; 4183 4184typedef struct _ATOM_HPD_INT_RECORD 4185{ 4186 ATOM_COMMON_RECORD_HEADER sheader; 4187 UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info 4188 UCHAR ucPlugged_PinState; 4189}ATOM_HPD_INT_RECORD; 4190 4191 4192typedef struct _ATOM_OUTPUT_PROTECTION_RECORD 4193{ 4194 ATOM_COMMON_RECORD_HEADER sheader; 4195 UCHAR ucProtectionFlag; 4196 UCHAR ucReserved; 4197}ATOM_OUTPUT_PROTECTION_RECORD; 4198 4199typedef struct _ATOM_CONNECTOR_DEVICE_TAG 4200{ 4201 ULONG ulACPIDeviceEnum; //Reserved for now 4202 USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT" 4203 USHORT usPadding; 4204}ATOM_CONNECTOR_DEVICE_TAG; 4205 4206typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD 4207{ 4208 ATOM_COMMON_RECORD_HEADER sheader; 4209 UCHAR ucNumberOfDevice; 4210 UCHAR ucReserved; 4211 ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation 4212}ATOM_CONNECTOR_DEVICE_TAG_RECORD; 4213 4214 4215typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD 4216{ 4217 ATOM_COMMON_RECORD_HEADER sheader; 4218 UCHAR ucConfigGPIOID; 4219 UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in 4220 UCHAR ucFlowinGPIPID; 4221 UCHAR ucExtInGPIPID; 4222}ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD; 4223 4224typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD 4225{ 4226 ATOM_COMMON_RECORD_HEADER sheader; 4227 UCHAR ucCTL1GPIO_ID; 4228 UCHAR ucCTL1GPIOState; //Set to 1 when it's active high 4229 UCHAR ucCTL2GPIO_ID; 4230 UCHAR ucCTL2GPIOState; //Set to 1 when it's active high 4231 UCHAR ucCTL3GPIO_ID; 4232 UCHAR ucCTL3GPIOState; //Set to 1 when it's active high 4233 UCHAR ucCTLFPGA_IN_ID; 4234 UCHAR ucPadding[3]; 4235}ATOM_ENCODER_FPGA_CONTROL_RECORD; 4236 4237typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD 4238{ 4239 ATOM_COMMON_RECORD_HEADER sheader; 4240 UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info 4241 UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected 4242}ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD; 4243 4244typedef struct _ATOM_JTAG_RECORD 4245{ 4246 ATOM_COMMON_RECORD_HEADER sheader; 4247 UCHAR ucTMSGPIO_ID; 4248 UCHAR ucTMSGPIOState; //Set to 1 when it's active high 4249 UCHAR ucTCKGPIO_ID; 4250 UCHAR ucTCKGPIOState; //Set to 1 when it's active high 4251 UCHAR ucTDOGPIO_ID; 4252 UCHAR ucTDOGPIOState; //Set to 1 when it's active high 4253 UCHAR ucTDIGPIO_ID; 4254 UCHAR ucTDIGPIOState; //Set to 1 when it's active high 4255 UCHAR ucPadding[2]; 4256}ATOM_JTAG_RECORD; 4257 4258 4259//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually 4260typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR 4261{ 4262 UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table 4263 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin 4264}ATOM_GPIO_PIN_CONTROL_PAIR; 4265 4266typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD 4267{ 4268 ATOM_COMMON_RECORD_HEADER sheader; 4269 UCHAR ucFlags; // Future expnadibility 4270 UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object 4271 ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins 4272}ATOM_OBJECT_GPIO_CNTL_RECORD; 4273 4274//Definitions for GPIO pin state 4275#define GPIO_PIN_TYPE_INPUT 0x00 4276#define GPIO_PIN_TYPE_OUTPUT 0x10 4277#define GPIO_PIN_TYPE_HW_CONTROL 0x20 4278 4279//For GPIO_PIN_TYPE_OUTPUT the following is defined 4280#define GPIO_PIN_OUTPUT_STATE_MASK 0x01 4281#define GPIO_PIN_OUTPUT_STATE_SHIFT 0 4282#define GPIO_PIN_STATE_ACTIVE_LOW 0x0 4283#define GPIO_PIN_STATE_ACTIVE_HIGH 0x1 4284 4285// Indexes to GPIO array in GLSync record 4286// GLSync record is for Frame Lock/Gen Lock feature. 4287#define ATOM_GPIO_INDEX_GLSYNC_REFCLK 0 4288#define ATOM_GPIO_INDEX_GLSYNC_HSYNC 1 4289#define ATOM_GPIO_INDEX_GLSYNC_VSYNC 2 4290#define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ 3 4291#define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT 4 4292#define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5 4293#define ATOM_GPIO_INDEX_GLSYNC_V_RESET 6 4294#define ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL 7 4295#define ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL 8 4296#define ATOM_GPIO_INDEX_GLSYNC_MAX 9 4297 4298typedef struct _ATOM_ENCODER_DVO_CF_RECORD 4299{ 4300 ATOM_COMMON_RECORD_HEADER sheader; 4301 ULONG ulStrengthControl; // DVOA strength control for CF 4302 UCHAR ucPadding[2]; 4303}ATOM_ENCODER_DVO_CF_RECORD; 4304 4305// Bit maps for ATOM_ENCODER_CAP_RECORD.ucEncoderCap 4306#define ATOM_ENCODER_CAP_RECORD_HBR2 0x01 // DP1.2 HBR2 is supported by HW encoder 4307#define ATOM_ENCODER_CAP_RECORD_HBR2_EN 0x02 // DP1.2 HBR2 setting is qualified and HBR2 can be enabled 4308 4309typedef struct _ATOM_ENCODER_CAP_RECORD 4310{ 4311 ATOM_COMMON_RECORD_HEADER sheader; 4312 union { 4313 USHORT usEncoderCap; 4314 struct { 4315#if ATOM_BIG_ENDIAN 4316 USHORT usReserved:14; // Bit1-15 may be defined for other capability in future 4317 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable 4318 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. 4319#else 4320 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. 4321 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable 4322 USHORT usReserved:14; // Bit1-15 may be defined for other capability in future 4323#endif 4324 }; 4325 }; 4326}ATOM_ENCODER_CAP_RECORD; 4327 4328// value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle 4329#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 4330#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2 4331 4332typedef struct _ATOM_CONNECTOR_CF_RECORD 4333{ 4334 ATOM_COMMON_RECORD_HEADER sheader; 4335 USHORT usMaxPixClk; 4336 UCHAR ucFlowCntlGpioId; 4337 UCHAR ucSwapCntlGpioId; 4338 UCHAR ucConnectedDvoBundle; 4339 UCHAR ucPadding; 4340}ATOM_CONNECTOR_CF_RECORD; 4341 4342typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD 4343{ 4344 ATOM_COMMON_RECORD_HEADER sheader; 4345 ATOM_DTD_FORMAT asTiming; 4346}ATOM_CONNECTOR_HARDCODE_DTD_RECORD; 4347 4348typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD 4349{ 4350 ATOM_COMMON_RECORD_HEADER sheader; //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 4351 UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A 4352 UCHAR ucReserved; 4353}ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD; 4354 4355 4356typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD 4357{ 4358 ATOM_COMMON_RECORD_HEADER sheader; 4359 UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state 4360 UCHAR ucMuxControlPin; 4361 UCHAR ucMuxState[2]; //for alligment purpose 4362}ATOM_ROUTER_DDC_PATH_SELECT_RECORD; 4363 4364typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD 4365{ 4366 ATOM_COMMON_RECORD_HEADER sheader; 4367 UCHAR ucMuxType; 4368 UCHAR ucMuxControlPin; 4369 UCHAR ucMuxState[2]; //for alligment purpose 4370}ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD; 4371 4372// define ucMuxType 4373#define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f 4374#define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01 4375 4376typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 4377{ 4378 ATOM_COMMON_RECORD_HEADER sheader; 4379 UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table 4380}ATOM_CONNECTOR_HPDPIN_LUT_RECORD; 4381 4382typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 4383{ 4384 ATOM_COMMON_RECORD_HEADER sheader; 4385 ATOM_I2C_ID_CONFIG ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES]; //An fixed size array which maps external pins to internal DDC ID 4386}ATOM_CONNECTOR_AUXDDC_LUT_RECORD; 4387 4388typedef struct _ATOM_OBJECT_LINK_RECORD 4389{ 4390 ATOM_COMMON_RECORD_HEADER sheader; 4391 USHORT usObjectID; //could be connector, encorder or other object in object.h 4392}ATOM_OBJECT_LINK_RECORD; 4393 4394typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD 4395{ 4396 ATOM_COMMON_RECORD_HEADER sheader; 4397 USHORT usReserved; 4398}ATOM_CONNECTOR_REMOTE_CAP_RECORD; 4399 4400/****************************************************************************/ 4401// ASIC voltage data table 4402/****************************************************************************/ 4403typedef struct _ATOM_VOLTAGE_INFO_HEADER 4404{ 4405 USHORT usVDDCBaseLevel; //In number of 50mv unit 4406 USHORT usReserved; //For possible extension table offset 4407 UCHAR ucNumOfVoltageEntries; 4408 UCHAR ucBytesPerVoltageEntry; 4409 UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit 4410 UCHAR ucDefaultVoltageEntry; 4411 UCHAR ucVoltageControlI2cLine; 4412 UCHAR ucVoltageControlAddress; 4413 UCHAR ucVoltageControlOffset; 4414}ATOM_VOLTAGE_INFO_HEADER; 4415 4416typedef struct _ATOM_VOLTAGE_INFO 4417{ 4418 ATOM_COMMON_TABLE_HEADER sHeader; 4419 ATOM_VOLTAGE_INFO_HEADER viHeader; 4420 UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry 4421}ATOM_VOLTAGE_INFO; 4422 4423 4424typedef struct _ATOM_VOLTAGE_FORMULA 4425{ 4426 USHORT usVoltageBaseLevel; // In number of 1mv unit 4427 USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit 4428 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage 4429 UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv 4430 UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep 4431 UCHAR ucReserved; 4432 UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries 4433}ATOM_VOLTAGE_FORMULA; 4434 4435typedef struct _VOLTAGE_LUT_ENTRY 4436{ 4437 USHORT usVoltageCode; // The Voltage ID, either GPIO or I2C code 4438 USHORT usVoltageValue; // The corresponding Voltage Value, in mV 4439}VOLTAGE_LUT_ENTRY; 4440 4441typedef struct _ATOM_VOLTAGE_FORMULA_V2 4442{ 4443 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage 4444 UCHAR ucReserved[3]; 4445 VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries 4446}ATOM_VOLTAGE_FORMULA_V2; 4447 4448typedef struct _ATOM_VOLTAGE_CONTROL 4449{ 4450 UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine 4451 UCHAR ucVoltageControlI2cLine; 4452 UCHAR ucVoltageControlAddress; 4453 UCHAR ucVoltageControlOffset; 4454 USHORT usGpioPin_AIndex; //GPIO_PAD register index 4455 UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff 4456 UCHAR ucReserved; 4457}ATOM_VOLTAGE_CONTROL; 4458 4459// Define ucVoltageControlId 4460#define VOLTAGE_CONTROLLED_BY_HW 0x00 4461#define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F 4462#define VOLTAGE_CONTROLLED_BY_GPIO 0x80 4463#define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage 4464#define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI 4465#define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage 4466#define VOLTAGE_CONTROL_ID_DS4402 0x04 4467#define VOLTAGE_CONTROL_ID_UP6266 0x05 4468#define VOLTAGE_CONTROL_ID_SCORPIO 0x06 4469#define VOLTAGE_CONTROL_ID_VT1556M 0x07 4470#define VOLTAGE_CONTROL_ID_CHL822x 0x08 4471#define VOLTAGE_CONTROL_ID_VT1586M 0x09 4472#define VOLTAGE_CONTROL_ID_UP1637 0x0A 4473#define VOLTAGE_CONTROL_ID_CHL8214 0x0B 4474#define VOLTAGE_CONTROL_ID_UP1801 0x0C 4475#define VOLTAGE_CONTROL_ID_ST6788A 0x0D 4476#define VOLTAGE_CONTROL_ID_CHLIR3564SVI2 0x0E 4477#define VOLTAGE_CONTROL_ID_AD527x 0x0F 4478#define VOLTAGE_CONTROL_ID_NCP81022 0x10 4479#define VOLTAGE_CONTROL_ID_LTC2635 0x11 4480 4481typedef struct _ATOM_VOLTAGE_OBJECT 4482{ 4483 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 4484 UCHAR ucSize; //Size of Object 4485 ATOM_VOLTAGE_CONTROL asControl; //describ how to control 4486 ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID 4487}ATOM_VOLTAGE_OBJECT; 4488 4489typedef struct _ATOM_VOLTAGE_OBJECT_V2 4490{ 4491 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 4492 UCHAR ucSize; //Size of Object 4493 ATOM_VOLTAGE_CONTROL asControl; //describ how to control 4494 ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID 4495}ATOM_VOLTAGE_OBJECT_V2; 4496 4497typedef struct _ATOM_VOLTAGE_OBJECT_INFO 4498{ 4499 ATOM_COMMON_TABLE_HEADER sHeader; 4500 ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control 4501}ATOM_VOLTAGE_OBJECT_INFO; 4502 4503typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V2 4504{ 4505 ATOM_COMMON_TABLE_HEADER sHeader; 4506 ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control 4507}ATOM_VOLTAGE_OBJECT_INFO_V2; 4508 4509typedef struct _ATOM_LEAKID_VOLTAGE 4510{ 4511 UCHAR ucLeakageId; 4512 UCHAR ucReserved; 4513 USHORT usVoltage; 4514}ATOM_LEAKID_VOLTAGE; 4515 4516typedef struct _ATOM_VOLTAGE_OBJECT_HEADER_V3{ 4517 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 4518 UCHAR ucVoltageMode; //Indicate voltage control mode: Init/Set/Leakage/Set phase 4519 USHORT usSize; //Size of Object 4520}ATOM_VOLTAGE_OBJECT_HEADER_V3; 4521 4522// ATOM_VOLTAGE_OBJECT_HEADER_V3.ucVoltageMode 4523#define VOLTAGE_OBJ_GPIO_LUT 0 //VOLTAGE and GPIO Lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3 4524#define VOLTAGE_OBJ_VR_I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OBJECT_V3 4525#define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3 4526#define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SVID2_VOLTAGE_OBJECT_V3 4527#define VOLTAGE_OBJ_PWRBOOST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 4528#define VOLTAGE_OBJ_HIGH_STATE_LEAKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 4529#define VOLTAGE_OBJ_HIGH1_STATE_LEAKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 4530 4531typedef struct _VOLTAGE_LUT_ENTRY_V2 4532{ 4533 ULONG ulVoltageId; // The Voltage ID which is used to program GPIO register 4534 USHORT usVoltageValue; // The corresponding Voltage Value, in mV 4535}VOLTAGE_LUT_ENTRY_V2; 4536 4537typedef struct _LEAKAGE_VOLTAGE_LUT_ENTRY_V2 4538{ 4539 USHORT usVoltageLevel; // The Voltage ID which is used to program GPIO register 4540 USHORT usVoltageId; 4541 USHORT usLeakageId; // The corresponding Voltage Value, in mV 4542}LEAKAGE_VOLTAGE_LUT_ENTRY_V2; 4543 4544typedef struct _ATOM_I2C_VOLTAGE_OBJECT_V3 4545{ 4546 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ 4547 UCHAR ucVoltageRegulatorId; //Indicate Voltage Regulator Id 4548 UCHAR ucVoltageControlI2cLine; 4549 UCHAR ucVoltageControlAddress; 4550 UCHAR ucVoltageControlOffset; 4551 ULONG ulReserved; 4552 VOLTAGE_LUT_ENTRY asVolI2cLut[1]; // end with 0xff 4553}ATOM_I2C_VOLTAGE_OBJECT_V3; 4554 4555typedef struct _ATOM_GPIO_VOLTAGE_OBJECT_V3 4556{ 4557 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT 4558 UCHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mode 4559 UCHAR ucGpioEntryNum; // indiate the entry numbers of Votlage/Gpio value Look up table 4560 UCHAR ucPhaseDelay; // phase delay in unit of micro second 4561 UCHAR ucReserved; 4562 ULONG ulGpioMaskVal; // GPIO Mask value 4563 VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[1]; 4564}ATOM_GPIO_VOLTAGE_OBJECT_V3; 4565 4566typedef struct _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 4567{ 4568 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = 0x10/0x11/0x12 4569 UCHAR ucLeakageCntlId; // default is 0 4570 UCHAR ucLeakageEntryNum; // indicate the entry number of LeakageId/Voltage Lut table 4571 UCHAR ucReserved[2]; 4572 ULONG ulMaxVoltageLevel; 4573 LEAKAGE_VOLTAGE_LUT_ENTRY_V2 asLeakageIdLut[1]; 4574}ATOM_LEAKAGE_VOLTAGE_OBJECT_V3; 4575 4576 4577typedef struct _ATOM_SVID2_VOLTAGE_OBJECT_V3 4578{ 4579 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_SVID2 4580// 14:7 – PSI0_VID 4581// 6 – PSI0_EN 4582// 5 – PSI1 4583// 4:2 – load line slope trim. 4584// 1:0 – offset trim, 4585 USHORT usLoadLine_PSI; 4586// GPU GPIO pin Id to SVID2 regulator VRHot pin. possible value 0~31. 0 means GPIO0, 31 means GPIO31 4587 UCHAR ucReserved[2]; 4588 ULONG ulReserved; 4589}ATOM_SVID2_VOLTAGE_OBJECT_V3; 4590 4591typedef union _ATOM_VOLTAGE_OBJECT_V3{ 4592 ATOM_GPIO_VOLTAGE_OBJECT_V3 asGpioVoltageObj; 4593 ATOM_I2C_VOLTAGE_OBJECT_V3 asI2cVoltageObj; 4594 ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 asLeakageObj; 4595 ATOM_SVID2_VOLTAGE_OBJECT_V3 asSVID2Obj; 4596}ATOM_VOLTAGE_OBJECT_V3; 4597 4598typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 4599{ 4600 ATOM_COMMON_TABLE_HEADER sHeader; 4601 ATOM_VOLTAGE_OBJECT_V3 asVoltageObj[3]; //Info for Voltage control 4602}ATOM_VOLTAGE_OBJECT_INFO_V3_1; 4603 4604typedef struct _ATOM_ASIC_PROFILE_VOLTAGE 4605{ 4606 UCHAR ucProfileId; 4607 UCHAR ucReserved; 4608 USHORT usSize; 4609 USHORT usEfuseSpareStartAddr; 4610 USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, 4611 ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage 4612}ATOM_ASIC_PROFILE_VOLTAGE; 4613 4614//ucProfileId 4615#define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1 4616#define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1 4617#define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2 4618 4619typedef struct _ATOM_ASIC_PROFILING_INFO 4620{ 4621 ATOM_COMMON_TABLE_HEADER asHeader; 4622 ATOM_ASIC_PROFILE_VOLTAGE asVoltage; 4623}ATOM_ASIC_PROFILING_INFO; 4624 4625typedef struct _ATOM_ASIC_PROFILING_INFO_V2_1 4626{ 4627 ATOM_COMMON_TABLE_HEADER asHeader; 4628 UCHAR ucLeakageBinNum; // indicate the entry number of LeakageId/Voltage Lut table 4629 USHORT usLeakageBinArrayOffset; // offset of USHORT Leakage Bin list array ( from lower LeakageId to higher) 4630 4631 UCHAR ucElbVDDC_Num; 4632 USHORT usElbVDDC_IdArrayOffset; // offset of USHORT virtual VDDC voltage id ( 0xff01~0xff08 ) 4633 USHORT usElbVDDC_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array 4634 4635 UCHAR ucElbVDDCI_Num; 4636 USHORT usElbVDDCI_IdArrayOffset; // offset of USHORT virtual VDDCI voltage id ( 0xff01~0xff08 ) 4637 USHORT usElbVDDCI_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array 4638}ATOM_ASIC_PROFILING_INFO_V2_1; 4639 4640typedef struct _ATOM_POWER_SOURCE_OBJECT 4641{ 4642 UCHAR ucPwrSrcId; // Power source 4643 UCHAR ucPwrSensorType; // GPIO, I2C or none 4644 UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id 4645 UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect 4646 UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect 4647 UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect 4648 UCHAR ucPwrSensActiveState; // high active or low active 4649 UCHAR ucReserve[3]; // reserve 4650 USHORT usSensPwr; // in unit of watt 4651}ATOM_POWER_SOURCE_OBJECT; 4652 4653typedef struct _ATOM_POWER_SOURCE_INFO 4654{ 4655 ATOM_COMMON_TABLE_HEADER asHeader; 4656 UCHAR asPwrbehave[16]; 4657 ATOM_POWER_SOURCE_OBJECT asPwrObj[1]; 4658}ATOM_POWER_SOURCE_INFO; 4659 4660 4661//Define ucPwrSrcId 4662#define POWERSOURCE_PCIE_ID1 0x00 4663#define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01 4664#define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02 4665#define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04 4666#define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08 4667 4668//define ucPwrSensorId 4669#define POWER_SENSOR_ALWAYS 0x00 4670#define POWER_SENSOR_GPIO 0x01 4671#define POWER_SENSOR_I2C 0x02 4672 4673typedef struct _ATOM_CLK_VOLT_CAPABILITY 4674{ 4675 ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table 4676 ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz 4677}ATOM_CLK_VOLT_CAPABILITY; 4678 4679typedef struct _ATOM_AVAILABLE_SCLK_LIST 4680{ 4681 ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz 4682 USHORT usVoltageIndex; // The Voltage Index indicated by FUSE for specified SCLK 4683 USHORT usVoltageID; // The Voltage ID indicated by FUSE for specified SCLK 4684}ATOM_AVAILABLE_SCLK_LIST; 4685 4686// ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition 4687#define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE 1 // refer to ulSystemConfig bit[0] 4688 4689// this IntegrateSystemInfoTable is used for Liano/Ontario APU 4690typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 4691{ 4692 ATOM_COMMON_TABLE_HEADER sHeader; 4693 ULONG ulBootUpEngineClock; 4694 ULONG ulDentistVCOFreq; 4695 ULONG ulBootUpUMAClock; 4696 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 4697 ULONG ulBootUpReqDisplayVector; 4698 ULONG ulOtherDisplayMisc; 4699 ULONG ulGPUCapInfo; 4700 ULONG ulSB_MMIO_Base_Addr; 4701 USHORT usRequestedPWMFreqInHz; 4702 UCHAR ucHtcTmpLmt; 4703 UCHAR ucHtcHystLmt; 4704 ULONG ulMinEngineClock; 4705 ULONG ulSystemConfig; 4706 ULONG ulCPUCapInfo; 4707 USHORT usNBP0Voltage; 4708 USHORT usNBP1Voltage; 4709 USHORT usBootUpNBVoltage; 4710 USHORT usExtDispConnInfoOffset; 4711 USHORT usPanelRefreshRateRange; 4712 UCHAR ucMemoryType; 4713 UCHAR ucUMAChannelNumber; 4714 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; 4715 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; 4716 ULONG ulCSR_M3_ARB_CNTL_FS3D[10]; 4717 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 4718 ULONG ulGMCRestoreResetTime; 4719 ULONG ulMinimumNClk; 4720 ULONG ulIdleNClk; 4721 ULONG ulDDR_DLL_PowerUpTime; 4722 ULONG ulDDR_PLL_PowerUpTime; 4723 USHORT usPCIEClkSSPercentage; 4724 USHORT usPCIEClkSSType; 4725 USHORT usLvdsSSPercentage; 4726 USHORT usLvdsSSpreadRateIn10Hz; 4727 USHORT usHDMISSPercentage; 4728 USHORT usHDMISSpreadRateIn10Hz; 4729 USHORT usDVISSPercentage; 4730 USHORT usDVISSpreadRateIn10Hz; 4731 ULONG SclkDpmBoostMargin; 4732 ULONG SclkDpmThrottleMargin; 4733 USHORT SclkDpmTdpLimitPG; 4734 USHORT SclkDpmTdpLimitBoost; 4735 ULONG ulBoostEngineCLock; 4736 UCHAR ulBoostVid_2bit; 4737 UCHAR EnableBoost; 4738 USHORT GnbTdpLimit; 4739 USHORT usMaxLVDSPclkFreqInSingleLink; 4740 UCHAR ucLvdsMisc; 4741 UCHAR ucLVDSReserved; 4742 ULONG ulReserved3[15]; 4743 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 4744}ATOM_INTEGRATED_SYSTEM_INFO_V6; 4745 4746// ulGPUCapInfo 4747#define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 4748#define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION 0x08 4749 4750//ucLVDSMisc: 4751#define SYS_INFO_LVDSMISC__888_FPDI_MODE 0x01 4752#define SYS_INFO_LVDSMISC__DL_CH_SWAP 0x02 4753#define SYS_INFO_LVDSMISC__888_BPC 0x04 4754#define SYS_INFO_LVDSMISC__OVERRIDE_EN 0x08 4755#define SYS_INFO_LVDSMISC__BLON_ACTIVE_LOW 0x10 4756// new since Trinity 4757#define SYS_INFO_LVDSMISC__TRAVIS_LVDS_VOL_OVERRIDE_EN 0x20 4758 4759// not used any more 4760#define SYS_INFO_LVDSMISC__VSYNC_ACTIVE_LOW 0x04 4761#define SYS_INFO_LVDSMISC__HSYNC_ACTIVE_LOW 0x08 4762 4763/********************************************************************************************************************** 4764 ATOM_INTEGRATED_SYSTEM_INFO_V6 Description 4765ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 4766ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 4767ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 4768sDISPCLK_Voltage: Report Display clock voltage requirement. 4769 4770ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects: 4771 ATOM_DEVICE_CRT1_SUPPORT 0x0001 4772 ATOM_DEVICE_CRT2_SUPPORT 0x0010 4773 ATOM_DEVICE_DFP1_SUPPORT 0x0008 4774 ATOM_DEVICE_DFP6_SUPPORT 0x0040 4775 ATOM_DEVICE_DFP2_SUPPORT 0x0080 4776 ATOM_DEVICE_DFP3_SUPPORT 0x0200 4777 ATOM_DEVICE_DFP4_SUPPORT 0x0400 4778 ATOM_DEVICE_DFP5_SUPPORT 0x0800 4779 ATOM_DEVICE_LCD1_SUPPORT 0x0002 4780ulOtherDisplayMisc: Other display related flags, not defined yet. 4781ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. 4782 =1: TMDS/HDMI Coherent Mode use signel PLL mode. 4783 bit[3]=0: Enable HW AUX mode detection logic 4784 =1: Disable HW AUX mode dettion logic 4785ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. 4786 4787usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 4788 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 4789 4790 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 4791 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 4792 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 4793 Changing BL using VBIOS function is functional in both driver and non-driver present environment; 4794 and enabling VariBri under the driver environment from PP table is optional. 4795 4796 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 4797 that BL control from GPU is expected. 4798 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 4799 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 4800 it's per platform 4801 and enabling VariBri under the driver environment from PP table is optional. 4802 4803ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. 4804 Threshold on value to enter HTC_active state. 4805ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 4806 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 4807ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. 4808ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 4809 =1: PCIE Power Gating Enabled 4810 Bit[1]=0: DDR-DLL shut-down feature disabled. 4811 1: DDR-DLL shut-down feature enabled. 4812 Bit[2]=0: DDR-PLL Power down feature disabled. 4813 1: DDR-PLL Power down feature enabled. 4814ulCPUCapInfo: TBD 4815usNBP0Voltage: VID for voltage on NB P0 State 4816usNBP1Voltage: VID for voltage on NB P1 State 4817usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. 4818usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 4819usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 4820 to indicate a range. 4821 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 4822 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 4823 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 4824 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 4825ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. 4826ucUMAChannelNumber: System memory channel numbers. 4827ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default 4828ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. 4829ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. 4830sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high 4831ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 4832ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. 4833ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. 4834ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 4835ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 4836usPCIEClkSSPercentage: PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%. 4837usPCIEClkSSType: PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for Center spread. 4838usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 4839usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 4840usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 4841usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 4842usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 4843usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 4844usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 4845ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 4846 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 4847 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 4848 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 4849 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 4850**********************************************************************************************************************/ 4851 4852// this Table is used for Liano/Ontario APU 4853typedef struct _ATOM_FUSION_SYSTEM_INFO_V1 4854{ 4855 ATOM_INTEGRATED_SYSTEM_INFO_V6 sIntegratedSysInfo; 4856 ULONG ulPowerplayTable[128]; 4857}ATOM_FUSION_SYSTEM_INFO_V1; 4858 4859 4860typedef struct _ATOM_TDP_CONFIG_BITS 4861{ 4862#if ATOM_BIG_ENDIAN 4863 ULONG uReserved:2; 4864 ULONG uTDP_Value:14; // Original TDP value in tens of milli watts 4865 ULONG uCTDP_Value:14; // Override value in tens of milli watts 4866 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value)) 4867#else 4868 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value)) 4869 ULONG uCTDP_Value:14; // Override value in tens of milli watts 4870 ULONG uTDP_Value:14; // Original TDP value in tens of milli watts 4871 ULONG uReserved:2; 4872#endif 4873}ATOM_TDP_CONFIG_BITS; 4874 4875typedef union _ATOM_TDP_CONFIG 4876{ 4877 ATOM_TDP_CONFIG_BITS TDP_config; 4878 ULONG TDP_config_all; 4879}ATOM_TDP_CONFIG; 4880 4881/********************************************************************************************************************** 4882 ATOM_FUSION_SYSTEM_INFO_V1 Description 4883sIntegratedSysInfo: refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition. 4884ulPowerplayTable[128]: This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0] 4885**********************************************************************************************************************/ 4886 4887// this IntegrateSystemInfoTable is used for Trinity APU 4888typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 4889{ 4890 ATOM_COMMON_TABLE_HEADER sHeader; 4891 ULONG ulBootUpEngineClock; 4892 ULONG ulDentistVCOFreq; 4893 ULONG ulBootUpUMAClock; 4894 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 4895 ULONG ulBootUpReqDisplayVector; 4896 ULONG ulOtherDisplayMisc; 4897 ULONG ulGPUCapInfo; 4898 ULONG ulSB_MMIO_Base_Addr; 4899 USHORT usRequestedPWMFreqInHz; 4900 UCHAR ucHtcTmpLmt; 4901 UCHAR ucHtcHystLmt; 4902 ULONG ulMinEngineClock; 4903 ULONG ulSystemConfig; 4904 ULONG ulCPUCapInfo; 4905 USHORT usNBP0Voltage; 4906 USHORT usNBP1Voltage; 4907 USHORT usBootUpNBVoltage; 4908 USHORT usExtDispConnInfoOffset; 4909 USHORT usPanelRefreshRateRange; 4910 UCHAR ucMemoryType; 4911 UCHAR ucUMAChannelNumber; 4912 UCHAR strVBIOSMsg[40]; 4913 ATOM_TDP_CONFIG asTdpConfig; 4914 ULONG ulReserved[19]; 4915 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 4916 ULONG ulGMCRestoreResetTime; 4917 ULONG ulMinimumNClk; 4918 ULONG ulIdleNClk; 4919 ULONG ulDDR_DLL_PowerUpTime; 4920 ULONG ulDDR_PLL_PowerUpTime; 4921 USHORT usPCIEClkSSPercentage; 4922 USHORT usPCIEClkSSType; 4923 USHORT usLvdsSSPercentage; 4924 USHORT usLvdsSSpreadRateIn10Hz; 4925 USHORT usHDMISSPercentage; 4926 USHORT usHDMISSpreadRateIn10Hz; 4927 USHORT usDVISSPercentage; 4928 USHORT usDVISSpreadRateIn10Hz; 4929 ULONG SclkDpmBoostMargin; 4930 ULONG SclkDpmThrottleMargin; 4931 USHORT SclkDpmTdpLimitPG; 4932 USHORT SclkDpmTdpLimitBoost; 4933 ULONG ulBoostEngineCLock; 4934 UCHAR ulBoostVid_2bit; 4935 UCHAR EnableBoost; 4936 USHORT GnbTdpLimit; 4937 USHORT usMaxLVDSPclkFreqInSingleLink; 4938 UCHAR ucLvdsMisc; 4939 UCHAR ucTravisLVDSVolAdjust; 4940 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 4941 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 4942 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 4943 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 4944 UCHAR ucLVDSOffToOnDelay_in4Ms; 4945 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 4946 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 4947 UCHAR ucMinAllowedBL_Level; 4948 ULONG ulLCDBitDepthControlVal; 4949 ULONG ulNbpStateMemclkFreq[4]; 4950 USHORT usNBP2Voltage; 4951 USHORT usNBP3Voltage; 4952 ULONG ulNbpStateNClkFreq[4]; 4953 UCHAR ucNBDPMEnable; 4954 UCHAR ucReserved[3]; 4955 UCHAR ucDPMState0VclkFid; 4956 UCHAR ucDPMState0DclkFid; 4957 UCHAR ucDPMState1VclkFid; 4958 UCHAR ucDPMState1DclkFid; 4959 UCHAR ucDPMState2VclkFid; 4960 UCHAR ucDPMState2DclkFid; 4961 UCHAR ucDPMState3VclkFid; 4962 UCHAR ucDPMState3DclkFid; 4963 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 4964}ATOM_INTEGRATED_SYSTEM_INFO_V1_7; 4965 4966// ulOtherDisplayMisc 4967#define INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT 0x01 4968#define INTEGRATED_SYSTEM_INFO__GET_BOOTUP_DISPLAY_CALLBACK_FUNC_SUPPORT 0x02 4969#define INTEGRATED_SYSTEM_INFO__GET_EXPANSION_CALLBACK_FUNC_SUPPORT 0x04 4970#define INTEGRATED_SYSTEM_INFO__FAST_BOOT_SUPPORT 0x08 4971 4972// ulGPUCapInfo 4973#define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 4974#define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE 0x02 4975#define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT 0x08 4976#define SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS 0x10 4977 4978/********************************************************************************************************************** 4979 ATOM_INTEGRATED_SYSTEM_INFO_V1_7 Description 4980ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 4981ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 4982ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 4983sDISPCLK_Voltage: Report Display clock voltage requirement. 4984 4985ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: 4986 ATOM_DEVICE_CRT1_SUPPORT 0x0001 4987 ATOM_DEVICE_DFP1_SUPPORT 0x0008 4988 ATOM_DEVICE_DFP6_SUPPORT 0x0040 4989 ATOM_DEVICE_DFP2_SUPPORT 0x0080 4990 ATOM_DEVICE_DFP3_SUPPORT 0x0200 4991 ATOM_DEVICE_DFP4_SUPPORT 0x0400 4992 ATOM_DEVICE_DFP5_SUPPORT 0x0800 4993 ATOM_DEVICE_LCD1_SUPPORT 0x0002 4994ulOtherDisplayMisc: bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. 4995 =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. 4996 bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS 4997 =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS 4998 bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS 4999 =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS 5000 bit[3]=0: VBIOS fast boot is disable
5001 =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open) 5002ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. 5003 =1: TMDS/HDMI Coherent Mode use signel PLL mode. 5004 bit[1]=0: DP mode use cascade PLL mode ( New for Trinity ) 5005 =1: DP mode use single PLL mode 5006 bit[3]=0: Enable AUX HW mode detection logic 5007 =1: Disable AUX HW mode detection logic 5008 5009ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. 5010 5011usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 5012 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 5013 5014 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 5015 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 5016 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 5017 Changing BL using VBIOS function is functional in both driver and non-driver present environment; 5018 and enabling VariBri under the driver environment from PP table is optional. 5019 5020 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 5021 that BL control from GPU is expected. 5022 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 5023 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 5024 it's per platform 5025 and enabling VariBri under the driver environment from PP table is optional. 5026 5027ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. 5028 Threshold on value to enter HTC_active state. 5029ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 5030 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 5031ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. 5032ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 5033 =1: PCIE Power Gating Enabled 5034 Bit[1]=0: DDR-DLL shut-down feature disabled. 5035 1: DDR-DLL shut-down feature enabled. 5036 Bit[2]=0: DDR-PLL Power down feature disabled. 5037 1: DDR-PLL Power down feature enabled. 5038ulCPUCapInfo: TBD 5039usNBP0Voltage: VID for voltage on NB P0 State 5040usNBP1Voltage: VID for voltage on NB P1 State 5041usNBP2Voltage: VID for voltage on NB P2 State 5042usNBP3Voltage: VID for voltage on NB P3 State 5043usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. 5044usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 5045usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 5046 to indicate a range. 5047 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 5048 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 5049 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 5050 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 5051ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. 5052ucUMAChannelNumber: System memory channel numbers. 5053ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default 5054ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. 5055ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. 5056sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high 5057ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 5058ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. 5059ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. 5060ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 5061ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 5062usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. 5063usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. 5064usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 5065usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5066usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 5067usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5068usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 5069usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5070usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 5071ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 5072 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 5073 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 5074 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 5075 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 5076 [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4 5077ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust 5078 value to program Travis register LVDS_CTRL_4 5079ucLVDSPwrOnSeqDIGONtoDE_in4Ms: LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). 5080 =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 5081 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5082ucLVDSPwrOnDEtoVARY_BL_in4Ms: LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). 5083 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 5084 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5085 5086ucLVDSPwrOffVARY_BLtoDE_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. 5087 =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 5088 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5089 5090ucLVDSPwrOffDEtoDIGON_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. 5091 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 5092 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5093 5094ucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. 5095 =0 means to use VBIOS default delay which is 125 ( 500ms ). 5096 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5097 5098ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms: 5099 LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. 5100 =0 means to use VBIOS default delay which is 0 ( 0ms ). 5101 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5102 5103ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: 5104 LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. 5105 =0 means to use VBIOS default delay which is 0 ( 0ms ). 5106 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5107 5108ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. 5109 5110ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB pstate. 5111 5112**********************************************************************************************************************/ 5113 5114// this IntegrateSystemInfoTable is used for Kaveri & Kabini APU 5115typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 5116{ 5117 ATOM_COMMON_TABLE_HEADER sHeader; 5118 ULONG ulBootUpEngineClock; 5119 ULONG ulDentistVCOFreq; 5120 ULONG ulBootUpUMAClock; 5121 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 5122 ULONG ulBootUpReqDisplayVector; 5123 ULONG ulVBIOSMisc; 5124 ULONG ulGPUCapInfo; 5125 ULONG ulDISP_CLK2Freq; 5126 USHORT usRequestedPWMFreqInHz; 5127 UCHAR ucHtcTmpLmt; 5128 UCHAR ucHtcHystLmt; 5129 ULONG ulReserved2; 5130 ULONG ulSystemConfig; 5131 ULONG ulCPUCapInfo; 5132 ULONG ulReserved3; 5133 USHORT usGPUReservedSysMemSize; 5134 USHORT usExtDispConnInfoOffset; 5135 USHORT usPanelRefreshRateRange; 5136 UCHAR ucMemoryType; 5137 UCHAR ucUMAChannelNumber; 5138 UCHAR strVBIOSMsg[40]; 5139 ATOM_TDP_CONFIG asTdpConfig; 5140 ULONG ulReserved[19]; 5141 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 5142 ULONG ulGMCRestoreResetTime; 5143 ULONG ulReserved4; 5144 ULONG ulIdleNClk; 5145 ULONG ulDDR_DLL_PowerUpTime; 5146 ULONG ulDDR_PLL_PowerUpTime; 5147 USHORT usPCIEClkSSPercentage; 5148 USHORT usPCIEClkSSType; 5149 USHORT usLvdsSSPercentage; 5150 USHORT usLvdsSSpreadRateIn10Hz; 5151 USHORT usHDMISSPercentage; 5152 USHORT usHDMISSpreadRateIn10Hz; 5153 USHORT usDVISSPercentage; 5154 USHORT usDVISSpreadRateIn10Hz; 5155 ULONG ulGPUReservedSysMemBaseAddrLo; 5156 ULONG ulGPUReservedSysMemBaseAddrHi; 5157 ULONG ulReserved5[3]; 5158 USHORT usMaxLVDSPclkFreqInSingleLink; 5159 UCHAR ucLvdsMisc; 5160 UCHAR ucTravisLVDSVolAdjust; 5161 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 5162 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 5163 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 5164 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 5165 UCHAR ucLVDSOffToOnDelay_in4Ms; 5166 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 5167 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 5168 UCHAR ucMinAllowedBL_Level; 5169 ULONG ulLCDBitDepthControlVal; 5170 ULONG ulNbpStateMemclkFreq[4]; 5171 ULONG ulReserved6; 5172 ULONG ulNbpStateNClkFreq[4]; 5173 USHORT usNBPStateVoltage[4]; 5174 USHORT usBootUpNBVoltage; 5175 USHORT usReserved2; 5176 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 5177}ATOM_INTEGRATED_SYSTEM_INFO_V1_8; 5178 5179/********************************************************************************************************************** 5180 ATOM_INTEGRATED_SYSTEM_INFO_V1_8 Description 5181ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 5182ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 5183ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 5184sDISPCLK_Voltage: Report Display clock frequency requirement on GNB voltage(up to 4 voltage levels). 5185 5186ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: 5187 ATOM_DEVICE_CRT1_SUPPORT 0x0001 5188 ATOM_DEVICE_DFP1_SUPPORT 0x0008 5189 ATOM_DEVICE_DFP6_SUPPORT 0x0040 5190 ATOM_DEVICE_DFP2_SUPPORT 0x0080 5191 ATOM_DEVICE_DFP3_SUPPORT 0x0200 5192 ATOM_DEVICE_DFP4_SUPPORT 0x0400 5193 ATOM_DEVICE_DFP5_SUPPORT 0x0800 5194 ATOM_DEVICE_LCD1_SUPPORT 0x0002 5195 5196ulVBIOSMisc: Miscellenous flags for VBIOS requirement and interface 5197 bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. 5198 =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. 5199 bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS 5200 =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS 5201 bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS 5202 =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS 5203 bit[3]=0: VBIOS fast boot is disable 5204 =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open) 5205 5206ulGPUCapInfo: bit[0~2]= Reserved 5207 bit[3]=0: Enable AUX HW mode detection logic 5208 =1: Disable AUX HW mode detection logic 5209 bit[4]=0: Disable DFS bypass feature 5210 =1: Enable DFS bypass feature 5211 5212usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 5213 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 5214 5215 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 5216 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 5217 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 5218 Changing BL using VBIOS function is functional in both driver and non-driver present environment; 5219 and enabling VariBri under the driver environment from PP table is optional. 5220 5221 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 5222 that BL control from GPU is expected. 5223 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 5224 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 5225 it's per platform 5226 and enabling VariBri under the driver environment from PP table is optional. 5227 5228ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to enter HTC_active state. 5229ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 5230 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 5231 5232ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 5233 =1: PCIE Power Gating Enabled 5234 Bit[1]=0: DDR-DLL shut-down feature disabled. 5235 1: DDR-DLL shut-down feature enabled. 5236 Bit[2]=0: DDR-PLL Power down feature disabled. 5237 1: DDR-PLL Power down feature enabled. 5238 Bit[3]=0: GNB DPM is disabled 5239 =1: GNB DPM is enabled 5240ulCPUCapInfo: TBD 5241 5242usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 5243usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 5244 to indicate a range. 5245 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 5246 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 5247 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 5248 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 5249 5250ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3;=5:GDDR5; [7:4] is reserved. 5251ucUMAChannelNumber: System memory channel numbers. 5252 5253strVBIOSMsg[40]: VBIOS boot up customized message string 5254 5255sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high 5256 5257ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 5258ulIdleNClk: NCLK speed while memory runs in self-refresh state, used to calculate self-refresh latency. Unit in 10kHz. 5259ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 5260ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 5261 5262usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. 5263usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. 5264usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 5265usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5266usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 5267usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5268usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 5269usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5270 5271usGPUReservedSysMemSize: Reserved system memory size for ACP engine in APU GNB, units in MB. 0/2/4MB based on CMOS options, current default could be 0MB. KV only, not on KB. 5272ulGPUReservedSysMemBaseAddrLo: Low 32 bits base address to the reserved system memory. 5273ulGPUReservedSysMemBaseAddrHi: High 32 bits base address to the reserved system memory. 5274 5275usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 5276ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 5277 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 5278 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 5279 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 5280 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 5281 [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4 5282ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust 5283 value to program Travis register LVDS_CTRL_4 5284ucLVDSPwrOnSeqDIGONtoDE_in4Ms: 5285 LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). 5286 =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 5287 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5288ucLVDSPwrOnDEtoVARY_BL_in4Ms: 5289 LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). 5290 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 5291 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5292ucLVDSPwrOffVARY_BLtoDE_in4Ms: 5293 LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. 5294 =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 5295 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5296ucLVDSPwrOffDEtoDIGON_in4Ms: 5297 LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. 5298 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 5299 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5300ucLVDSOffToOnDelay_in4Ms: 5301 LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. 5302 =0 means to use VBIOS default delay which is 125 ( 500ms ). 5303 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5304ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms: 5305 LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. 5306 =0 means to use VBIOS default delay which is 0 ( 0ms ). 5307 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5308 5309ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: 5310 LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. 5311 =0 means to use VBIOS default delay which is 0 ( 0ms ). 5312 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5313ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. 5314 5315ulLCDBitDepthControlVal: GPU display control encoder bit dither control setting, used to program register mmFMT_BIT_DEPTH_CONTROL 5316 5317ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-State(P0, P1, P2 & P3). 5318ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State 5319usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage 5320usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded 5321sExtDispConnInfo: Display connector information table provided to VBIOS 5322 5323**********************************************************************************************************************/ 5324 5325// this Table is used for Kaveri/Kabini APU 5326typedef struct _ATOM_FUSION_SYSTEM_INFO_V2 5327{ 5328 ATOM_INTEGRATED_SYSTEM_INFO_V1_8 sIntegratedSysInfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition 5329 ULONG ulPowerplayTable[128]; // Update comments here to link new powerplay table definition structure 5330}ATOM_FUSION_SYSTEM_INFO_V2; 5331 5332 5333/**************************************************************************/ 5334// This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design 5335//Memory SS Info Table 5336//Define Memory Clock SS chip ID 5337#define ICS91719 1 5338#define ICS91720 2 5339 5340//Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol 5341typedef struct _ATOM_I2C_DATA_RECORD 5342{ 5343 UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop" 5344 UCHAR ucI2CData[1]; //I2C data in bytes, should be less than 16 bytes usually 5345}ATOM_I2C_DATA_RECORD; 5346 5347 5348//Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information 5349typedef struct _ATOM_I2C_DEVICE_SETUP_INFO 5350{ 5351 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap. 5352 UCHAR ucSSChipID; //SS chip being used 5353 UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip 5354 UCHAR ucNumOfI2CDataRecords; //number of data block 5355 ATOM_I2C_DATA_RECORD asI2CData[1]; 5356}ATOM_I2C_DEVICE_SETUP_INFO; 5357 5358//========================================================================================== 5359typedef struct _ATOM_ASIC_MVDD_INFO 5360{ 5361 ATOM_COMMON_TABLE_HEADER sHeader; 5362 ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1]; 5363}ATOM_ASIC_MVDD_INFO; 5364 5365//========================================================================================== 5366#define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO 5367 5368//========================================================================================== 5369/**************************************************************************/ 5370 5371typedef struct _ATOM_ASIC_SS_ASSIGNMENT 5372{ 5373 ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz 5374 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 5375 USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq 5376 UCHAR ucClockIndication; //Indicate which clock source needs SS 5377 UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread. 5378 UCHAR ucReserved[2]; 5379}ATOM_ASIC_SS_ASSIGNMENT; 5380 5381//Define ucClockIndication, SW uses the IDs below to search if the SS is required/enabled on a clock branch/signal type. 5382//SS is not required or enabled if a match is not found. 5383#define ASIC_INTERNAL_MEMORY_SS 1 5384#define ASIC_INTERNAL_ENGINE_SS 2 5385#define ASIC_INTERNAL_UVD_SS 3 5386#define ASIC_INTERNAL_SS_ON_TMDS 4 5387#define ASIC_INTERNAL_SS_ON_HDMI 5 5388#define ASIC_INTERNAL_SS_ON_LVDS 6 5389#define ASIC_INTERNAL_SS_ON_DP 7 5390#define ASIC_INTERNAL_SS_ON_DCPLL 8 5391#define ASIC_EXTERNAL_SS_ON_DP_CLOCK 9 5392#define ASIC_INTERNAL_VCE_SS 10 5393#define ASIC_INTERNAL_GPUPLL_SS 11 5394 5395 5396typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2 5397{ 5398 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz 5399 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) 5400 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% or 0.001%, decided by ucSpreadSpectrumMode bit4 5401 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq 5402 UCHAR ucClockIndication; //Indicate which clock source needs SS 5403 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS 5404 UCHAR ucReserved[2]; 5405}ATOM_ASIC_SS_ASSIGNMENT_V2; 5406 5407//ucSpreadSpectrumMode 5408//#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 5409//#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 5410//#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 5411//#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 5412//#define ATOM_INTERNAL_SS_MASK 0x00000000 5413//#define ATOM_EXTERNAL_SS_MASK 0x00000002 5414 5415typedef struct _ATOM_ASIC_INTERNAL_SS_INFO 5416{ 5417 ATOM_COMMON_TABLE_HEADER sHeader; 5418 ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4]; 5419}ATOM_ASIC_INTERNAL_SS_INFO; 5420 5421typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 5422{ 5423 ATOM_COMMON_TABLE_HEADER sHeader; 5424 ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[1]; //this is point only. 5425}ATOM_ASIC_INTERNAL_SS_INFO_V2; 5426 5427typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3 5428{ 5429 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz 5430 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) 5431 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 5432 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq 5433 UCHAR ucClockIndication; //Indicate which clock source needs SS 5434 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS 5435 UCHAR ucReserved[2]; 5436}ATOM_ASIC_SS_ASSIGNMENT_V3; 5437 5438//ATOM_ASIC_SS_ASSIGNMENT_V3.ucSpreadSpectrumMode 5439#define SS_MODE_V3_CENTRE_SPREAD_MASK 0x01 5440#define SS_MODE_V3_EXTERNAL_SS_MASK 0x02 5441#define SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK 0x10 5442 5443typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 5444{ 5445 ATOM_COMMON_TABLE_HEADER sHeader; 5446 ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[1]; //this is pointer only. 5447}ATOM_ASIC_INTERNAL_SS_INFO_V3; 5448 5449 5450//==============================Scratch Pad Definition Portion=============================== 5451#define ATOM_DEVICE_CONNECT_INFO_DEF 0 5452#define ATOM_ROM_LOCATION_DEF 1 5453#define ATOM_TV_STANDARD_DEF 2 5454#define ATOM_ACTIVE_INFO_DEF 3 5455#define ATOM_LCD_INFO_DEF 4 5456#define ATOM_DOS_REQ_INFO_DEF 5 5457#define ATOM_ACC_CHANGE_INFO_DEF 6 5458#define ATOM_DOS_MODE_INFO_DEF 7 5459#define ATOM_I2C_CHANNEL_STATUS_DEF 8 5460#define ATOM_I2C_CHANNEL_STATUS1_DEF 9 5461#define ATOM_INTERNAL_TIMER_DEF 10 5462 5463// BIOS_0_SCRATCH Definition 5464#define ATOM_S0_CRT1_MONO 0x00000001L 5465#define ATOM_S0_CRT1_COLOR 0x00000002L 5466#define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR) 5467 5468#define ATOM_S0_TV1_COMPOSITE_A 0x00000004L 5469#define ATOM_S0_TV1_SVIDEO_A 0x00000008L 5470#define ATOM_S0_TV1_MASK_A (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A) 5471 5472#define ATOM_S0_CV_A 0x00000010L 5473#define ATOM_S0_CV_DIN_A 0x00000020L 5474#define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A) 5475 5476 5477#define ATOM_S0_CRT2_MONO 0x00000100L 5478#define ATOM_S0_CRT2_COLOR 0x00000200L 5479#define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR) 5480 5481#define ATOM_S0_TV1_COMPOSITE 0x00000400L 5482#define ATOM_S0_TV1_SVIDEO 0x00000800L 5483#define ATOM_S0_TV1_SCART 0x00004000L 5484#define ATOM_S0_TV1_MASK (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART) 5485 5486#define ATOM_S0_CV 0x00001000L 5487#define ATOM_S0_CV_DIN 0x00002000L 5488#define ATOM_S0_CV_MASK (ATOM_S0_CV+ATOM_S0_CV_DIN) 5489 5490#define ATOM_S0_DFP1 0x00010000L 5491#define ATOM_S0_DFP2 0x00020000L 5492#define ATOM_S0_LCD1 0x00040000L 5493#define ATOM_S0_LCD2 0x00080000L 5494#define ATOM_S0_DFP6 0x00100000L 5495#define ATOM_S0_DFP3 0x00200000L 5496#define ATOM_S0_DFP4 0x00400000L 5497#define ATOM_S0_DFP5 0x00800000L 5498 5499#define ATOM_S0_DFP_MASK ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6 5500 5501#define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with 5502 // the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx 5503 5504#define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L 5505#define ATOM_S0_THERMAL_STATE_SHIFT 26 5506 5507#define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L 5508#define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 5509 5510#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 5511#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 5512#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 5513#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4 5514 5515//Byte aligned definition for BIOS usage 5516#define ATOM_S0_CRT1_MONOb0 0x01 5517#define ATOM_S0_CRT1_COLORb0 0x02 5518#define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0) 5519 5520#define ATOM_S0_TV1_COMPOSITEb0 0x04 5521#define ATOM_S0_TV1_SVIDEOb0 0x08 5522#define ATOM_S0_TV1_MASKb0 (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0) 5523 5524#define ATOM_S0_CVb0 0x10 5525#define ATOM_S0_CV_DINb0 0x20 5526#define ATOM_S0_CV_MASKb0 (ATOM_S0_CVb0+ATOM_S0_CV_DINb0) 5527 5528#define ATOM_S0_CRT2_MONOb1 0x01 5529#define ATOM_S0_CRT2_COLORb1 0x02 5530#define ATOM_S0_CRT2_MASKb1 (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1) 5531 5532#define ATOM_S0_TV1_COMPOSITEb1 0x04 5533#define ATOM_S0_TV1_SVIDEOb1 0x08 5534#define ATOM_S0_TV1_SCARTb1 0x40 5535#define ATOM_S0_TV1_MASKb1 (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1) 5536 5537#define ATOM_S0_CVb1 0x10 5538#define ATOM_S0_CV_DINb1 0x20 5539#define ATOM_S0_CV_MASKb1 (ATOM_S0_CVb1+ATOM_S0_CV_DINb1) 5540 5541#define ATOM_S0_DFP1b2 0x01 5542#define ATOM_S0_DFP2b2 0x02 5543#define ATOM_S0_LCD1b2 0x04 5544#define ATOM_S0_LCD2b2 0x08 5545#define ATOM_S0_DFP6b2 0x10 5546#define ATOM_S0_DFP3b2 0x20 5547#define ATOM_S0_DFP4b2 0x40 5548#define ATOM_S0_DFP5b2 0x80 5549 5550 5551#define ATOM_S0_THERMAL_STATE_MASKb3 0x1C 5552#define ATOM_S0_THERMAL_STATE_SHIFTb3 2 5553 5554#define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0 5555#define ATOM_S0_LCD1_SHIFT 18 5556 5557// BIOS_1_SCRATCH Definition 5558#define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL 5559#define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L 5560 5561// BIOS_2_SCRATCH Definition 5562#define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL 5563#define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L 5564#define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8 5565 5566#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L 5567#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26 5568#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L 5569 5570#define ATOM_S2_DEVICE_DPMS_STATE 0x00010000L 5571#define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L 5572 5573#define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0 5574#define ATOM_S2_DISPLAY_ROTATION_90_DEGREE 0x1 5575#define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2 5576#define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3 5577#define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30 5578#define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L 5579 5580 5581//Byte aligned definition for BIOS usage 5582#define ATOM_S2_TV1_STANDARD_MASKb0 0x0F 5583#define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF 5584#define ATOM_S2_DEVICE_DPMS_STATEb2 0x01 5585 5586#define ATOM_S2_DEVICE_DPMS_MASKw1 0x3FF 5587#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3 0x0C 5588#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGEb3 0x10 5589#define ATOM_S2_TMDS_COHERENT_MODEb3 0x10 // used by VBIOS code only, use coherent mode for TMDS/HDMI mode 5590#define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20 5591#define ATOM_S2_ROTATION_STATE_MASKb3 0xC0 5592 5593 5594// BIOS_3_SCRATCH Definition 5595#define ATOM_S3_CRT1_ACTIVE 0x00000001L 5596#define ATOM_S3_LCD1_ACTIVE 0x00000002L 5597#define ATOM_S3_TV1_ACTIVE 0x00000004L 5598#define ATOM_S3_DFP1_ACTIVE 0x00000008L 5599#define ATOM_S3_CRT2_ACTIVE 0x00000010L 5600#define ATOM_S3_LCD2_ACTIVE 0x00000020L 5601#define ATOM_S3_DFP6_ACTIVE 0x00000040L 5602#define ATOM_S3_DFP2_ACTIVE 0x00000080L 5603#define ATOM_S3_CV_ACTIVE 0x00000100L 5604#define ATOM_S3_DFP3_ACTIVE 0x00000200L 5605#define ATOM_S3_DFP4_ACTIVE 0x00000400L 5606#define ATOM_S3_DFP5_ACTIVE 0x00000800L 5607 5608#define ATOM_S3_DEVICE_ACTIVE_MASK 0x00000FFFL 5609 5610#define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L 5611#define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L 5612 5613#define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L 5614#define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L 5615#define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L 5616#define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L 5617#define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L 5618#define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L 5619#define ATOM_S3_DFP6_CRTC_ACTIVE 0x00400000L 5620#define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L 5621#define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L 5622#define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L 5623#define ATOM_S3_DFP4_CRTC_ACTIVE 0x04000000L 5624#define ATOM_S3_DFP5_CRTC_ACTIVE 0x08000000L 5625 5626#define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L 5627#define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L 5628//Below two definitions are not supported in pplib, but in the old powerplay in DAL 5629#define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L 5630#define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L 5631 5632//Byte aligned definition for BIOS usage 5633#define ATOM_S3_CRT1_ACTIVEb0 0x01 5634#define ATOM_S3_LCD1_ACTIVEb0 0x02 5635#define ATOM_S3_TV1_ACTIVEb0 0x04 5636#define ATOM_S3_DFP1_ACTIVEb0 0x08 5637#define ATOM_S3_CRT2_ACTIVEb0 0x10 5638#define ATOM_S3_LCD2_ACTIVEb0 0x20 5639#define ATOM_S3_DFP6_ACTIVEb0 0x40 5640#define ATOM_S3_DFP2_ACTIVEb0 0x80 5641#define ATOM_S3_CV_ACTIVEb1 0x01 5642#define ATOM_S3_DFP3_ACTIVEb1 0x02 5643#define ATOM_S3_DFP4_ACTIVEb1 0x04 5644#define ATOM_S3_DFP5_ACTIVEb1 0x08 5645 5646#define ATOM_S3_ACTIVE_CRTC1w0 0xFFF 5647 5648#define ATOM_S3_CRT1_CRTC_ACTIVEb2 0x01 5649#define ATOM_S3_LCD1_CRTC_ACTIVEb2 0x02 5650#define ATOM_S3_TV1_CRTC_ACTIVEb2 0x04 5651#define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08 5652#define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10 5653#define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20 5654#define ATOM_S3_DFP6_CRTC_ACTIVEb2 0x40 5655#define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80 5656#define ATOM_S3_CV_CRTC_ACTIVEb3 0x01 5657#define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02 5658#define ATOM_S3_DFP4_CRTC_ACTIVEb3 0x04 5659#define ATOM_S3_DFP5_CRTC_ACTIVEb3 0x08 5660 5661#define ATOM_S3_ACTIVE_CRTC2w1 0xFFF 5662 5663// BIOS_4_SCRATCH Definition 5664#define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL 5665#define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L 5666#define ATOM_S4_LCD1_REFRESH_SHIFT 8 5667 5668//Byte aligned definition for BIOS usage 5669#define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF 5670#define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0 5671#define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0 5672 5673// BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!! 5674#define ATOM_S5_DOS_REQ_CRT1b0 0x01 5675#define ATOM_S5_DOS_REQ_LCD1b0 0x02 5676#define ATOM_S5_DOS_REQ_TV1b0 0x04 5677#define ATOM_S5_DOS_REQ_DFP1b0 0x08 5678#define ATOM_S5_DOS_REQ_CRT2b0 0x10 5679#define ATOM_S5_DOS_REQ_LCD2b0 0x20 5680#define ATOM_S5_DOS_REQ_DFP6b0 0x40 5681#define ATOM_S5_DOS_REQ_DFP2b0 0x80 5682#define ATOM_S5_DOS_REQ_CVb1 0x01 5683#define ATOM_S5_DOS_REQ_DFP3b1 0x02 5684#define ATOM_S5_DOS_REQ_DFP4b1 0x04 5685#define ATOM_S5_DOS_REQ_DFP5b1 0x08 5686 5687#define ATOM_S5_DOS_REQ_DEVICEw0 0x0FFF 5688 5689#define ATOM_S5_DOS_REQ_CRT1 0x0001 5690#define ATOM_S5_DOS_REQ_LCD1 0x0002 5691#define ATOM_S5_DOS_REQ_TV1 0x0004 5692#define ATOM_S5_DOS_REQ_DFP1 0x0008 5693#define ATOM_S5_DOS_REQ_CRT2 0x0010 5694#define ATOM_S5_DOS_REQ_LCD2 0x0020 5695#define ATOM_S5_DOS_REQ_DFP6 0x0040 5696#define ATOM_S5_DOS_REQ_DFP2 0x0080 5697#define ATOM_S5_DOS_REQ_CV 0x0100 5698#define ATOM_S5_DOS_REQ_DFP3 0x0200 5699#define ATOM_S5_DOS_REQ_DFP4 0x0400 5700#define ATOM_S5_DOS_REQ_DFP5 0x0800 5701 5702#define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0 5703#define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0 5704#define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0 5705#define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1 5706#define ATOM_S5_DOS_FORCE_DEVICEw1 (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\ 5707 (ATOM_S5_DOS_FORCE_CVb3<<8)) 5708 5709// BIOS_6_SCRATCH Definition 5710#define ATOM_S6_DEVICE_CHANGE 0x00000001L 5711#define ATOM_S6_SCALER_CHANGE 0x00000002L 5712#define ATOM_S6_LID_CHANGE 0x00000004L 5713#define ATOM_S6_DOCKING_CHANGE 0x00000008L 5714#define ATOM_S6_ACC_MODE 0x00000010L 5715#define ATOM_S6_EXT_DESKTOP_MODE 0x00000020L 5716#define ATOM_S6_LID_STATE 0x00000040L 5717#define ATOM_S6_DOCK_STATE 0x00000080L 5718#define ATOM_S6_CRITICAL_STATE 0x00000100L 5719#define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L 5720#define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L 5721#define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L 5722#define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD 5723#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for LCD 5724 5725#define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion 5726#define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion 5727 5728#define ATOM_S6_ACC_REQ_CRT1 0x00010000L 5729#define ATOM_S6_ACC_REQ_LCD1 0x00020000L 5730#define ATOM_S6_ACC_REQ_TV1 0x00040000L 5731#define ATOM_S6_ACC_REQ_DFP1 0x00080000L 5732#define ATOM_S6_ACC_REQ_CRT2 0x00100000L 5733#define ATOM_S6_ACC_REQ_LCD2 0x00200000L 5734#define ATOM_S6_ACC_REQ_DFP6 0x00400000L 5735#define ATOM_S6_ACC_REQ_DFP2 0x00800000L 5736#define ATOM_S6_ACC_REQ_CV 0x01000000L 5737#define ATOM_S6_ACC_REQ_DFP3 0x02000000L 5738#define ATOM_S6_ACC_REQ_DFP4 0x04000000L 5739#define ATOM_S6_ACC_REQ_DFP5 0x08000000L 5740 5741#define ATOM_S6_ACC_REQ_MASK 0x0FFF0000L 5742#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L 5743#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L 5744#define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L 5745#define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L 5746 5747//Byte aligned definition for BIOS usage 5748#define ATOM_S6_DEVICE_CHANGEb0 0x01 5749#define ATOM_S6_SCALER_CHANGEb0 0x02 5750#define ATOM_S6_LID_CHANGEb0 0x04 5751#define ATOM_S6_DOCKING_CHANGEb0 0x08 5752#define ATOM_S6_ACC_MODEb0 0x10 5753#define ATOM_S6_EXT_DESKTOP_MODEb0 0x20 5754#define ATOM_S6_LID_STATEb0 0x40 5755#define ATOM_S6_DOCK_STATEb0 0x80 5756#define ATOM_S6_CRITICAL_STATEb1 0x01 5757#define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02 5758#define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04 5759#define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08 5760#define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10 5761#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20 5762 5763#define ATOM_S6_ACC_REQ_CRT1b2 0x01 5764#define ATOM_S6_ACC_REQ_LCD1b2 0x02 5765#define ATOM_S6_ACC_REQ_TV1b2 0x04 5766#define ATOM_S6_ACC_REQ_DFP1b2 0x08 5767#define ATOM_S6_ACC_REQ_CRT2b2 0x10 5768#define ATOM_S6_ACC_REQ_LCD2b2 0x20 5769#define ATOM_S6_ACC_REQ_DFP6b2 0x40 5770#define ATOM_S6_ACC_REQ_DFP2b2 0x80 5771#define ATOM_S6_ACC_REQ_CVb3 0x01 5772#define ATOM_S6_ACC_REQ_DFP3b3 0x02 5773#define ATOM_S6_ACC_REQ_DFP4b3 0x04 5774#define ATOM_S6_ACC_REQ_DFP5b3 0x08 5775 5776#define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0 5777#define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10 5778#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20 5779#define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 0x40 5780#define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 0x80 5781 5782#define ATOM_S6_DEVICE_CHANGE_SHIFT 0 5783#define ATOM_S6_SCALER_CHANGE_SHIFT 1 5784#define ATOM_S6_LID_CHANGE_SHIFT 2 5785#define ATOM_S6_DOCKING_CHANGE_SHIFT 3 5786#define ATOM_S6_ACC_MODE_SHIFT 4 5787#define ATOM_S6_EXT_DESKTOP_MODE_SHIFT 5 5788#define ATOM_S6_LID_STATE_SHIFT 6 5789#define ATOM_S6_DOCK_STATE_SHIFT 7 5790#define ATOM_S6_CRITICAL_STATE_SHIFT 8 5791#define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT 9 5792#define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT 10 5793#define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT 11 5794#define ATOM_S6_REQ_SCALER_SHIFT 12 5795#define ATOM_S6_REQ_SCALER_ARATIO_SHIFT 13 5796#define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT 14 5797#define ATOM_S6_I2C_STATE_CHANGE_SHIFT 15 5798#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT 28 5799#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT 29 5800#define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30 5801#define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31 5802 5803// BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!! 5804#define ATOM_S7_DOS_MODE_TYPEb0 0x03 5805#define ATOM_S7_DOS_MODE_VGAb0 0x00 5806#define ATOM_S7_DOS_MODE_VESAb0 0x01 5807#define ATOM_S7_DOS_MODE_EXTb0 0x02 5808#define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C 5809#define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0 5810#define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01 5811#define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF 5812 5813#define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8 5814 5815// BIOS_8_SCRATCH Definition 5816#define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF 5817#define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000 5818 5819#define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0 5820#define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16 5821 5822// BIOS_9_SCRATCH Definition 5823#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 5824#define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF 5825#endif 5826#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK 5827#define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000 5828#endif 5829#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 5830#define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0 5831#endif 5832#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 5833#define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16 5834#endif 5835 5836 5837#define ATOM_FLAG_SET 0x20 5838#define ATOM_FLAG_CLEAR 0 5839#define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR) 5840#define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET) 5841#define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET) 5842#define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET) 5843#define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET) 5844 5845#define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET) 5846#define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR) 5847 5848#define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET) 5849#define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET) 5850#define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR) 5851 5852#define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET) 5853#define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET) 5854#define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET) 5855 5856#define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET) 5857#define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR) 5858 5859#define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET) 5860#define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR ) 5861 5862#define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET ) 5863#define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR ) 5864 5865#define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) 5866 5867#define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) 5868 5869#define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET) 5870#define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR ) 5871#define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET ) 5872#define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR ) 5873 5874/****************************************************************************/ 5875//Portion II: Definitinos only used in Driver 5876/****************************************************************************/ 5877 5878// Macros used by driver 5879#ifdef __cplusplus 5880#define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast<char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<char*>(0))/sizeof(USHORT)) 5881 5882#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F) 5883#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F) 5884#else // not __cplusplus 5885#define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT)) 5886 5887#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F) 5888#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F) 5889#endif // __cplusplus 5890 5891#define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION 5892#define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION 5893 5894/****************************************************************************/ 5895//Portion III: Definitinos only used in VBIOS 5896/****************************************************************************/ 5897#define ATOM_DAC_SRC 0x80 5898#define ATOM_SRC_DAC1 0 5899#define ATOM_SRC_DAC2 0x80 5900 5901typedef struct _MEMORY_PLLINIT_PARAMETERS 5902{ 5903 ULONG ulTargetMemoryClock; //In 10Khz unit 5904 UCHAR ucAction; //not define yet 5905 UCHAR ucFbDiv_Hi; //Fbdiv Hi byte 5906 UCHAR ucFbDiv; //FB value 5907 UCHAR ucPostDiv; //Post div 5908}MEMORY_PLLINIT_PARAMETERS; 5909 5910#define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS 5911 5912 5913#define GPIO_PIN_WRITE 0x01 5914#define GPIO_PIN_READ 0x00 5915 5916typedef struct _GPIO_PIN_CONTROL_PARAMETERS 5917{ 5918 UCHAR ucGPIO_ID; //return value, read from GPIO pins 5919 UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update 5920 UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask 5921 UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write 5922}GPIO_PIN_CONTROL_PARAMETERS; 5923 5924typedef struct _ENABLE_SCALER_PARAMETERS 5925{ 5926 UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2 5927 UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION 5928 UCHAR ucTVStandard; // 5929 UCHAR ucPadding[1]; 5930}ENABLE_SCALER_PARAMETERS; 5931#define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS 5932 5933//ucEnable: 5934#define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0 5935#define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1 5936#define SCALER_ENABLE_2TAP_ALPHA_MODE 2 5937#define SCALER_ENABLE_MULTITAP_MODE 3 5938 5939typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS 5940{ 5941 ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position 5942 UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset 5943 UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset 5944 UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2 5945 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 5946}ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS; 5947 5948typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION 5949{ 5950 ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon; 5951 ENABLE_CRTC_PARAMETERS sReserved; 5952}ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION; 5953 5954typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS 5955{ 5956 USHORT usHight; // Image Hight 5957 USHORT usWidth; // Image Width 5958 UCHAR ucSurface; // Surface 1 or 2 5959 UCHAR ucPadding[3]; 5960}ENABLE_GRAPH_SURFACE_PARAMETERS; 5961 5962typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2 5963{ 5964 USHORT usHight; // Image Hight 5965 USHORT usWidth; // Image Width 5966 UCHAR ucSurface; // Surface 1 or 2 5967 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 5968 UCHAR ucPadding[2]; 5969}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2; 5970 5971typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3 5972{ 5973 USHORT usHight; // Image Hight 5974 USHORT usWidth; // Image Width 5975 UCHAR ucSurface; // Surface 1 or 2 5976 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 5977 USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0. 5978}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3; 5979 5980typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4 5981{ 5982 USHORT usHight; // Image Hight 5983 USHORT usWidth; // Image Width 5984 USHORT usGraphPitch; 5985 UCHAR ucColorDepth; 5986 UCHAR ucPixelFormat; 5987 UCHAR ucSurface; // Surface 1 or 2 5988 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 5989 UCHAR ucModeType; 5990 UCHAR ucReserved; 5991}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4; 5992 5993// ucEnable 5994#define ATOM_GRAPH_CONTROL_SET_PITCH 0x0f 5995#define ATOM_GRAPH_CONTROL_SET_DISP_START 0x10 5996 5997typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION 5998{ 5999 ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface; 6000 ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one
6001}ENABLE_GRAPH_SURFACE_PS_ALLOCATION; 6002 6003typedef struct _MEMORY_CLEAN_UP_PARAMETERS 6004{ 6005 USHORT usMemoryStart; //in 8Kb boundary, offset from memory base address 6006 USHORT usMemorySize; //8Kb blocks aligned 6007}MEMORY_CLEAN_UP_PARAMETERS; 6008#define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS 6009 6010typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS 6011{ 6012 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC 6013 USHORT usY_Size; 6014}GET_DISPLAY_SURFACE_SIZE_PARAMETERS; 6015 6016typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2 6017{ 6018 union{ 6019 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC 6020 USHORT usSurface; 6021 }; 6022 USHORT usY_Size; 6023 USHORT usDispXStart; 6024 USHORT usDispYStart; 6025}GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2; 6026 6027 6028typedef struct _PALETTE_DATA_CONTROL_PARAMETERS_V3 6029{ 6030 UCHAR ucLutId; 6031 UCHAR ucAction; 6032 USHORT usLutStartIndex; 6033 USHORT usLutLength; 6034 USHORT usLutOffsetInVram; 6035}PALETTE_DATA_CONTROL_PARAMETERS_V3; 6036 6037// ucAction: 6038#define PALETTE_DATA_AUTO_FILL 1 6039#define PALETTE_DATA_READ 2 6040#define PALETTE_DATA_WRITE 3 6041 6042 6043typedef struct _INTERRUPT_SERVICE_PARAMETERS_V2 6044{ 6045 UCHAR ucInterruptId; 6046 UCHAR ucServiceId; 6047 UCHAR ucStatus; 6048 UCHAR ucReserved; 6049}INTERRUPT_SERVICE_PARAMETER_V2; 6050 6051// ucInterruptId 6052#define HDP1_INTERRUPT_ID 1 6053#define HDP2_INTERRUPT_ID 2 6054#define HDP3_INTERRUPT_ID 3 6055#define HDP4_INTERRUPT_ID 4 6056#define HDP5_INTERRUPT_ID 5 6057#define HDP6_INTERRUPT_ID 6 6058#define SW_INTERRUPT_ID 11 6059 6060// ucAction 6061#define INTERRUPT_SERVICE_GEN_SW_INT 1 6062#define INTERRUPT_SERVICE_GET_STATUS 2 6063 6064 // ucStatus 6065#define INTERRUPT_STATUS__INT_TRIGGER 1 6066#define INTERRUPT_STATUS__HPD_HIGH 2 6067 6068typedef struct _INDIRECT_IO_ACCESS 6069{ 6070 ATOM_COMMON_TABLE_HEADER sHeader; 6071 UCHAR IOAccessSequence[256]; 6072} INDIRECT_IO_ACCESS; 6073 6074#define INDIRECT_READ 0x00 6075#define INDIRECT_WRITE 0x80 6076 6077#define INDIRECT_IO_MM 0 6078#define INDIRECT_IO_PLL 1 6079#define INDIRECT_IO_MC 2 6080#define INDIRECT_IO_PCIE 3 6081#define INDIRECT_IO_PCIEP 4 6082#define INDIRECT_IO_NBMISC 5 6083#define INDIRECT_IO_SMU 5 6084 6085#define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL | INDIRECT_READ 6086#define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL | INDIRECT_WRITE 6087#define INDIRECT_IO_MC_READ INDIRECT_IO_MC | INDIRECT_READ 6088#define INDIRECT_IO_MC_WRITE INDIRECT_IO_MC | INDIRECT_WRITE 6089#define INDIRECT_IO_PCIE_READ INDIRECT_IO_PCIE | INDIRECT_READ 6090#define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE | INDIRECT_WRITE 6091#define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP | INDIRECT_READ 6092#define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP | INDIRECT_WRITE 6093#define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC | INDIRECT_READ 6094#define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC | INDIRECT_WRITE 6095#define INDIRECT_IO_SMU_READ INDIRECT_IO_SMU | INDIRECT_READ 6096#define INDIRECT_IO_SMU_WRITE INDIRECT_IO_SMU | INDIRECT_WRITE 6097 6098typedef struct _ATOM_OEM_INFO 6099{ 6100 ATOM_COMMON_TABLE_HEADER sHeader; 6101 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 6102}ATOM_OEM_INFO; 6103 6104typedef struct _ATOM_TV_MODE 6105{ 6106 UCHAR ucVMode_Num; //Video mode number 6107 UCHAR ucTV_Mode_Num; //Internal TV mode number 6108}ATOM_TV_MODE; 6109 6110typedef struct _ATOM_BIOS_INT_TVSTD_MODE 6111{ 6112 ATOM_COMMON_TABLE_HEADER sHeader; 6113 USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table 6114 USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table 6115 USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table 6116 USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table 6117 USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table 6118}ATOM_BIOS_INT_TVSTD_MODE; 6119 6120 6121typedef struct _ATOM_TV_MODE_SCALER_PTR 6122{ 6123 USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients 6124 USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients 6125 UCHAR ucTV_Mode_Num; 6126}ATOM_TV_MODE_SCALER_PTR; 6127 6128typedef struct _ATOM_STANDARD_VESA_TIMING 6129{ 6130 ATOM_COMMON_TABLE_HEADER sHeader; 6131 ATOM_DTD_FORMAT aModeTimings[16]; // 16 is not the real array number, just for initial allocation 6132}ATOM_STANDARD_VESA_TIMING; 6133 6134 6135typedef struct _ATOM_STD_FORMAT 6136{ 6137 USHORT usSTD_HDisp; 6138 USHORT usSTD_VDisp; 6139 USHORT usSTD_RefreshRate; 6140 USHORT usReserved; 6141}ATOM_STD_FORMAT; 6142 6143typedef struct _ATOM_VESA_TO_EXTENDED_MODE 6144{ 6145 USHORT usVESA_ModeNumber; 6146 USHORT usExtendedModeNumber; 6147}ATOM_VESA_TO_EXTENDED_MODE; 6148 6149typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT 6150{ 6151 ATOM_COMMON_TABLE_HEADER sHeader; 6152 ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76]; 6153}ATOM_VESA_TO_INTENAL_MODE_LUT; 6154 6155/*************** ATOM Memory Related Data Structure ***********************/ 6156typedef struct _ATOM_MEMORY_VENDOR_BLOCK{ 6157 UCHAR ucMemoryType; 6158 UCHAR ucMemoryVendor; 6159 UCHAR ucAdjMCId; 6160 UCHAR ucDynClkId; 6161 ULONG ulDllResetClkRange; 6162}ATOM_MEMORY_VENDOR_BLOCK; 6163 6164 6165typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{ 6166#if ATOM_BIG_ENDIAN 6167 ULONG ucMemBlkId:8; 6168 ULONG ulMemClockRange:24; 6169#else 6170 ULONG ulMemClockRange:24; 6171 ULONG ucMemBlkId:8; 6172#endif 6173}ATOM_MEMORY_SETTING_ID_CONFIG; 6174 6175typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS 6176{ 6177 ATOM_MEMORY_SETTING_ID_CONFIG slAccess; 6178 ULONG ulAccess; 6179}ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS; 6180 6181 6182typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{ 6183 ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID; 6184 ULONG aulMemData[1]; 6185}ATOM_MEMORY_SETTING_DATA_BLOCK; 6186 6187 6188typedef struct _ATOM_INIT_REG_INDEX_FORMAT{ 6189 USHORT usRegIndex; // MC register index 6190 UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf 6191}ATOM_INIT_REG_INDEX_FORMAT; 6192 6193 6194typedef struct _ATOM_INIT_REG_BLOCK{ 6195 USHORT usRegIndexTblSize; //size of asRegIndexBuf 6196 USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK 6197 ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1]; 6198 ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1]; 6199}ATOM_INIT_REG_BLOCK; 6200 6201#define END_OF_REG_INDEX_BLOCK 0x0ffff 6202#define END_OF_REG_DATA_BLOCK 0x00000000 6203#define ATOM_INIT_REG_MASK_FLAG 0x80 //Not used in BIOS 6204#define CLOCK_RANGE_HIGHEST 0x00ffffff 6205 6206#define VALUE_DWORD SIZEOF ULONG 6207#define VALUE_SAME_AS_ABOVE 0 6208#define VALUE_MASK_DWORD 0x84 6209 6210#define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1) 6211#define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1) 6212#define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1) 6213//#define ACCESS_MCIODEBUGIND 0x40 //defined in BIOS code 6214#define ACCESS_PLACEHOLDER 0x80 6215 6216typedef struct _ATOM_MC_INIT_PARAM_TABLE 6217{ 6218 ATOM_COMMON_TABLE_HEADER sHeader; 6219 USHORT usAdjustARB_SEQDataOffset; 6220 USHORT usMCInitMemTypeTblOffset; 6221 USHORT usMCInitCommonTblOffset; 6222 USHORT usMCInitPowerDownTblOffset; 6223 ULONG ulARB_SEQDataBuf[32]; 6224 ATOM_INIT_REG_BLOCK asMCInitMemType; 6225 ATOM_INIT_REG_BLOCK asMCInitCommon; 6226}ATOM_MC_INIT_PARAM_TABLE; 6227 6228 6229#define _4Mx16 0x2 6230#define _4Mx32 0x3 6231#define _8Mx16 0x12 6232#define _8Mx32 0x13 6233#define _16Mx16 0x22 6234#define _16Mx32 0x23 6235#define _32Mx16 0x32 6236#define _32Mx32 0x33 6237#define _64Mx8 0x41 6238#define _64Mx16 0x42 6239#define _64Mx32 0x43 6240#define _128Mx8 0x51 6241#define _128Mx16 0x52 6242#define _128Mx32 0x53 6243#define _256Mx8 0x61 6244#define _256Mx16 0x62 6245 6246#define SAMSUNG 0x1 6247#define INFINEON 0x2 6248#define ELPIDA 0x3 6249#define ETRON 0x4 6250#define NANYA 0x5 6251#define HYNIX 0x6 6252#define MOSEL 0x7 6253#define WINBOND 0x8 6254#define ESMT 0x9 6255#define MICRON 0xF 6256 6257#define QIMONDA INFINEON 6258#define PROMOS MOSEL 6259#define KRETON INFINEON 6260#define ELIXIR NANYA 6261#define MEZZA ELPIDA 6262 6263 6264/////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM///////////// 6265 6266#define UCODE_ROM_START_ADDRESS 0x1b800 6267#define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode 6268 6269//uCode block header for reference 6270 6271typedef struct _MCuCodeHeader 6272{ 6273 ULONG ulSignature; 6274 UCHAR ucRevision; 6275 UCHAR ucChecksum; 6276 UCHAR ucReserved1; 6277 UCHAR ucReserved2; 6278 USHORT usParametersLength; 6279 USHORT usUCodeLength; 6280 USHORT usReserved1; 6281 USHORT usReserved2; 6282} MCuCodeHeader; 6283 6284////////////////////////////////////////////////////////////////////////////////// 6285 6286#define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16 6287 6288#define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF 6289typedef struct _ATOM_VRAM_MODULE_V1 6290{ 6291 ULONG ulReserved; 6292 USHORT usEMRSValue; 6293 USHORT usMRSValue; 6294 USHORT usReserved; 6295 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6296 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved; 6297 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender 6298 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... 6299 UCHAR ucRow; // Number of Row,in power of 2; 6300 UCHAR ucColumn; // Number of Column,in power of 2; 6301 UCHAR ucBank; // Nunber of Bank; 6302 UCHAR ucRank; // Number of Rank, in power of 2 6303 UCHAR ucChannelNum; // Number of channel; 6304 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 6305 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; 6306 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; 6307 UCHAR ucReserved[2]; 6308}ATOM_VRAM_MODULE_V1; 6309 6310 6311typedef struct _ATOM_VRAM_MODULE_V2 6312{ 6313 ULONG ulReserved; 6314 ULONG ulFlags; // To enable/disable functionalities based on memory type 6315 ULONG ulEngineClock; // Override of default engine clock for particular memory type 6316 ULONG ulMemoryClock; // Override of default memory clock for particular memory type 6317 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 6318 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 6319 USHORT usEMRSValue; 6320 USHORT usMRSValue; 6321 USHORT usReserved; 6322 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6323 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; 6324 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed 6325 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... 6326 UCHAR ucRow; // Number of Row,in power of 2; 6327 UCHAR ucColumn; // Number of Column,in power of 2; 6328 UCHAR ucBank; // Nunber of Bank; 6329 UCHAR ucRank; // Number of Rank, in power of 2 6330 UCHAR ucChannelNum; // Number of channel; 6331 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 6332 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; 6333 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; 6334 UCHAR ucRefreshRateFactor; 6335 UCHAR ucReserved[3]; 6336}ATOM_VRAM_MODULE_V2; 6337 6338 6339typedef struct _ATOM_MEMORY_TIMING_FORMAT 6340{ 6341 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 6342 union{ 6343 USHORT usMRS; // mode register 6344 USHORT usDDR3_MR0; 6345 }; 6346 union{ 6347 USHORT usEMRS; // extended mode register 6348 USHORT usDDR3_MR1; 6349 }; 6350 UCHAR ucCL; // CAS latency 6351 UCHAR ucWL; // WRITE Latency 6352 UCHAR uctRAS; // tRAS 6353 UCHAR uctRC; // tRC 6354 UCHAR uctRFC; // tRFC 6355 UCHAR uctRCDR; // tRCDR 6356 UCHAR uctRCDW; // tRCDW 6357 UCHAR uctRP; // tRP 6358 UCHAR uctRRD; // tRRD 6359 UCHAR uctWR; // tWR 6360 UCHAR uctWTR; // tWTR 6361 UCHAR uctPDIX; // tPDIX 6362 UCHAR uctFAW; // tFAW 6363 UCHAR uctAOND; // tAOND 6364 union 6365 { 6366 struct { 6367 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 6368 UCHAR ucReserved; 6369 }; 6370 USHORT usDDR3_MR2; 6371 }; 6372}ATOM_MEMORY_TIMING_FORMAT; 6373 6374 6375typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1 6376{ 6377 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 6378 USHORT usMRS; // mode register 6379 USHORT usEMRS; // extended mode register 6380 UCHAR ucCL; // CAS latency 6381 UCHAR ucWL; // WRITE Latency 6382 UCHAR uctRAS; // tRAS 6383 UCHAR uctRC; // tRC 6384 UCHAR uctRFC; // tRFC 6385 UCHAR uctRCDR; // tRCDR 6386 UCHAR uctRCDW; // tRCDW 6387 UCHAR uctRP; // tRP 6388 UCHAR uctRRD; // tRRD 6389 UCHAR uctWR; // tWR 6390 UCHAR uctWTR; // tWTR 6391 UCHAR uctPDIX; // tPDIX 6392 UCHAR uctFAW; // tFAW 6393 UCHAR uctAOND; // tAOND 6394 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 6395////////////////////////////////////GDDR parameters/////////////////////////////////// 6396 UCHAR uctCCDL; // 6397 UCHAR uctCRCRL; // 6398 UCHAR uctCRCWL; // 6399 UCHAR uctCKE; // 6400 UCHAR uctCKRSE; // 6401 UCHAR uctCKRSX; // 6402 UCHAR uctFAW32; // 6403 UCHAR ucMR5lo; // 6404 UCHAR ucMR5hi; // 6405 UCHAR ucTerminator; 6406}ATOM_MEMORY_TIMING_FORMAT_V1; 6407 6408typedef struct _ATOM_MEMORY_TIMING_FORMAT_V2 6409{ 6410 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 6411 USHORT usMRS; // mode register 6412 USHORT usEMRS; // extended mode register 6413 UCHAR ucCL; // CAS latency 6414 UCHAR ucWL; // WRITE Latency 6415 UCHAR uctRAS; // tRAS 6416 UCHAR uctRC; // tRC 6417 UCHAR uctRFC; // tRFC 6418 UCHAR uctRCDR; // tRCDR 6419 UCHAR uctRCDW; // tRCDW 6420 UCHAR uctRP; // tRP 6421 UCHAR uctRRD; // tRRD 6422 UCHAR uctWR; // tWR 6423 UCHAR uctWTR; // tWTR 6424 UCHAR uctPDIX; // tPDIX 6425 UCHAR uctFAW; // tFAW 6426 UCHAR uctAOND; // tAOND 6427 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 6428////////////////////////////////////GDDR parameters/////////////////////////////////// 6429 UCHAR uctCCDL; // 6430 UCHAR uctCRCRL; // 6431 UCHAR uctCRCWL; // 6432 UCHAR uctCKE; // 6433 UCHAR uctCKRSE; // 6434 UCHAR uctCKRSX; // 6435 UCHAR uctFAW32; // 6436 UCHAR ucMR4lo; // 6437 UCHAR ucMR4hi; // 6438 UCHAR ucMR5lo; // 6439 UCHAR ucMR5hi; // 6440 UCHAR ucTerminator; 6441 UCHAR ucReserved; 6442}ATOM_MEMORY_TIMING_FORMAT_V2; 6443 6444typedef struct _ATOM_MEMORY_FORMAT 6445{ 6446 ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock 6447 union{ 6448 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 6449 USHORT usDDR3_Reserved; // Not used for DDR3 memory 6450 }; 6451 union{ 6452 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 6453 USHORT usDDR3_MR3; // Used for DDR3 memory 6454 }; 6455 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; 6456 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed 6457 UCHAR ucRow; // Number of Row,in power of 2; 6458 UCHAR ucColumn; // Number of Column,in power of 2; 6459 UCHAR ucBank; // Nunber of Bank; 6460 UCHAR ucRank; // Number of Rank, in power of 2 6461 UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8 6462 UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register ) 6463 UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms 6464 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 6465 UCHAR ucPreamble; //[7:4] Write Preamble, [3:0] Read Preamble 6466 UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc 6467 ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; //Memory Timing block sort from lower clock to higher clock 6468}ATOM_MEMORY_FORMAT; 6469 6470 6471typedef struct _ATOM_VRAM_MODULE_V3 6472{ 6473 ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination 6474 USHORT usSize; // size of ATOM_VRAM_MODULE_V3 6475 USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage 6476 USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage 6477 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6478 UCHAR ucChannelNum; // board dependent parameter:Number of channel; 6479 UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit 6480 UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv 6481 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 6482 UCHAR ucFlag; // To enable/disable functionalities based on memory type 6483 ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec 6484}ATOM_VRAM_MODULE_V3; 6485 6486 6487//ATOM_VRAM_MODULE_V3.ucNPL_RT 6488#define NPL_RT_MASK 0x0f 6489#define BATTERY_ODT_MASK 0xc0 6490 6491#define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3 6492 6493typedef struct _ATOM_VRAM_MODULE_V4 6494{ 6495 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 6496 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 6497 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6498 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 6499 USHORT usReserved; 6500 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6501 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 6502 UCHAR ucChannelNum; // Number of channels present in this module config 6503 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 6504 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 6505 UCHAR ucFlag; // To enable/disable functionalities based on memory type 6506 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 6507 UCHAR ucVREFI; // board dependent parameter 6508 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 6509 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 6510 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6511 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 6512 UCHAR ucReserved[3]; 6513 6514//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 6515 union{ 6516 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 6517 USHORT usDDR3_Reserved; 6518 }; 6519 union{ 6520 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 6521 USHORT usDDR3_MR3; // Used for DDR3 memory 6522 }; 6523 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 6524 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 6525 UCHAR ucReserved2[2]; 6526 ATOM_MEMORY_TIMING_FORMAT asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 6527}ATOM_VRAM_MODULE_V4; 6528 6529#define VRAM_MODULE_V4_MISC_RANK_MASK 0x3 6530#define VRAM_MODULE_V4_MISC_DUAL_RANK 0x1 6531#define VRAM_MODULE_V4_MISC_BL_MASK 0x4 6532#define VRAM_MODULE_V4_MISC_BL8 0x4 6533#define VRAM_MODULE_V4_MISC_DUAL_CS 0x10 6534 6535typedef struct _ATOM_VRAM_MODULE_V5 6536{ 6537 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 6538 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 6539 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6540 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 6541 USHORT usReserved; 6542 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6543 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 6544 UCHAR ucChannelNum; // Number of channels present in this module config 6545 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 6546 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 6547 UCHAR ucFlag; // To enable/disable functionalities based on memory type 6548 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 6549 UCHAR ucVREFI; // board dependent parameter 6550 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 6551 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 6552 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6553 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 6554 UCHAR ucReserved[3]; 6555 6556//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 6557 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 6558 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 6559 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 6560 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 6561 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth 6562 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 6563 ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 6564}ATOM_VRAM_MODULE_V5; 6565 6566typedef struct _ATOM_VRAM_MODULE_V6 6567{ 6568 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 6569 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 6570 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6571 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 6572 USHORT usReserved; 6573 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6574 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 6575 UCHAR ucChannelNum; // Number of channels present in this module config 6576 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 6577 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 6578 UCHAR ucFlag; // To enable/disable functionalities based on memory type 6579 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 6580 UCHAR ucVREFI; // board dependent parameter 6581 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 6582 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 6583 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6584 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 6585 UCHAR ucReserved[3]; 6586 6587//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 6588 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 6589 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 6590 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 6591 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 6592 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth 6593 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 6594 ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 6595}ATOM_VRAM_MODULE_V6; 6596 6597typedef struct _ATOM_VRAM_MODULE_V7 6598{ 6599// Design Specific Values 6600 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP 6601 USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7 6602 USHORT usPrivateReserved; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 6603 USHORT usEnableChannels; // bit vector which indicate which channels are enabled 6604 UCHAR ucExtMemoryID; // Current memory module ID 6605 UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5 6606 UCHAR ucChannelNum; // Number of mem. channels supported in this module 6607 UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 6608 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 6609 UCHAR ucReserve; // Former container for Mx_FLAGS like DBI_AC_MODE_ENABLE_ASIC for GDDR4. Not used now. 6610 UCHAR ucMisc; // RANK_OF_THISMEMORY etc. 6611 UCHAR ucVREFI; // Not used. 6612 UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2. 6613 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 6614 UCHAR ucMemorySize; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 6615 USHORT usSEQSettingOffset; 6616 UCHAR ucReserved; 6617// Memory Module specific values 6618 USHORT usEMRS2Value; // EMRS2/MR2 Value. 6619 USHORT usEMRS3Value; // EMRS3/MR3 Value. 6620 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code 6621 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 6622 UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory 6623 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 6624 char strMemPNString[20]; // part number end with '0'. 6625}ATOM_VRAM_MODULE_V7; 6626 6627typedef struct _ATOM_VRAM_INFO_V2 6628{ 6629 ATOM_COMMON_TABLE_HEADER sHeader; 6630 UCHAR ucNumOfVRAMModule; 6631 ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 6632}ATOM_VRAM_INFO_V2; 6633 6634typedef struct _ATOM_VRAM_INFO_V3 6635{ 6636 ATOM_COMMON_TABLE_HEADER sHeader; 6637 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 6638 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 6639 USHORT usRerseved; 6640 UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator 6641 UCHAR ucNumOfVRAMModule; 6642 ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 6643 ATOM_INIT_REG_BLOCK asMemPatch; // for allocation 6644 // ATOM_INIT_REG_BLOCK aMemAdjust; 6645}ATOM_VRAM_INFO_V3; 6646 6647#define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3 6648 6649typedef struct _ATOM_VRAM_INFO_V4 6650{ 6651 ATOM_COMMON_TABLE_HEADER sHeader; 6652 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 6653 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 6654 USHORT usRerseved; 6655 UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3 6656 ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21] 6657 UCHAR ucReservde[4]; 6658 UCHAR ucNumOfVRAMModule; 6659 ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 6660 ATOM_INIT_REG_BLOCK asMemPatch; // for allocation 6661 // ATOM_INIT_REG_BLOCK aMemAdjust; 6662}ATOM_VRAM_INFO_V4; 6663 6664typedef struct _ATOM_VRAM_INFO_HEADER_V2_1 6665{ 6666 ATOM_COMMON_TABLE_HEADER sHeader; 6667 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 6668 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 6669 USHORT usPerBytePresetOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings 6670 USHORT usReserved[3]; 6671 UCHAR ucNumOfVRAMModule; // indicate number of VRAM module 6672 UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list 6673 UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version 6674 UCHAR ucReserved; 6675 ATOM_VRAM_MODULE_V7 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 6676}ATOM_VRAM_INFO_HEADER_V2_1; 6677 6678 6679typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO 6680{ 6681 ATOM_COMMON_TABLE_HEADER sHeader; 6682 UCHAR aVID_PinsShift[9]; //8 bit strap maximum+terminator 6683}ATOM_VRAM_GPIO_DETECTION_INFO; 6684 6685 6686typedef struct _ATOM_MEMORY_TRAINING_INFO 6687{ 6688 ATOM_COMMON_TABLE_HEADER sHeader; 6689 UCHAR ucTrainingLoop; 6690 UCHAR ucReserved[3]; 6691 ATOM_INIT_REG_BLOCK asMemTrainingSetting; 6692}ATOM_MEMORY_TRAINING_INFO; 6693 6694 6695typedef struct SW_I2C_CNTL_DATA_PARAMETERS 6696{ 6697 UCHAR ucControl; 6698 UCHAR ucData; 6699 UCHAR ucSatus; 6700 UCHAR ucTemp; 6701} SW_I2C_CNTL_DATA_PARAMETERS; 6702 6703#define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS 6704 6705typedef struct _SW_I2C_IO_DATA_PARAMETERS 6706{ 6707 USHORT GPIO_Info; 6708 UCHAR ucAct; 6709 UCHAR ucData; 6710 } SW_I2C_IO_DATA_PARAMETERS; 6711 6712#define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS 6713 6714/****************************SW I2C CNTL DEFINITIONS**********************/ 6715#define SW_I2C_IO_RESET 0 6716#define SW_I2C_IO_GET 1 6717#define SW_I2C_IO_DRIVE 2 6718#define SW_I2C_IO_SET 3 6719#define SW_I2C_IO_START 4 6720 6721#define SW_I2C_IO_CLOCK 0 6722#define SW_I2C_IO_DATA 0x80 6723 6724#define SW_I2C_IO_ZERO 0 6725#define SW_I2C_IO_ONE 0x100 6726 6727#define SW_I2C_CNTL_READ 0 6728#define SW_I2C_CNTL_WRITE 1 6729#define SW_I2C_CNTL_START 2 6730#define SW_I2C_CNTL_STOP 3 6731#define SW_I2C_CNTL_OPEN 4 6732#define SW_I2C_CNTL_CLOSE 5 6733#define SW_I2C_CNTL_WRITE1BIT 6 6734 6735//==============================VESA definition Portion=============================== 6736#define VESA_OEM_PRODUCT_REV "01.00" 6737#define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support 6738#define VESA_MODE_WIN_ATTRIBUTE 7 6739#define VESA_WIN_SIZE 64 6740 6741typedef struct _PTR_32_BIT_STRUCTURE 6742{ 6743 USHORT Offset16; 6744 USHORT Segment16; 6745} PTR_32_BIT_STRUCTURE; 6746 6747typedef union _PTR_32_BIT_UNION 6748{ 6749 PTR_32_BIT_STRUCTURE SegmentOffset; 6750 ULONG Ptr32_Bit; 6751} PTR_32_BIT_UNION; 6752 6753typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE 6754{ 6755 UCHAR VbeSignature[4]; 6756 USHORT VbeVersion; 6757 PTR_32_BIT_UNION OemStringPtr; 6758 UCHAR Capabilities[4]; 6759 PTR_32_BIT_UNION VideoModePtr; 6760 USHORT TotalMemory; 6761} VBE_1_2_INFO_BLOCK_UPDATABLE; 6762 6763 6764typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE 6765{ 6766 VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock; 6767 USHORT OemSoftRev; 6768 PTR_32_BIT_UNION OemVendorNamePtr; 6769 PTR_32_BIT_UNION OemProductNamePtr; 6770 PTR_32_BIT_UNION OemProductRevPtr; 6771} VBE_2_0_INFO_BLOCK_UPDATABLE; 6772 6773typedef union _VBE_VERSION_UNION 6774{ 6775 VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock; 6776 VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock; 6777} VBE_VERSION_UNION; 6778 6779typedef struct _VBE_INFO_BLOCK 6780{ 6781 VBE_VERSION_UNION UpdatableVBE_Info; 6782 UCHAR Reserved[222]; 6783 UCHAR OemData[256]; 6784} VBE_INFO_BLOCK; 6785 6786typedef struct _VBE_FP_INFO 6787{ 6788 USHORT HSize; 6789 USHORT VSize; 6790 USHORT FPType; 6791 UCHAR RedBPP; 6792 UCHAR GreenBPP; 6793 UCHAR BlueBPP; 6794 UCHAR ReservedBPP; 6795 ULONG RsvdOffScrnMemSize; 6796 ULONG RsvdOffScrnMEmPtr; 6797 UCHAR Reserved[14]; 6798} VBE_FP_INFO; 6799 6800typedef struct _VESA_MODE_INFO_BLOCK 6801{ 6802// Mandatory information for all VBE revisions 6803 USHORT ModeAttributes; // dw ? ; mode attributes 6804 UCHAR WinAAttributes; // db ? ; window A attributes 6805 UCHAR WinBAttributes; // db ? ; window B attributes 6806 USHORT WinGranularity; // dw ? ; window granularity 6807 USHORT WinSize; // dw ? ; window size 6808 USHORT WinASegment; // dw ? ; window A start segment 6809 USHORT WinBSegment; // dw ? ; window B start segment 6810 ULONG WinFuncPtr; // dd ? ; real mode pointer to window function 6811 USHORT BytesPerScanLine;// dw ? ; bytes per scan line 6812 6813//; Mandatory information for VBE 1.2 and above 6814 USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters 6815 USHORT YResolution; // dw ? ; vertical resolution in pixels or characters 6816 UCHAR XCharSize; // db ? ; character cell width in pixels 6817 UCHAR YCharSize; // db ? ; character cell height in pixels 6818 UCHAR NumberOfPlanes; // db ? ; number of memory planes 6819 UCHAR BitsPerPixel; // db ? ; bits per pixel 6820 UCHAR NumberOfBanks; // db ? ; number of banks 6821 UCHAR MemoryModel; // db ? ; memory model type 6822 UCHAR BankSize; // db ? ; bank size in KB 6823 UCHAR NumberOfImagePages;// db ? ; number of images 6824 UCHAR ReservedForPageFunction;//db 1 ; reserved for page function 6825 6826//; Direct Color fields(required for direct/6 and YUV/7 memory models) 6827 UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits 6828 UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask 6829 UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits 6830 UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask 6831 UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits 6832 UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask 6833 UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits 6834 UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask 6835 UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes 6836 6837//; Mandatory information for VBE 2.0 and above 6838 ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer 6839 ULONG Reserved_1; // dd 0 ; reserved - always set to 0 6840 USHORT Reserved_2; // dw 0 ; reserved - always set to 0 6841 6842//; Mandatory information for VBE 3.0 and above 6843 USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes 6844 UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes 6845 UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes 6846 UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes) 6847 UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes) 6848 UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes) 6849 UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes) 6850 UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes) 6851 UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes) 6852 UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes) 6853 UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes) 6854 ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode 6855 UCHAR Reserved; // db 190 dup (0) 6856} VESA_MODE_INFO_BLOCK; 6857 6858// BIOS function CALLS 6859#define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code 6860#define ATOM_BIOS_FUNCTION_COP_MODE 0x00 6861#define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04 6862#define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05 6863#define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06 6864#define ATOM_BIOS_FUNCTION_GET_DDC 0x0B 6865#define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E 6866#define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F 6867#define ATOM_BIOS_FUNCTION_STV_STD 0x16 6868#define ATOM_BIOS_FUNCTION_DEVICE_DET 0x17 6869#define ATOM_BIOS_FUNCTION_DEVICE_SWITCH 0x18 6870 6871#define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82 6872#define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83 6873#define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84 6874#define ATOM_BIOS_FUNCTION_HW_ICON 0x8A 6875#define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B 6876#define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80 6877#define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80 6878 6879#define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D 6880#define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E 6881#define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F 6882#define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03 6883#define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7 6884#define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state 6885#define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state 6886#define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85 6887#define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89 6888#define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported 6889 6890 6891#define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS 6892#define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01 6893#define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02 6894#define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON. 6895#define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY 6896#define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND 6897#define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF 6898#define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED) 6899 6900#define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L 6901#define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L 6902#define ATOM_BIOS_REG_LOW_MASK 0x000000FFL 6903 6904// structure used for VBIOS only 6905 6906//DispOutInfoTable 6907typedef struct _ASIC_TRANSMITTER_INFO 6908{ 6909 USHORT usTransmitterObjId; 6910 USHORT usSupportDevice; 6911 UCHAR ucTransmitterCmdTblId; 6912 UCHAR ucConfig; 6913 UCHAR ucEncoderID; //available 1st encoder ( default ) 6914 UCHAR ucOptionEncoderID; //available 2nd encoder ( optional ) 6915 UCHAR uc2ndEncoderID; 6916 UCHAR ucReserved; 6917}ASIC_TRANSMITTER_INFO; 6918 6919#define ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE 0x01 6920#define ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE 0x02 6921#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK 0xc4 6922#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A 0x00 6923#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B 0x04 6924#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C 0x40 6925#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D 0x44 6926#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E 0x80 6927#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F 0x84 6928 6929typedef struct _ASIC_ENCODER_INFO 6930{ 6931 UCHAR ucEncoderID; 6932 UCHAR ucEncoderConfig; 6933 USHORT usEncoderCmdTblId; 6934}ASIC_ENCODER_INFO; 6935 6936typedef struct _ATOM_DISP_OUT_INFO 6937{ 6938 ATOM_COMMON_TABLE_HEADER sHeader; 6939 USHORT ptrTransmitterInfo; 6940 USHORT ptrEncoderInfo; 6941 ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; 6942 ASIC_ENCODER_INFO asEncoderInfo[1]; 6943}ATOM_DISP_OUT_INFO; 6944 6945typedef struct _ATOM_DISP_OUT_INFO_V2 6946{ 6947 ATOM_COMMON_TABLE_HEADER sHeader; 6948 USHORT ptrTransmitterInfo; 6949 USHORT ptrEncoderInfo; 6950 USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. 6951 ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; 6952 ASIC_ENCODER_INFO asEncoderInfo[1]; 6953}ATOM_DISP_OUT_INFO_V2; 6954 6955 6956typedef struct _ATOM_DISP_CLOCK_ID { 6957 UCHAR ucPpllId; 6958 UCHAR ucPpllAttribute; 6959}ATOM_DISP_CLOCK_ID; 6960 6961// ucPpllAttribute 6962#define CLOCK_SOURCE_SHAREABLE 0x01 6963#define CLOCK_SOURCE_DP_MODE 0x02 6964#define CLOCK_SOURCE_NONE_DP_MODE 0x04 6965 6966//DispOutInfoTable 6967typedef struct _ASIC_TRANSMITTER_INFO_V2 6968{ 6969 USHORT usTransmitterObjId; 6970 USHORT usDispClkIdOffset; // point to clock source id list supported by Encoder Object 6971 UCHAR ucTransmitterCmdTblId; 6972 UCHAR ucConfig; 6973 UCHAR ucEncoderID; // available 1st encoder ( default ) 6974 UCHAR ucOptionEncoderID; // available 2nd encoder ( optional ) 6975 UCHAR uc2ndEncoderID; 6976 UCHAR ucReserved; 6977}ASIC_TRANSMITTER_INFO_V2; 6978 6979typedef struct _ATOM_DISP_OUT_INFO_V3 6980{ 6981 ATOM_COMMON_TABLE_HEADER sHeader; 6982 USHORT ptrTransmitterInfo; 6983 USHORT ptrEncoderInfo; 6984 USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. 6985 USHORT usReserved; 6986 UCHAR ucDCERevision; 6987 UCHAR ucMaxDispEngineNum; 6988 UCHAR ucMaxActiveDispEngineNum; 6989 UCHAR ucMaxPPLLNum; 6990 UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE 6991 UCHAR ucReserved[3]; 6992 ASIC_TRANSMITTER_INFO_V2 asTransmitterInfo[1]; // for alligment only 6993}ATOM_DISP_OUT_INFO_V3; 6994 6995//ucDispCaps 6996#define DISPLAY_CAPS__DP_PCLK_FROM_PPLL 0x01 6997#define DISPLAY_CAPS__FORCE_DISPDEV_CONNECTED 0x02 6998 6999typedef enum CORE_REF_CLK_SOURCE{ 7000 CLOCK_SRC_XTALIN=0,
7001 CLOCK_SRC_XO_IN=1, 7002 CLOCK_SRC_XO_IN2=2, 7003}CORE_REF_CLK_SOURCE; 7004 7005// DispDevicePriorityInfo 7006typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO 7007{ 7008 ATOM_COMMON_TABLE_HEADER sHeader; 7009 USHORT asDevicePriority[16]; 7010}ATOM_DISPLAY_DEVICE_PRIORITY_INFO; 7011 7012//ProcessAuxChannelTransactionTable 7013typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS 7014{ 7015 USHORT lpAuxRequest; 7016 USHORT lpDataOut; 7017 UCHAR ucChannelID; 7018 union 7019 { 7020 UCHAR ucReplyStatus; 7021 UCHAR ucDelay; 7022 }; 7023 UCHAR ucDataOutLen; 7024 UCHAR ucReserved; 7025}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS; 7026 7027//ProcessAuxChannelTransactionTable 7028typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 7029{ 7030 USHORT lpAuxRequest; 7031 USHORT lpDataOut; 7032 UCHAR ucChannelID; 7033 union 7034 { 7035 UCHAR ucReplyStatus; 7036 UCHAR ucDelay; 7037 }; 7038 UCHAR ucDataOutLen; 7039 UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 7040}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2; 7041 7042#define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS 7043 7044//GetSinkType 7045 7046typedef struct _DP_ENCODER_SERVICE_PARAMETERS 7047{ 7048 USHORT ucLinkClock; 7049 union 7050 { 7051 UCHAR ucConfig; // for DP training command 7052 UCHAR ucI2cId; // use for GET_SINK_TYPE command 7053 }; 7054 UCHAR ucAction; 7055 UCHAR ucStatus; 7056 UCHAR ucLaneNum; 7057 UCHAR ucReserved[2]; 7058}DP_ENCODER_SERVICE_PARAMETERS; 7059 7060// ucAction 7061#define ATOM_DP_ACTION_GET_SINK_TYPE 0x01 7062/* obselete */ 7063#define ATOM_DP_ACTION_TRAINING_START 0x02 7064#define ATOM_DP_ACTION_TRAINING_COMPLETE 0x03 7065#define ATOM_DP_ACTION_TRAINING_PATTERN_SEL 0x04 7066#define ATOM_DP_ACTION_SET_VSWING_PREEMP 0x05 7067#define ATOM_DP_ACTION_GET_VSWING_PREEMP 0x06 7068#define ATOM_DP_ACTION_BLANKING 0x07 7069 7070// ucConfig 7071#define ATOM_DP_CONFIG_ENCODER_SEL_MASK 0x03 7072#define ATOM_DP_CONFIG_DIG1_ENCODER 0x00 7073#define ATOM_DP_CONFIG_DIG2_ENCODER 0x01 7074#define ATOM_DP_CONFIG_EXTERNAL_ENCODER 0x02 7075#define ATOM_DP_CONFIG_LINK_SEL_MASK 0x04 7076#define ATOM_DP_CONFIG_LINK_A 0x00 7077#define ATOM_DP_CONFIG_LINK_B 0x04 7078/* /obselete */ 7079#define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 7080 7081 7082typedef struct _DP_ENCODER_SERVICE_PARAMETERS_V2 7083{ 7084 USHORT usExtEncoderObjId; // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION 7085 UCHAR ucAuxId; 7086 UCHAR ucAction; 7087 UCHAR ucSinkType; // Iput and Output parameters. 7088 UCHAR ucHPDId; // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION 7089 UCHAR ucReserved[2]; 7090}DP_ENCODER_SERVICE_PARAMETERS_V2; 7091 7092typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2 7093{ 7094 DP_ENCODER_SERVICE_PARAMETERS_V2 asDPServiceParam; 7095 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 asAuxParam; 7096}DP_ENCODER_SERVICE_PS_ALLOCATION_V2; 7097 7098// ucAction 7099#define DP_SERVICE_V2_ACTION_GET_SINK_TYPE 0x01 7100#define DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION 0x02 7101 7102 7103// DP_TRAINING_TABLE 7104#define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR 7105#define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 ) 7106#define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 ) 7107#define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 ) 7108#define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32) 7109#define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40) 7110#define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48) 7111#define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 60) 7112#define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64) 7113#define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72) 7114#define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76) 7115#define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80) 7116#define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 84) 7117 7118typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS 7119{ 7120 UCHAR ucI2CSpeed; 7121 union 7122 { 7123 UCHAR ucRegIndex; 7124 UCHAR ucStatus; 7125 }; 7126 USHORT lpI2CDataOut; 7127 UCHAR ucFlag; 7128 UCHAR ucTransBytes; 7129 UCHAR ucSlaveAddr; 7130 UCHAR ucLineNumber; 7131}PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS; 7132 7133#define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS 7134 7135//ucFlag 7136#define HW_I2C_WRITE 1 7137#define HW_I2C_READ 0 7138#define I2C_2BYTE_ADDR 0x02 7139 7140/****************************************************************************/ 7141// Structures used by HW_Misc_OperationTable 7142/****************************************************************************/ 7143typedef struct _ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 7144{ 7145 UCHAR ucCmd; // Input: To tell which action to take 7146 UCHAR ucReserved[3]; 7147 ULONG ulReserved; 7148}ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1; 7149 7150typedef struct _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1 7151{ 7152 UCHAR ucReturnCode; // Output: Return value base on action was taken 7153 UCHAR ucReserved[3]; 7154 ULONG ulReserved; 7155}ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1; 7156 7157// Actions code 7158#define ATOM_GET_SDI_SUPPORT 0xF0 7159 7160// Return code 7161#define ATOM_UNKNOWN_CMD 0 7162#define ATOM_FEATURE_NOT_SUPPORTED 1 7163#define ATOM_FEATURE_SUPPORTED 2 7164 7165typedef struct _ATOM_HW_MISC_OPERATION_PS_ALLOCATION 7166{ 7167 ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 sInput_Output; 7168 PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS sReserved; 7169}ATOM_HW_MISC_OPERATION_PS_ALLOCATION; 7170 7171/****************************************************************************/ 7172 7173typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2 7174{ 7175 UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ... 7176 UCHAR ucReserved[3]; 7177}SET_HWBLOCK_INSTANCE_PARAMETER_V2; 7178 7179#define HWBLKINST_INSTANCE_MASK 0x07 7180#define HWBLKINST_HWBLK_MASK 0xF0 7181#define HWBLKINST_HWBLK_SHIFT 0x04 7182 7183//ucHWBlock 7184#define SELECT_DISP_ENGINE 0 7185#define SELECT_DISP_PLL 1 7186#define SELECT_DCIO_UNIPHY_LINK0 2 7187#define SELECT_DCIO_UNIPHY_LINK1 3 7188#define SELECT_DCIO_IMPCAL 4 7189#define SELECT_DCIO_DIG 6 7190#define SELECT_CRTC_PIXEL_RATE 7 7191#define SELECT_VGA_BLK 8 7192 7193// DIGTransmitterInfoTable structure used to program UNIPHY settings 7194typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_1{ 7195 ATOM_COMMON_TABLE_HEADER sHeader; 7196 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock 7197 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info 7198 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range 7199 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info 7200 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings 7201}DIG_TRANSMITTER_INFO_HEADER_V3_1; 7202 7203typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_2{ 7204 ATOM_COMMON_TABLE_HEADER sHeader; 7205 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock 7206 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info 7207 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range 7208 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info 7209 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings 7210 USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info 7211 USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings 7212}DIG_TRANSMITTER_INFO_HEADER_V3_2; 7213 7214typedef struct _CLOCK_CONDITION_REGESTER_INFO{ 7215 USHORT usRegisterIndex; 7216 UCHAR ucStartBit; 7217 UCHAR ucEndBit; 7218}CLOCK_CONDITION_REGESTER_INFO; 7219 7220typedef struct _CLOCK_CONDITION_SETTING_ENTRY{ 7221 USHORT usMaxClockFreq; 7222 UCHAR ucEncodeMode; 7223 UCHAR ucPhySel; 7224 ULONG ulAnalogSetting[1]; 7225}CLOCK_CONDITION_SETTING_ENTRY; 7226 7227typedef struct _CLOCK_CONDITION_SETTING_INFO{ 7228 USHORT usEntrySize; 7229 CLOCK_CONDITION_SETTING_ENTRY asClkCondSettingEntry[1]; 7230}CLOCK_CONDITION_SETTING_INFO; 7231 7232typedef struct _PHY_CONDITION_REG_VAL{ 7233 ULONG ulCondition; 7234 ULONG ulRegVal; 7235}PHY_CONDITION_REG_VAL; 7236 7237typedef struct _PHY_CONDITION_REG_VAL_V2{ 7238 ULONG ulCondition; 7239 UCHAR ucCondition2; 7240 ULONG ulRegVal; 7241}PHY_CONDITION_REG_VAL_V2; 7242 7243typedef struct _PHY_CONDITION_REG_INFO{ 7244 USHORT usRegIndex; 7245 USHORT usSize; 7246 PHY_CONDITION_REG_VAL asRegVal[1]; 7247}PHY_CONDITION_REG_INFO; 7248 7249typedef struct _PHY_CONDITION_REG_INFO_V2{ 7250 USHORT usRegIndex; 7251 USHORT usSize; 7252 PHY_CONDITION_REG_VAL_V2 asRegVal[1]; 7253}PHY_CONDITION_REG_INFO_V2; 7254 7255typedef struct _PHY_ANALOG_SETTING_INFO{ 7256 UCHAR ucEncodeMode; 7257 UCHAR ucPhySel; 7258 USHORT usSize; 7259 PHY_CONDITION_REG_INFO asAnalogSetting[1]; 7260}PHY_ANALOG_SETTING_INFO; 7261 7262typedef struct _PHY_ANALOG_SETTING_INFO_V2{ 7263 UCHAR ucEncodeMode; 7264 UCHAR ucPhySel; 7265 USHORT usSize; 7266 PHY_CONDITION_REG_INFO_V2 asAnalogSetting[1]; 7267}PHY_ANALOG_SETTING_INFO_V2; 7268 7269typedef struct _GFX_HAVESTING_PARAMETERS { 7270 UCHAR ucGfxBlkId; //GFX blk id to be harvested, like CU, RB or PRIM 7271 UCHAR ucReserved; //reserved 7272 UCHAR ucActiveUnitNumPerSH; //requested active CU/RB/PRIM number per shader array 7273 UCHAR ucMaxUnitNumPerSH; //max CU/RB/PRIM number per shader array 7274} GFX_HAVESTING_PARAMETERS; 7275 7276//ucGfxBlkId 7277#define GFX_HARVESTING_CU_ID 0 7278#define GFX_HARVESTING_RB_ID 1 7279#define GFX_HARVESTING_PRIM_ID 2 7280 7281/****************************************************************************/ 7282//Portion VI: Definitinos for vbios MC scratch registers that driver used 7283/****************************************************************************/ 7284 7285#define MC_MISC0__MEMORY_TYPE_MASK 0xF0000000 7286#define MC_MISC0__MEMORY_TYPE__GDDR1 0x10000000 7287#define MC_MISC0__MEMORY_TYPE__DDR2 0x20000000 7288#define MC_MISC0__MEMORY_TYPE__GDDR3 0x30000000 7289#define MC_MISC0__MEMORY_TYPE__GDDR4 0x40000000 7290#define MC_MISC0__MEMORY_TYPE__GDDR5 0x50000000 7291#define MC_MISC0__MEMORY_TYPE__HBM 0x60000000 7292#define MC_MISC0__MEMORY_TYPE__DDR3 0xB0000000 7293 7294#define ATOM_MEM_TYPE_DDR_STRING "DDR" 7295#define ATOM_MEM_TYPE_DDR2_STRING "DDR2" 7296#define ATOM_MEM_TYPE_GDDR3_STRING "GDDR3" 7297#define ATOM_MEM_TYPE_GDDR4_STRING "GDDR4" 7298#define ATOM_MEM_TYPE_GDDR5_STRING "GDDR5" 7299#define ATOM_MEM_TYPE_HBM_STRING "HBM" 7300#define ATOM_MEM_TYPE_DDR3_STRING "DDR3" 7301 7302/****************************************************************************/ 7303//Portion VI: Definitinos being oboselete 7304/****************************************************************************/ 7305 7306//========================================================================================== 7307//Remove the definitions below when driver is ready! 7308typedef struct _ATOM_DAC_INFO 7309{ 7310 ATOM_COMMON_TABLE_HEADER sHeader; 7311 USHORT usMaxFrequency; // in 10kHz unit 7312 USHORT usReserved; 7313}ATOM_DAC_INFO; 7314 7315 7316typedef struct _COMPASSIONATE_DATA 7317{ 7318 ATOM_COMMON_TABLE_HEADER sHeader; 7319 7320 //============================== DAC1 portion 7321 UCHAR ucDAC1_BG_Adjustment; 7322 UCHAR ucDAC1_DAC_Adjustment; 7323 USHORT usDAC1_FORCE_Data; 7324 //============================== DAC2 portion 7325 UCHAR ucDAC2_CRT2_BG_Adjustment; 7326 UCHAR ucDAC2_CRT2_DAC_Adjustment; 7327 USHORT usDAC2_CRT2_FORCE_Data; 7328 USHORT usDAC2_CRT2_MUX_RegisterIndex; 7329 UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 7330 UCHAR ucDAC2_NTSC_BG_Adjustment; 7331 UCHAR ucDAC2_NTSC_DAC_Adjustment; 7332 USHORT usDAC2_TV1_FORCE_Data; 7333 USHORT usDAC2_TV1_MUX_RegisterIndex; 7334 UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 7335 UCHAR ucDAC2_CV_BG_Adjustment; 7336 UCHAR ucDAC2_CV_DAC_Adjustment; 7337 USHORT usDAC2_CV_FORCE_Data; 7338 USHORT usDAC2_CV_MUX_RegisterIndex; 7339 UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 7340 UCHAR ucDAC2_PAL_BG_Adjustment; 7341 UCHAR ucDAC2_PAL_DAC_Adjustment; 7342 USHORT usDAC2_TV2_FORCE_Data; 7343}COMPASSIONATE_DATA; 7344 7345/****************************Supported Device Info Table Definitions**********************/ 7346// ucConnectInfo: 7347// [7:4] - connector type 7348// = 1 - VGA connector 7349// = 2 - DVI-I 7350// = 3 - DVI-D 7351// = 4 - DVI-A 7352// = 5 - SVIDEO 7353// = 6 - COMPOSITE 7354// = 7 - LVDS 7355// = 8 - DIGITAL LINK 7356// = 9 - SCART 7357// = 0xA - HDMI_type A 7358// = 0xB - HDMI_type B 7359// = 0xE - Special case1 (DVI+DIN) 7360// Others=TBD 7361// [3:0] - DAC Associated 7362// = 0 - no DAC 7363// = 1 - DACA 7364// = 2 - DACB 7365// = 3 - External DAC 7366// Others=TBD 7367// 7368 7369typedef struct _ATOM_CONNECTOR_INFO 7370{ 7371#if ATOM_BIG_ENDIAN 7372 UCHAR bfConnectorType:4; 7373 UCHAR bfAssociatedDAC:4; 7374#else 7375 UCHAR bfAssociatedDAC:4; 7376 UCHAR bfConnectorType:4; 7377#endif 7378}ATOM_CONNECTOR_INFO; 7379 7380typedef union _ATOM_CONNECTOR_INFO_ACCESS 7381{ 7382 ATOM_CONNECTOR_INFO sbfAccess; 7383 UCHAR ucAccess; 7384}ATOM_CONNECTOR_INFO_ACCESS; 7385 7386typedef struct _ATOM_CONNECTOR_INFO_I2C 7387{ 7388 ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo; 7389 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 7390}ATOM_CONNECTOR_INFO_I2C; 7391 7392 7393typedef struct _ATOM_SUPPORTED_DEVICES_INFO 7394{ 7395 ATOM_COMMON_TABLE_HEADER sHeader; 7396 USHORT usDeviceSupport; 7397 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO]; 7398}ATOM_SUPPORTED_DEVICES_INFO; 7399 7400#define NO_INT_SRC_MAPPED 0xFF 7401 7402typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP 7403{ 7404 UCHAR ucIntSrcBitmap; 7405}ATOM_CONNECTOR_INC_SRC_BITMAP; 7406 7407typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2 7408{ 7409 ATOM_COMMON_TABLE_HEADER sHeader; 7410 USHORT usDeviceSupport; 7411 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; 7412 ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; 7413}ATOM_SUPPORTED_DEVICES_INFO_2; 7414 7415typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 7416{ 7417 ATOM_COMMON_TABLE_HEADER sHeader; 7418 USHORT usDeviceSupport; 7419 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE]; 7420 ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE]; 7421}ATOM_SUPPORTED_DEVICES_INFO_2d1; 7422 7423#define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1 7424 7425 7426 7427typedef struct _ATOM_MISC_CONTROL_INFO 7428{ 7429 USHORT usFrequency; 7430 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control 7431 UCHAR ucPLL_DutyCycle; // PLL duty cycle control 7432 UCHAR ucPLL_VCO_Gain; // PLL VCO gain control 7433 UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control 7434}ATOM_MISC_CONTROL_INFO; 7435 7436 7437#define ATOM_MAX_MISC_INFO 4 7438 7439typedef struct _ATOM_TMDS_INFO 7440{ 7441 ATOM_COMMON_TABLE_HEADER sHeader; 7442 USHORT usMaxFrequency; // in 10Khz 7443 ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO]; 7444}ATOM_TMDS_INFO; 7445 7446 7447typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE 7448{ 7449 UCHAR ucTVStandard; //Same as TV standards defined above, 7450 UCHAR ucPadding[1]; 7451}ATOM_ENCODER_ANALOG_ATTRIBUTE; 7452 7453typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE 7454{ 7455 UCHAR ucAttribute; //Same as other digital encoder attributes defined above 7456 UCHAR ucPadding[1]; 7457}ATOM_ENCODER_DIGITAL_ATTRIBUTE; 7458 7459typedef union _ATOM_ENCODER_ATTRIBUTE 7460{ 7461 ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib; 7462 ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib; 7463}ATOM_ENCODER_ATTRIBUTE; 7464 7465 7466typedef struct _DVO_ENCODER_CONTROL_PARAMETERS 7467{ 7468 USHORT usPixelClock; 7469 USHORT usEncoderID; 7470 UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only. 7471 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 7472 ATOM_ENCODER_ATTRIBUTE usDevAttr; 7473}DVO_ENCODER_CONTROL_PARAMETERS; 7474 7475typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION 7476{ 7477 DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder; 7478 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 7479}DVO_ENCODER_CONTROL_PS_ALLOCATION; 7480 7481 7482#define ATOM_XTMDS_ASIC_SI164_ID 1 7483#define ATOM_XTMDS_ASIC_SI178_ID 2 7484#define ATOM_XTMDS_ASIC_TFP513_ID 3 7485#define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001 7486#define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002 7487#define ATOM_XTMDS_MVPU_FPGA 0x00000004 7488 7489 7490typedef struct _ATOM_XTMDS_INFO 7491{ 7492 ATOM_COMMON_TABLE_HEADER sHeader; 7493 USHORT usSingleLinkMaxFrequency; 7494 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip 7495 UCHAR ucXtransimitterID; 7496 UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported 7497 UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters 7498 // due to design. This ID is used to alert driver that the sequence is not "standard"! 7499 UCHAR ucMasterAddress; // Address to control Master xTMDS Chip 7500 UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip 7501}ATOM_XTMDS_INFO; 7502 7503typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS 7504{ 7505 UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off 7506 UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX.... 7507 UCHAR ucPadding[2]; 7508}DFP_DPMS_STATUS_CHANGE_PARAMETERS; 7509 7510/****************************Legacy Power Play Table Definitions **********************/ 7511 7512//Definitions for ulPowerPlayMiscInfo 7513#define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L 7514#define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L 7515#define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L 7516 7517#define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT 0x00000004L 7518#define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH 0x00000008L 7519 7520#define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN 0x00000010L 7521 7522#define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L 7523#define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L 7524#define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program 7525 7526#define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L 7527#define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L 7528#define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L 7529#define ATOM_PM_MISCINFO_LOAD_BALANCE_EN 0x00000800L 7530#define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE 0x00001000L 7531#define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L 7532#define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L 7533 7534#define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L 7535#define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L 7536#define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L 7537#define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L 7538#define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L 7539 7540#define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved 7541#define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20 7542 7543#define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L 7544#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L 7545#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L 7546#define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic 7547#define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic 7548#define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode 7549 7550#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) 7551#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28 7552#define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L 7553 7554#define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L 7555#define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L 7556#define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L 7557#define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L 7558#define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L 7559#define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L 7560#define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. 7561 //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback 7562#define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L 7563#define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L 7564#define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L 7565 7566//ucTableFormatRevision=1 7567//ucTableContentRevision=1 7568typedef struct _ATOM_POWERMODE_INFO 7569{ 7570 ULONG ulMiscInfo; //The power level should be arranged in ascending order 7571 ULONG ulReserved1; // must set to 0 7572 ULONG ulReserved2; // must set to 0 7573 USHORT usEngineClock; 7574 USHORT usMemoryClock; 7575 UCHAR ucVoltageDropIndex; // index to GPIO table 7576 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 7577 UCHAR ucMinTemperature; 7578 UCHAR ucMaxTemperature; 7579 UCHAR ucNumPciELanes; // number of PCIE lanes 7580}ATOM_POWERMODE_INFO; 7581 7582//ucTableFormatRevision=2 7583//ucTableContentRevision=1 7584typedef struct _ATOM_POWERMODE_INFO_V2 7585{ 7586 ULONG ulMiscInfo; //The power level should be arranged in ascending order 7587 ULONG ulMiscInfo2; 7588 ULONG ulEngineClock; 7589 ULONG ulMemoryClock; 7590 UCHAR ucVoltageDropIndex; // index to GPIO table 7591 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 7592 UCHAR ucMinTemperature; 7593 UCHAR ucMaxTemperature; 7594 UCHAR ucNumPciELanes; // number of PCIE lanes 7595}ATOM_POWERMODE_INFO_V2; 7596 7597//ucTableFormatRevision=2 7598//ucTableContentRevision=2 7599typedef struct _ATOM_POWERMODE_INFO_V3 7600{ 7601 ULONG ulMiscInfo; //The power level should be arranged in ascending order 7602 ULONG ulMiscInfo2; 7603 ULONG ulEngineClock; 7604 ULONG ulMemoryClock; 7605 UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table 7606 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 7607 UCHAR ucMinTemperature; 7608 UCHAR ucMaxTemperature; 7609 UCHAR ucNumPciELanes; // number of PCIE lanes 7610 UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table 7611}ATOM_POWERMODE_INFO_V3; 7612 7613 7614#define ATOM_MAX_NUMBEROF_POWER_BLOCK 8 7615 7616#define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN 0x01 7617#define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE 0x02 7618 7619#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 0x01 7620#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 0x02 7621#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 0x03 7622#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04 7623#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05 7624#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06 7625#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 // Andigilog 7626 7627 7628typedef struct _ATOM_POWERPLAY_INFO 7629{ 7630 ATOM_COMMON_TABLE_HEADER sHeader; 7631 UCHAR ucOverdriveThermalController; 7632 UCHAR ucOverdriveI2cLine; 7633 UCHAR ucOverdriveIntBitmap; 7634 UCHAR ucOverdriveControllerAddress; 7635 UCHAR ucSizeOfPowerModeEntry; 7636 UCHAR ucNumOfPowerModeEntries; 7637 ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 7638}ATOM_POWERPLAY_INFO; 7639 7640typedef struct _ATOM_POWERPLAY_INFO_V2 7641{ 7642 ATOM_COMMON_TABLE_HEADER sHeader; 7643 UCHAR ucOverdriveThermalController; 7644 UCHAR ucOverdriveI2cLine; 7645 UCHAR ucOverdriveIntBitmap; 7646 UCHAR ucOverdriveControllerAddress; 7647 UCHAR ucSizeOfPowerModeEntry; 7648 UCHAR ucNumOfPowerModeEntries; 7649 ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 7650}ATOM_POWERPLAY_INFO_V2; 7651 7652typedef struct _ATOM_POWERPLAY_INFO_V3 7653{ 7654 ATOM_COMMON_TABLE_HEADER sHeader; 7655 UCHAR ucOverdriveThermalController; 7656 UCHAR ucOverdriveI2cLine; 7657 UCHAR ucOverdriveIntBitmap; 7658 UCHAR ucOverdriveControllerAddress; 7659 UCHAR ucSizeOfPowerModeEntry; 7660 UCHAR ucNumOfPowerModeEntries; 7661 ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 7662}ATOM_POWERPLAY_INFO_V3; 7663 7664 7665// Following definitions are for compatibility issue in different SW components. 7666#define ATOM_MASTER_DATA_TABLE_REVISION 0x01 7667#define Object_Info Object_Header 7668#define AdjustARB_SEQ MC_InitParameter 7669#define VRAM_GPIO_DetectionInfo VoltageObjectInfo 7670#define ASIC_VDDCI_Info ASIC_ProfilingInfo 7671#define ASIC_MVDDQ_Info MemoryTrainingInfo 7672#define SS_Info PPLL_SS_Info 7673#define ASIC_MVDDC_Info ASIC_InternalSS_Info 7674#define DispDevicePriorityInfo SaveRestoreInfo 7675#define DispOutInfo TV_VideoMode 7676 7677 7678#define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE 7679#define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE 7680 7681//New device naming, remove them when both DAL/VBIOS is ready 7682#define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS 7683#define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS 7684 7685#define DFP1X_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS 7686#define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS 7687 7688#define DFP1I_OUTPUT_CONTROL_PARAMETERS DFP1_OUTPUT_CONTROL_PARAMETERS 7689#define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION 7690 7691#define ATOM_DEVICE_DFP1I_SUPPORT ATOM_DEVICE_DFP1_SUPPORT 7692#define ATOM_DEVICE_DFP1X_SUPPORT ATOM_DEVICE_DFP2_SUPPORT 7693 7694#define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX 7695#define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX 7696 7697#define ATOM_DEVICE_DFP2I_INDEX 0x00000009 7698#define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX) 7699 7700#define ATOM_S0_DFP1I ATOM_S0_DFP1 7701#define ATOM_S0_DFP1X ATOM_S0_DFP2 7702 7703#define ATOM_S0_DFP2I 0x00200000L 7704#define ATOM_S0_DFP2Ib2 0x20 7705 7706#define ATOM_S2_DFP1I_DPMS_STATE ATOM_S2_DFP1_DPMS_STATE 7707#define ATOM_S2_DFP1X_DPMS_STATE ATOM_S2_DFP2_DPMS_STATE 7708 7709#define ATOM_S2_DFP2I_DPMS_STATE 0x02000000L 7710#define ATOM_S2_DFP2I_DPMS_STATEb3 0x02 7711 7712#define ATOM_S3_DFP2I_ACTIVEb1 0x02 7713 7714#define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE 7715#define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE 7716 7717#define ATOM_S3_DFP2I_ACTIVE 0x00000200L 7718 7719#define ATOM_S3_DFP1I_CRTC_ACTIVE ATOM_S3_DFP1_CRTC_ACTIVE 7720#define ATOM_S3_DFP1X_CRTC_ACTIVE ATOM_S3_DFP2_CRTC_ACTIVE 7721#define ATOM_S3_DFP2I_CRTC_ACTIVE 0x02000000L 7722 7723#define ATOM_S3_DFP2I_CRTC_ACTIVEb3 0x02 7724#define ATOM_S5_DOS_REQ_DFP2Ib1 0x02 7725 7726#define ATOM_S5_DOS_REQ_DFP2I 0x0200 7727#define ATOM_S6_ACC_REQ_DFP1I ATOM_S6_ACC_REQ_DFP1 7728#define ATOM_S6_ACC_REQ_DFP1X ATOM_S6_ACC_REQ_DFP2 7729 7730#define ATOM_S6_ACC_REQ_DFP2Ib3 0x02 7731#define ATOM_S6_ACC_REQ_DFP2I 0x02000000L 7732 7733#define TMDS1XEncoderControl DVOEncoderControl 7734#define DFP1XOutputControl DVOOutputControl 7735 7736#define ExternalDFPOutputControl DFP1XOutputControl 7737#define EnableExternalTMDS_Encoder TMDS1XEncoderControl 7738 7739#define DFP1IOutputControl TMDSAOutputControl 7740#define DFP2IOutputControl LVTMAOutputControl 7741 7742#define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS 7743#define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION 7744 7745#define DAC2_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS 7746#define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION 7747 7748#define ucDac1Standard ucDacStandard 7749#define ucDac2Standard ucDacStandard 7750 7751#define TMDS1EncoderControl TMDSAEncoderControl 7752#define TMDS2EncoderControl LVTMAEncoderControl 7753 7754#define DFP1OutputControl TMDSAOutputControl 7755#define DFP2OutputControl LVTMAOutputControl 7756#define CRT1OutputControl DAC1OutputControl 7757#define CRT2OutputControl DAC2OutputControl 7758 7759//These two lines will be removed for sure in a few days, will follow up with Michael V. 7760#define EnableLVDS_SS EnableSpreadSpectrumOnPPLL 7761#define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL 7762 7763//#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L 7764//#define ATOM_S2_LCD1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 7765//#define ATOM_S2_TV1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 7766//#define ATOM_S2_DFP1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 7767//#define ATOM_S2_CRT2_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 7768 7769#define ATOM_S6_ACC_REQ_TV2 0x00400000L 7770#define ATOM_DEVICE_TV2_INDEX 0x00000006 7771#define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX) 7772#define ATOM_S0_TV2 0x00100000L 7773#define ATOM_S3_TV2_ACTIVE ATOM_S3_DFP6_ACTIVE 7774#define ATOM_S3_TV2_CRTC_ACTIVE ATOM_S3_DFP6_CRTC_ACTIVE 7775 7776// 7777#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L 7778#define ATOM_S2_LCD1_DPMS_STATE 0x00020000L 7779#define ATOM_S2_TV1_DPMS_STATE 0x00040000L 7780#define ATOM_S2_DFP1_DPMS_STATE 0x00080000L 7781#define ATOM_S2_CRT2_DPMS_STATE 0x00100000L 7782#define ATOM_S2_LCD2_DPMS_STATE 0x00200000L 7783#define ATOM_S2_TV2_DPMS_STATE 0x00400000L 7784#define ATOM_S2_DFP2_DPMS_STATE 0x00800000L 7785#define ATOM_S2_CV_DPMS_STATE 0x01000000L 7786#define ATOM_S2_DFP3_DPMS_STATE 0x02000000L 7787#define ATOM_S2_DFP4_DPMS_STATE 0x04000000L 7788#define ATOM_S2_DFP5_DPMS_STATE 0x08000000L 7789 7790#define ATOM_S2_CRT1_DPMS_STATEb2 0x01 7791#define ATOM_S2_LCD1_DPMS_STATEb2 0x02 7792#define ATOM_S2_TV1_DPMS_STATEb2 0x04 7793#define ATOM_S2_DFP1_DPMS_STATEb2 0x08 7794#define ATOM_S2_CRT2_DPMS_STATEb2 0x10 7795#define ATOM_S2_LCD2_DPMS_STATEb2 0x20 7796#define ATOM_S2_TV2_DPMS_STATEb2 0x40 7797#define ATOM_S2_DFP2_DPMS_STATEb2 0x80 7798#define ATOM_S2_CV_DPMS_STATEb3 0x01 7799#define ATOM_S2_DFP3_DPMS_STATEb3 0x02 7800#define ATOM_S2_DFP4_DPMS_STATEb3 0x04 7801#define ATOM_S2_DFP5_DPMS_STATEb3 0x08 7802 7803#define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3 0x20 7804#define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40 7805#define ATOM_S3_RQST_GPU_USE_MIN_PWRb3 0x80 7806 7807/*********************************************************************************/ 7808 7809#pragma pack() // BIOS data must use byte aligment 7810 7811// 7812// AMD ACPI Table 7813// 7814#pragma pack(1) 7815 7816typedef struct { 7817 ULONG Signature; 7818 ULONG TableLength; //Length 7819 UCHAR Revision; 7820 UCHAR Checksum; 7821 UCHAR OemId[6]; 7822 UCHAR OemTableId[8]; //UINT64 OemTableId; 7823 ULONG OemRevision; 7824 ULONG CreatorId; 7825 ULONG CreatorRevision; 7826} AMD_ACPI_DESCRIPTION_HEADER; 7827/* 7828//EFI_ACPI_DESCRIPTION_HEADER from AcpiCommon.h 7829typedef struct { 7830 UINT32 Signature; //0x0 7831 UINT32 Length; //0x4 7832 UINT8 Revision; //0x8 7833 UINT8 Checksum; //0x9 7834 UINT8 OemId[6]; //0xA 7835 UINT64 OemTableId; //0x10 7836 UINT32 OemRevision; //0x18 7837 UINT32 CreatorId; //0x1C 7838 UINT32 CreatorRevision; //0x20 7839}EFI_ACPI_DESCRIPTION_HEADER; 7840*/ 7841typedef struct { 7842 AMD_ACPI_DESCRIPTION_HEADER SHeader; 7843 UCHAR TableUUID[16]; //0x24 7844 ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture. 7845 ULONG Lib1ImageOffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture. 7846 ULONG Reserved[4]; //0x3C 7847}UEFI_ACPI_VFCT; 7848 7849typedef struct { 7850 ULONG PCIBus; //0x4C 7851 ULONG PCIDevice; //0x50 7852 ULONG PCIFunction; //0x54 7853 USHORT VendorID; //0x58 7854 USHORT DeviceID; //0x5A 7855 USHORT SSVID; //0x5C 7856 USHORT SSID; //0x5E 7857 ULONG Revision; //0x60 7858 ULONG ImageLength; //0x64 7859}VFCT_IMAGE_HEADER; 7860 7861 7862typedef struct { 7863 VFCT_IMAGE_HEADER VbiosHeader; 7864 UCHAR VbiosContent[1]; 7865}GOP_VBIOS_CONTENT; 7866 7867typedef struct { 7868 VFCT_IMAGE_HEADER Lib1Header; 7869 UCHAR Lib1Content[1]; 7870}GOP_LIB1_CONTENT; 7871 7872#pragma pack() 7873 7874 7875#endif /* _ATOMBIOS_H */ 7876 7877#include "pptable.h" 7878 7879