1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23#ifndef __CI_DPM_H__
24#define __CI_DPM_H__
25
26#include "ppsmc.h"
27
28#define SMU__NUM_SCLK_DPM_STATE 8
29#define SMU__NUM_MCLK_DPM_LEVELS 6
30#define SMU__NUM_LCLK_DPM_LEVELS 8
31#define SMU__NUM_PCIE_DPM_LEVELS 8
32#include "smu7_discrete.h"
33
34#define CISLANDS_MAX_HARDWARE_POWERLEVELS 2
35
36struct ci_pl {
37 u32 mclk;
38 u32 sclk;
39 enum radeon_pcie_gen pcie_gen;
40 u16 pcie_lane;
41};
42
43struct ci_ps {
44 u16 performance_level_count;
45 bool dc_compatible;
46 u32 sclk_t;
47 struct ci_pl performance_levels[CISLANDS_MAX_HARDWARE_POWERLEVELS];
48};
49
50struct ci_dpm_level {
51 bool enabled;
52 u32 value;
53 u32 param1;
54};
55
56#define CISLAND_MAX_DEEPSLEEP_DIVIDER_ID 5
57#define MAX_REGULAR_DPM_NUMBER 8
58#define CISLAND_MINIMUM_ENGINE_CLOCK 800
59
60struct ci_single_dpm_table {
61 u32 count;
62 struct ci_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
63};
64
65struct ci_dpm_table {
66 struct ci_single_dpm_table sclk_table;
67 struct ci_single_dpm_table mclk_table;
68 struct ci_single_dpm_table pcie_speed_table;
69 struct ci_single_dpm_table vddc_table;
70 struct ci_single_dpm_table vddci_table;
71 struct ci_single_dpm_table mvdd_table;
72};
73
74struct ci_mc_reg_entry {
75 u32 mclk_max;
76 u32 mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
77};
78
79struct ci_mc_reg_table {
80 u8 last;
81 u8 num_entries;
82 u16 valid_flag;
83 struct ci_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
84 SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
85};
86
87struct ci_ulv_parm
88{
89 bool supported;
90 u32 cg_ulv_parameter;
91 u32 volt_change_delay;
92 struct ci_pl pl;
93};
94
95#define CISLANDS_MAX_LEAKAGE_COUNT 8
96
97struct ci_leakage_voltage {
98 u16 count;
99 u16 leakage_id[CISLANDS_MAX_LEAKAGE_COUNT];
100 u16 actual_voltage[CISLANDS_MAX_LEAKAGE_COUNT];
101};
102
103struct ci_dpm_level_enable_mask {
104 u32 uvd_dpm_enable_mask;
105 u32 vce_dpm_enable_mask;
106 u32 acp_dpm_enable_mask;
107 u32 samu_dpm_enable_mask;
108 u32 sclk_dpm_enable_mask;
109 u32 mclk_dpm_enable_mask;
110 u32 pcie_dpm_enable_mask;
111};
112
113struct ci_vbios_boot_state
114{
115 u16 mvdd_bootup_value;
116 u16 vddc_bootup_value;
117 u16 vddci_bootup_value;
118 u32 sclk_bootup_value;
119 u32 mclk_bootup_value;
120 u16 pcie_gen_bootup_value;
121 u16 pcie_lane_bootup_value;
122};
123
124struct ci_clock_registers {
125 u32 cg_spll_func_cntl;
126 u32 cg_spll_func_cntl_2;
127 u32 cg_spll_func_cntl_3;
128 u32 cg_spll_func_cntl_4;
129 u32 cg_spll_spread_spectrum;
130 u32 cg_spll_spread_spectrum_2;
131 u32 dll_cntl;
132 u32 mclk_pwrmgt_cntl;
133 u32 mpll_ad_func_cntl;
134 u32 mpll_dq_func_cntl;
135 u32 mpll_func_cntl;
136 u32 mpll_func_cntl_1;
137 u32 mpll_func_cntl_2;
138 u32 mpll_ss1;
139 u32 mpll_ss2;
140};
141
142struct ci_thermal_temperature_setting {
143 s32 temperature_low;
144 s32 temperature_high;
145 s32 temperature_shutdown;
146};
147
148struct ci_pcie_perf_range {
149 u16 max;
150 u16 min;
151};
152
153enum ci_pt_config_reg_type {
154 CISLANDS_CONFIGREG_MMR = 0,
155 CISLANDS_CONFIGREG_SMC_IND,
156 CISLANDS_CONFIGREG_DIDT_IND,
157 CISLANDS_CONFIGREG_CACHE,
158 CISLANDS_CONFIGREG_MAX
159};
160
161#define POWERCONTAINMENT_FEATURE_BAPM 0x00000001
162#define POWERCONTAINMENT_FEATURE_TDCLimit 0x00000002
163#define POWERCONTAINMENT_FEATURE_PkgPwrLimit 0x00000004
164
165struct ci_pt_config_reg {
166 u32 offset;
167 u32 mask;
168 u32 shift;
169 u32 value;
170 enum ci_pt_config_reg_type type;
171};
172
173struct ci_pt_defaults {
174 u8 svi_load_line_en;
175 u8 svi_load_line_vddc;
176 u8 tdc_vddc_throttle_release_limit_perc;
177 u8 tdc_mawt;
178 u8 tdc_waterfall_ctl;
179 u8 dte_ambient_temp_base;
180 u32 display_cac;
181 u32 bapm_temp_gradient;
182 u16 bapmti_r[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS];
183 u16 bapmti_rc[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS];
184};
185
186#define DPMTABLE_OD_UPDATE_SCLK 0x00000001
187#define DPMTABLE_OD_UPDATE_MCLK 0x00000002
188#define DPMTABLE_UPDATE_SCLK 0x00000004
189#define DPMTABLE_UPDATE_MCLK 0x00000008
190
191struct ci_power_info {
192 struct ci_dpm_table dpm_table;
193 u32 voltage_control;
194 u32 mvdd_control;
195 u32 vddci_control;
196 u32 active_auto_throttle_sources;
197 struct ci_clock_registers clock_registers;
198 u16 acpi_vddc;
199 u16 acpi_vddci;
200 enum radeon_pcie_gen force_pcie_gen;
201 enum radeon_pcie_gen acpi_pcie_gen;
202 struct ci_leakage_voltage vddc_leakage;
203 struct ci_leakage_voltage vddci_leakage;
204 u16 max_vddc_in_pp_table;
205 u16 min_vddc_in_pp_table;
206 u16 max_vddci_in_pp_table;
207 u16 min_vddci_in_pp_table;
208 u32 mclk_strobe_mode_threshold;
209 u32 mclk_stutter_mode_threshold;
210 u32 mclk_edc_enable_threshold;
211 u32 mclk_edc_wr_enable_threshold;
212 struct ci_vbios_boot_state vbios_boot_state;
213
214 u32 sram_end;
215 u32 dpm_table_start;
216 u32 soft_regs_start;
217 u32 mc_reg_table_start;
218 u32 fan_table_start;
219 u32 arb_table_start;
220
221 SMU7_Discrete_DpmTable smc_state_table;
222 SMU7_Discrete_MCRegisters smc_mc_reg_table;
223 SMU7_Discrete_PmFuses smc_powertune_table;
224
225 struct ci_mc_reg_table mc_reg_table;
226 struct atom_voltage_table vddc_voltage_table;
227 struct atom_voltage_table vddci_voltage_table;
228 struct atom_voltage_table mvdd_voltage_table;
229 struct ci_ulv_parm ulv;
230 u32 power_containment_features;
231 const struct ci_pt_defaults *powertune_defaults;
232 u32 dte_tj_offset;
233 bool vddc_phase_shed_control;
234 struct ci_thermal_temperature_setting thermal_temp_setting;
235 struct ci_dpm_level_enable_mask dpm_level_enable_mask;
236 u32 need_update_smu7_dpm_table;
237 u32 sclk_dpm_key_disabled;
238 u32 mclk_dpm_key_disabled;
239 u32 pcie_dpm_key_disabled;
240 struct ci_pcie_perf_range pcie_gen_performance;
241 struct ci_pcie_perf_range pcie_lane_performance;
242 struct ci_pcie_perf_range pcie_gen_powersaving;
243 struct ci_pcie_perf_range pcie_lane_powersaving;
244 u32 activity_target[SMU7_MAX_LEVELS_GRAPHICS];
245 u32 mclk_activity_target;
246 u32 low_sclk_interrupt_t;
247 u32 last_mclk_dpm_enable_mask;
248 u32 sys_pcie_mask;
249
250 bool caps_power_containment;
251 bool caps_cac;
252 bool caps_sq_ramping;
253 bool caps_db_ramping;
254 bool caps_td_ramping;
255 bool caps_tcp_ramping;
256 bool caps_fps;
257 bool caps_sclk_ds;
258 bool caps_sclk_ss_support;
259 bool caps_mclk_ss_support;
260 bool caps_uvd_dpm;
261 bool caps_vce_dpm;
262 bool caps_samu_dpm;
263 bool caps_acp_dpm;
264 bool caps_automatic_dc_transition;
265 bool caps_sclk_throttle_low_notification;
266 bool caps_dynamic_ac_timing;
267
268 bool thermal_protection;
269 bool pcie_performance_request;
270 bool dynamic_ss;
271 bool dll_default_on;
272 bool cac_enabled;
273 bool uvd_enabled;
274 bool battery_state;
275 bool pspp_notify_required;
276 bool mem_gddr5;
277 bool enable_bapm_feature;
278 bool enable_tdc_limit_feature;
279 bool enable_pkg_pwr_tracking_feature;
280 bool use_pcie_performance_levels;
281 bool use_pcie_powersaving_levels;
282 bool uvd_power_gated;
283
284 struct radeon_ps current_rps;
285 struct ci_ps current_ps;
286 struct radeon_ps requested_rps;
287 struct ci_ps requested_ps;
288};
289
290#define CISLANDS_VOLTAGE_CONTROL_NONE 0x0
291#define CISLANDS_VOLTAGE_CONTROL_BY_GPIO 0x1
292#define CISLANDS_VOLTAGE_CONTROL_BY_SVID2 0x2
293
294#define CISLANDS_Q88_FORMAT_CONVERSION_UNIT 256
295
296#define CISLANDS_VRC_DFLT0 0x3FFFC000
297#define CISLANDS_VRC_DFLT1 0x000400
298#define CISLANDS_VRC_DFLT2 0xC00080
299#define CISLANDS_VRC_DFLT3 0xC00200
300#define CISLANDS_VRC_DFLT4 0xC01680
301#define CISLANDS_VRC_DFLT5 0xC00033
302#define CISLANDS_VRC_DFLT6 0xC00033
303#define CISLANDS_VRC_DFLT7 0x3FFFC000
304
305#define CISLANDS_CGULVPARAMETER_DFLT 0x00040035
306#define CISLAND_TARGETACTIVITY_DFLT 30
307#define CISLAND_MCLK_TARGETACTIVITY_DFLT 10
308
309#define PCIE_PERF_REQ_REMOVE_REGISTRY 0
310#define PCIE_PERF_REQ_FORCE_LOWPOWER 1
311#define PCIE_PERF_REQ_PECI_GEN1 2
312#define PCIE_PERF_REQ_PECI_GEN2 3
313#define PCIE_PERF_REQ_PECI_GEN3 4
314
315int ci_copy_bytes_to_smc(struct radeon_device *rdev,
316 u32 smc_start_address,
317 const u8 *src, u32 byte_count, u32 limit);
318void ci_start_smc(struct radeon_device *rdev);
319void ci_reset_smc(struct radeon_device *rdev);
320int ci_program_jump_on_start(struct radeon_device *rdev);
321void ci_stop_smc_clock(struct radeon_device *rdev);
322void ci_start_smc_clock(struct radeon_device *rdev);
323bool ci_is_smc_running(struct radeon_device *rdev);
324PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg);
325PPSMC_Result ci_wait_for_smc_inactive(struct radeon_device *rdev);
326int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit);
327int ci_read_smc_sram_dword(struct radeon_device *rdev,
328 u32 smc_address, u32 *value, u32 limit);
329int ci_write_smc_sram_dword(struct radeon_device *rdev,
330 u32 smc_address, u32 value, u32 limit);
331
332#endif
333
