1/* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23#ifndef PP_SMC_H 24#define PP_SMC_H 25 26#pragma pack(push, 1) 27 28#define PPSMC_SWSTATE_FLAG_DC 0x01 29#define PPSMC_SWSTATE_FLAG_UVD 0x02 30#define PPSMC_SWSTATE_FLAG_VCE 0x04 31#define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08 32 33#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00 34#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01 35#define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff 36 37#define PPSMC_SYSTEMFLAG_GPIO_DC 0x01 38#define PPSMC_SYSTEMFLAG_STEPVDDC 0x02 39#define PPSMC_SYSTEMFLAG_GDDR5 0x04 40#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08 41#define PPSMC_SYSTEMFLAG_REGULATOR_HOT 0x10 42#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG 0x20 43#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO 0x40 44 45#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK 0x07 46#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK 0x08 47#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE 0x00 48#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE 0x01 49#define PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH 0x02 50 51#define PPSMC_DISPLAY_WATERMARK_LOW 0 52#define PPSMC_DISPLAY_WATERMARK_HIGH 1 53 54#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01 55#define PPSMC_STATEFLAG_POWERBOOST 0x02 56#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20 57#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS 0x40 58 59#define PPSMC_Result_OK ((uint8_t)0x01) 60#define PPSMC_Result_Failed ((uint8_t)0xFF) 61 62typedef uint8_t PPSMC_Result; 63 64#define PPSMC_MSG_Halt ((uint8_t)0x10) 65#define PPSMC_MSG_Resume ((uint8_t)0x11) 66#define PPSMC_MSG_ZeroLevelsDisabled ((uint8_t)0x13) 67#define PPSMC_MSG_OneLevelsDisabled ((uint8_t)0x14) 68#define PPSMC_MSG_TwoLevelsDisabled ((uint8_t)0x15) 69#define PPSMC_MSG_EnableThermalInterrupt ((uint8_t)0x16) 70#define PPSMC_MSG_RunningOnAC ((uint8_t)0x17) 71#define PPSMC_MSG_SwitchToSwState ((uint8_t)0x20) 72#define PPSMC_MSG_SwitchToInitialState ((uint8_t)0x40) 73#define PPSMC_MSG_NoForcedLevel ((uint8_t)0x41) 74#define PPSMC_MSG_ForceHigh ((uint8_t)0x42) 75#define PPSMC_MSG_ForceMediumOrHigh ((uint8_t)0x43) 76#define PPSMC_MSG_SwitchToMinimumPower ((uint8_t)0x51) 77#define PPSMC_MSG_ResumeFromMinimumPower ((uint8_t)0x52) 78#define PPSMC_MSG_EnableCac ((uint8_t)0x53) 79#define PPSMC_MSG_DisableCac ((uint8_t)0x54) 80#define PPSMC_TDPClampingActive ((uint8_t)0x59) 81#define PPSMC_TDPClampingInactive ((uint8_t)0x5A) 82#define PPSMC_MSG_NoDisplay ((uint8_t)0x5D) 83#define PPSMC_MSG_HasDisplay ((uint8_t)0x5E) 84#define PPSMC_MSG_UVDPowerOFF ((uint8_t)0x60) 85#define PPSMC_MSG_UVDPowerON ((uint8_t)0x61) 86#define PPSMC_MSG_EnableULV ((uint8_t)0x62) 87#define PPSMC_MSG_DisableULV ((uint8_t)0x63) 88#define PPSMC_MSG_EnterULV ((uint8_t)0x64) 89#define PPSMC_MSG_ExitULV ((uint8_t)0x65) 90#define PPSMC_CACLongTermAvgEnable ((uint8_t)0x6E) 91#define PPSMC_CACLongTermAvgDisable ((uint8_t)0x6F) 92#define PPSMC_MSG_CollectCAC_PowerCorreln ((uint8_t)0x7A) 93#define PPSMC_FlushDataCache ((uint8_t)0x80) 94#define PPSMC_MSG_SetEnabledLevels ((uint8_t)0x82) 95#define PPSMC_MSG_SetForcedLevels ((uint8_t)0x83) 96#define PPSMC_MSG_ResetToDefaults ((uint8_t)0x84) 97#define PPSMC_MSG_EnableDTE ((uint8_t)0x87) 98#define PPSMC_MSG_DisableDTE ((uint8_t)0x88) 99#define PPSMC_MSG_ThrottleOVRDSCLKDS ((uint8_t)0x96) 100#define PPSMC_MSG_CancelThrottleOVRDSCLKDS ((uint8_t)0x97) 101 102/* CI/KV/KB */ 103#define PPSMC_MSG_UVDDPM_SetEnabledMask ((uint16_t) 0x12D) 104#define PPSMC_MSG_VCEDPM_SetEnabledMask ((uint16_t) 0x12E) 105#define PPSMC_MSG_ACPDPM_SetEnabledMask ((uint16_t) 0x12F) 106#define PPSMC_MSG_SAMUDPM_SetEnabledMask ((uint16_t) 0x130) 107#define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131) 108#define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132) 109#define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135) 110#define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136) 111#define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d) 112#define PPSMC_MSG_ACPPowerOFF ((uint16_t) 0x137) 113#define PPSMC_MSG_ACPPowerON ((uint16_t) 0x138) 114#define PPSMC_MSG_SAMPowerOFF ((uint16_t) 0x139) 115#define PPSMC_MSG_SAMPowerON ((uint16_t) 0x13a) 116#define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d) 117#define PPSMC_MSG_NBDPM_Enable ((uint16_t) 0x140) 118#define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0x141) 119#define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0x145) 120#define PPSMC_MSG_MCLKDPM_SetEnabledMask ((uint16_t) 0x146) 121#define PPSMC_MSG_PCIeDPM_ForceLevel ((uint16_t) 0x147) 122#define PPSMC_MSG_PCIeDPM_UnForceLevel ((uint16_t) 0x148) 123#define PPSMC_MSG_EnableVRHotGPIOInterrupt ((uint16_t) 0x14a) 124#define PPSMC_MSG_DPM_Enable ((uint16_t) 0x14e) 125#define PPSMC_MSG_DPM_Disable ((uint16_t) 0x14f) 126#define PPSMC_MSG_MCLKDPM_Enable ((uint16_t) 0x150) 127#define PPSMC_MSG_MCLKDPM_Disable ((uint16_t) 0x151) 128#define PPSMC_MSG_UVDDPM_Enable ((uint16_t) 0x154) 129#define PPSMC_MSG_UVDDPM_Disable ((uint16_t) 0x155) 130#define PPSMC_MSG_SAMUDPM_Enable ((uint16_t) 0x156) 131#define PPSMC_MSG_SAMUDPM_Disable ((uint16_t) 0x157) 132#define PPSMC_MSG_ACPDPM_Enable ((uint16_t) 0x158) 133#define PPSMC_MSG_ACPDPM_Disable ((uint16_t) 0x159) 134#define PPSMC_MSG_VCEDPM_Enable ((uint16_t) 0x15a) 135#define PPSMC_MSG_VCEDPM_Disable ((uint16_t) 0x15b) 136#define PPSMC_MSG_VddC_Request ((uint16_t) 0x15f) 137#define PPSMC_MSG_SCLKDPM_GetEnabledMask ((uint16_t) 0x162) 138#define PPSMC_MSG_PCIeDPM_SetEnabledMask ((uint16_t) 0x167) 139#define PPSMC_MSG_TDCLimitEnable ((uint16_t) 0x169) 140#define PPSMC_MSG_TDCLimitDisable ((uint16_t) 0x16a) 141#define PPSMC_MSG_PkgPwrLimitEnable ((uint16_t) 0x185) 142#define PPSMC_MSG_PkgPwrLimitDisable ((uint16_t) 0x186) 143#define PPSMC_MSG_PkgPwrSetLimit ((uint16_t) 0x187) 144#define PPSMC_MSG_OverDriveSetTargetTdp ((uint16_t) 0x188) 145#define PPSMC_MSG_SCLKDPM_FreezeLevel ((uint16_t) 0x189) 146#define PPSMC_MSG_SCLKDPM_UnfreezeLevel ((uint16_t) 0x18A) 147#define PPSMC_MSG_MCLKDPM_FreezeLevel ((uint16_t) 0x18B) 148#define PPSMC_MSG_MCLKDPM_UnfreezeLevel ((uint16_t) 0x18C) 149#define PPSMC_MSG_MASTER_DeepSleep_ON ((uint16_t) 0x18F) 150#define PPSMC_MSG_MASTER_DeepSleep_OFF ((uint16_t) 0x190) 151#define PPSMC_MSG_Remove_DC_Clamp ((uint16_t) 0x191) 152 153#define PPSMC_MSG_API_GetSclkFrequency ((uint16_t) 0x200) 154#define PPSMC_MSG_API_GetMclkFrequency ((uint16_t) 0x201) 155 156/* TN */ 157#define PPSMC_MSG_DPM_Config ((uint32_t) 0x102) 158#define PPSMC_MSG_DPM_ForceState ((uint32_t) 0x104) 159#define PPSMC_MSG_PG_SIMD_Config ((uint32_t) 0x108) 160#define PPSMC_MSG_DPM_N_LevelsDisabled ((uint32_t) 0x112) 161#define PPSMC_MSG_Voltage_Cntl_Enable ((uint32_t) 0x109) 162#define PPSMC_MSG_VCEPowerOFF ((uint32_t) 0x10e) 163#define PPSMC_MSG_VCEPowerON ((uint32_t) 0x10f) 164#define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint32_t) 0x11d) 165#define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint32_t) 0x11e) 166#define PPSMC_MSG_EnableBAPM ((uint32_t) 0x120) 167#define PPSMC_MSG_DisableBAPM ((uint32_t) 0x121) 168#define PPSMC_MSG_UVD_DPM_Config ((uint32_t) 0x124) 169 170 171typedef uint16_t PPSMC_Msg; 172 173#pragma pack(pop) 174 175#endif 176