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10
11#define IDE_IN(a,b,c) ( ((a)<(b)) ? (b) : ( (a)>(c) ? (c) : (a)) )
12
13#define IDE_IMPLY(a,b) ((!(a)) || (b))
14
15#define QD_TIM1_PORT (base)
16#define QD_CONFIG_PORT (base+0x01)
17#define QD_TIM2_PORT (base+0x02)
18#define QD_CONTROL_PORT (base+0x03)
19
20#define QD_CONFIG_IDE_BASEPORT 0x01
21#define QD_CONFIG_BASEPORT 0x02
22#define QD_CONFIG_ID3 0x04
23#define QD_CONFIG_DISABLED 0x08
24#define QD_CONFIG_QD6500 0xc0
25#define QD_CONFIG_QD6580_A 0xa0
26#define QD_CONFIG_QD6580_B 0x50
27
28#define QD_CONTR_SEC_DISABLED 0x01
29
30#define QD_ID3 ((config & QD_CONFIG_ID3)!=0)
31
32#define QD_CONFIG(hwif) ((hwif)->config_data & 0x00ff)
33
34static inline u8 QD_TIMING(ide_drive_t *drive)
35{
36 return (unsigned long)ide_get_drivedata(drive) & 0x00ff;
37}
38
39static inline u8 QD_TIMREG(ide_drive_t *drive)
40{
41 return ((unsigned long)ide_get_drivedata(drive) & 0xff00) >> 8;
42}
43
44#define QD6500_DEF_DATA ((QD_TIM1_PORT<<8) | (QD_ID3 ? 0x0c : 0x08))
45#define QD6580_DEF_DATA ((QD_TIM1_PORT<<8) | (QD_ID3 ? 0x0a : 0x00))
46#define QD6580_DEF_DATA2 ((QD_TIM2_PORT<<8) | (QD_ID3 ? 0x0a : 0x00))
47#define QD_DEF_CONTR (0x40 | ((control & 0x02) ? 0x9f : 0x1f))
48
49#define QD_TESTVAL 0x19
50
51
52
53static struct qd65xx_timing_s {
54 s8 offset;
55 char model[4];
56 s16 active;
57 s16 recovery;
58} qd65xx_timing [] = {
59 { 30, "2040", 110, 225 },
60 { 30, "2045", 135, 225 },
61 { 30, "1040", 155, 325 },
62 { 30, "1047", 135, 265 },
63 { 30, "5344", 135, 225 },
64 { 30, "01 4", 175, 405 },
65 { 27, "C030", 175, 375 },
66 { 8, "PL42", 110, 295 },
67 { 8, "PL21", 110, 315 },
68 { 8, "PL25", 175, 385 },
69 { 4, "PA24", 110, 285 },
70 { 6, "2200", 110, 260 },
71 { 6, "3204", 110, 235 },
72 { 6, "1202", 110, 265 },
73 { 0, "DS3-", 135, 315 },
74 { 8, "KM32", 175, 355 },
75 { 2, "53A1", 175, 355 },
76 { 2, "4108", 175, 295 },
77 { 2, "1344", 175, 335 },
78 { 6, "7 12", 110, 225 },
79 { 30, "02F4", 145, 295 },
80 { 2, "1302", 175, 335 },
81 { 2, "2334", 145, 265 },
82 { 2, "2338", 145, 275 },
83 { 2, "3309", 145, 275 },
84 { 2, "5305", 145, 275 },
85 { 2, "4100", 175, 295 },
86 { 2, "4110", 175, 295 },
87 { 2, "6300", 135, 265 },
88 { 2, "5300", 135, 265 },
89 { 6, "7 31", 135, 225 },
90 { 6, "7 43", 115, 265 },
91 { 6, "7 42", 110, 255 },
92 { 6, "3 04", 135, 265 },
93 { 6, "61 0", 135, 285 },
94 { 6, "1107", 135, 235 },
95 { 6, "2101", 110, 220 },
96 { 6, "4202", 135, 245 },
97 { 6, "41 0", 175, 355 },
98 { 6, "82 0", 175, 355 },
99 { 8, "PL01", 175, 375 },
100 { 8, "PL25", 110, 295 },
101 { 10, "4S 2", 175, 385 },
102 { 10, "8S 5", 175, 385 },
103 { 10, "1S72", 175, 385 },
104 { 10, "1S07", 175, 385 },
105 { 8, "ZE42", 135, 295 },
106 { 8, "ZE21", 175, 385 },
107 { 8, "ZE58", 175, 385 },
108 { 8, "ZE24", 175, 385 },
109 { 27, "C036", 155, 325 },
110 { 27, "C038", 155, 325 },
111 { 6, "2205", 110, 255 },
112 { 2, " CHA", 140, 415 },
113 { 2, " CLA", 140, 415 },
114 { 4, "UC41", 140, 415 },
115 { 6, "1207", 130, 275 },
116 { 6, "2107", 130, 275 },
117 { 6, "5204", 130, 275 },
118 { 30, "3004", 110, 235 },
119 { 30, "0345", 135, 255 },
120 { 12, "12A3", 175, 320 },
121 { 12, "43A0", 145, 240 },
122 { 6, "7 21", 180, 290 },
123 { 6, "7 71", 135, 240 },
124 { 12, "45\0000", 110, 205 },
125 { 8, "PL11", 180, 290 },
126 { 8, "OG21", 150, 275 },
127 { 12, "42A5", 175, 320 },
128 { 2, "2309", 175, 295 },
129 { 2, "3358", 180, 310 },
130 { 2, "6355", 180, 310 },
131 { 2, "1900", 175, 270 },
132 { 2, "1954", 175, 270 },
133 { 2, "1909", 175, 270 },
134 { 2, "2953", 175, 270 },
135 { 2, "1359", 175, 270 },
136 { 24, "3R11", 175, 290 },
137 { 0, "2M26", 175, 215 },
138 { 4, "2253", 175, 300 },
139 { 4, "-32A", 145, 245 },
140 { 30, "0326", 150, 270 },
141 { 30, "3044", 110, 195 },
142 { 30, "43A0", 110, 195 },
143 { -1, " ", 175, 415 }
144};
145
