LXR linux/drivers/iio/imu/inv_mpu6050/inv_mpu

   1/*
   2* Copyright (C) 2012 Invensense, Inc.
   3*
   4* This software is licensed under the terms of the GNU General Public
   5* License version 2, as published by the Free Software Foundation, and
   6* may be copied, distributed, and modified under those terms.
   7*
   8* This program is distributed in the hope that it will be useful,
   9* but WITHOUT ANY WARRANTY; without even the implied warranty of
  10* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11* GNU General Public License for more details.
  12*/
  13#include <linux/i2c.h>
  14#include <linux/kfifo.h>
  15#include <linux/spinlock.h>
  16#include <linux/iio/iio.h>
  17#include <linux/iio/buffer.h>
  18#include <linux/iio/sysfs.h>
  19#include <linux/iio/kfifo_buf.h>
  20#include <linux/iio/trigger.h>
  21#include <linux/iio/triggered_buffer.h>
  22#include <linux/iio/trigger_consumer.h>
  23#include <linux/platform_data/invensense_mpu6050.h>
  24
  25/**
  26 *  struct inv_mpu6050_reg_map - Notable registers.
  27 *  @sample_rate_div:   Divider applied to gyro output rate.
  28 *  @lpf:               Configures internal low pass filter.
  29 *  @user_ctrl:         Enables/resets the FIFO.
  30 *  @fifo_en:           Determines which data will appear in FIFO.
  31 *  @gyro_config:       gyro config register.
  32 *  @accl_config:       accel config register
  33 *  @fifo_count_h:      Upper byte of FIFO count.
  34 *  @fifo_r_w:          FIFO register.
  35 *  @raw_gyro:          Address of first gyro register.
  36 *  @raw_accl:          Address of first accel register.
  37 *  @temperature:       temperature register
  38 *  @int_enable:        Interrupt enable register.
  39 *  @pwr_mgmt_1:        Controls chip's power state and clock source.
  40 *  @pwr_mgmt_2:        Controls power state of individual sensors.
  41 */
  42struct inv_mpu6050_reg_map {
  43        u8 sample_rate_div;
  44        u8 lpf;
  45        u8 user_ctrl;
  46        u8 fifo_en;
  47        u8 gyro_config;
  48        u8 accl_config;
  49        u8 fifo_count_h;
  50        u8 fifo_r_w;
  51        u8 raw_gyro;
  52        u8 raw_accl;
  53        u8 temperature;
  54        u8 int_enable;
  55        u8 pwr_mgmt_1;
  56        u8 pwr_mgmt_2;
  57};
  58
  59/*device enum */
  60enum inv_devices {
  61        INV_MPU6050,
  62        INV_NUM_PARTS
  63};
  64
  65/**
  66 *  struct inv_mpu6050_chip_config - Cached chip configuration data.
  67 *  @fsr:               Full scale range.
  68 *  @lpf:               Digital low pass filter frequency.
  69 *  @accl_fs:           accel full scale range.
  70 *  @enable:            master enable state.
  71 *  @accl_fifo_enable:  enable accel data output
  72 *  @gyro_fifo_enable:  enable gyro data output
  73 *  @fifo_rate:         FIFO update rate.
  74 */
  75struct inv_mpu6050_chip_config {
  76        unsigned int fsr:2;
  77        unsigned int lpf:3;
  78        unsigned int accl_fs:2;
  79        unsigned int enable:1;
  80        unsigned int accl_fifo_enable:1;
  81        unsigned int gyro_fifo_enable:1;
  82        u16 fifo_rate;
  83};
  84
  85/**
  86 *  struct inv_mpu6050_hw - Other important hardware information.
  87 *  @num_reg:   Number of registers on device.
  88 *  @name:      name of the chip.
  89 *  @reg:   register map of the chip.
  90 *  @config:    configuration of the chip.
  91 */
  92struct inv_mpu6050_hw {
  93        u8 num_reg;
  94        u8 *name;
  95        const struct inv_mpu6050_reg_map *reg;
  96        const struct inv_mpu6050_chip_config *config;
  97};
  98
  99/*
 100 *  struct inv_mpu6050_state - Driver state variables.
 101 *  @TIMESTAMP_FIFO_SIZE: fifo size for timestamp.
 102 *  @trig:              IIO trigger.
 103 *  @chip_config:       Cached attribute information.
 104 *  @reg:               Map of important registers.
 105 *  @hw:                Other hardware-specific information.
 106 *  @chip_type:         chip type.
 107 *  @time_stamp_lock:   spin lock to time stamp.
 108 *  @client:            i2c client handle.
 109 *  @plat_data:         platform data.
 110 *  @timestamps:        kfifo queue to store time stamp.
 111 */
 112struct inv_mpu6050_state {
 113#define TIMESTAMP_FIFO_SIZE 16
 114        struct iio_trigger  *trig;
 115        struct inv_mpu6050_chip_config chip_config;
 116        const struct inv_mpu6050_reg_map *reg;
 117        const struct inv_mpu6050_hw *hw;
 118        enum   inv_devices chip_type;
 119        spinlock_t time_stamp_lock;
 120        struct i2c_client *client;
 121        struct inv_mpu6050_platform_data plat_data;
 122        DECLARE_KFIFO(timestamps, long long, TIMESTAMP_FIFO_SIZE);
 123};
 124
 125/*register and associated bit definition*/
 126#define INV_MPU6050_REG_SAMPLE_RATE_DIV     0x19
 127#define INV_MPU6050_REG_CONFIG              0x1A
 128#define INV_MPU6050_REG_GYRO_CONFIG         0x1B
 129#define INV_MPU6050_REG_ACCEL_CONFIG        0x1C
 130
 131#define INV_MPU6050_REG_FIFO_EN             0x23
 132#define INV_MPU6050_BIT_ACCEL_OUT                   0x08
 133#define INV_MPU6050_BITS_GYRO_OUT                   0x70
 134
 135#define INV_MPU6050_REG_INT_ENABLE          0x38
 136#define INV_MPU6050_BIT_DATA_RDY_EN                 0x01
 137#define INV_MPU6050_BIT_DMP_INT_EN                  0x02
 138
 139#define INV_MPU6050_REG_RAW_ACCEL           0x3B
 140#define INV_MPU6050_REG_TEMPERATURE         0x41
 141#define INV_MPU6050_REG_RAW_GYRO            0x43
 142
 143#define INV_MPU6050_REG_USER_CTRL           0x6A
 144#define INV_MPU6050_BIT_FIFO_RST                    0x04
 145#define INV_MPU6050_BIT_DMP_RST                     0x08
 146#define INV_MPU6050_BIT_I2C_MST_EN                  0x20
 147#define INV_MPU6050_BIT_FIFO_EN                     0x40
 148#define INV_MPU6050_BIT_DMP_EN                      0x80
 149
 150#define INV_MPU6050_REG_PWR_MGMT_1          0x6B
 151#define INV_MPU6050_BIT_H_RESET                     0x80
 152#define INV_MPU6050_BIT_SLEEP                       0x40
 153#define INV_MPU6050_BIT_CLK_MASK                    0x7
 154
 155#define INV_MPU6050_REG_PWR_MGMT_2          0x6C
 156#define INV_MPU6050_BIT_PWR_ACCL_STBY               0x38
 157#define INV_MPU6050_BIT_PWR_GYRO_STBY               0x07
 158
 159#define INV_MPU6050_REG_FIFO_COUNT_H        0x72
 160#define INV_MPU6050_REG_FIFO_R_W            0x74
 161
 162#define INV_MPU6050_BYTES_PER_3AXIS_SENSOR   6
 163#define INV_MPU6050_FIFO_COUNT_BYTE          2
 164#define INV_MPU6050_FIFO_THRESHOLD           500
 165#define INV_MPU6050_POWER_UP_TIME            100
 166#define INV_MPU6050_TEMP_UP_TIME             100
 167#define INV_MPU6050_SENSOR_UP_TIME           30
 168#define INV_MPU6050_REG_UP_TIME              5
 169
 170#define INV_MPU6050_TEMP_OFFSET              12421
 171#define INV_MPU6050_TEMP_SCALE               2941
 172#define INV_MPU6050_MAX_GYRO_FS_PARAM        3
 173#define INV_MPU6050_MAX_ACCL_FS_PARAM        3
 174#define INV_MPU6050_THREE_AXIS               3
 175#define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT    3
 176#define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT    3
 177
 178/* 6 + 6 round up and plus 8 */
 179#define INV_MPU6050_OUTPUT_DATA_SIZE         24
 180
 181/* init parameters */
 182#define INV_MPU6050_INIT_FIFO_RATE           50
 183#define INV_MPU6050_TIME_STAMP_TOR                        5
 184#define INV_MPU6050_MAX_FIFO_RATE                         1000
 185#define INV_MPU6050_MIN_FIFO_RATE                         4
 186#define INV_MPU6050_ONE_K_HZ                              1000
 187
 188/* scan element definition */
 189enum inv_mpu6050_scan {
 190        INV_MPU6050_SCAN_ACCL_X,
 191        INV_MPU6050_SCAN_ACCL_Y,
 192        INV_MPU6050_SCAN_ACCL_Z,
 193        INV_MPU6050_SCAN_GYRO_X,
 194        INV_MPU6050_SCAN_GYRO_Y,
 195        INV_MPU6050_SCAN_GYRO_Z,
 196        INV_MPU6050_SCAN_TIMESTAMP,
 197};
 198
 199enum inv_mpu6050_filter_e {
 200        INV_MPU6050_FILTER_256HZ_NOLPF2 = 0,
 201        INV_MPU6050_FILTER_188HZ,
 202        INV_MPU6050_FILTER_98HZ,
 203        INV_MPU6050_FILTER_42HZ,
 204        INV_MPU6050_FILTER_20HZ,
 205        INV_MPU6050_FILTER_10HZ,
 206        INV_MPU6050_FILTER_5HZ,
 207        INV_MPU6050_FILTER_2100HZ_NOLPF,
 208        NUM_MPU6050_FILTER
 209};
 210
 211/* IIO attribute address */
 212enum INV_MPU6050_IIO_ATTR_ADDR {
 213        ATTR_GYRO_MATRIX,
 214        ATTR_ACCL_MATRIX,
 215};
 216
 217enum inv_mpu6050_accl_fs_e {
 218        INV_MPU6050_FS_02G = 0,
 219        INV_MPU6050_FS_04G,
 220        INV_MPU6050_FS_08G,
 221        INV_MPU6050_FS_16G,
 222        NUM_ACCL_FSR
 223};
 224
 225enum inv_mpu6050_fsr_e {
 226        INV_MPU6050_FSR_250DPS = 0,
 227        INV_MPU6050_FSR_500DPS,
 228        INV_MPU6050_FSR_1000DPS,
 229        INV_MPU6050_FSR_2000DPS,
 230        NUM_MPU6050_FSR
 231};
 232
 233enum inv_mpu6050_clock_sel_e {
 234        INV_CLK_INTERNAL = 0,
 235        INV_CLK_PLL,
 236        NUM_CLK
 237};
 238
 239irqreturn_t inv_mpu6050_irq_handler(int irq, void *p);
 240irqreturn_t inv_mpu6050_read_fifo(int irq, void *p);
 241int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev);
 242void inv_mpu6050_remove_trigger(struct inv_mpu6050_state *st);
 243int inv_reset_fifo(struct iio_dev *indio_dev);
 244int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask);
 245int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val);
 246int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on);
 247