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12
13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15#include <linux/types.h>
16#include <linux/delay.h>
17#include <linux/module.h>
18#include <linux/interrupt.h>
19#include <linux/ioport.h>
20#include <linux/init.h>
21#include <linux/serio.h>
22#include <linux/err.h>
23#include <linux/rcupdate.h>
24#include <linux/platform_device.h>
25#include <linux/i8042.h>
26#include <linux/slab.h>
27
28#include <asm/io.h>
29
30MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>");
31MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver");
32MODULE_LICENSE("GPL");
33
34static bool i8042_nokbd;
35module_param_named(nokbd, i8042_nokbd, bool, 0);
36MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port.");
37
38static bool i8042_noaux;
39module_param_named(noaux, i8042_noaux, bool, 0);
40MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port.");
41
42static bool i8042_nomux;
43module_param_named(nomux, i8042_nomux, bool, 0);
44MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing controller is present.");
45
46static bool i8042_unlock;
47module_param_named(unlock, i8042_unlock, bool, 0);
48MODULE_PARM_DESC(unlock, "Ignore keyboard lock.");
49
50static bool i8042_reset;
51module_param_named(reset, i8042_reset, bool, 0);
52MODULE_PARM_DESC(reset, "Reset controller during init and cleanup.");
53
54static bool i8042_direct;
55module_param_named(direct, i8042_direct, bool, 0);
56MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode.");
57
58static bool i8042_dumbkbd;
59module_param_named(dumbkbd, i8042_dumbkbd, bool, 0);
60MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard");
61
62static bool i8042_noloop;
63module_param_named(noloop, i8042_noloop, bool, 0);
64MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port");
65
66static bool i8042_notimeout;
67module_param_named(notimeout, i8042_notimeout, bool, 0);
68MODULE_PARM_DESC(notimeout, "Ignore timeouts signalled by i8042");
69
70#ifdef CONFIG_X86
71static bool i8042_dritek;
72module_param_named(dritek, i8042_dritek, bool, 0);
73MODULE_PARM_DESC(dritek, "Force enable the Dritek keyboard extension");
74#endif
75
76#ifdef CONFIG_PNP
77static bool i8042_nopnp;
78module_param_named(nopnp, i8042_nopnp, bool, 0);
79MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings");
80#endif
81
82#define DEBUG
83#ifdef DEBUG
84static bool i8042_debug;
85module_param_named(debug, i8042_debug, bool, 0600);
86MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off");
87#endif
88
89static bool i8042_bypass_aux_irq_test;
90
91#include "i8042.h"
92
93
94
95
96
97static DEFINE_SPINLOCK(i8042_lock);
98
99
100
101
102
103
104
105
106
107static DEFINE_MUTEX(i8042_mutex);
108
109struct i8042_port {
110 struct serio *serio;
111 int irq;
112 bool exists;
113 signed char mux;
114};
115
116#define I8042_KBD_PORT_NO 0
117#define I8042_AUX_PORT_NO 1
118#define I8042_MUX_PORT_NO 2
119#define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2)
120
121static struct i8042_port i8042_ports[I8042_NUM_PORTS];
122
123static unsigned char i8042_initial_ctr;
124static unsigned char i8042_ctr;
125static bool i8042_mux_present;
126static bool i8042_kbd_irq_registered;
127static bool i8042_aux_irq_registered;
128static unsigned char i8042_suppress_kbd_ack;
129static struct platform_device *i8042_platform_device;
130
131static irqreturn_t i8042_interrupt(int irq, void *dev_id);
132static bool (*i8042_platform_filter)(unsigned char data, unsigned char str,
133 struct serio *serio);
134
135void i8042_lock_chip(void)
136{
137 mutex_lock(&i8042_mutex);
138}
139EXPORT_SYMBOL(i8042_lock_chip);
140
141void i8042_unlock_chip(void)
142{
143 mutex_unlock(&i8042_mutex);
144}
145EXPORT_SYMBOL(i8042_unlock_chip);
146
147int i8042_install_filter(bool (*filter)(unsigned char data, unsigned char str,
148 struct serio *serio))
149{
150 unsigned long flags;
151 int ret = 0;
152
153 spin_lock_irqsave(&i8042_lock, flags);
154
155 if (i8042_platform_filter) {
156 ret = -EBUSY;
157 goto out;
158 }
159
160 i8042_platform_filter = filter;
161
162out:
163 spin_unlock_irqrestore(&i8042_lock, flags);
164 return ret;
165}
166EXPORT_SYMBOL(i8042_install_filter);
167
168int i8042_remove_filter(bool (*filter)(unsigned char data, unsigned char str,
169 struct serio *port))
170{
171 unsigned long flags;
172 int ret = 0;
173
174 spin_lock_irqsave(&i8042_lock, flags);
175
176 if (i8042_platform_filter != filter) {
177 ret = -EINVAL;
178 goto out;
179 }
180
181 i8042_platform_filter = NULL;
182
183out:
184 spin_unlock_irqrestore(&i8042_lock, flags);
185 return ret;
186}
187EXPORT_SYMBOL(i8042_remove_filter);
188
189
190
191
192
193
194
195static int i8042_wait_read(void)
196{
197 int i = 0;
198
199 while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) {
200 udelay(50);
201 i++;
202 }
203 return -(i == I8042_CTL_TIMEOUT);
204}
205
206static int i8042_wait_write(void)
207{
208 int i = 0;
209
210 while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) {
211 udelay(50);
212 i++;
213 }
214 return -(i == I8042_CTL_TIMEOUT);
215}
216
217
218
219
220
221
222static int i8042_flush(void)
223{
224 unsigned long flags;
225 unsigned char data, str;
226 int count = 0;
227 int retval = 0;
228
229 spin_lock_irqsave(&i8042_lock, flags);
230
231 while ((str = i8042_read_status()) & I8042_STR_OBF) {
232 if (count++ < I8042_BUFFER_SIZE) {
233 udelay(50);
234 data = i8042_read_data();
235 dbg("%02x <- i8042 (flush, %s)\n",
236 data, str & I8042_STR_AUXDATA ? "aux" : "kbd");
237 } else {
238 retval = -EIO;
239 break;
240 }
241 }
242
243 spin_unlock_irqrestore(&i8042_lock, flags);
244
245 return retval;
246}
247
248
249
250
251
252
253
254
255
256static int __i8042_command(unsigned char *param, int command)
257{
258 int i, error;
259
260 if (i8042_noloop && command == I8042_CMD_AUX_LOOP)
261 return -1;
262
263 error = i8042_wait_write();
264 if (error)
265 return error;
266
267 dbg("%02x -> i8042 (command)\n", command & 0xff);
268 i8042_write_command(command & 0xff);
269
270 for (i = 0; i < ((command >> 12) & 0xf); i++) {
271 error = i8042_wait_write();
272 if (error)
273 return error;
274 dbg("%02x -> i8042 (parameter)\n", param[i]);
275 i8042_write_data(param[i]);
276 }
277
278 for (i = 0; i < ((command >> 8) & 0xf); i++) {
279 error = i8042_wait_read();
280 if (error) {
281 dbg(" -- i8042 (timeout)\n");
282 return error;
283 }
284
285 if (command == I8042_CMD_AUX_LOOP &&
286 !(i8042_read_status() & I8042_STR_AUXDATA)) {
287 dbg(" -- i8042 (auxerr)\n");
288 return -1;
289 }
290
291 param[i] = i8042_read_data();
292 dbg("%02x <- i8042 (return)\n", param[i]);
293 }
294
295 return 0;
296}
297
298int i8042_command(unsigned char *param, int command)
299{
300 unsigned long flags;
301 int retval;
302
303 spin_lock_irqsave(&i8042_lock, flags);
304 retval = __i8042_command(param, command);
305 spin_unlock_irqrestore(&i8042_lock, flags);
306
307 return retval;
308}
309EXPORT_SYMBOL(i8042_command);
310
311
312
313
314
315static int i8042_kbd_write(struct serio *port, unsigned char c)
316{
317 unsigned long flags;
318 int retval = 0;
319
320 spin_lock_irqsave(&i8042_lock, flags);
321
322 if (!(retval = i8042_wait_write())) {
323 dbg("%02x -> i8042 (kbd-data)\n", c);
324 i8042_write_data(c);
325 }
326
327 spin_unlock_irqrestore(&i8042_lock, flags);
328
329 return retval;
330}
331
332
333
334
335
336static int i8042_aux_write(struct serio *serio, unsigned char c)
337{
338 struct i8042_port *port = serio->port_data;
339
340 return i8042_command(&c, port->mux == -1 ?
341 I8042_CMD_AUX_SEND :
342 I8042_CMD_MUX_SEND + port->mux);
343}
344
345
346
347
348
349
350
351static void i8042_port_close(struct serio *serio)
352{
353 int irq_bit;
354 int disable_bit;
355 const char *port_name;
356
357 if (serio == i8042_ports[I8042_AUX_PORT_NO].serio) {
358 irq_bit = I8042_CTR_AUXINT;
359 disable_bit = I8042_CTR_AUXDIS;
360 port_name = "AUX";
361 } else {
362 irq_bit = I8042_CTR_KBDINT;
363 disable_bit = I8042_CTR_KBDDIS;
364 port_name = "KBD";
365 }
366
367 i8042_ctr &= ~irq_bit;
368 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
369 pr_warn("Can't write CTR while closing %s port\n", port_name);
370
371 udelay(50);
372
373 i8042_ctr &= ~disable_bit;
374 i8042_ctr |= irq_bit;
375 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
376 pr_err("Can't reactivate %s port\n", port_name);
377
378
379
380
381
382 i8042_interrupt(0, NULL);
383}
384
385
386
387
388
389
390static int i8042_start(struct serio *serio)
391{
392 struct i8042_port *port = serio->port_data;
393
394 port->exists = true;
395 mb();
396 return 0;
397}
398
399
400
401
402
403
404static void i8042_stop(struct serio *serio)
405{
406 struct i8042_port *port = serio->port_data;
407
408 port->exists = false;
409
410
411
412
413
414
415 synchronize_irq(I8042_AUX_IRQ);
416 synchronize_irq(I8042_KBD_IRQ);
417 port->serio = NULL;
418}
419
420
421
422
423
424
425static bool i8042_filter(unsigned char data, unsigned char str,
426 struct serio *serio)
427{
428 if (unlikely(i8042_suppress_kbd_ack)) {
429 if ((~str & I8042_STR_AUXDATA) &&
430 (data == 0xfa || data == 0xfe)) {
431 i8042_suppress_kbd_ack--;
432 dbg("Extra keyboard ACK - filtered out\n");
433 return true;
434 }
435 }
436
437 if (i8042_platform_filter && i8042_platform_filter(data, str, serio)) {
438 dbg("Filtered out by platform filter\n");
439 return true;
440 }
441
442 return false;
443}
444
445
446
447
448
449
450
451static irqreturn_t i8042_interrupt(int irq, void *dev_id)
452{
453 struct i8042_port *port;
454 struct serio *serio;
455 unsigned long flags;
456 unsigned char str, data;
457 unsigned int dfl;
458 unsigned int port_no;
459 bool filtered;
460 int ret = 1;
461
462 spin_lock_irqsave(&i8042_lock, flags);
463
464 str = i8042_read_status();
465 if (unlikely(~str & I8042_STR_OBF)) {
466 spin_unlock_irqrestore(&i8042_lock, flags);
467 if (irq)
468 dbg("Interrupt %d, without any data\n", irq);
469 ret = 0;
470 goto out;
471 }
472
473 data = i8042_read_data();
474
475 if (i8042_mux_present && (str & I8042_STR_AUXDATA)) {
476 static unsigned long last_transmit;
477 static unsigned char last_str;
478
479 dfl = 0;
480 if (str & I8042_STR_MUXERR) {
481 dbg("MUX error, status is %02x, data is %02x\n",
482 str, data);
483
484
485
486
487
488
489
490
491
492
493
494
495
496 switch (data) {
497 default:
498 if (time_before(jiffies, last_transmit + HZ/10)) {
499 str = last_str;
500 break;
501 }
502
503 case 0xfc:
504 case 0xfd:
505 case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break;
506 case 0xff: dfl = SERIO_PARITY; data = 0xfe; break;
507 }
508 }
509
510 port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3);
511 last_str = str;
512 last_transmit = jiffies;
513 } else {
514
515 dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) |
516 ((str & I8042_STR_TIMEOUT && !i8042_notimeout) ? SERIO_TIMEOUT : 0);
517
518 port_no = (str & I8042_STR_AUXDATA) ?
519 I8042_AUX_PORT_NO : I8042_KBD_PORT_NO;
520 }
521
522 port = &i8042_ports[port_no];
523 serio = port->exists ? port->serio : NULL;
524
525 dbg("%02x <- i8042 (interrupt, %d, %d%s%s)\n",
526 data, port_no, irq,
527 dfl & SERIO_PARITY ? ", bad parity" : "",
528 dfl & SERIO_TIMEOUT ? ", timeout" : "");
529
530 filtered = i8042_filter(data, str, serio);
531
532 spin_unlock_irqrestore(&i8042_lock, flags);
533
534 if (likely(port->exists && !filtered))
535 serio_interrupt(serio, data, dfl);
536
537 out:
538 return IRQ_RETVAL(ret);
539}
540
541
542
543
544
545static int i8042_enable_kbd_port(void)
546{
547 i8042_ctr &= ~I8042_CTR_KBDDIS;
548 i8042_ctr |= I8042_CTR_KBDINT;
549
550 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
551 i8042_ctr &= ~I8042_CTR_KBDINT;
552 i8042_ctr |= I8042_CTR_KBDDIS;
553 pr_err("Failed to enable KBD port\n");
554 return -EIO;
555 }
556
557 return 0;
558}
559
560
561
562
563
564static int i8042_enable_aux_port(void)
565{
566 i8042_ctr &= ~I8042_CTR_AUXDIS;
567 i8042_ctr |= I8042_CTR_AUXINT;
568
569 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
570 i8042_ctr &= ~I8042_CTR_AUXINT;
571 i8042_ctr |= I8042_CTR_AUXDIS;
572 pr_err("Failed to enable AUX port\n");
573 return -EIO;
574 }
575
576 return 0;
577}
578
579
580
581
582
583
584static int i8042_enable_mux_ports(void)
585{
586 unsigned char param;
587 int i;
588
589 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) {
590 i8042_command(¶m, I8042_CMD_MUX_PFX + i);
591 i8042_command(¶m, I8042_CMD_AUX_ENABLE);
592 }
593
594 return i8042_enable_aux_port();
595}
596
597
598
599
600
601
602
603static int i8042_set_mux_mode(bool multiplex, unsigned char *mux_version)
604{
605
606 unsigned char param, val;
607
608
609
610
611 i8042_flush();
612
613
614
615
616
617
618 param = val = 0xf0;
619 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val)
620 return -1;
621 param = val = multiplex ? 0x56 : 0xf6;
622 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val)
623 return -1;
624 param = val = multiplex ? 0xa4 : 0xa5;
625 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == val)
626 return -1;
627
628
629
630
631
632 if (param == 0xac)
633 return -1;
634
635 if (mux_version)
636 *mux_version = param;
637
638 return 0;
639}
640
641
642
643
644
645
646
647static int __init i8042_check_mux(void)
648{
649 unsigned char mux_version;
650
651 if (i8042_set_mux_mode(true, &mux_version))
652 return -1;
653
654 pr_info("Detected active multiplexing controller, rev %d.%d\n",
655 (mux_version >> 4) & 0xf, mux_version & 0xf);
656
657
658
659
660 i8042_ctr |= I8042_CTR_AUXDIS;
661 i8042_ctr &= ~I8042_CTR_AUXINT;
662
663 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
664 pr_err("Failed to disable AUX port, can't use MUX\n");
665 return -EIO;
666 }
667
668 i8042_mux_present = true;
669
670 return 0;
671}
672
673
674
675
676static struct completion i8042_aux_irq_delivered __initdata;
677static bool i8042_irq_being_tested __initdata;
678
679static irqreturn_t __init i8042_aux_test_irq(int irq, void *dev_id)
680{
681 unsigned long flags;
682 unsigned char str, data;
683 int ret = 0;
684
685 spin_lock_irqsave(&i8042_lock, flags);
686 str = i8042_read_status();
687 if (str & I8042_STR_OBF) {
688 data = i8042_read_data();
689 dbg("%02x <- i8042 (aux_test_irq, %s)\n",
690 data, str & I8042_STR_AUXDATA ? "aux" : "kbd");
691 if (i8042_irq_being_tested &&
692 data == 0xa5 && (str & I8042_STR_AUXDATA))
693 complete(&i8042_aux_irq_delivered);
694 ret = 1;
695 }
696 spin_unlock_irqrestore(&i8042_lock, flags);
697
698 return IRQ_RETVAL(ret);
699}
700
701
702
703
704
705
706static int __init i8042_toggle_aux(bool on)
707{
708 unsigned char param;
709 int i;
710
711 if (i8042_command(¶m,
712 on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE))
713 return -1;
714
715
716 for (i = 0; i < 100; i++) {
717 udelay(50);
718
719 if (i8042_command(¶m, I8042_CMD_CTL_RCTR))
720 return -1;
721
722 if (!(param & I8042_CTR_AUXDIS) == on)
723 return 0;
724 }
725
726 return -1;
727}
728
729
730
731
732
733
734static int __init i8042_check_aux(void)
735{
736 int retval = -1;
737 bool irq_registered = false;
738 bool aux_loop_broken = false;
739 unsigned long flags;
740 unsigned char param;
741
742
743
744
745
746 i8042_flush();
747
748
749
750
751
752
753
754 param = 0x5a;
755 retval = i8042_command(¶m, I8042_CMD_AUX_LOOP);
756 if (retval || param != 0x5a) {
757
758
759
760
761
762
763
764
765
766 if (i8042_command(¶m, I8042_CMD_AUX_TEST) ||
767 (param && param != 0xfa && param != 0xff))
768 return -1;
769
770
771
772
773
774 if (!retval)
775 aux_loop_broken = true;
776 }
777
778
779
780
781
782 if (i8042_toggle_aux(false)) {
783 pr_warn("Failed to disable AUX port, but continuing anyway... Is this a SiS?\n");
784 pr_warn("If AUX port is really absent please use the 'i8042.noaux' option\n");
785 }
786
787 if (i8042_toggle_aux(true))
788 return -1;
789
790
791
792
793
794
795 if (i8042_noloop || i8042_bypass_aux_irq_test || aux_loop_broken) {
796
797
798
799
800 retval = 0;
801 goto out;
802 }
803
804 if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED,
805 "i8042", i8042_platform_device))
806 goto out;
807
808 irq_registered = true;
809
810 if (i8042_enable_aux_port())
811 goto out;
812
813 spin_lock_irqsave(&i8042_lock, flags);
814
815 init_completion(&i8042_aux_irq_delivered);
816 i8042_irq_being_tested = true;
817
818 param = 0xa5;
819 retval = __i8042_command(¶m, I8042_CMD_AUX_LOOP & 0xf0ff);
820
821 spin_unlock_irqrestore(&i8042_lock, flags);
822
823 if (retval)
824 goto out;
825
826 if (wait_for_completion_timeout(&i8042_aux_irq_delivered,
827 msecs_to_jiffies(250)) == 0) {
828
829
830
831
832 dbg(" -- i8042 (aux irq test timeout)\n");
833 i8042_flush();
834 retval = -1;
835 }
836
837 out:
838
839
840
841
842
843 i8042_ctr |= I8042_CTR_AUXDIS;
844 i8042_ctr &= ~I8042_CTR_AUXINT;
845
846 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
847 retval = -1;
848
849 if (irq_registered)
850 free_irq(I8042_AUX_IRQ, i8042_platform_device);
851
852 return retval;
853}
854
855static int i8042_controller_check(void)
856{
857 if (i8042_flush()) {
858 pr_err("No controller found\n");
859 return -ENODEV;
860 }
861
862 return 0;
863}
864
865static int i8042_controller_selftest(void)
866{
867 unsigned char param;
868 int i = 0;
869
870
871
872
873
874 do {
875
876 if (i8042_command(¶m, I8042_CMD_CTL_TEST)) {
877 pr_err("i8042 controller selftest timeout\n");
878 return -ENODEV;
879 }
880
881 if (param == I8042_RET_CTL_TEST)
882 return 0;
883
884 dbg("i8042 controller selftest: %#x != %#x\n",
885 param, I8042_RET_CTL_TEST);
886 msleep(50);
887 } while (i++ < 5);
888
889#ifdef CONFIG_X86
890
891
892
893
894
895
896 pr_info("giving up on controller selftest, continuing anyway...\n");
897 return 0;
898#else
899 pr_err("i8042 controller selftest failed\n");
900 return -EIO;
901#endif
902}
903
904
905
906
907
908
909
910static int i8042_controller_init(void)
911{
912 unsigned long flags;
913 int n = 0;
914 unsigned char ctr[2];
915
916
917
918
919
920 do {
921 if (n >= 10) {
922 pr_err("Unable to get stable CTR read\n");
923 return -EIO;
924 }
925
926 if (n != 0)
927 udelay(50);
928
929 if (i8042_command(&ctr[n++ % 2], I8042_CMD_CTL_RCTR)) {
930 pr_err("Can't read CTR while initializing i8042\n");
931 return -EIO;
932 }
933
934 } while (n < 2 || ctr[0] != ctr[1]);
935
936 i8042_initial_ctr = i8042_ctr = ctr[0];
937
938
939
940
941
942 i8042_ctr |= I8042_CTR_KBDDIS;
943 i8042_ctr &= ~I8042_CTR_KBDINT;
944
945
946
947
948
949 spin_lock_irqsave(&i8042_lock, flags);
950 if (~i8042_read_status() & I8042_STR_KEYLOCK) {
951 if (i8042_unlock)
952 i8042_ctr |= I8042_CTR_IGNKEYLOCK;
953 else
954 pr_warn("Warning: Keylock active\n");
955 }
956 spin_unlock_irqrestore(&i8042_lock, flags);
957
958
959
960
961
962
963 if (~i8042_ctr & I8042_CTR_XLATE)
964 i8042_direct = true;
965
966
967
968
969
970
971
972
973 if (i8042_direct)
974 i8042_ctr &= ~I8042_CTR_XLATE;
975
976
977
978
979
980 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
981 pr_err("Can't write CTR while initializing i8042\n");
982 return -EIO;
983 }
984
985
986
987
988
989 i8042_flush();
990
991 return 0;
992}
993
994
995
996
997
998
999static void i8042_controller_reset(bool force_reset)
1000{
1001 i8042_flush();
1002
1003
1004
1005
1006
1007 i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS;
1008 i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT);
1009
1010 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
1011 pr_warn("Can't write CTR while resetting\n");
1012
1013
1014
1015
1016
1017 if (i8042_mux_present)
1018 i8042_set_mux_mode(false, NULL);
1019
1020
1021
1022
1023
1024 if (i8042_reset || force_reset)
1025 i8042_controller_selftest();
1026
1027
1028
1029
1030
1031 if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR))
1032 pr_warn("Can't restore CTR\n");
1033}
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046#define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0)
1047
1048static long i8042_panic_blink(int state)
1049{
1050 long delay = 0;
1051 char led;
1052
1053 led = (state) ? 0x01 | 0x04 : 0;
1054 while (i8042_read_status() & I8042_STR_IBF)
1055 DELAY;
1056 dbg("%02x -> i8042 (panic blink)\n", 0xed);
1057 i8042_suppress_kbd_ack = 2;
1058 i8042_write_data(0xed);
1059 DELAY;
1060 while (i8042_read_status() & I8042_STR_IBF)
1061 DELAY;
1062 DELAY;
1063 dbg("%02x -> i8042 (panic blink)\n", led);
1064 i8042_write_data(led);
1065 DELAY;
1066 return delay;
1067}
1068
1069#undef DELAY
1070
1071#ifdef CONFIG_X86
1072static void i8042_dritek_enable(void)
1073{
1074 unsigned char param = 0x90;
1075 int error;
1076
1077 error = i8042_command(¶m, 0x1059);
1078 if (error)
1079 pr_warn("Failed to enable DRITEK extension: %d\n", error);
1080}
1081#endif
1082
1083#ifdef CONFIG_PM
1084
1085
1086
1087
1088
1089
1090static int i8042_controller_resume(bool force_reset)
1091{
1092 int error;
1093
1094 error = i8042_controller_check();
1095 if (error)
1096 return error;
1097
1098 if (i8042_reset || force_reset) {
1099 error = i8042_controller_selftest();
1100 if (error)
1101 return error;
1102 }
1103
1104
1105
1106
1107
1108 i8042_ctr = i8042_initial_ctr;
1109 if (i8042_direct)
1110 i8042_ctr &= ~I8042_CTR_XLATE;
1111 i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS;
1112 i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT);
1113 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
1114 pr_warn("Can't write CTR to resume, retrying...\n");
1115 msleep(50);
1116 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
1117 pr_err("CTR write retry failed\n");
1118 return -EIO;
1119 }
1120 }
1121
1122
1123#ifdef CONFIG_X86
1124 if (i8042_dritek)
1125 i8042_dritek_enable();
1126#endif
1127
1128 if (i8042_mux_present) {
1129 if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports())
1130 pr_warn("failed to resume active multiplexor, mouse won't work\n");
1131 } else if (i8042_ports[I8042_AUX_PORT_NO].serio)
1132 i8042_enable_aux_port();
1133
1134 if (i8042_ports[I8042_KBD_PORT_NO].serio)
1135 i8042_enable_kbd_port();
1136
1137 i8042_interrupt(0, NULL);
1138
1139 return 0;
1140}
1141
1142
1143
1144
1145
1146
1147static int i8042_pm_suspend(struct device *dev)
1148{
1149 i8042_controller_reset(true);
1150
1151 return 0;
1152}
1153
1154static int i8042_pm_resume(struct device *dev)
1155{
1156
1157
1158
1159
1160
1161 return i8042_controller_resume(true);
1162}
1163
1164static int i8042_pm_thaw(struct device *dev)
1165{
1166 i8042_interrupt(0, NULL);
1167
1168 return 0;
1169}
1170
1171static int i8042_pm_reset(struct device *dev)
1172{
1173 i8042_controller_reset(false);
1174
1175 return 0;
1176}
1177
1178static int i8042_pm_restore(struct device *dev)
1179{
1180 return i8042_controller_resume(false);
1181}
1182
1183static const struct dev_pm_ops i8042_pm_ops = {
1184 .suspend = i8042_pm_suspend,
1185 .resume = i8042_pm_resume,
1186 .thaw = i8042_pm_thaw,
1187 .poweroff = i8042_pm_reset,
1188 .restore = i8042_pm_restore,
1189};
1190
1191#endif
1192
1193
1194
1195
1196
1197
1198static void i8042_shutdown(struct platform_device *dev)
1199{
1200 i8042_controller_reset(false);
1201}
1202
1203static int __init i8042_create_kbd_port(void)
1204{
1205 struct serio *serio;
1206 struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO];
1207
1208 serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
1209 if (!serio)
1210 return -ENOMEM;
1211
1212 serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL;
1213 serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write;
1214 serio->start = i8042_start;
1215 serio->stop = i8042_stop;
1216 serio->close = i8042_port_close;
1217 serio->port_data = port;
1218 serio->dev.parent = &i8042_platform_device->dev;
1219 strlcpy(serio->name, "i8042 KBD port", sizeof(serio->name));
1220 strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys));
1221
1222 port->serio = serio;
1223 port->irq = I8042_KBD_IRQ;
1224
1225 return 0;
1226}
1227
1228static int __init i8042_create_aux_port(int idx)
1229{
1230 struct serio *serio;
1231 int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx;
1232 struct i8042_port *port = &i8042_ports[port_no];
1233
1234 serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
1235 if (!serio)
1236 return -ENOMEM;
1237
1238 serio->id.type = SERIO_8042;
1239 serio->write = i8042_aux_write;
1240 serio->start = i8042_start;
1241 serio->stop = i8042_stop;
1242 serio->port_data = port;
1243 serio->dev.parent = &i8042_platform_device->dev;
1244 if (idx < 0) {
1245 strlcpy(serio->name, "i8042 AUX port", sizeof(serio->name));
1246 strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys));
1247 serio->close = i8042_port_close;
1248 } else {
1249 snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx);
1250 snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1);
1251 }
1252
1253 port->serio = serio;
1254 port->mux = idx;
1255 port->irq = I8042_AUX_IRQ;
1256
1257 return 0;
1258}
1259
1260static void __init i8042_free_kbd_port(void)
1261{
1262 kfree(i8042_ports[I8042_KBD_PORT_NO].serio);
1263 i8042_ports[I8042_KBD_PORT_NO].serio = NULL;
1264}
1265
1266static void __init i8042_free_aux_ports(void)
1267{
1268 int i;
1269
1270 for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) {
1271 kfree(i8042_ports[i].serio);
1272 i8042_ports[i].serio = NULL;
1273 }
1274}
1275
1276static void __init i8042_register_ports(void)
1277{
1278 int i;
1279
1280 for (i = 0; i < I8042_NUM_PORTS; i++) {
1281 if (i8042_ports[i].serio) {
1282 printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n",
1283 i8042_ports[i].serio->name,
1284 (unsigned long) I8042_DATA_REG,
1285 (unsigned long) I8042_COMMAND_REG,
1286 i8042_ports[i].irq);
1287 serio_register_port(i8042_ports[i].serio);
1288 }
1289 }
1290}
1291
1292static void i8042_unregister_ports(void)
1293{
1294 int i;
1295
1296 for (i = 0; i < I8042_NUM_PORTS; i++) {
1297 if (i8042_ports[i].serio) {
1298 serio_unregister_port(i8042_ports[i].serio);
1299 i8042_ports[i].serio = NULL;
1300 }
1301 }
1302}
1303
1304
1305
1306
1307bool i8042_check_port_owner(const struct serio *port)
1308{
1309 int i;
1310
1311 for (i = 0; i < I8042_NUM_PORTS; i++)
1312 if (i8042_ports[i].serio == port)
1313 return true;
1314
1315 return false;
1316}
1317EXPORT_SYMBOL(i8042_check_port_owner);
1318
1319static void i8042_free_irqs(void)
1320{
1321 if (i8042_aux_irq_registered)
1322 free_irq(I8042_AUX_IRQ, i8042_platform_device);
1323 if (i8042_kbd_irq_registered)
1324 free_irq(I8042_KBD_IRQ, i8042_platform_device);
1325
1326 i8042_aux_irq_registered = i8042_kbd_irq_registered = false;
1327}
1328
1329static int __init i8042_setup_aux(void)
1330{
1331 int (*aux_enable)(void);
1332 int error;
1333 int i;
1334
1335 if (i8042_check_aux())
1336 return -ENODEV;
1337
1338 if (i8042_nomux || i8042_check_mux()) {
1339 error = i8042_create_aux_port(-1);
1340 if (error)
1341 goto err_free_ports;
1342 aux_enable = i8042_enable_aux_port;
1343 } else {
1344 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) {
1345 error = i8042_create_aux_port(i);
1346 if (error)
1347 goto err_free_ports;
1348 }
1349 aux_enable = i8042_enable_mux_ports;
1350 }
1351
1352 error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED,
1353 "i8042", i8042_platform_device);
1354 if (error)
1355 goto err_free_ports;
1356
1357 if (aux_enable())
1358 goto err_free_irq;
1359
1360 i8042_aux_irq_registered = true;
1361 return 0;
1362
1363 err_free_irq:
1364 free_irq(I8042_AUX_IRQ, i8042_platform_device);
1365 err_free_ports:
1366 i8042_free_aux_ports();
1367 return error;
1368}
1369
1370static int __init i8042_setup_kbd(void)
1371{
1372 int error;
1373
1374 error = i8042_create_kbd_port();
1375 if (error)
1376 return error;
1377
1378 error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED,
1379 "i8042", i8042_platform_device);
1380 if (error)
1381 goto err_free_port;
1382
1383 error = i8042_enable_kbd_port();
1384 if (error)
1385 goto err_free_irq;
1386
1387 i8042_kbd_irq_registered = true;
1388 return 0;
1389
1390 err_free_irq:
1391 free_irq(I8042_KBD_IRQ, i8042_platform_device);
1392 err_free_port:
1393 i8042_free_kbd_port();
1394 return error;
1395}
1396
1397static int __init i8042_probe(struct platform_device *dev)
1398{
1399 int error;
1400
1401 i8042_platform_device = dev;
1402
1403 if (i8042_reset) {
1404 error = i8042_controller_selftest();
1405 if (error)
1406 return error;
1407 }
1408
1409 error = i8042_controller_init();
1410 if (error)
1411 return error;
1412
1413#ifdef CONFIG_X86
1414 if (i8042_dritek)
1415 i8042_dritek_enable();
1416#endif
1417
1418 if (!i8042_noaux) {
1419 error = i8042_setup_aux();
1420 if (error && error != -ENODEV && error != -EBUSY)
1421 goto out_fail;
1422 }
1423
1424 if (!i8042_nokbd) {
1425 error = i8042_setup_kbd();
1426 if (error)
1427 goto out_fail;
1428 }
1429
1430
1431
1432 i8042_register_ports();
1433
1434 return 0;
1435
1436 out_fail:
1437 i8042_free_aux_ports();
1438 i8042_free_irqs();
1439 i8042_controller_reset(false);
1440 i8042_platform_device = NULL;
1441
1442 return error;
1443}
1444
1445static int i8042_remove(struct platform_device *dev)
1446{
1447 i8042_unregister_ports();
1448 i8042_free_irqs();
1449 i8042_controller_reset(false);
1450 i8042_platform_device = NULL;
1451
1452 return 0;
1453}
1454
1455static struct platform_driver i8042_driver = {
1456 .driver = {
1457 .name = "i8042",
1458 .owner = THIS_MODULE,
1459#ifdef CONFIG_PM
1460 .pm = &i8042_pm_ops,
1461#endif
1462 },
1463 .remove = i8042_remove,
1464 .shutdown = i8042_shutdown,
1465};
1466
1467static int __init i8042_init(void)
1468{
1469 struct platform_device *pdev;
1470 int err;
1471
1472 dbg_init();
1473
1474 err = i8042_platform_init();
1475 if (err)
1476 return err;
1477
1478 err = i8042_controller_check();
1479 if (err)
1480 goto err_platform_exit;
1481
1482 pdev = platform_create_bundle(&i8042_driver, i8042_probe, NULL, 0, NULL, 0);
1483 if (IS_ERR(pdev)) {
1484 err = PTR_ERR(pdev);
1485 goto err_platform_exit;
1486 }
1487
1488 panic_blink = i8042_panic_blink;
1489
1490 return 0;
1491
1492 err_platform_exit:
1493 i8042_platform_exit();
1494 return err;
1495}
1496
1497static void __exit i8042_exit(void)
1498{
1499 platform_device_unregister(i8042_platform_device);
1500 platform_driver_unregister(&i8042_driver);
1501 i8042_platform_exit();
1502
1503 panic_blink = NULL;
1504}
1505
1506module_init(i8042_init);
1507module_exit(i8042_exit);
1508