1/* 2 Auvitek AU8522 QAM/8VSB demodulator driver 3 4 Copyright (C) 2008 Steven Toth <stoth@linuxtv.org> 5 Copyright (C) 2008 Devin Heitmueller <dheitmueller@linuxtv.org> 6 Copyright (C) 2005-2008 Auvitek International, Ltd. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 22*/ 23 24#include <linux/kernel.h> 25#include <linux/init.h> 26#include <linux/module.h> 27#include <linux/string.h> 28#include <linux/slab.h> 29#include <linux/delay.h> 30#include <linux/videodev2.h> 31#include <media/v4l2-device.h> 32#include <media/v4l2-ctrls.h> 33#include <linux/i2c.h> 34#include "dvb_frontend.h" 35#include "au8522.h" 36#include "tuner-i2c.h" 37 38#define AU8522_ANALOG_MODE 0 39#define AU8522_DIGITAL_MODE 1 40 41struct au8522_state { 42 struct i2c_client *c; 43 struct i2c_adapter *i2c; 44 45 u8 operational_mode; 46 47 /* Used for sharing of the state between analog and digital mode */ 48 struct tuner_i2c_props i2c_props; 49 struct list_head hybrid_tuner_instance_list; 50 51 /* configuration settings */ 52 const struct au8522_config *config; 53 54 struct dvb_frontend frontend; 55 56 u32 current_frequency; 57 fe_modulation_t current_modulation; 58 59 u32 fe_status; 60 unsigned int led_state; 61 62 /* Analog settings */ 63 struct v4l2_subdev sd; 64 v4l2_std_id std; 65 int vid_input; 66 int aud_input; 67 u32 id; 68 u32 rev; 69 struct v4l2_ctrl_handler hdl; 70}; 71 72/* These are routines shared by both the VSB/QAM demodulator and the analog 73 decoder */ 74int au8522_writereg(struct au8522_state *state, u16 reg, u8 data); 75u8 au8522_readreg(struct au8522_state *state, u16 reg); 76int au8522_init(struct dvb_frontend *fe); 77int au8522_sleep(struct dvb_frontend *fe); 78 79int au8522_get_state(struct au8522_state **state, struct i2c_adapter *i2c, 80 u8 client_address); 81void au8522_release_state(struct au8522_state *state); 82int au8522_i2c_gate_ctrl(struct dvb_frontend *fe, int enable); 83int au8522_analog_i2c_gate_ctrl(struct dvb_frontend *fe, int enable); 84int au8522_led_ctrl(struct au8522_state *state, int led); 85 86/* REGISTERS */ 87#define AU8522_INPUT_CONTROL_REG081H 0x081 88#define AU8522_PGA_CONTROL_REG082H 0x082 89#define AU8522_CLAMPING_CONTROL_REG083H 0x083 90 91#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H 0x0A3 92#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H 0x0A4 93#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H 0x0A5 94#define AU8522_AGC_CONTROL_RANGE_REG0A6H 0x0A6 95#define AU8522_SYSTEM_GAIN_CONTROL_REG0A7H 0x0A7 96#define AU8522_TUNER_AGC_RF_STOP_REG0A8H 0x0A8 97#define AU8522_TUNER_AGC_RF_START_REG0A9H 0x0A9 98#define AU8522_TUNER_RF_AGC_DEFAULT_REG0AAH 0x0AA 99#define AU8522_TUNER_AGC_IF_STOP_REG0ABH 0x0AB 100#define AU8522_TUNER_AGC_IF_START_REG0ACH 0x0AC 101#define AU8522_TUNER_AGC_IF_DEFAULT_REG0ADH 0x0AD 102#define AU8522_TUNER_AGC_STEP_REG0AEH 0x0AE 103#define AU8522_TUNER_GAIN_STEP_REG0AFH 0x0AF 104 105/* Receiver registers */ 106#define AU8522_FRMREGTHRD1_REG0B0H 0x0B0 107#define AU8522_FRMREGAGC1H_REG0B1H 0x0B1 108#define AU8522_FRMREGSHIFT1_REG0B2H 0x0B2 109#define AU8522_TOREGAGC1_REG0B3H 0x0B3 110#define AU8522_TOREGASHIFT1_REG0B4H 0x0B4 111#define AU8522_FRMREGBBH_REG0B5H 0x0B5 112#define AU8522_FRMREGBBM_REG0B6H 0x0B6 113#define AU8522_FRMREGBBL_REG0B7H 0x0B7 114/* 0xB8 TO 0xD7 are the filter coefficients */ 115#define AU8522_FRMREGTHRD2_REG0D8H 0x0D8 116#define AU8522_FRMREGAGC2H_REG0D9H 0x0D9 117#define AU8522_TOREGAGC2_REG0DAH 0x0DA 118#define AU8522_TOREGSHIFT2_REG0DBH 0x0DB 119#define AU8522_FRMREGPILOTH_REG0DCH 0x0DC 120#define AU8522_FRMREGPILOTM_REG0DDH 0x0DD 121#define AU8522_FRMREGPILOTL_REG0DEH 0x0DE 122#define AU8522_TOREGFREQ_REG0DFH 0x0DF 123 124#define AU8522_RX_PGA_RFOUT_REG0EBH 0x0EB 125#define AU8522_RX_PGA_IFOUT_REG0ECH 0x0EC 126#define AU8522_RX_PGA_PGAOUT_REG0EDH 0x0ED 127 128#define AU8522_CHIP_MODE_REG0FEH 0x0FE 129 130/* I2C bus control registers */ 131#define AU8522_I2C_CONTROL_REG0_REG090H 0x090 132#define AU8522_I2C_CONTROL_REG1_REG091H 0x091 133#define AU8522_I2C_STATUS_REG092H 0x092 134#define AU8522_I2C_WR_DATA0_REG093H 0x093 135#define AU8522_I2C_WR_DATA1_REG094H 0x094 136#define AU8522_I2C_WR_DATA2_REG095H 0x095 137#define AU8522_I2C_WR_DATA3_REG096H 0x096 138#define AU8522_I2C_WR_DATA4_REG097H 0x097 139#define AU8522_I2C_WR_DATA5_REG098H 0x098 140#define AU8522_I2C_WR_DATA6_REG099H 0x099 141#define AU8522_I2C_WR_DATA7_REG09AH 0x09A 142#define AU8522_I2C_RD_DATA0_REG09BH 0x09B 143#define AU8522_I2C_RD_DATA1_REG09CH 0x09C 144#define AU8522_I2C_RD_DATA2_REG09DH 0x09D 145#define AU8522_I2C_RD_DATA3_REG09EH 0x09E 146#define AU8522_I2C_RD_DATA4_REG09FH 0x09F 147#define AU8522_I2C_RD_DATA5_REG0A0H 0x0A0 148#define AU8522_I2C_RD_DATA6_REG0A1H 0x0A1 149#define AU8522_I2C_RD_DATA7_REG0A2H 0x0A2 150 151#define AU8522_ENA_USB_REG101H 0x101 152 153#define AU8522_I2S_CTRL_0_REG110H 0x110 154#define AU8522_I2S_CTRL_1_REG111H 0x111 155#define AU8522_I2S_CTRL_2_REG112H 0x112 156 157#define AU8522_FRMREGFFECONTROL_REG121H 0x121 158#define AU8522_FRMREGDFECONTROL_REG122H 0x122 159 160#define AU8522_CARRFREQOFFSET0_REG201H 0x201 161#define AU8522_CARRFREQOFFSET1_REG202H 0x202 162 163#define AU8522_DECIMATION_GAIN_REG21AH 0x21A 164#define AU8522_FRMREGIFSLP_REG21BH 0x21B 165#define AU8522_FRMREGTHRDL2_REG21CH 0x21C 166#define AU8522_FRMREGSTEP3DB_REG21DH 0x21D 167#define AU8522_DAGC_GAIN_ADJUSTMENT_REG21EH 0x21E 168#define AU8522_FRMREGPLLMODE_REG21FH 0x21F 169#define AU8522_FRMREGCSTHRD_REG220H 0x220 170#define AU8522_FRMREGCRLOCKDMAX_REG221H 0x221 171#define AU8522_FRMREGCRPERIODMASK_REG222H 0x222 172#define AU8522_FRMREGCRLOCK0THH_REG223H 0x223 173#define AU8522_FRMREGCRLOCK1THH_REG224H 0x224 174#define AU8522_FRMREGCRLOCK0THL_REG225H 0x225 175#define AU8522_FRMREGCRLOCK1THL_REG226H 0x226 176#define AU_FRMREGPLLACQPHASESCL_REG227H 0x227 177#define AU8522_FRMREGFREQFBCTRL_REG228H 0x228 178 179/* Analog TV Decoder */ 180#define AU8522_TVDEC_STATUS_REG000H 0x000 181#define AU8522_TVDEC_INT_STATUS_REG001H 0x001 182#define AU8522_TVDEC_MACROVISION_STATUS_REG002H 0x002 183#define AU8522_TVDEC_SHARPNESSREG009H 0x009 184#define AU8522_TVDEC_BRIGHTNESS_REG00AH 0x00A 185#define AU8522_TVDEC_CONTRAST_REG00BH 0x00B 186#define AU8522_TVDEC_SATURATION_CB_REG00CH 0x00C 187#define AU8522_TVDEC_SATURATION_CR_REG00DH 0x00D 188#define AU8522_TVDEC_HUE_H_REG00EH 0x00E 189#define AU8522_TVDEC_HUE_L_REG00FH 0x00F 190#define AU8522_TVDEC_INT_MASK_REG010H 0x010 191#define AU8522_VIDEO_MODE_REG011H 0x011 192#define AU8522_TVDEC_PGA_REG012H 0x012 193#define AU8522_TVDEC_COMB_MODE_REG015H 0x015 194#define AU8522_REG016H 0x016 195#define AU8522_TVDED_DBG_MODE_REG060H 0x060 196#define AU8522_TVDEC_FORMAT_CTRL1_REG061H 0x061 197#define AU8522_TVDEC_FORMAT_CTRL2_REG062H 0x062 198#define AU8522_TVDEC_VCR_DET_LLIM_REG063H 0x063 199#define AU8522_TVDEC_VCR_DET_HLIM_REG064H 0x064 200#define AU8522_TVDEC_COMB_VDIF_THR1_REG065H 0x065 201#define AU8522_TVDEC_COMB_VDIF_THR2_REG066H 0x066 202#define AU8522_TVDEC_COMB_VDIF_THR3_REG067H 0x067 203#define AU8522_TVDEC_COMB_NOTCH_THR_REG068H 0x068 204#define AU8522_TVDEC_COMB_HDIF_THR1_REG069H 0x069 205#define AU8522_TVDEC_COMB_HDIF_THR2_REG06AH 0x06A 206#define AU8522_TVDEC_COMB_HDIF_THR3_REG06BH 0x06B 207#define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH 0x06C 208#define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH 0x06D 209#define AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH 0x06E 210#define AU8522_TVDEC_UV_SEP_THR_REG06FH 0x06F 211#define AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H 0x070 212#define AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H 0x073 213#define AU8522_TVDEC_DCAGC_CTRL_REG077H 0x077 214#define AU8522_TVDEC_PIC_START_ADJ_REG078H 0x078 215#define AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H 0x079 216#define AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH 0x07A 217#define AU8522_TVDEC_INTRP_CTRL_REG07BH 0x07B 218#define AU8522_TVDEC_PLL_STATUS_REG07EH 0x07E 219#define AU8522_TVDEC_FSC_FREQ_REG07FH 0x07F 220 221#define AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H 0x0E4 222#define AU8522_TOREGAAGC_REG0E5H 0x0E5 223 224#define AU8522_TVDEC_CHROMA_AGC_REG401H 0x401 225#define AU8522_TVDEC_CHROMA_SFT_REG402H 0x402 226#define AU8522_FILTER_COEF_R410 0x410 227#define AU8522_FILTER_COEF_R411 0x411 228#define AU8522_FILTER_COEF_R412 0x412 229#define AU8522_FILTER_COEF_R413 0x413 230#define AU8522_FILTER_COEF_R414 0x414 231#define AU8522_FILTER_COEF_R415 0x415 232#define AU8522_FILTER_COEF_R416 0x416 233#define AU8522_FILTER_COEF_R417 0x417 234#define AU8522_FILTER_COEF_R418 0x418 235#define AU8522_FILTER_COEF_R419 0x419 236#define AU8522_FILTER_COEF_R41A 0x41A 237#define AU8522_FILTER_COEF_R41B 0x41B 238#define AU8522_FILTER_COEF_R41C 0x41C 239#define AU8522_FILTER_COEF_R41D 0x41D 240#define AU8522_FILTER_COEF_R41E 0x41E 241#define AU8522_FILTER_COEF_R41F 0x41F 242#define AU8522_FILTER_COEF_R420 0x420 243#define AU8522_FILTER_COEF_R421 0x421 244#define AU8522_FILTER_COEF_R422 0x422 245#define AU8522_FILTER_COEF_R423 0x423 246#define AU8522_FILTER_COEF_R424 0x424 247#define AU8522_FILTER_COEF_R425 0x425 248#define AU8522_FILTER_COEF_R426 0x426 249#define AU8522_FILTER_COEF_R427 0x427 250#define AU8522_FILTER_COEF_R428 0x428 251#define AU8522_FILTER_COEF_R429 0x429 252#define AU8522_FILTER_COEF_R42A 0x42A 253#define AU8522_FILTER_COEF_R42B 0x42B 254#define AU8522_FILTER_COEF_R42C 0x42C 255#define AU8522_FILTER_COEF_R42D 0x42D 256 257/* VBI Control Registers */ 258#define AU8522_TVDEC_VBI_RX_FIFO_CONTAIN_REG004H 0x004 259#define AU8522_TVDEC_VBI_TX_FIFO_CONTAIN_REG005H 0x005 260#define AU8522_TVDEC_VBI_RX_FIFO_READ_REG006H 0x006 261#define AU8522_TVDEC_VBI_FIFO_STATUS_REG007H 0x007 262#define AU8522_TVDEC_VBI_CTRL_H_REG017H 0x017 263#define AU8522_TVDEC_VBI_CTRL_L_REG018H 0x018 264#define AU8522_TVDEC_VBI_USER_TOTAL_BITS_REG019H 0x019 265#define AU8522_TVDEC_VBI_USER_TUNIT_H_REG01AH 0x01A 266#define AU8522_TVDEC_VBI_USER_TUNIT_L_REG01BH 0x01B 267#define AU8522_TVDEC_VBI_USER_THRESH1_REG01CH 0x01C 268#define AU8522_TVDEC_VBI_USER_FRAME_PAT2_REG01EH 0x01E 269#define AU8522_TVDEC_VBI_USER_FRAME_PAT1_REG01FH 0x01F 270#define AU8522_TVDEC_VBI_USER_FRAME_PAT0_REG020H 0x020 271#define AU8522_TVDEC_VBI_USER_FRAME_MASK2_REG021H 0x021 272#define AU8522_TVDEC_VBI_USER_FRAME_MASK1_REG022H 0x022 273#define AU8522_TVDEC_VBI_USER_FRAME_MASK0_REG023H 0x023 274 275#define AU8522_REG071H 0x071 276#define AU8522_REG072H 0x072 277#define AU8522_REG074H 0x074 278#define AU8522_REG075H 0x075 279 280/* Digital Demodulator Registers */ 281#define AU8522_FRAME_COUNT0_REG084H 0x084 282#define AU8522_RS_STATUS_G0_REG085H 0x085 283#define AU8522_RS_STATUS_B0_REG086H 0x086 284#define AU8522_RS_STATUS_E_REG087H 0x087 285#define AU8522_DEMODULATION_STATUS_REG088H 0x088 286#define AU8522_TOREGTRESTATUS_REG0E6H 0x0E6 287#define AU8522_TSPORT_CONTROL_REG10BH 0x10B 288#define AU8522_TSTHES_REG10CH 0x10C 289#define AU8522_FRMREGDFEKEEP_REG301H 0x301 290#define AU8522_DFE_AVERAGE_REG302H 0x302 291#define AU8522_FRMREGEQLERRWIN_REG303H 0x303 292#define AU8522_FRMREGFFEKEEP_REG304H 0x304 293#define AU8522_FRMREGDFECONTROL1_REG305H 0x305 294#define AU8522_FRMREGEQLERRLOW_REG306H 0x306 295 296#define AU8522_REG42EH 0x42E 297#define AU8522_REG42FH 0x42F 298#define AU8522_REG430H 0x430 299#define AU8522_REG431H 0x431 300#define AU8522_REG432H 0x432 301#define AU8522_REG433H 0x433 302#define AU8522_REG434H 0x434 303#define AU8522_REG435H 0x435 304#define AU8522_REG436H 0x436 305 306/* GPIO Registers */ 307#define AU8522_GPIO_CONTROL_REG0E0H 0x0E0 308#define AU8522_GPIO_STATUS_REG0E1H 0x0E1 309#define AU8522_GPIO_DATA_REG0E2H 0x0E2 310 311/* Audio Control Registers */ 312#define AU8522_AUDIOAGC_REG0EEH 0x0EE 313#define AU8522_AUDIO_STATUS_REG0F0H 0x0F0 314#define AU8522_AUDIO_MODE_REG0F1H 0x0F1 315#define AU8522_AUDIO_VOLUME_L_REG0F2H 0x0F2 316#define AU8522_AUDIO_VOLUME_R_REG0F3H 0x0F3 317#define AU8522_AUDIO_VOLUME_REG0F4H 0x0F4 318#define AU8522_FRMREGAUPHASE_REG0F7H 0x0F7 319#define AU8522_REG0F9H 0x0F9 320 321#define AU8522_AUDIOAGC2_REG605H 0x605 322#define AU8522_AUDIOFREQ_REG606H 0x606 323 324 325/**************************************************************/ 326 327/* Format control 1 */ 328 329/* VCR Mode 7-6 */ 330#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_VCR_MODE_YES 0x80 331#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_VCR_MODE_NO 0x40 332#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_VCR_MODE_AUTO 0x00 333/* Field len 5-4 */ 334#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_625 0x20 335#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_525 0x10 336#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_AUTO 0x00 337/* Line len (us) 3-2 */ 338#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_64_000 0x0b 339#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_492 0x08 340#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_556 0x04 341/* Subcarrier freq 1-0 */ 342#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_AUTO 0x03 343#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_443 0x02 344#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_MN 0x01 345#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_50 0x00 346 347/* Format control 2 */ 348#define AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_AUTODETECT 0x00 349#define AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_NTSC 0x01 350 351 352#define AU8522_INPUT_CONTROL_REG081H_ATSC 0xC4 353#define AU8522_INPUT_CONTROL_REG081H_ATVRF 0xC4 354#define AU8522_INPUT_CONTROL_REG081H_ATVRF13 0xC4 355#define AU8522_INPUT_CONTROL_REG081H_J83B64 0xC4 356#define AU8522_INPUT_CONTROL_REG081H_J83B256 0xC4 357#define AU8522_INPUT_CONTROL_REG081H_CVBS 0x20 358#define AU8522_INPUT_CONTROL_REG081H_CVBS_CH1 0xA2 359#define AU8522_INPUT_CONTROL_REG081H_CVBS_CH2 0xA0 360#define AU8522_INPUT_CONTROL_REG081H_CVBS_CH3 0x69 361#define AU8522_INPUT_CONTROL_REG081H_CVBS_CH4 0x68 362#define AU8522_INPUT_CONTROL_REG081H_CVBS_CH4_SIF 0x28 363/* CH1 AS Y,CH3 AS C */ 364#define AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13 0x23 365/* CH2 AS Y,CH4 AS C */ 366#define AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24 0x20 367#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATSC 0x0C 368#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_J83B64 0x09 369#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_J83B256 0x09 370#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS 0x12 371#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATVRF 0x1A 372#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATVRF13 0x1A 373#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_SVIDEO 0x02 374 375#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CLEAR 0x00 376#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_SVIDEO 0x9C 377#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS 0x9D 378#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATSC 0xE8 379#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_J83B256 0xCA 380#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_J83B64 0xCA 381#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATVRF 0xDD 382#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATVRF13 0xDD 383#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_PAL 0xDD 384#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_FM 0xDD 385 386#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATSC 0x80 387#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_J83B256 0x80 388#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_J83B64 0x80 389#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_ATSC 0x40 390#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_J83B256 0x40 391#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_J83B64 0x40 392#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_CLEAR 0x00 393#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATVRF 0x01 394#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATVRF13 0x01 395#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_SVIDEO 0x04 396#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_CVBS 0x01 397#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_PWM 0x03 398#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_IIS 0x09 399#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_PAL 0x01 400#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_FM 0x01 401 402/* STILL NEED TO BE REFACTORED @@@@@@@@@@@@@@ */ 403#define AU8522_TVDEC_CONTRAST_REG00BH_CVBS 0x79 404#define AU8522_TVDEC_SATURATION_CB_REG00CH_CVBS 0x80 405#define AU8522_TVDEC_SATURATION_CR_REG00DH_CVBS 0x80 406#define AU8522_TVDEC_HUE_H_REG00EH_CVBS 0x00 407#define AU8522_TVDEC_HUE_L_REG00FH_CVBS 0x00 408#define AU8522_TVDEC_PGA_REG012H_CVBS 0x0F 409#define AU8522_TVDEC_COMB_MODE_REG015H_CVBS 0x00 410#define AU8522_REG016H_CVBS 0x00 411#define AU8522_TVDED_DBG_MODE_REG060H_CVBS 0x00 412#define AU8522_TVDEC_VCR_DET_LLIM_REG063H_CVBS 0x19 413#define AU8522_REG0F9H_AUDIO 0x20 414#define AU8522_TVDEC_VCR_DET_HLIM_REG064H_CVBS 0xA7 415#define AU8522_TVDEC_COMB_VDIF_THR1_REG065H_CVBS 0x0A 416#define AU8522_TVDEC_COMB_VDIF_THR2_REG066H_CVBS 0x32 417#define AU8522_TVDEC_COMB_VDIF_THR3_REG067H_CVBS 0x19 418#define AU8522_TVDEC_COMB_NOTCH_THR_REG068H_CVBS 0x23 419#define AU8522_TVDEC_COMB_HDIF_THR1_REG069H_CVBS 0x41 420#define AU8522_TVDEC_COMB_HDIF_THR2_REG06AH_CVBS 0x0A 421#define AU8522_TVDEC_COMB_HDIF_THR3_REG06BH_CVBS 0x32 422#define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS 0x34 423#define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_SVIDEO 0x2a 424#define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS 0x05 425#define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_SVIDEO 0x15 426#define AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH_CVBS 0x6E 427#define AU8522_TVDEC_UV_SEP_THR_REG06FH_CVBS 0x0F 428#define AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H_CVBS 0x80 429#define AU8522_REG071H_CVBS 0x18 430#define AU8522_REG072H_CVBS 0x30 431#define AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H_CVBS 0xF0 432#define AU8522_REG074H_CVBS 0x80 433#define AU8522_REG075H_CVBS 0xF0 434#define AU8522_TVDEC_DCAGC_CTRL_REG077H_CVBS 0xFB 435#define AU8522_TVDEC_PIC_START_ADJ_REG078H_CVBS 0x04 436#define AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H_CVBS 0x00 437#define AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH_CVBS 0x00 438#define AU8522_TVDEC_INTRP_CTRL_REG07BH_CVBS 0xEE 439#define AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H_CVBS 0xFE 440#define AU8522_TOREGAAGC_REG0E5H_CVBS 0x00 441#define AU8522_TVDEC_VBI6A_REG035H_CVBS 0x40 442 443/* Enables Closed captioning */ 444#define AU8522_TVDEC_VBI_CTRL_H_REG017H_CCON 0x21 445