linux/drivers/media/dvb-frontends/stv0297.c
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   1/*
   2    Driver for STV0297 demodulator
   3
   4    Copyright (C) 2004 Andrew de Quincey <adq_dvb@lidskialf.net>
   5    Copyright (C) 2003-2004 Dennis Noermann <dennis.noermann@noernet.de>
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; if not, write to the Free Software
  19    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20*/
  21
  22#include <linux/init.h>
  23#include <linux/kernel.h>
  24#include <linux/module.h>
  25#include <linux/string.h>
  26#include <linux/delay.h>
  27#include <linux/jiffies.h>
  28#include <linux/slab.h>
  29
  30#include "dvb_frontend.h"
  31#include "stv0297.h"
  32
  33struct stv0297_state {
  34        struct i2c_adapter *i2c;
  35        const struct stv0297_config *config;
  36        struct dvb_frontend frontend;
  37
  38        unsigned long last_ber;
  39        unsigned long base_freq;
  40};
  41
  42#if 1
  43#define dprintk(x...) printk(x)
  44#else
  45#define dprintk(x...)
  46#endif
  47
  48#define STV0297_CLOCK_KHZ   28900
  49
  50
  51static int stv0297_writereg(struct stv0297_state *state, u8 reg, u8 data)
  52{
  53        int ret;
  54        u8 buf[] = { reg, data };
  55        struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 2 };
  56
  57        ret = i2c_transfer(state->i2c, &msg, 1);
  58
  59        if (ret != 1)
  60                dprintk("%s: writereg error (reg == 0x%02x, val == 0x%02x, "
  61                        "ret == %i)\n", __func__, reg, data, ret);
  62
  63        return (ret != 1) ? -1 : 0;
  64}
  65
  66static int stv0297_readreg(struct stv0297_state *state, u8 reg)
  67{
  68        int ret;
  69        u8 b0[] = { reg };
  70        u8 b1[] = { 0 };
  71        struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf = b0,.len = 1},
  72                                 {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1}
  73                               };
  74
  75        // this device needs a STOP between the register and data
  76        if (state->config->stop_during_read) {
  77                if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) {
  78                        dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg, ret);
  79                        return -1;
  80                }
  81                if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) {
  82                        dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg, ret);
  83                        return -1;
  84                }
  85        } else {
  86                if ((ret = i2c_transfer(state->i2c, msg, 2)) != 2) {
  87                        dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg, ret);
  88                        return -1;
  89                }
  90        }
  91
  92        return b1[0];
  93}
  94
  95static int stv0297_writereg_mask(struct stv0297_state *state, u8 reg, u8 mask, u8 data)
  96{
  97        int val;
  98
  99        val = stv0297_readreg(state, reg);
 100        val &= ~mask;
 101        val |= (data & mask);
 102        stv0297_writereg(state, reg, val);
 103
 104        return 0;
 105}
 106
 107static int stv0297_readregs(struct stv0297_state *state, u8 reg1, u8 * b, u8 len)
 108{
 109        int ret;
 110        struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf =
 111                                  &reg1,.len = 1},
 112        {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b,.len = len}
 113        };
 114
 115        // this device needs a STOP between the register and data
 116        if (state->config->stop_during_read) {
 117                if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) {
 118                        dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret);
 119                        return -1;
 120                }
 121                if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) {
 122                        dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret);
 123                        return -1;
 124                }
 125        } else {
 126                if ((ret = i2c_transfer(state->i2c, msg, 2)) != 2) {
 127                        dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret);
 128                        return -1;
 129                }
 130        }
 131
 132        return 0;
 133}
 134
 135static u32 stv0297_get_symbolrate(struct stv0297_state *state)
 136{
 137        u64 tmp;
 138
 139        tmp = stv0297_readreg(state, 0x55);
 140        tmp |= stv0297_readreg(state, 0x56) << 8;
 141        tmp |= stv0297_readreg(state, 0x57) << 16;
 142        tmp |= stv0297_readreg(state, 0x58) << 24;
 143
 144        tmp *= STV0297_CLOCK_KHZ;
 145        tmp >>= 32;
 146
 147        return (u32) tmp;
 148}
 149
 150static void stv0297_set_symbolrate(struct stv0297_state *state, u32 srate)
 151{
 152        long tmp;
 153
 154        tmp = 131072L * srate;  /* 131072 = 2^17  */
 155        tmp = tmp / (STV0297_CLOCK_KHZ / 4);    /* 1/4 = 2^-2 */
 156        tmp = tmp * 8192L;      /* 8192 = 2^13 */
 157
 158        stv0297_writereg(state, 0x55, (unsigned char) (tmp & 0xFF));
 159        stv0297_writereg(state, 0x56, (unsigned char) (tmp >> 8));
 160        stv0297_writereg(state, 0x57, (unsigned char) (tmp >> 16));
 161        stv0297_writereg(state, 0x58, (unsigned char) (tmp >> 24));
 162}
 163
 164static void stv0297_set_sweeprate(struct stv0297_state *state, short fshift, long symrate)
 165{
 166        long tmp;
 167
 168        tmp = (long) fshift *262144L;   /* 262144 = 2*18 */
 169        tmp /= symrate;
 170        tmp *= 1024;            /* 1024 = 2*10   */
 171
 172        // adjust
 173        if (tmp >= 0) {
 174                tmp += 500000;
 175        } else {
 176                tmp -= 500000;
 177        }
 178        tmp /= 1000000;
 179
 180        stv0297_writereg(state, 0x60, tmp & 0xFF);
 181        stv0297_writereg_mask(state, 0x69, 0xF0, (tmp >> 4) & 0xf0);
 182}
 183
 184static void stv0297_set_carrieroffset(struct stv0297_state *state, long offset)
 185{
 186        long tmp;
 187
 188        /* symrate is hardcoded to 10000 */
 189        tmp = offset * 26844L;  /* (2**28)/10000 */
 190        if (tmp < 0)
 191                tmp += 0x10000000;
 192        tmp &= 0x0FFFFFFF;
 193
 194        stv0297_writereg(state, 0x66, (unsigned char) (tmp & 0xFF));
 195        stv0297_writereg(state, 0x67, (unsigned char) (tmp >> 8));
 196        stv0297_writereg(state, 0x68, (unsigned char) (tmp >> 16));
 197        stv0297_writereg_mask(state, 0x69, 0x0F, (tmp >> 24) & 0x0f);
 198}
 199
 200/*
 201static long stv0297_get_carrieroffset(struct stv0297_state *state)
 202{
 203        s64 tmp;
 204
 205        stv0297_writereg(state, 0x6B, 0x00);
 206
 207        tmp = stv0297_readreg(state, 0x66);
 208        tmp |= (stv0297_readreg(state, 0x67) << 8);
 209        tmp |= (stv0297_readreg(state, 0x68) << 16);
 210        tmp |= (stv0297_readreg(state, 0x69) & 0x0F) << 24;
 211
 212        tmp *= stv0297_get_symbolrate(state);
 213        tmp >>= 28;
 214
 215        return (s32) tmp;
 216}
 217*/
 218
 219static void stv0297_set_initialdemodfreq(struct stv0297_state *state, long freq)
 220{
 221        s32 tmp;
 222
 223        if (freq > 10000)
 224                freq -= STV0297_CLOCK_KHZ;
 225
 226        tmp = (STV0297_CLOCK_KHZ * 1000) / (1 << 16);
 227        tmp = (freq * 1000) / tmp;
 228        if (tmp > 0xffff)
 229                tmp = 0xffff;
 230
 231        stv0297_writereg_mask(state, 0x25, 0x80, 0x80);
 232        stv0297_writereg(state, 0x21, tmp >> 8);
 233        stv0297_writereg(state, 0x20, tmp);
 234}
 235
 236static int stv0297_set_qam(struct stv0297_state *state, fe_modulation_t modulation)
 237{
 238        int val = 0;
 239
 240        switch (modulation) {
 241        case QAM_16:
 242                val = 0;
 243                break;
 244
 245        case QAM_32:
 246                val = 1;
 247                break;
 248
 249        case QAM_64:
 250                val = 4;
 251                break;
 252
 253        case QAM_128:
 254                val = 2;
 255                break;
 256
 257        case QAM_256:
 258                val = 3;
 259                break;
 260
 261        default:
 262                return -EINVAL;
 263        }
 264
 265        stv0297_writereg_mask(state, 0x00, 0x70, val << 4);
 266
 267        return 0;
 268}
 269
 270static int stv0297_set_inversion(struct stv0297_state *state, fe_spectral_inversion_t inversion)
 271{
 272        int val = 0;
 273
 274        switch (inversion) {
 275        case INVERSION_OFF:
 276                val = 0;
 277                break;
 278
 279        case INVERSION_ON:
 280                val = 1;
 281                break;
 282
 283        default:
 284                return -EINVAL;
 285        }
 286
 287        stv0297_writereg_mask(state, 0x83, 0x08, val << 3);
 288
 289        return 0;
 290}
 291
 292static int stv0297_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
 293{
 294        struct stv0297_state *state = fe->demodulator_priv;
 295
 296        if (enable) {
 297                stv0297_writereg(state, 0x87, 0x78);
 298                stv0297_writereg(state, 0x86, 0xc8);
 299        }
 300
 301        return 0;
 302}
 303
 304static int stv0297_init(struct dvb_frontend *fe)
 305{
 306        struct stv0297_state *state = fe->demodulator_priv;
 307        int i;
 308
 309        /* load init table */
 310        for (i=0; !(state->config->inittab[i] == 0xff && state->config->inittab[i+1] == 0xff); i+=2)
 311                stv0297_writereg(state, state->config->inittab[i], state->config->inittab[i+1]);
 312        msleep(200);
 313
 314        state->last_ber = 0;
 315
 316        return 0;
 317}
 318
 319static int stv0297_sleep(struct dvb_frontend *fe)
 320{
 321        struct stv0297_state *state = fe->demodulator_priv;
 322
 323        stv0297_writereg_mask(state, 0x80, 1, 1);
 324
 325        return 0;
 326}
 327
 328static int stv0297_read_status(struct dvb_frontend *fe, fe_status_t * status)
 329{
 330        struct stv0297_state *state = fe->demodulator_priv;
 331
 332        u8 sync = stv0297_readreg(state, 0xDF);
 333
 334        *status = 0;
 335        if (sync & 0x80)
 336                *status |=
 337                        FE_HAS_SYNC | FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_LOCK;
 338        return 0;
 339}
 340
 341static int stv0297_read_ber(struct dvb_frontend *fe, u32 * ber)
 342{
 343        struct stv0297_state *state = fe->demodulator_priv;
 344        u8 BER[3];
 345
 346        stv0297_readregs(state, 0xA0, BER, 3);
 347        if (!(BER[0] & 0x80)) {
 348                state->last_ber = BER[2] << 8 | BER[1];
 349                stv0297_writereg_mask(state, 0xA0, 0x80, 0x80);
 350        }
 351
 352        *ber = state->last_ber;
 353
 354        return 0;
 355}
 356
 357
 358static int stv0297_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
 359{
 360        struct stv0297_state *state = fe->demodulator_priv;
 361        u8 STRENGTH[3];
 362        u16 tmp;
 363
 364        stv0297_readregs(state, 0x41, STRENGTH, 3);
 365        tmp = (STRENGTH[1] & 0x03) << 8 | STRENGTH[0];
 366        if (STRENGTH[2] & 0x20) {
 367                if (tmp < 0x200)
 368                        tmp = 0;
 369                else
 370                        tmp = tmp - 0x200;
 371        } else {
 372                if (tmp > 0x1ff)
 373                        tmp = 0;
 374                else
 375                        tmp = 0x1ff - tmp;
 376        }
 377        *strength = (tmp << 7) | (tmp >> 2);
 378        return 0;
 379}
 380
 381static int stv0297_read_snr(struct dvb_frontend *fe, u16 * snr)
 382{
 383        struct stv0297_state *state = fe->demodulator_priv;
 384        u8 SNR[2];
 385
 386        stv0297_readregs(state, 0x07, SNR, 2);
 387        *snr = SNR[1] << 8 | SNR[0];
 388
 389        return 0;
 390}
 391
 392static int stv0297_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
 393{
 394        struct stv0297_state *state = fe->demodulator_priv;
 395
 396        stv0297_writereg_mask(state, 0xDF, 0x03, 0x03); /* freeze the counters */
 397
 398        *ucblocks = (stv0297_readreg(state, 0xD5) << 8)
 399                | stv0297_readreg(state, 0xD4);
 400
 401        stv0297_writereg_mask(state, 0xDF, 0x03, 0x02); /* clear the counters */
 402        stv0297_writereg_mask(state, 0xDF, 0x03, 0x01); /* re-enable the counters */
 403
 404        return 0;
 405}
 406
 407static int stv0297_set_frontend(struct dvb_frontend *fe)
 408{
 409        struct dtv_frontend_properties *p = &fe->dtv_property_cache;
 410        struct stv0297_state *state = fe->demodulator_priv;
 411        int u_threshold;
 412        int initial_u;
 413        int blind_u;
 414        int delay;
 415        int sweeprate;
 416        int carrieroffset;
 417        unsigned long timeout;
 418        fe_spectral_inversion_t inversion;
 419
 420        switch (p->modulation) {
 421        case QAM_16:
 422        case QAM_32:
 423        case QAM_64:
 424                delay = 100;
 425                sweeprate = 1000;
 426                break;
 427
 428        case QAM_128:
 429        case QAM_256:
 430                delay = 200;
 431                sweeprate = 500;
 432                break;
 433
 434        default:
 435                return -EINVAL;
 436        }
 437
 438        // determine inversion dependent parameters
 439        inversion = p->inversion;
 440        if (state->config->invert)
 441                inversion = (inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;
 442        carrieroffset = -330;
 443        switch (inversion) {
 444        case INVERSION_OFF:
 445                break;
 446
 447        case INVERSION_ON:
 448                sweeprate = -sweeprate;
 449                carrieroffset = -carrieroffset;
 450                break;
 451
 452        default:
 453                return -EINVAL;
 454        }
 455
 456        stv0297_init(fe);
 457        if (fe->ops.tuner_ops.set_params) {
 458                fe->ops.tuner_ops.set_params(fe);
 459                if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
 460        }
 461
 462        /* clear software interrupts */
 463        stv0297_writereg(state, 0x82, 0x0);
 464
 465        /* set initial demodulation frequency */
 466        stv0297_set_initialdemodfreq(state, 7250);
 467
 468        /* setup AGC */
 469        stv0297_writereg_mask(state, 0x43, 0x10, 0x00);
 470        stv0297_writereg(state, 0x41, 0x00);
 471        stv0297_writereg_mask(state, 0x42, 0x03, 0x01);
 472        stv0297_writereg_mask(state, 0x36, 0x60, 0x00);
 473        stv0297_writereg_mask(state, 0x36, 0x18, 0x00);
 474        stv0297_writereg_mask(state, 0x71, 0x80, 0x80);
 475        stv0297_writereg(state, 0x72, 0x00);
 476        stv0297_writereg(state, 0x73, 0x00);
 477        stv0297_writereg_mask(state, 0x74, 0x0F, 0x00);
 478        stv0297_writereg_mask(state, 0x43, 0x08, 0x00);
 479        stv0297_writereg_mask(state, 0x71, 0x80, 0x00);
 480
 481        /* setup STL */
 482        stv0297_writereg_mask(state, 0x5a, 0x20, 0x20);
 483        stv0297_writereg_mask(state, 0x5b, 0x02, 0x02);
 484        stv0297_writereg_mask(state, 0x5b, 0x02, 0x00);
 485        stv0297_writereg_mask(state, 0x5b, 0x01, 0x00);
 486        stv0297_writereg_mask(state, 0x5a, 0x40, 0x40);
 487
 488        /* disable frequency sweep */
 489        stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);
 490
 491        /* reset deinterleaver */
 492        stv0297_writereg_mask(state, 0x81, 0x01, 0x01);
 493        stv0297_writereg_mask(state, 0x81, 0x01, 0x00);
 494
 495        /* ??? */
 496        stv0297_writereg_mask(state, 0x83, 0x20, 0x20);
 497        stv0297_writereg_mask(state, 0x83, 0x20, 0x00);
 498
 499        /* reset equaliser */
 500        u_threshold = stv0297_readreg(state, 0x00) & 0xf;
 501        initial_u = stv0297_readreg(state, 0x01) >> 4;
 502        blind_u = stv0297_readreg(state, 0x01) & 0xf;
 503        stv0297_writereg_mask(state, 0x84, 0x01, 0x01);
 504        stv0297_writereg_mask(state, 0x84, 0x01, 0x00);
 505        stv0297_writereg_mask(state, 0x00, 0x0f, u_threshold);
 506        stv0297_writereg_mask(state, 0x01, 0xf0, initial_u << 4);
 507        stv0297_writereg_mask(state, 0x01, 0x0f, blind_u);
 508
 509        /* data comes from internal A/D */
 510        stv0297_writereg_mask(state, 0x87, 0x80, 0x00);
 511
 512        /* clear phase registers */
 513        stv0297_writereg(state, 0x63, 0x00);
 514        stv0297_writereg(state, 0x64, 0x00);
 515        stv0297_writereg(state, 0x65, 0x00);
 516        stv0297_writereg(state, 0x66, 0x00);
 517        stv0297_writereg(state, 0x67, 0x00);
 518        stv0297_writereg(state, 0x68, 0x00);
 519        stv0297_writereg_mask(state, 0x69, 0x0f, 0x00);
 520
 521        /* set parameters */
 522        stv0297_set_qam(state, p->modulation);
 523        stv0297_set_symbolrate(state, p->symbol_rate / 1000);
 524        stv0297_set_sweeprate(state, sweeprate, p->symbol_rate / 1000);
 525        stv0297_set_carrieroffset(state, carrieroffset);
 526        stv0297_set_inversion(state, inversion);
 527
 528        /* kick off lock */
 529        /* Disable corner detection for higher QAMs */
 530        if (p->modulation == QAM_128 ||
 531                p->modulation == QAM_256)
 532                stv0297_writereg_mask(state, 0x88, 0x08, 0x00);
 533        else
 534                stv0297_writereg_mask(state, 0x88, 0x08, 0x08);
 535
 536        stv0297_writereg_mask(state, 0x5a, 0x20, 0x00);
 537        stv0297_writereg_mask(state, 0x6a, 0x01, 0x01);
 538        stv0297_writereg_mask(state, 0x43, 0x40, 0x40);
 539        stv0297_writereg_mask(state, 0x5b, 0x30, 0x00);
 540        stv0297_writereg_mask(state, 0x03, 0x0c, 0x0c);
 541        stv0297_writereg_mask(state, 0x03, 0x03, 0x03);
 542        stv0297_writereg_mask(state, 0x43, 0x10, 0x10);
 543
 544        /* wait for WGAGC lock */
 545        timeout = jiffies + msecs_to_jiffies(2000);
 546        while (time_before(jiffies, timeout)) {
 547                msleep(10);
 548                if (stv0297_readreg(state, 0x43) & 0x08)
 549                        break;
 550        }
 551        if (time_after(jiffies, timeout)) {
 552                goto timeout;
 553        }
 554        msleep(20);
 555
 556        /* wait for equaliser partial convergence */
 557        timeout = jiffies + msecs_to_jiffies(500);
 558        while (time_before(jiffies, timeout)) {
 559                msleep(10);
 560
 561                if (stv0297_readreg(state, 0x82) & 0x04) {
 562                        break;
 563                }
 564        }
 565        if (time_after(jiffies, timeout)) {
 566                goto timeout;
 567        }
 568
 569        /* wait for equaliser full convergence */
 570        timeout = jiffies + msecs_to_jiffies(delay);
 571        while (time_before(jiffies, timeout)) {
 572                msleep(10);
 573
 574                if (stv0297_readreg(state, 0x82) & 0x08) {
 575                        break;
 576                }
 577        }
 578        if (time_after(jiffies, timeout)) {
 579                goto timeout;
 580        }
 581
 582        /* disable sweep */
 583        stv0297_writereg_mask(state, 0x6a, 1, 0);
 584        stv0297_writereg_mask(state, 0x88, 8, 0);
 585
 586        /* wait for main lock */
 587        timeout = jiffies + msecs_to_jiffies(20);
 588        while (time_before(jiffies, timeout)) {
 589                msleep(10);
 590
 591                if (stv0297_readreg(state, 0xDF) & 0x80) {
 592                        break;
 593                }
 594        }
 595        if (time_after(jiffies, timeout)) {
 596                goto timeout;
 597        }
 598        msleep(100);
 599
 600        /* is it still locked after that delay? */
 601        if (!(stv0297_readreg(state, 0xDF) & 0x80)) {
 602                goto timeout;
 603        }
 604
 605        /* success!! */
 606        stv0297_writereg_mask(state, 0x5a, 0x40, 0x00);
 607        state->base_freq = p->frequency;
 608        return 0;
 609
 610timeout:
 611        stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);
 612        return 0;
 613}
 614
 615static int stv0297_get_frontend(struct dvb_frontend *fe)
 616{
 617        struct dtv_frontend_properties *p = &fe->dtv_property_cache;
 618        struct stv0297_state *state = fe->demodulator_priv;
 619        int reg_00, reg_83;
 620
 621        reg_00 = stv0297_readreg(state, 0x00);
 622        reg_83 = stv0297_readreg(state, 0x83);
 623
 624        p->frequency = state->base_freq;
 625        p->inversion = (reg_83 & 0x08) ? INVERSION_ON : INVERSION_OFF;
 626        if (state->config->invert)
 627                p->inversion = (p->inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;
 628        p->symbol_rate = stv0297_get_symbolrate(state) * 1000;
 629        p->fec_inner = FEC_NONE;
 630
 631        switch ((reg_00 >> 4) & 0x7) {
 632        case 0:
 633                p->modulation = QAM_16;
 634                break;
 635        case 1:
 636                p->modulation = QAM_32;
 637                break;
 638        case 2:
 639                p->modulation = QAM_128;
 640                break;
 641        case 3:
 642                p->modulation = QAM_256;
 643                break;
 644        case 4:
 645                p->modulation = QAM_64;
 646                break;
 647        }
 648
 649        return 0;
 650}
 651
 652static void stv0297_release(struct dvb_frontend *fe)
 653{
 654        struct stv0297_state *state = fe->demodulator_priv;
 655        kfree(state);
 656}
 657
 658static struct dvb_frontend_ops stv0297_ops;
 659
 660struct dvb_frontend *stv0297_attach(const struct stv0297_config *config,
 661                                    struct i2c_adapter *i2c)
 662{
 663        struct stv0297_state *state = NULL;
 664
 665        /* allocate memory for the internal state */
 666        state = kzalloc(sizeof(struct stv0297_state), GFP_KERNEL);
 667        if (state == NULL)
 668                goto error;
 669
 670        /* setup the state */
 671        state->config = config;
 672        state->i2c = i2c;
 673        state->last_ber = 0;
 674        state->base_freq = 0;
 675
 676        /* check if the demod is there */
 677        if ((stv0297_readreg(state, 0x80) & 0x70) != 0x20)
 678                goto error;
 679
 680        /* create dvb_frontend */
 681        memcpy(&state->frontend.ops, &stv0297_ops, sizeof(struct dvb_frontend_ops));
 682        state->frontend.demodulator_priv = state;
 683        return &state->frontend;
 684
 685error:
 686        kfree(state);
 687        return NULL;
 688}
 689
 690static struct dvb_frontend_ops stv0297_ops = {
 691        .delsys = { SYS_DVBC_ANNEX_A },
 692        .info = {
 693                 .name = "ST STV0297 DVB-C",
 694                 .frequency_min = 47000000,
 695                 .frequency_max = 862000000,
 696                 .frequency_stepsize = 62500,
 697                 .symbol_rate_min = 870000,
 698                 .symbol_rate_max = 11700000,
 699                 .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
 700                 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO},
 701
 702        .release = stv0297_release,
 703
 704        .init = stv0297_init,
 705        .sleep = stv0297_sleep,
 706        .i2c_gate_ctrl = stv0297_i2c_gate_ctrl,
 707
 708        .set_frontend = stv0297_set_frontend,
 709        .get_frontend = stv0297_get_frontend,
 710
 711        .read_status = stv0297_read_status,
 712        .read_ber = stv0297_read_ber,
 713        .read_signal_strength = stv0297_read_signal_strength,
 714        .read_snr = stv0297_read_snr,
 715        .read_ucblocks = stv0297_read_ucblocks,
 716};
 717
 718MODULE_DESCRIPTION("ST STV0297 DVB-C Demodulator driver");
 719MODULE_AUTHOR("Dennis Noermann and Andrew de Quincey");
 720MODULE_LICENSE("GPL");
 721
 722EXPORT_SYMBOL(stv0297_attach);
 723
Hosted by Missing Link Electronics. The original LXR software by the LXR community, this experimental version by lxr@linux.no.