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25#include "cx18-driver.h"
26#include "cx18-io.h"
27#include "cx18-fileops.h"
28#include "cx18-mailbox.h"
29#include "cx18-i2c.h"
30#include "cx18-queue.h"
31#include "cx18-ioctl.h"
32#include "cx18-streams.h"
33#include "cx18-cards.h"
34#include "cx18-scb.h"
35#include "cx18-dvb.h"
36
37#define CX18_DSP0_INTERRUPT_MASK 0xd0004C
38
39static struct v4l2_file_operations cx18_v4l2_enc_fops = {
40 .owner = THIS_MODULE,
41 .read = cx18_v4l2_read,
42 .open = cx18_v4l2_open,
43 .unlocked_ioctl = video_ioctl2,
44 .release = cx18_v4l2_close,
45 .poll = cx18_v4l2_enc_poll,
46 .mmap = cx18_v4l2_mmap,
47};
48
49
50#define CX18_V4L2_ENC_TS_OFFSET 16
51
52#define CX18_V4L2_ENC_PCM_OFFSET 24
53
54#define CX18_V4L2_ENC_YUV_OFFSET 32
55
56static struct {
57 const char *name;
58 int vfl_type;
59 int num_offset;
60 int dma;
61} cx18_stream_info[] = {
62 {
63 "encoder MPEG",
64 VFL_TYPE_GRABBER, 0,
65 PCI_DMA_FROMDEVICE,
66 },
67 {
68 "TS",
69 VFL_TYPE_GRABBER, -1,
70 PCI_DMA_FROMDEVICE,
71 },
72 {
73 "encoder YUV",
74 VFL_TYPE_GRABBER, CX18_V4L2_ENC_YUV_OFFSET,
75 PCI_DMA_FROMDEVICE,
76 },
77 {
78 "encoder VBI",
79 VFL_TYPE_VBI, 0,
80 PCI_DMA_FROMDEVICE,
81 },
82 {
83 "encoder PCM audio",
84 VFL_TYPE_GRABBER, CX18_V4L2_ENC_PCM_OFFSET,
85 PCI_DMA_FROMDEVICE,
86 },
87 {
88 "encoder IDX",
89 VFL_TYPE_GRABBER, -1,
90 PCI_DMA_FROMDEVICE,
91 },
92 {
93 "encoder radio",
94 VFL_TYPE_RADIO, 0,
95 PCI_DMA_NONE,
96 },
97};
98
99
100static void cx18_dma_free(struct videobuf_queue *q,
101 struct cx18_stream *s, struct cx18_videobuf_buffer *buf)
102{
103 videobuf_waiton(q, &buf->vb, 0, 0);
104 videobuf_vmalloc_free(&buf->vb);
105 buf->vb.state = VIDEOBUF_NEEDS_INIT;
106}
107
108static int cx18_prepare_buffer(struct videobuf_queue *q,
109 struct cx18_stream *s,
110 struct cx18_videobuf_buffer *buf,
111 u32 pixelformat,
112 unsigned int width, unsigned int height,
113 enum v4l2_field field)
114{
115 struct cx18 *cx = s->cx;
116 int rc = 0;
117
118
119 buf->bytes_used = 0;
120
121 if ((width < 48) || (height < 32))
122 return -EINVAL;
123
124 buf->vb.size = (width * height * 2);
125 if ((buf->vb.baddr != 0) && (buf->vb.bsize < buf->vb.size))
126 return -EINVAL;
127
128
129 if (buf->vb.width != width || buf->vb.height != height ||
130 buf->vb.field != field || s->pixelformat != pixelformat ||
131 buf->tvnorm != cx->std) {
132
133 buf->vb.width = width;
134 buf->vb.height = height;
135 buf->vb.field = field;
136 buf->tvnorm = cx->std;
137 s->pixelformat = pixelformat;
138
139
140
141 if (s->pixelformat == V4L2_PIX_FMT_HM12)
142 s->vb_bytes_per_frame = height * 720 * 3 / 2;
143 else
144 s->vb_bytes_per_frame = height * 720 * 2;
145 cx18_dma_free(q, s, buf);
146 }
147
148 if ((buf->vb.baddr != 0) && (buf->vb.bsize < buf->vb.size))
149 return -EINVAL;
150
151 if (buf->vb.field == 0)
152 buf->vb.field = V4L2_FIELD_INTERLACED;
153
154 if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
155 buf->vb.width = width;
156 buf->vb.height = height;
157 buf->vb.field = field;
158 buf->tvnorm = cx->std;
159 s->pixelformat = pixelformat;
160
161
162
163 if (s->pixelformat == V4L2_PIX_FMT_HM12)
164 s->vb_bytes_per_frame = height * 720 * 3 / 2;
165 else
166 s->vb_bytes_per_frame = height * 720 * 2;
167 rc = videobuf_iolock(q, &buf->vb, NULL);
168 if (rc != 0)
169 goto fail;
170 }
171 buf->vb.state = VIDEOBUF_PREPARED;
172 return 0;
173
174fail:
175 cx18_dma_free(q, s, buf);
176 return rc;
177
178}
179
180
181
182
183#define VB_MIN_BUFFERS 32
184#define VB_MIN_BUFSIZE 4147200
185
186static int buffer_setup(struct videobuf_queue *q,
187 unsigned int *count, unsigned int *size)
188{
189 struct cx18_stream *s = q->priv_data;
190 struct cx18 *cx = s->cx;
191
192 *size = 2 * cx->cxhdl.width * cx->cxhdl.height;
193 if (*count == 0)
194 *count = VB_MIN_BUFFERS;
195
196 while (*size * *count > VB_MIN_BUFFERS * VB_MIN_BUFSIZE)
197 (*count)--;
198
199 q->field = V4L2_FIELD_INTERLACED;
200 q->last = V4L2_FIELD_INTERLACED;
201
202 return 0;
203}
204
205static int buffer_prepare(struct videobuf_queue *q,
206 struct videobuf_buffer *vb,
207 enum v4l2_field field)
208{
209 struct cx18_videobuf_buffer *buf =
210 container_of(vb, struct cx18_videobuf_buffer, vb);
211 struct cx18_stream *s = q->priv_data;
212 struct cx18 *cx = s->cx;
213
214 return cx18_prepare_buffer(q, s, buf, s->pixelformat,
215 cx->cxhdl.width, cx->cxhdl.height, field);
216}
217
218static void buffer_release(struct videobuf_queue *q,
219 struct videobuf_buffer *vb)
220{
221 struct cx18_videobuf_buffer *buf =
222 container_of(vb, struct cx18_videobuf_buffer, vb);
223 struct cx18_stream *s = q->priv_data;
224
225 cx18_dma_free(q, s, buf);
226}
227
228static void buffer_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
229{
230 struct cx18_videobuf_buffer *buf =
231 container_of(vb, struct cx18_videobuf_buffer, vb);
232 struct cx18_stream *s = q->priv_data;
233
234 buf->vb.state = VIDEOBUF_QUEUED;
235
236 list_add_tail(&buf->vb.queue, &s->vb_capture);
237}
238
239static struct videobuf_queue_ops cx18_videobuf_qops = {
240 .buf_setup = buffer_setup,
241 .buf_prepare = buffer_prepare,
242 .buf_queue = buffer_queue,
243 .buf_release = buffer_release,
244};
245
246static void cx18_stream_init(struct cx18 *cx, int type)
247{
248 struct cx18_stream *s = &cx->streams[type];
249 struct video_device *video_dev = s->video_dev;
250
251
252 memset(s, 0, sizeof(*s));
253 s->video_dev = video_dev;
254
255
256 s->dvb = NULL;
257 s->cx = cx;
258 s->type = type;
259 s->name = cx18_stream_info[type].name;
260 s->handle = CX18_INVALID_TASK_HANDLE;
261
262 s->dma = cx18_stream_info[type].dma;
263 s->buffers = cx->stream_buffers[type];
264 s->buf_size = cx->stream_buf_size[type];
265 INIT_LIST_HEAD(&s->buf_pool);
266 s->bufs_per_mdl = 1;
267 s->mdl_size = s->buf_size * s->bufs_per_mdl;
268
269 init_waitqueue_head(&s->waitq);
270 s->id = -1;
271 spin_lock_init(&s->q_free.lock);
272 cx18_queue_init(&s->q_free);
273 spin_lock_init(&s->q_busy.lock);
274 cx18_queue_init(&s->q_busy);
275 spin_lock_init(&s->q_full.lock);
276 cx18_queue_init(&s->q_full);
277 spin_lock_init(&s->q_idle.lock);
278 cx18_queue_init(&s->q_idle);
279
280 INIT_WORK(&s->out_work_order, cx18_out_work_handler);
281
282 INIT_LIST_HEAD(&s->vb_capture);
283 s->vb_timeout.function = cx18_vb_timeout;
284 s->vb_timeout.data = (unsigned long)s;
285 init_timer(&s->vb_timeout);
286 spin_lock_init(&s->vb_lock);
287 if (type == CX18_ENC_STREAM_TYPE_YUV) {
288 spin_lock_init(&s->vbuf_q_lock);
289
290 s->vb_type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
291 videobuf_queue_vmalloc_init(&s->vbuf_q, &cx18_videobuf_qops,
292 &cx->pci_dev->dev, &s->vbuf_q_lock,
293 V4L2_BUF_TYPE_VIDEO_CAPTURE,
294 V4L2_FIELD_INTERLACED,
295 sizeof(struct cx18_videobuf_buffer),
296 s, &cx->serialize_lock);
297
298
299 s->pixelformat = V4L2_PIX_FMT_HM12;
300 s->vb_bytes_per_frame = cx->cxhdl.height * 720 * 3 / 2;
301 }
302}
303
304static int cx18_prep_dev(struct cx18 *cx, int type)
305{
306 struct cx18_stream *s = &cx->streams[type];
307 u32 cap = cx->v4l2_cap;
308 int num_offset = cx18_stream_info[type].num_offset;
309 int num = cx->instance + cx18_first_minor + num_offset;
310
311
312
313
314
315
316
317
318 s->video_dev = NULL;
319 s->dvb = NULL;
320 s->cx = cx;
321 s->type = type;
322 s->name = cx18_stream_info[type].name;
323
324
325 if (type == CX18_ENC_STREAM_TYPE_RAD && !(cap & V4L2_CAP_RADIO))
326 return 0;
327
328
329 if (type == CX18_ENC_STREAM_TYPE_VBI &&
330 !(cap & (V4L2_CAP_VBI_CAPTURE | V4L2_CAP_SLICED_VBI_CAPTURE)))
331 return 0;
332
333
334
335 if (cx18_stream_info[type].dma != PCI_DMA_NONE &&
336 cx->stream_buffers[type] == 0) {
337 CX18_INFO("Disabled %s device\n", cx18_stream_info[type].name);
338 return 0;
339 }
340
341 cx18_stream_init(cx, type);
342
343
344 if (type == CX18_ENC_STREAM_TYPE_TS) {
345 if (cx->card->hw_all & CX18_HW_DVB) {
346 s->dvb = kzalloc(sizeof(struct cx18_dvb), GFP_KERNEL);
347 if (s->dvb == NULL) {
348 CX18_ERR("Couldn't allocate cx18_dvb structure"
349 " for %s\n", s->name);
350 return -ENOMEM;
351 }
352 } else {
353
354 s->buffers = 0;
355 }
356 }
357
358 if (num_offset == -1)
359 return 0;
360
361
362 s->video_dev = video_device_alloc();
363 if (s->video_dev == NULL) {
364 CX18_ERR("Couldn't allocate v4l2 video_device for %s\n",
365 s->name);
366 return -ENOMEM;
367 }
368
369 snprintf(s->video_dev->name, sizeof(s->video_dev->name), "%s %s",
370 cx->v4l2_dev.name, s->name);
371
372 s->video_dev->num = num;
373 s->video_dev->v4l2_dev = &cx->v4l2_dev;
374 s->video_dev->fops = &cx18_v4l2_enc_fops;
375 s->video_dev->release = video_device_release;
376 s->video_dev->tvnorms = V4L2_STD_ALL;
377 s->video_dev->lock = &cx->serialize_lock;
378 set_bit(V4L2_FL_USE_FH_PRIO, &s->video_dev->flags);
379 cx18_set_funcs(s->video_dev);
380 return 0;
381}
382
383
384int cx18_streams_setup(struct cx18 *cx)
385{
386 int type, ret;
387
388
389 for (type = 0; type < CX18_MAX_STREAMS; type++) {
390
391 ret = cx18_prep_dev(cx, type);
392 if (ret < 0)
393 break;
394
395
396 ret = cx18_stream_alloc(&cx->streams[type]);
397 if (ret < 0)
398 break;
399 }
400 if (type == CX18_MAX_STREAMS)
401 return 0;
402
403
404 cx18_streams_cleanup(cx, 0);
405 return ret;
406}
407
408static int cx18_reg_dev(struct cx18 *cx, int type)
409{
410 struct cx18_stream *s = &cx->streams[type];
411 int vfl_type = cx18_stream_info[type].vfl_type;
412 const char *name;
413 int num, ret;
414
415 if (type == CX18_ENC_STREAM_TYPE_TS && s->dvb != NULL) {
416 ret = cx18_dvb_register(s);
417 if (ret < 0) {
418 CX18_ERR("DVB failed to register\n");
419 return ret;
420 }
421 }
422
423 if (s->video_dev == NULL)
424 return 0;
425
426 num = s->video_dev->num;
427
428 if (type != CX18_ENC_STREAM_TYPE_MPG) {
429 struct cx18_stream *s_mpg = &cx->streams[CX18_ENC_STREAM_TYPE_MPG];
430
431 if (s_mpg->video_dev)
432 num = s_mpg->video_dev->num
433 + cx18_stream_info[type].num_offset;
434 }
435 video_set_drvdata(s->video_dev, s);
436
437
438 ret = video_register_device_no_warn(s->video_dev, vfl_type, num);
439 if (ret < 0) {
440 CX18_ERR("Couldn't register v4l2 device for %s (device node number %d)\n",
441 s->name, num);
442 video_device_release(s->video_dev);
443 s->video_dev = NULL;
444 return ret;
445 }
446
447 name = video_device_node_name(s->video_dev);
448
449 switch (vfl_type) {
450 case VFL_TYPE_GRABBER:
451 CX18_INFO("Registered device %s for %s (%d x %d.%02d kB)\n",
452 name, s->name, cx->stream_buffers[type],
453 cx->stream_buf_size[type] / 1024,
454 (cx->stream_buf_size[type] * 100 / 1024) % 100);
455 break;
456
457 case VFL_TYPE_RADIO:
458 CX18_INFO("Registered device %s for %s\n", name, s->name);
459 break;
460
461 case VFL_TYPE_VBI:
462 if (cx->stream_buffers[type])
463 CX18_INFO("Registered device %s for %s "
464 "(%d x %d bytes)\n",
465 name, s->name, cx->stream_buffers[type],
466 cx->stream_buf_size[type]);
467 else
468 CX18_INFO("Registered device %s for %s\n",
469 name, s->name);
470 break;
471 }
472
473 return 0;
474}
475
476
477int cx18_streams_register(struct cx18 *cx)
478{
479 int type;
480 int err;
481 int ret = 0;
482
483
484 for (type = 0; type < CX18_MAX_STREAMS; type++) {
485 err = cx18_reg_dev(cx, type);
486 if (err && ret == 0)
487 ret = err;
488 }
489
490 if (ret == 0)
491 return 0;
492
493
494 cx18_streams_cleanup(cx, 1);
495 return ret;
496}
497
498
499void cx18_streams_cleanup(struct cx18 *cx, int unregister)
500{
501 struct video_device *vdev;
502 int type;
503
504
505 for (type = 0; type < CX18_MAX_STREAMS; type++) {
506
507
508 if (type == CX18_ENC_STREAM_TYPE_TS) {
509 if (cx->streams[type].dvb != NULL) {
510 if (unregister)
511 cx18_dvb_unregister(&cx->streams[type]);
512 kfree(cx->streams[type].dvb);
513 cx->streams[type].dvb = NULL;
514 cx18_stream_free(&cx->streams[type]);
515 }
516 continue;
517 }
518
519
520 if (type == CX18_ENC_STREAM_TYPE_IDX) {
521
522 if (cx->stream_buffers[type] != 0) {
523 cx->stream_buffers[type] = 0;
524
525
526
527
528
529
530 if (cx->streams[type].buffers != 0)
531 cx18_stream_free(&cx->streams[type]);
532 }
533 continue;
534 }
535
536
537 vdev = cx->streams[type].video_dev;
538
539 cx->streams[type].video_dev = NULL;
540 if (vdev == NULL)
541 continue;
542
543 if (type == CX18_ENC_STREAM_TYPE_YUV)
544 videobuf_mmap_free(&cx->streams[type].vbuf_q);
545
546 cx18_stream_free(&cx->streams[type]);
547
548
549 if (unregister)
550 video_unregister_device(vdev);
551 else
552 video_device_release(vdev);
553 }
554}
555
556static void cx18_vbi_setup(struct cx18_stream *s)
557{
558 struct cx18 *cx = s->cx;
559 int raw = cx18_raw_vbi(cx);
560 u32 data[CX2341X_MBOX_MAX_DATA];
561 int lines;
562
563 if (cx->is_60hz) {
564 cx->vbi.count = 12;
565 cx->vbi.start[0] = 10;
566 cx->vbi.start[1] = 273;
567 } else {
568 cx->vbi.count = 18;
569 cx->vbi.start[0] = 6;
570 cx->vbi.start[1] = 318;
571 }
572
573
574 if (raw)
575 v4l2_subdev_call(cx->sd_av, vbi, s_raw_fmt, &cx->vbi.in.fmt.vbi);
576 else
577 v4l2_subdev_call(cx->sd_av, vbi, s_sliced_fmt, &cx->vbi.in.fmt.sliced);
578
579
580
581
582
583
584
585
586
587 if (raw) {
588 lines = cx->vbi.count * 2;
589 } else {
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604 lines = cx->is_60hz ? (21 - 4 + 1) * 2 : (23 - 2 + 1) * 2;
605 }
606
607 data[0] = s->handle;
608
609 data[1] = (lines / 2) | ((lines / 2) << 16);
610
611 data[2] = (raw ? vbi_active_samples
612 : (cx->is_60hz ? vbi_hblank_samples_60Hz
613 : vbi_hblank_samples_50Hz));
614
615
616 data[3] = 1;
617
618
619
620
621 if (raw) {
622
623
624
625
626
627 data[4] = 0x20602060;
628
629
630
631
632
633
634
635 data[5] = 0x307090d0;
636 } else {
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651 data[4] = 0xB0F0B0F0;
652
653
654
655
656
657 data[5] = 0xA0E0A0E0;
658 }
659
660 CX18_DEBUG_INFO("Setup VBI h: %d lines %x bpl %d fr %d %x %x\n",
661 data[0], data[1], data[2], data[3], data[4], data[5]);
662
663 cx18_api(cx, CX18_CPU_SET_RAW_VBI_PARAM, 6, data);
664}
665
666void cx18_stream_rotate_idx_mdls(struct cx18 *cx)
667{
668 struct cx18_stream *s = &cx->streams[CX18_ENC_STREAM_TYPE_IDX];
669 struct cx18_mdl *mdl;
670
671 if (!cx18_stream_enabled(s))
672 return;
673
674
675 if ((atomic_read(&s->q_free.depth) + atomic_read(&s->q_busy.depth)) >=
676 CX18_ENC_STREAM_TYPE_IDX_FW_MDL_MIN)
677 return;
678
679
680 if (atomic_read(&s->q_full.depth) < 2)
681 return;
682
683
684
685
686
687 mdl = cx18_dequeue(s, &s->q_full);
688 if (mdl != NULL)
689 cx18_enqueue(s, mdl, &s->q_free);
690}
691
692static
693struct cx18_queue *_cx18_stream_put_mdl_fw(struct cx18_stream *s,
694 struct cx18_mdl *mdl)
695{
696 struct cx18 *cx = s->cx;
697 struct cx18_queue *q;
698
699
700 if (s->handle == CX18_INVALID_TASK_HANDLE ||
701 test_bit(CX18_F_S_STOPPING, &s->s_flags) ||
702 !test_bit(CX18_F_S_STREAMING, &s->s_flags))
703 return cx18_enqueue(s, mdl, &s->q_free);
704
705 q = cx18_enqueue(s, mdl, &s->q_busy);
706 if (q != &s->q_busy)
707 return q;
708
709 cx18_mdl_sync_for_device(s, mdl);
710 cx18_vapi(cx, CX18_CPU_DE_SET_MDL, 5, s->handle,
711 (void __iomem *) &cx->scb->cpu_mdl[mdl->id] - cx->enc_mem,
712 s->bufs_per_mdl, mdl->id, s->mdl_size);
713 return q;
714}
715
716static
717void _cx18_stream_load_fw_queue(struct cx18_stream *s)
718{
719 struct cx18_queue *q;
720 struct cx18_mdl *mdl;
721
722 if (atomic_read(&s->q_free.depth) == 0 ||
723 atomic_read(&s->q_busy.depth) >= CX18_MAX_FW_MDLS_PER_STREAM)
724 return;
725
726
727 do {
728 mdl = cx18_dequeue(s, &s->q_free);
729 if (mdl == NULL)
730 break;
731 q = _cx18_stream_put_mdl_fw(s, mdl);
732 } while (atomic_read(&s->q_busy.depth) < CX18_MAX_FW_MDLS_PER_STREAM
733 && q == &s->q_busy);
734}
735
736void cx18_out_work_handler(struct work_struct *work)
737{
738 struct cx18_stream *s =
739 container_of(work, struct cx18_stream, out_work_order);
740
741 _cx18_stream_load_fw_queue(s);
742}
743
744static void cx18_stream_configure_mdls(struct cx18_stream *s)
745{
746 cx18_unload_queues(s);
747
748 switch (s->type) {
749 case CX18_ENC_STREAM_TYPE_YUV:
750
751
752
753
754
755 if (s->pixelformat == V4L2_PIX_FMT_HM12)
756 s->mdl_size = 720 * s->cx->cxhdl.height * 3 / 2;
757 else
758 s->mdl_size = 720 * s->cx->cxhdl.height * 2;
759 s->bufs_per_mdl = s->mdl_size / s->buf_size;
760 if (s->mdl_size % s->buf_size)
761 s->bufs_per_mdl++;
762 break;
763 case CX18_ENC_STREAM_TYPE_VBI:
764 s->bufs_per_mdl = 1;
765 if (cx18_raw_vbi(s->cx)) {
766 s->mdl_size = (s->cx->is_60hz ? 12 : 18)
767 * 2 * vbi_active_samples;
768 } else {
769
770
771
772
773
774 s->mdl_size = s->cx->is_60hz
775 ? (21 - 4 + 1) * 2 * vbi_hblank_samples_60Hz
776 : (23 - 2 + 1) * 2 * vbi_hblank_samples_50Hz;
777 }
778 break;
779 default:
780 s->bufs_per_mdl = 1;
781 s->mdl_size = s->buf_size * s->bufs_per_mdl;
782 break;
783 }
784
785 cx18_load_queues(s);
786}
787
788int cx18_start_v4l2_encode_stream(struct cx18_stream *s)
789{
790 u32 data[MAX_MB_ARGUMENTS];
791 struct cx18 *cx = s->cx;
792 int captype = 0;
793 struct cx18_stream *s_idx;
794
795 if (!cx18_stream_enabled(s))
796 return -EINVAL;
797
798 CX18_DEBUG_INFO("Start encoder stream %s\n", s->name);
799
800 switch (s->type) {
801 case CX18_ENC_STREAM_TYPE_MPG:
802 captype = CAPTURE_CHANNEL_TYPE_MPEG;
803 cx->mpg_data_received = cx->vbi_data_inserted = 0;
804 cx->dualwatch_jiffies = jiffies;
805 cx->dualwatch_stereo_mode = v4l2_ctrl_g_ctrl(cx->cxhdl.audio_mode);
806 cx->search_pack_header = 0;
807 break;
808
809 case CX18_ENC_STREAM_TYPE_IDX:
810 captype = CAPTURE_CHANNEL_TYPE_INDEX;
811 break;
812 case CX18_ENC_STREAM_TYPE_TS:
813 captype = CAPTURE_CHANNEL_TYPE_TS;
814 break;
815 case CX18_ENC_STREAM_TYPE_YUV:
816 captype = CAPTURE_CHANNEL_TYPE_YUV;
817 break;
818 case CX18_ENC_STREAM_TYPE_PCM:
819 captype = CAPTURE_CHANNEL_TYPE_PCM;
820 break;
821 case CX18_ENC_STREAM_TYPE_VBI:
822#ifdef CX18_ENCODER_PARSES_SLICED
823 captype = cx18_raw_vbi(cx) ?
824 CAPTURE_CHANNEL_TYPE_VBI : CAPTURE_CHANNEL_TYPE_SLICED_VBI;
825#else
826
827
828
829
830 captype = CAPTURE_CHANNEL_TYPE_VBI;
831#endif
832 cx->vbi.frame = 0;
833 cx->vbi.inserted_frame = 0;
834 memset(cx->vbi.sliced_mpeg_size,
835 0, sizeof(cx->vbi.sliced_mpeg_size));
836 break;
837 default:
838 return -EINVAL;
839 }
840
841
842 clear_bit(CX18_F_S_STREAMOFF, &s->s_flags);
843
844 cx18_vapi_result(cx, data, CX18_CREATE_TASK, 1, CPU_CMD_MASK_CAPTURE);
845 s->handle = data[0];
846 cx18_vapi(cx, CX18_CPU_SET_CHANNEL_TYPE, 2, s->handle, captype);
847
848
849
850
851
852
853
854
855
856
857
858
859 if (captype != CAPTURE_CHANNEL_TYPE_TS) {
860 cx18_vapi(cx, CX18_CPU_SET_VER_CROP_LINE, 2, s->handle, 0);
861 cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 3, s->handle, 3, 1);
862 cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 3, s->handle, 8, 0);
863 cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 3, s->handle, 4, 1);
864
865
866
867
868
869 if (atomic_read(&cx->ana_capturing) == 0)
870 cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 2,
871 s->handle, 12);
872
873
874
875
876
877
878
879 cx18_vapi(cx, CX18_CPU_SET_CAPTURE_LINE_NO, 3,
880 s->handle, 312, 313);
881
882 if (cx->v4l2_cap & V4L2_CAP_VBI_CAPTURE)
883 cx18_vbi_setup(s);
884
885
886
887
888
889
890 s_idx = &cx->streams[CX18_ENC_STREAM_TYPE_IDX];
891 cx18_vapi_result(cx, data, CX18_CPU_SET_INDEXTABLE, 2,
892 s->handle, cx18_stream_enabled(s_idx) ? 7 : 0);
893
894
895 cx->cxhdl.priv = s;
896 cx2341x_handler_setup(&cx->cxhdl);
897
898
899
900
901
902 if (!cx->cxhdl.video_mute &&
903 test_bit(CX18_F_I_RADIO_USER, &cx->i_flags))
904 cx18_vapi(cx, CX18_CPU_SET_VIDEO_MUTE, 2, s->handle,
905 (v4l2_ctrl_g_ctrl(cx->cxhdl.video_mute_yuv) << 8) | 1);
906
907
908
909
910 if (captype == CAPTURE_CHANNEL_TYPE_YUV) {
911 if (s->pixelformat == V4L2_PIX_FMT_UYVY)
912 cx18_vapi(cx, CX18_CPU_SET_VFC_PARAM, 2,
913 s->handle, 1);
914 else
915
916 cx18_vapi(cx, CX18_CPU_SET_VFC_PARAM, 2,
917 s->handle, 0);
918 }
919 }
920
921 if (atomic_read(&cx->tot_capturing) == 0) {
922 cx2341x_handler_set_busy(&cx->cxhdl, 1);
923 clear_bit(CX18_F_I_EOS, &cx->i_flags);
924 cx18_write_reg(cx, 7, CX18_DSP0_INTERRUPT_MASK);
925 }
926
927 cx18_vapi(cx, CX18_CPU_DE_SET_MDL_ACK, 3, s->handle,
928 (void __iomem *)&cx->scb->cpu_mdl_ack[s->type][0] - cx->enc_mem,
929 (void __iomem *)&cx->scb->cpu_mdl_ack[s->type][1] - cx->enc_mem);
930
931
932 cx18_stream_configure_mdls(s);
933 _cx18_stream_load_fw_queue(s);
934
935
936 if (cx18_vapi(cx, CX18_CPU_CAPTURE_START, 1, s->handle)) {
937 CX18_DEBUG_WARN("Error starting capture!\n");
938
939 set_bit(CX18_F_S_STOPPING, &s->s_flags);
940 if (s->type == CX18_ENC_STREAM_TYPE_MPG)
941 cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 2, s->handle, 1);
942 else
943 cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 1, s->handle);
944 clear_bit(CX18_F_S_STREAMING, &s->s_flags);
945
946 cx18_vapi(cx, CX18_CPU_DE_RELEASE_MDL, 1, s->handle);
947 cx18_vapi(cx, CX18_DESTROY_TASK, 1, s->handle);
948 s->handle = CX18_INVALID_TASK_HANDLE;
949 clear_bit(CX18_F_S_STOPPING, &s->s_flags);
950 if (atomic_read(&cx->tot_capturing) == 0) {
951 set_bit(CX18_F_I_EOS, &cx->i_flags);
952 cx18_write_reg(cx, 5, CX18_DSP0_INTERRUPT_MASK);
953 }
954 return -EINVAL;
955 }
956
957
958 if (captype != CAPTURE_CHANNEL_TYPE_TS)
959 atomic_inc(&cx->ana_capturing);
960 atomic_inc(&cx->tot_capturing);
961 return 0;
962}
963EXPORT_SYMBOL(cx18_start_v4l2_encode_stream);
964
965void cx18_stop_all_captures(struct cx18 *cx)
966{
967 int i;
968
969 for (i = CX18_MAX_STREAMS - 1; i >= 0; i--) {
970 struct cx18_stream *s = &cx->streams[i];
971
972 if (!cx18_stream_enabled(s))
973 continue;
974 if (test_bit(CX18_F_S_STREAMING, &s->s_flags))
975 cx18_stop_v4l2_encode_stream(s, 0);
976 }
977}
978
979int cx18_stop_v4l2_encode_stream(struct cx18_stream *s, int gop_end)
980{
981 struct cx18 *cx = s->cx;
982
983 if (!cx18_stream_enabled(s))
984 return -EINVAL;
985
986
987
988
989 CX18_DEBUG_INFO("Stop Capture\n");
990
991 if (atomic_read(&cx->tot_capturing) == 0)
992 return 0;
993
994 set_bit(CX18_F_S_STOPPING, &s->s_flags);
995 if (s->type == CX18_ENC_STREAM_TYPE_MPG)
996 cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 2, s->handle, !gop_end);
997 else
998 cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 1, s->handle);
999
1000 if (s->type == CX18_ENC_STREAM_TYPE_MPG && gop_end) {
1001 CX18_INFO("ignoring gop_end: not (yet?) supported by the firmware\n");
1002 }
1003
1004 if (s->type != CX18_ENC_STREAM_TYPE_TS)
1005 atomic_dec(&cx->ana_capturing);
1006 atomic_dec(&cx->tot_capturing);
1007
1008
1009 clear_bit(CX18_F_S_STREAMING, &s->s_flags);
1010
1011
1012 cx18_vapi(cx, CX18_CPU_DE_RELEASE_MDL, 1, s->handle);
1013
1014 cx18_vapi(cx, CX18_DESTROY_TASK, 1, s->handle);
1015 s->handle = CX18_INVALID_TASK_HANDLE;
1016 clear_bit(CX18_F_S_STOPPING, &s->s_flags);
1017
1018 if (atomic_read(&cx->tot_capturing) > 0)
1019 return 0;
1020
1021 cx2341x_handler_set_busy(&cx->cxhdl, 0);
1022 cx18_write_reg(cx, 5, CX18_DSP0_INTERRUPT_MASK);
1023 wake_up(&s->waitq);
1024
1025 return 0;
1026}
1027EXPORT_SYMBOL(cx18_stop_v4l2_encode_stream);
1028
1029u32 cx18_find_handle(struct cx18 *cx)
1030{
1031 int i;
1032
1033
1034 for (i = 0; i < CX18_MAX_STREAMS; i++) {
1035 struct cx18_stream *s = &cx->streams[i];
1036
1037 if (s->video_dev && (s->handle != CX18_INVALID_TASK_HANDLE))
1038 return s->handle;
1039 }
1040 return CX18_INVALID_TASK_HANDLE;
1041}
1042
1043struct cx18_stream *cx18_handle_to_stream(struct cx18 *cx, u32 handle)
1044{
1045 int i;
1046 struct cx18_stream *s;
1047
1048 if (handle == CX18_INVALID_TASK_HANDLE)
1049 return NULL;
1050
1051 for (i = 0; i < CX18_MAX_STREAMS; i++) {
1052 s = &cx->streams[i];
1053 if (s->handle != handle)
1054 continue;
1055 if (cx18_stream_enabled(s))
1056 return s;
1057 }
1058 return NULL;
1059}
1060