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16#ifndef S5P_MFC_COMMON_H_
17#define S5P_MFC_COMMON_H_
18
19#include <linux/platform_device.h>
20#include <linux/videodev2.h>
21#include <media/v4l2-ctrls.h>
22#include <media/v4l2-device.h>
23#include <media/v4l2-ioctl.h>
24#include <media/videobuf2-core.h>
25#include "regs-mfc.h"
26#include "regs-mfc-v6.h"
27#include "regs-mfc-v7.h"
28
29
30
31
32
33#define DST_QUEUE_OFF_BASE (TASK_SIZE / 2)
34
35#define MFC_BANK1_ALLOC_CTX 0
36#define MFC_BANK2_ALLOC_CTX 1
37
38#define MFC_BANK1_ALIGN_ORDER 13
39#define MFC_BANK2_ALIGN_ORDER 13
40#define MFC_BASE_ALIGN_ORDER 17
41
42#include <media/videobuf2-dma-contig.h>
43
44static inline dma_addr_t s5p_mfc_mem_cookie(void *a, void *b)
45{
46
47 dma_addr_t *paddr = vb2_dma_contig_memops.cookie(b);
48
49 return *paddr;
50}
51
52
53#define MFC_MAX_EXTRA_DPB 5
54#define MFC_MAX_BUFFERS 32
55#define MFC_NUM_CONTEXTS 4
56
57#define MFC_INT_TIMEOUT 2000
58
59#define MFC_BW_TIMEOUT 500
60
61#define MFC_WATCHDOG_INTERVAL 1000
62
63#define MFC_WATCHDOG_CNT 10
64#define MFC_NO_INSTANCE_SET -1
65#define MFC_ENC_CAP_PLANE_COUNT 1
66#define MFC_ENC_OUT_PLANE_COUNT 2
67#define STUFF_BYTE 4
68#define MFC_MAX_CTRLS 77
69
70#define S5P_MFC_CODEC_NONE -1
71#define S5P_MFC_CODEC_H264_DEC 0
72#define S5P_MFC_CODEC_H264_MVC_DEC 1
73#define S5P_MFC_CODEC_VC1_DEC 2
74#define S5P_MFC_CODEC_MPEG4_DEC 3
75#define S5P_MFC_CODEC_MPEG2_DEC 4
76#define S5P_MFC_CODEC_H263_DEC 5
77#define S5P_MFC_CODEC_VC1RCV_DEC 6
78#define S5P_MFC_CODEC_VP8_DEC 7
79
80#define S5P_MFC_CODEC_H264_ENC 20
81#define S5P_MFC_CODEC_H264_MVC_ENC 21
82#define S5P_MFC_CODEC_MPEG4_ENC 22
83#define S5P_MFC_CODEC_H263_ENC 23
84#define S5P_MFC_CODEC_VP8_ENC 24
85
86#define S5P_MFC_R2H_CMD_EMPTY 0
87#define S5P_MFC_R2H_CMD_SYS_INIT_RET 1
88#define S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET 2
89#define S5P_MFC_R2H_CMD_SEQ_DONE_RET 3
90#define S5P_MFC_R2H_CMD_INIT_BUFFERS_RET 4
91#define S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET 6
92#define S5P_MFC_R2H_CMD_SLEEP_RET 7
93#define S5P_MFC_R2H_CMD_WAKEUP_RET 8
94#define S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET 9
95#define S5P_MFC_R2H_CMD_DPB_FLUSH_RET 10
96#define S5P_MFC_R2H_CMD_NAL_ABORT_RET 11
97#define S5P_MFC_R2H_CMD_FW_STATUS_RET 12
98#define S5P_MFC_R2H_CMD_FRAME_DONE_RET 13
99#define S5P_MFC_R2H_CMD_FIELD_DONE_RET 14
100#define S5P_MFC_R2H_CMD_SLICE_DONE_RET 15
101#define S5P_MFC_R2H_CMD_ENC_BUFFER_FUL_RET 16
102#define S5P_MFC_R2H_CMD_ERR_RET 32
103
104#define mfc_read(dev, offset) readl(dev->regs_base + (offset))
105#define mfc_write(dev, data, offset) writel((data), dev->regs_base + \
106 (offset))
107
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109
110
111enum s5p_mfc_fmt_type {
112 MFC_FMT_DEC,
113 MFC_FMT_ENC,
114 MFC_FMT_RAW,
115};
116
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118
119
120enum s5p_mfc_node_type {
121 MFCNODE_INVALID = -1,
122 MFCNODE_DECODER = 0,
123 MFCNODE_ENCODER = 1,
124};
125
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127
128
129enum s5p_mfc_inst_type {
130 MFCINST_INVALID,
131 MFCINST_DECODER,
132 MFCINST_ENCODER,
133};
134
135
136
137
138enum s5p_mfc_inst_state {
139 MFCINST_FREE = 0,
140 MFCINST_INIT = 100,
141 MFCINST_GOT_INST,
142 MFCINST_HEAD_PARSED,
143 MFCINST_HEAD_PRODUCED,
144 MFCINST_BUFS_SET,
145 MFCINST_RUNNING,
146 MFCINST_FINISHING,
147 MFCINST_FINISHED,
148 MFCINST_RETURN_INST,
149 MFCINST_ERROR,
150 MFCINST_ABORT,
151 MFCINST_FLUSH,
152 MFCINST_RES_CHANGE_INIT,
153 MFCINST_RES_CHANGE_FLUSH,
154 MFCINST_RES_CHANGE_END,
155};
156
157
158
159
160enum s5p_mfc_queue_state {
161 QUEUE_FREE,
162 QUEUE_BUFS_REQUESTED,
163 QUEUE_BUFS_QUERIED,
164 QUEUE_BUFS_MMAPED,
165};
166
167
168
169
170enum s5p_mfc_decode_arg {
171 MFC_DEC_FRAME,
172 MFC_DEC_LAST_FRAME,
173 MFC_DEC_RES_CHANGE,
174};
175
176#define MFC_BUF_FLAG_USED (1 << 0)
177#define MFC_BUF_FLAG_EOS (1 << 1)
178
179struct s5p_mfc_ctx;
180
181
182
183
184struct s5p_mfc_buf {
185 struct list_head list;
186 struct vb2_buffer *b;
187 union {
188 struct {
189 size_t luma;
190 size_t chroma;
191 } raw;
192 size_t stream;
193 } cookie;
194 int flags;
195};
196
197
198
199
200struct s5p_mfc_pm {
201 struct clk *clock;
202 struct clk *clock_gate;
203 atomic_t power;
204 struct device *device;
205};
206
207struct s5p_mfc_buf_size_v5 {
208 unsigned int h264_ctx;
209 unsigned int non_h264_ctx;
210 unsigned int dsc;
211 unsigned int shm;
212};
213
214struct s5p_mfc_buf_size_v6 {
215 unsigned int dev_ctx;
216 unsigned int h264_dec_ctx;
217 unsigned int other_dec_ctx;
218 unsigned int h264_enc_ctx;
219 unsigned int other_enc_ctx;
220};
221
222struct s5p_mfc_buf_size {
223 unsigned int fw;
224 unsigned int cpb;
225 void *priv;
226};
227
228struct s5p_mfc_buf_align {
229 unsigned int base;
230};
231
232struct s5p_mfc_variant {
233 unsigned int version;
234 unsigned int port_num;
235 struct s5p_mfc_buf_size *buf_size;
236 struct s5p_mfc_buf_align *buf_align;
237 char *fw_name;
238};
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250struct s5p_mfc_priv_buf {
251 void *alloc;
252 unsigned long ofs;
253 void *virt;
254 dma_addr_t dma;
255 size_t size;
256};
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301struct s5p_mfc_dev {
302 struct v4l2_device v4l2_dev;
303 struct video_device *vfd_dec;
304 struct video_device *vfd_enc;
305 struct platform_device *plat_dev;
306 struct device *mem_dev_l;
307 struct device *mem_dev_r;
308 void __iomem *regs_base;
309 int irq;
310 struct v4l2_ctrl_handler dec_ctrl_handler;
311 struct v4l2_ctrl_handler enc_ctrl_handler;
312 struct s5p_mfc_pm pm;
313 struct s5p_mfc_variant *variant;
314 int num_inst;
315 spinlock_t irqlock;
316 spinlock_t condlock;
317
318 struct mutex mfc_mutex;
319 int int_cond;
320 int int_type;
321 unsigned int int_err;
322 wait_queue_head_t queue;
323 size_t fw_size;
324 void *fw_virt_addr;
325 dma_addr_t bank1;
326 dma_addr_t bank2;
327 unsigned long hw_lock;
328 struct s5p_mfc_ctx *ctx[MFC_NUM_CONTEXTS];
329 int curr_ctx;
330 unsigned long ctx_work_bits;
331 atomic_t watchdog_cnt;
332 struct timer_list watchdog_timer;
333 struct workqueue_struct *watchdog_workqueue;
334 struct work_struct watchdog_work;
335 void *alloc_ctx[2];
336 unsigned long enter_suspend;
337
338 struct s5p_mfc_priv_buf ctx_buf;
339 int warn_start;
340 struct s5p_mfc_hw_ops *mfc_ops;
341 struct s5p_mfc_hw_cmds *mfc_cmds;
342};
343
344
345
346
347struct s5p_mfc_h264_enc_params {
348 enum v4l2_mpeg_video_h264_profile profile;
349 enum v4l2_mpeg_video_h264_loop_filter_mode loop_filter_mode;
350 s8 loop_filter_alpha;
351 s8 loop_filter_beta;
352 enum v4l2_mpeg_video_h264_entropy_mode entropy_mode;
353 u8 max_ref_pic;
354 u8 num_ref_pic_4p;
355 int _8x8_transform;
356 int rc_mb_dark;
357 int rc_mb_smooth;
358 int rc_mb_static;
359 int rc_mb_activity;
360 int vui_sar;
361 u8 vui_sar_idc;
362 u16 vui_ext_sar_width;
363 u16 vui_ext_sar_height;
364 int open_gop;
365 u16 open_gop_size;
366 u8 rc_frame_qp;
367 u8 rc_min_qp;
368 u8 rc_max_qp;
369 u8 rc_p_frame_qp;
370 u8 rc_b_frame_qp;
371 enum v4l2_mpeg_video_h264_level level_v4l2;
372 int level;
373 u16 cpb_size;
374 int interlace;
375 u8 hier_qp;
376 u8 hier_qp_type;
377 u8 hier_qp_layer;
378 u8 hier_qp_layer_qp[7];
379 u8 sei_frame_packing;
380 u8 sei_fp_curr_frame_0;
381 u8 sei_fp_arrangement_type;
382
383 u8 fmo;
384 u8 fmo_map_type;
385 u8 fmo_slice_grp;
386 u8 fmo_chg_dir;
387 u32 fmo_chg_rate;
388 u32 fmo_run_len[4];
389 u8 aso;
390 u32 aso_slice_order[8];
391};
392
393
394
395
396struct s5p_mfc_mpeg4_enc_params {
397
398 enum v4l2_mpeg_video_mpeg4_profile profile;
399 int quarter_pixel;
400
401 u16 vop_time_res;
402 u16 vop_frm_delta;
403 u8 rc_frame_qp;
404 u8 rc_min_qp;
405 u8 rc_max_qp;
406 u8 rc_p_frame_qp;
407 u8 rc_b_frame_qp;
408 enum v4l2_mpeg_video_mpeg4_level level_v4l2;
409 int level;
410};
411
412
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414
415struct s5p_mfc_vp8_enc_params {
416 u8 imd_4x4;
417 enum v4l2_vp8_num_partitions num_partitions;
418 enum v4l2_vp8_num_ref_frames num_ref;
419 u8 filter_level;
420 u8 filter_sharpness;
421 u32 golden_frame_ref_period;
422 enum v4l2_vp8_golden_frame_sel golden_frame_sel;
423 u8 hier_layer;
424 u8 hier_layer_qp[3];
425};
426
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428
429
430struct s5p_mfc_enc_params {
431 u16 width;
432 u16 height;
433
434 u16 gop_size;
435 enum v4l2_mpeg_video_multi_slice_mode slice_mode;
436 u16 slice_mb;
437 u32 slice_bit;
438 u16 intra_refresh_mb;
439 int pad;
440 u8 pad_luma;
441 u8 pad_cb;
442 u8 pad_cr;
443 int rc_frame;
444 int rc_mb;
445 u32 rc_bitrate;
446 u16 rc_reaction_coeff;
447 u16 vbv_size;
448 u32 vbv_delay;
449
450 enum v4l2_mpeg_video_header_mode seq_hdr_mode;
451 enum v4l2_mpeg_mfc51_video_frame_skip_mode frame_skip_mode;
452 int fixed_target_bit;
453
454 u8 num_b_frame;
455 u32 rc_framerate_num;
456 u32 rc_framerate_denom;
457
458 struct {
459 struct s5p_mfc_h264_enc_params h264;
460 struct s5p_mfc_mpeg4_enc_params mpeg4;
461 struct s5p_mfc_vp8_enc_params vp8;
462 } codec;
463
464};
465
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467
468
469struct s5p_mfc_codec_ops {
470
471 int (*pre_seq_start) (struct s5p_mfc_ctx *ctx);
472 int (*post_seq_start) (struct s5p_mfc_ctx *ctx);
473
474 int (*pre_frame_start) (struct s5p_mfc_ctx *ctx);
475 int (*post_frame_start) (struct s5p_mfc_ctx *ctx);
476};
477
478#define call_cop(c, op, args...) \
479 (((c)->c_ops->op) ? \
480 ((c)->c_ops->op(args)) : 0)
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557struct s5p_mfc_ctx {
558 struct s5p_mfc_dev *dev;
559 struct v4l2_fh fh;
560
561 int num;
562
563 int int_cond;
564 int int_type;
565 unsigned int int_err;
566 wait_queue_head_t queue;
567
568 struct s5p_mfc_fmt *src_fmt;
569 struct s5p_mfc_fmt *dst_fmt;
570
571 struct vb2_queue vq_src;
572 struct vb2_queue vq_dst;
573
574 struct list_head src_queue;
575 struct list_head dst_queue;
576
577 unsigned int src_queue_cnt;
578 unsigned int dst_queue_cnt;
579
580 enum s5p_mfc_inst_type type;
581 enum s5p_mfc_inst_state state;
582 int inst_no;
583
584
585 int img_width;
586 int img_height;
587 int buf_width;
588 int buf_height;
589
590 int luma_size;
591 int chroma_size;
592 int mv_size;
593
594 unsigned long consumed_stream;
595
596 unsigned int dpb_flush_flag;
597 unsigned int head_processed;
598
599 struct s5p_mfc_priv_buf bank1;
600 struct s5p_mfc_priv_buf bank2;
601
602 enum s5p_mfc_queue_state capture_state;
603 enum s5p_mfc_queue_state output_state;
604
605 struct s5p_mfc_buf src_bufs[MFC_MAX_BUFFERS];
606 int src_bufs_cnt;
607 struct s5p_mfc_buf dst_bufs[MFC_MAX_BUFFERS];
608 int dst_bufs_cnt;
609
610 unsigned int sequence;
611 unsigned long dec_dst_flag;
612 size_t dec_src_buf_size;
613
614
615 int codec_mode;
616 int slice_interface;
617 int loop_filter_mpeg4;
618 int display_delay;
619 int display_delay_enable;
620 int after_packed_pb;
621 int sei_fp_parse;
622
623 int pb_count;
624 int total_dpb_count;
625 int mv_count;
626
627 struct s5p_mfc_priv_buf ctx;
628 struct s5p_mfc_priv_buf dsc;
629 struct s5p_mfc_priv_buf shm;
630
631 struct s5p_mfc_enc_params enc_params;
632
633 size_t enc_dst_buf_size;
634 size_t luma_dpb_size;
635 size_t chroma_dpb_size;
636 size_t me_buffer_size;
637 size_t tmv_buffer_size;
638
639 enum v4l2_mpeg_mfc51_video_force_frame_type force_frame_type;
640
641 struct list_head ref_queue;
642 unsigned int ref_queue_cnt;
643
644 enum v4l2_mpeg_video_multi_slice_mode slice_mode;
645 union {
646 unsigned int mb;
647 unsigned int bits;
648 } slice_size;
649
650 struct s5p_mfc_codec_ops *c_ops;
651
652 struct v4l2_ctrl *ctrls[MFC_MAX_CTRLS];
653 struct v4l2_ctrl_handler ctrl_handler;
654 unsigned int frame_tag;
655 size_t scratch_buf_size;
656};
657
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661
662struct s5p_mfc_fmt {
663 char *name;
664 u32 fourcc;
665 u32 codec_mode;
666 enum s5p_mfc_fmt_type type;
667 u32 num_planes;
668};
669
670
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672
673
674struct mfc_control {
675 __u32 id;
676 enum v4l2_ctrl_type type;
677 __u8 name[32];
678 __s32 minimum;
679 __s32 maximum;
680 __s32 step;
681 __u32 menu_skip_mask;
682 __s32 default_value;
683 __u32 flags;
684 __u32 reserved[2];
685 __u8 is_volatile;
686};
687
688
689#define s5p_mfc_hw_call(f, op, args...) \
690 ((f && f->op) ? f->op(args) : -ENODEV)
691
692#define fh_to_ctx(__fh) container_of(__fh, struct s5p_mfc_ctx, fh)
693#define ctrl_to_ctx(__ctrl) \
694 container_of((__ctrl)->handler, struct s5p_mfc_ctx, ctrl_handler)
695
696void clear_work_bit(struct s5p_mfc_ctx *ctx);
697void set_work_bit(struct s5p_mfc_ctx *ctx);
698void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx);
699void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx);
700
701#define HAS_PORTNUM(dev) (dev ? (dev->variant ? \
702 (dev->variant->port_num ? 1 : 0) : 0) : 0)
703#define IS_TWOPORT(dev) (dev->variant->port_num == 2 ? 1 : 0)
704#define IS_MFCV6_PLUS(dev) (dev->variant->version >= 0x60 ? 1 : 0)
705#define IS_MFCV7(dev) (dev->variant->version >= 0x70 ? 1 : 0)
706
707#endif
708