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19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/sched.h>
22#include <linux/slab.h>
23#include <linux/init.h>
24#include <linux/errno.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/device.h>
28#include <linux/mutex.h>
29#include <linux/mfd/ucb1x00.h>
30#include <linux/pm.h>
31#include <linux/gpio.h>
32
33static DEFINE_MUTEX(ucb1x00_mutex);
34static LIST_HEAD(ucb1x00_drivers);
35static LIST_HEAD(ucb1x00_devices);
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52
53void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int in, unsigned int out)
54{
55 unsigned long flags;
56
57 spin_lock_irqsave(&ucb->io_lock, flags);
58 ucb->io_dir |= out;
59 ucb->io_dir &= ~in;
60
61 ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir);
62 spin_unlock_irqrestore(&ucb->io_lock, flags);
63}
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81void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int set, unsigned int clear)
82{
83 unsigned long flags;
84
85 spin_lock_irqsave(&ucb->io_lock, flags);
86 ucb->io_out |= set;
87 ucb->io_out &= ~clear;
88
89 ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out);
90 spin_unlock_irqrestore(&ucb->io_lock, flags);
91}
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105unsigned int ucb1x00_io_read(struct ucb1x00 *ucb)
106{
107 return ucb1x00_reg_read(ucb, UCB_IO_DATA);
108}
109
110static void ucb1x00_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
111{
112 struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio);
113 unsigned long flags;
114
115 spin_lock_irqsave(&ucb->io_lock, flags);
116 if (value)
117 ucb->io_out |= 1 << offset;
118 else
119 ucb->io_out &= ~(1 << offset);
120
121 ucb1x00_enable(ucb);
122 ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out);
123 ucb1x00_disable(ucb);
124 spin_unlock_irqrestore(&ucb->io_lock, flags);
125}
126
127static int ucb1x00_gpio_get(struct gpio_chip *chip, unsigned offset)
128{
129 struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio);
130 unsigned val;
131
132 ucb1x00_enable(ucb);
133 val = ucb1x00_reg_read(ucb, UCB_IO_DATA);
134 ucb1x00_disable(ucb);
135
136 return val & (1 << offset);
137}
138
139static int ucb1x00_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
140{
141 struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio);
142 unsigned long flags;
143
144 spin_lock_irqsave(&ucb->io_lock, flags);
145 ucb->io_dir &= ~(1 << offset);
146 ucb1x00_enable(ucb);
147 ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir);
148 ucb1x00_disable(ucb);
149 spin_unlock_irqrestore(&ucb->io_lock, flags);
150
151 return 0;
152}
153
154static int ucb1x00_gpio_direction_output(struct gpio_chip *chip, unsigned offset
155 , int value)
156{
157 struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio);
158 unsigned long flags;
159 unsigned old, mask = 1 << offset;
160
161 spin_lock_irqsave(&ucb->io_lock, flags);
162 old = ucb->io_out;
163 if (value)
164 ucb->io_out |= mask;
165 else
166 ucb->io_out &= ~mask;
167
168 ucb1x00_enable(ucb);
169 if (old != ucb->io_out)
170 ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out);
171
172 if (!(ucb->io_dir & mask)) {
173 ucb->io_dir |= mask;
174 ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir);
175 }
176 ucb1x00_disable(ucb);
177 spin_unlock_irqrestore(&ucb->io_lock, flags);
178
179 return 0;
180}
181
182static int ucb1x00_to_irq(struct gpio_chip *chip, unsigned offset)
183{
184 struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio);
185
186 return ucb->irq_base > 0 ? ucb->irq_base + offset : -ENXIO;
187}
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214void ucb1x00_adc_enable(struct ucb1x00 *ucb)
215{
216 mutex_lock(&ucb->adc_mutex);
217
218 ucb->adc_cr |= UCB_ADC_ENA;
219
220 ucb1x00_enable(ucb);
221 ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr);
222}
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240unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync)
241{
242 unsigned int val;
243
244 if (sync)
245 adc_channel |= UCB_ADC_SYNC_ENA;
246
247 ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel);
248 ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel | UCB_ADC_START);
249
250 for (;;) {
251 val = ucb1x00_reg_read(ucb, UCB_ADC_DATA);
252 if (val & UCB_ADC_DAT_VAL)
253 break;
254
255 set_current_state(TASK_INTERRUPTIBLE);
256 schedule_timeout(1);
257 }
258
259 return UCB_ADC_DAT(val);
260}
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267
268void ucb1x00_adc_disable(struct ucb1x00 *ucb)
269{
270 ucb->adc_cr &= ~UCB_ADC_ENA;
271 ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr);
272 ucb1x00_disable(ucb);
273
274 mutex_unlock(&ucb->adc_mutex);
275}
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285static void ucb1x00_irq(unsigned int irq, struct irq_desc *desc)
286{
287 struct ucb1x00 *ucb = irq_desc_get_handler_data(desc);
288 unsigned int isr, i;
289
290 ucb1x00_enable(ucb);
291 isr = ucb1x00_reg_read(ucb, UCB_IE_STATUS);
292 ucb1x00_reg_write(ucb, UCB_IE_CLEAR, isr);
293 ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
294
295 for (i = 0; i < 16 && isr; i++, isr >>= 1, irq++)
296 if (isr & 1)
297 generic_handle_irq(ucb->irq_base + i);
298 ucb1x00_disable(ucb);
299}
300
301static void ucb1x00_irq_update(struct ucb1x00 *ucb, unsigned mask)
302{
303 ucb1x00_enable(ucb);
304 if (ucb->irq_ris_enbl & mask)
305 ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl &
306 ucb->irq_mask);
307 if (ucb->irq_fal_enbl & mask)
308 ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl &
309 ucb->irq_mask);
310 ucb1x00_disable(ucb);
311}
312
313static void ucb1x00_irq_noop(struct irq_data *data)
314{
315}
316
317static void ucb1x00_irq_mask(struct irq_data *data)
318{
319 struct ucb1x00 *ucb = irq_data_get_irq_chip_data(data);
320 unsigned mask = 1 << (data->irq - ucb->irq_base);
321
322 raw_spin_lock(&ucb->irq_lock);
323 ucb->irq_mask &= ~mask;
324 ucb1x00_irq_update(ucb, mask);
325 raw_spin_unlock(&ucb->irq_lock);
326}
327
328static void ucb1x00_irq_unmask(struct irq_data *data)
329{
330 struct ucb1x00 *ucb = irq_data_get_irq_chip_data(data);
331 unsigned mask = 1 << (data->irq - ucb->irq_base);
332
333 raw_spin_lock(&ucb->irq_lock);
334 ucb->irq_mask |= mask;
335 ucb1x00_irq_update(ucb, mask);
336 raw_spin_unlock(&ucb->irq_lock);
337}
338
339static int ucb1x00_irq_set_type(struct irq_data *data, unsigned int type)
340{
341 struct ucb1x00 *ucb = irq_data_get_irq_chip_data(data);
342 unsigned mask = 1 << (data->irq - ucb->irq_base);
343
344 raw_spin_lock(&ucb->irq_lock);
345 if (type & IRQ_TYPE_EDGE_RISING)
346 ucb->irq_ris_enbl |= mask;
347 else
348 ucb->irq_ris_enbl &= ~mask;
349
350 if (type & IRQ_TYPE_EDGE_FALLING)
351 ucb->irq_fal_enbl |= mask;
352 else
353 ucb->irq_fal_enbl &= ~mask;
354 if (ucb->irq_mask & mask) {
355 ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl &
356 ucb->irq_mask);
357 ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl &
358 ucb->irq_mask);
359 }
360 raw_spin_unlock(&ucb->irq_lock);
361
362 return 0;
363}
364
365static int ucb1x00_irq_set_wake(struct irq_data *data, unsigned int on)
366{
367 struct ucb1x00 *ucb = irq_data_get_irq_chip_data(data);
368 struct ucb1x00_plat_data *pdata = ucb->mcp->attached_device.platform_data;
369 unsigned mask = 1 << (data->irq - ucb->irq_base);
370
371 if (!pdata || !pdata->can_wakeup)
372 return -EINVAL;
373
374 raw_spin_lock(&ucb->irq_lock);
375 if (on)
376 ucb->irq_wake |= mask;
377 else
378 ucb->irq_wake &= ~mask;
379 raw_spin_unlock(&ucb->irq_lock);
380
381 return 0;
382}
383
384static struct irq_chip ucb1x00_irqchip = {
385 .name = "ucb1x00",
386 .irq_ack = ucb1x00_irq_noop,
387 .irq_mask = ucb1x00_irq_mask,
388 .irq_unmask = ucb1x00_irq_unmask,
389 .irq_set_type = ucb1x00_irq_set_type,
390 .irq_set_wake = ucb1x00_irq_set_wake,
391};
392
393static int ucb1x00_add_dev(struct ucb1x00 *ucb, struct ucb1x00_driver *drv)
394{
395 struct ucb1x00_dev *dev;
396 int ret;
397
398 dev = kmalloc(sizeof(struct ucb1x00_dev), GFP_KERNEL);
399 if (!dev)
400 return -ENOMEM;
401
402 dev->ucb = ucb;
403 dev->drv = drv;
404
405 ret = drv->add(dev);
406 if (ret) {
407 kfree(dev);
408 return ret;
409 }
410
411 list_add_tail(&dev->dev_node, &ucb->devs);
412 list_add_tail(&dev->drv_node, &drv->devs);
413
414 return ret;
415}
416
417static void ucb1x00_remove_dev(struct ucb1x00_dev *dev)
418{
419 dev->drv->remove(dev);
420 list_del(&dev->dev_node);
421 list_del(&dev->drv_node);
422 kfree(dev);
423}
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443
444static int ucb1x00_detect_irq(struct ucb1x00 *ucb)
445{
446 unsigned long mask;
447
448 mask = probe_irq_on();
449 if (!mask) {
450 probe_irq_off(mask);
451 return NO_IRQ;
452 }
453
454
455
456
457 ucb1x00_reg_write(ucb, UCB_IE_RIS, UCB_IE_ADC);
458 ucb1x00_reg_write(ucb, UCB_IE_FAL, UCB_IE_ADC);
459 ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff);
460 ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
461
462
463
464
465 ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA);
466 ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | UCB_ADC_START);
467
468
469
470
471 while ((ucb1x00_reg_read(ucb, UCB_ADC_DATA) & UCB_ADC_DAT_VAL) == 0);
472 ucb1x00_reg_write(ucb, UCB_ADC_CR, 0);
473
474
475
476
477 ucb1x00_reg_write(ucb, UCB_IE_RIS, 0);
478 ucb1x00_reg_write(ucb, UCB_IE_FAL, 0);
479 ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff);
480 ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
481
482
483
484
485 return probe_irq_off(mask);
486}
487
488static void ucb1x00_release(struct device *dev)
489{
490 struct ucb1x00 *ucb = classdev_to_ucb1x00(dev);
491 kfree(ucb);
492}
493
494static struct class ucb1x00_class = {
495 .name = "ucb1x00",
496 .dev_release = ucb1x00_release,
497};
498
499static int ucb1x00_probe(struct mcp *mcp)
500{
501 struct ucb1x00_plat_data *pdata = mcp->attached_device.platform_data;
502 struct ucb1x00_driver *drv;
503 struct ucb1x00 *ucb;
504 unsigned id, i, irq_base;
505 int ret = -ENODEV;
506
507
508 if (pdata && pdata->reset)
509 pdata->reset(UCB_RST_PROBE);
510
511 mcp_enable(mcp);
512 id = mcp_reg_read(mcp, UCB_ID);
513 mcp_disable(mcp);
514
515 if (id != UCB_ID_1200 && id != UCB_ID_1300 && id != UCB_ID_TC35143) {
516 printk(KERN_WARNING "UCB1x00 ID not found: %04x\n", id);
517 goto out;
518 }
519
520 ucb = kzalloc(sizeof(struct ucb1x00), GFP_KERNEL);
521 ret = -ENOMEM;
522 if (!ucb)
523 goto out;
524
525 device_initialize(&ucb->dev);
526 ucb->dev.class = &ucb1x00_class;
527 ucb->dev.parent = &mcp->attached_device;
528 dev_set_name(&ucb->dev, "ucb1x00");
529
530 raw_spin_lock_init(&ucb->irq_lock);
531 spin_lock_init(&ucb->io_lock);
532 mutex_init(&ucb->adc_mutex);
533
534 ucb->id = id;
535 ucb->mcp = mcp;
536
537 ret = device_add(&ucb->dev);
538 if (ret)
539 goto err_dev_add;
540
541 ucb1x00_enable(ucb);
542 ucb->irq = ucb1x00_detect_irq(ucb);
543 ucb1x00_disable(ucb);
544 if (ucb->irq == NO_IRQ) {
545 dev_err(&ucb->dev, "IRQ probe failed\n");
546 ret = -ENODEV;
547 goto err_no_irq;
548 }
549
550 ucb->gpio.base = -1;
551 irq_base = pdata ? pdata->irq_base : 0;
552 ucb->irq_base = irq_alloc_descs(-1, irq_base, 16, -1);
553 if (ucb->irq_base < 0) {
554 dev_err(&ucb->dev, "unable to allocate 16 irqs: %d\n",
555 ucb->irq_base);
556 goto err_irq_alloc;
557 }
558
559 for (i = 0; i < 16; i++) {
560 unsigned irq = ucb->irq_base + i;
561
562 irq_set_chip_and_handler(irq, &ucb1x00_irqchip, handle_edge_irq);
563 irq_set_chip_data(irq, ucb);
564 set_irq_flags(irq, IRQF_VALID | IRQ_NOREQUEST);
565 }
566
567 irq_set_irq_type(ucb->irq, IRQ_TYPE_EDGE_RISING);
568 irq_set_handler_data(ucb->irq, ucb);
569 irq_set_chained_handler(ucb->irq, ucb1x00_irq);
570
571 if (pdata && pdata->gpio_base) {
572 ucb->gpio.label = dev_name(&ucb->dev);
573 ucb->gpio.dev = &ucb->dev;
574 ucb->gpio.owner = THIS_MODULE;
575 ucb->gpio.base = pdata->gpio_base;
576 ucb->gpio.ngpio = 10;
577 ucb->gpio.set = ucb1x00_gpio_set;
578 ucb->gpio.get = ucb1x00_gpio_get;
579 ucb->gpio.direction_input = ucb1x00_gpio_direction_input;
580 ucb->gpio.direction_output = ucb1x00_gpio_direction_output;
581 ucb->gpio.to_irq = ucb1x00_to_irq;
582 ret = gpiochip_add(&ucb->gpio);
583 if (ret)
584 goto err_gpio_add;
585 } else
586 dev_info(&ucb->dev, "gpio_base not set so no gpiolib support");
587
588 mcp_set_drvdata(mcp, ucb);
589
590 if (pdata)
591 device_set_wakeup_capable(&ucb->dev, pdata->can_wakeup);
592
593 INIT_LIST_HEAD(&ucb->devs);
594 mutex_lock(&ucb1x00_mutex);
595 list_add_tail(&ucb->node, &ucb1x00_devices);
596 list_for_each_entry(drv, &ucb1x00_drivers, node) {
597 ucb1x00_add_dev(ucb, drv);
598 }
599 mutex_unlock(&ucb1x00_mutex);
600
601 return ret;
602
603 err_gpio_add:
604 irq_set_chained_handler(ucb->irq, NULL);
605 err_irq_alloc:
606 if (ucb->irq_base > 0)
607 irq_free_descs(ucb->irq_base, 16);
608 err_no_irq:
609 device_del(&ucb->dev);
610 err_dev_add:
611 put_device(&ucb->dev);
612 out:
613 if (pdata && pdata->reset)
614 pdata->reset(UCB_RST_PROBE_FAIL);
615 return ret;
616}
617
618static void ucb1x00_remove(struct mcp *mcp)
619{
620 struct ucb1x00_plat_data *pdata = mcp->attached_device.platform_data;
621 struct ucb1x00 *ucb = mcp_get_drvdata(mcp);
622 struct list_head *l, *n;
623 int ret;
624
625 mutex_lock(&ucb1x00_mutex);
626 list_del(&ucb->node);
627 list_for_each_safe(l, n, &ucb->devs) {
628 struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, dev_node);
629 ucb1x00_remove_dev(dev);
630 }
631 mutex_unlock(&ucb1x00_mutex);
632
633 if (ucb->gpio.base != -1) {
634 ret = gpiochip_remove(&ucb->gpio);
635 if (ret)
636 dev_err(&ucb->dev, "Can't remove gpio chip: %d\n", ret);
637 }
638
639 irq_set_chained_handler(ucb->irq, NULL);
640 irq_free_descs(ucb->irq_base, 16);
641 device_unregister(&ucb->dev);
642
643 if (pdata && pdata->reset)
644 pdata->reset(UCB_RST_REMOVE);
645}
646
647int ucb1x00_register_driver(struct ucb1x00_driver *drv)
648{
649 struct ucb1x00 *ucb;
650
651 INIT_LIST_HEAD(&drv->devs);
652 mutex_lock(&ucb1x00_mutex);
653 list_add_tail(&drv->node, &ucb1x00_drivers);
654 list_for_each_entry(ucb, &ucb1x00_devices, node) {
655 ucb1x00_add_dev(ucb, drv);
656 }
657 mutex_unlock(&ucb1x00_mutex);
658 return 0;
659}
660
661void ucb1x00_unregister_driver(struct ucb1x00_driver *drv)
662{
663 struct list_head *n, *l;
664
665 mutex_lock(&ucb1x00_mutex);
666 list_del(&drv->node);
667 list_for_each_safe(l, n, &drv->devs) {
668 struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, drv_node);
669 ucb1x00_remove_dev(dev);
670 }
671 mutex_unlock(&ucb1x00_mutex);
672}
673
674#ifdef CONFIG_PM_SLEEP
675static int ucb1x00_suspend(struct device *dev)
676{
677 struct ucb1x00_plat_data *pdata = dev_get_platdata(dev);
678 struct ucb1x00 *ucb = dev_get_drvdata(dev);
679 struct ucb1x00_dev *udev;
680
681 mutex_lock(&ucb1x00_mutex);
682 list_for_each_entry(udev, &ucb->devs, dev_node) {
683 if (udev->drv->suspend)
684 udev->drv->suspend(udev);
685 }
686 mutex_unlock(&ucb1x00_mutex);
687
688 if (ucb->irq_wake) {
689 unsigned long flags;
690
691 raw_spin_lock_irqsave(&ucb->irq_lock, flags);
692 ucb1x00_enable(ucb);
693 ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl &
694 ucb->irq_wake);
695 ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl &
696 ucb->irq_wake);
697 ucb1x00_disable(ucb);
698 raw_spin_unlock_irqrestore(&ucb->irq_lock, flags);
699
700 enable_irq_wake(ucb->irq);
701 } else if (pdata && pdata->reset)
702 pdata->reset(UCB_RST_SUSPEND);
703
704 return 0;
705}
706
707static int ucb1x00_resume(struct device *dev)
708{
709 struct ucb1x00_plat_data *pdata = dev_get_platdata(dev);
710 struct ucb1x00 *ucb = dev_get_drvdata(dev);
711 struct ucb1x00_dev *udev;
712
713 if (!ucb->irq_wake && pdata && pdata->reset)
714 pdata->reset(UCB_RST_RESUME);
715
716 ucb1x00_enable(ucb);
717 ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out);
718 ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir);
719
720 if (ucb->irq_wake) {
721 unsigned long flags;
722
723 raw_spin_lock_irqsave(&ucb->irq_lock, flags);
724 ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl &
725 ucb->irq_mask);
726 ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl &
727 ucb->irq_mask);
728 raw_spin_unlock_irqrestore(&ucb->irq_lock, flags);
729
730 disable_irq_wake(ucb->irq);
731 }
732 ucb1x00_disable(ucb);
733
734 mutex_lock(&ucb1x00_mutex);
735 list_for_each_entry(udev, &ucb->devs, dev_node) {
736 if (udev->drv->resume)
737 udev->drv->resume(udev);
738 }
739 mutex_unlock(&ucb1x00_mutex);
740 return 0;
741}
742#endif
743
744static const struct dev_pm_ops ucb1x00_pm_ops = {
745 SET_SYSTEM_SLEEP_PM_OPS(ucb1x00_suspend, ucb1x00_resume)
746};
747
748static struct mcp_driver ucb1x00_driver = {
749 .drv = {
750 .name = "ucb1x00",
751 .owner = THIS_MODULE,
752 .pm = &ucb1x00_pm_ops,
753 },
754 .probe = ucb1x00_probe,
755 .remove = ucb1x00_remove,
756};
757
758static int __init ucb1x00_init(void)
759{
760 int ret = class_register(&ucb1x00_class);
761 if (ret == 0) {
762 ret = mcp_driver_register(&ucb1x00_driver);
763 if (ret)
764 class_unregister(&ucb1x00_class);
765 }
766 return ret;
767}
768
769static void __exit ucb1x00_exit(void)
770{
771 mcp_driver_unregister(&ucb1x00_driver);
772 class_unregister(&ucb1x00_class);
773}
774
775module_init(ucb1x00_init);
776module_exit(ucb1x00_exit);
777
778EXPORT_SYMBOL(ucb1x00_io_set_dir);
779EXPORT_SYMBOL(ucb1x00_io_write);
780EXPORT_SYMBOL(ucb1x00_io_read);
781
782EXPORT_SYMBOL(ucb1x00_adc_enable);
783EXPORT_SYMBOL(ucb1x00_adc_read);
784EXPORT_SYMBOL(ucb1x00_adc_disable);
785
786EXPORT_SYMBOL(ucb1x00_register_driver);
787EXPORT_SYMBOL(ucb1x00_unregister_driver);
788
789MODULE_ALIAS("mcp:ucb1x00");
790MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
791MODULE_DESCRIPTION("UCB1x00 core driver");
792MODULE_LICENSE("GPL");
793