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22#include <linux/module.h>
23#include <linux/slab.h>
24#include <linux/highmem.h>
25#include <linux/delay.h>
26#include <linux/platform_device.h>
27#include <linux/mmc/host.h>
28#include <linux/mmc/mmc.h>
29#include <linux/mmc/sd.h>
30#include <linux/mmc/card.h>
31#include <linux/mfd/rtsx_pci.h>
32#include <asm/unaligned.h>
33
34
35
36
37struct timing_phase_path {
38 int start;
39 int end;
40 int mid;
41 int len;
42};
43
44struct realtek_pci_sdmmc {
45 struct platform_device *pdev;
46 struct rtsx_pcr *pcr;
47 struct mmc_host *mmc;
48 struct mmc_request *mrq;
49
50 struct mutex host_mutex;
51
52 u8 ssc_depth;
53 unsigned int clock;
54 bool vpclk;
55 bool double_clk;
56 bool eject;
57 bool initial_mode;
58 int power_state;
59#define SDMMC_POWER_ON 1
60#define SDMMC_POWER_OFF 0
61};
62
63static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host)
64{
65 return &(host->pdev->dev);
66}
67
68static inline void sd_clear_error(struct realtek_pci_sdmmc *host)
69{
70 rtsx_pci_write_register(host->pcr, CARD_STOP,
71 SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
72}
73
74#ifdef DEBUG
75static void sd_print_debug_regs(struct realtek_pci_sdmmc *host)
76{
77 struct rtsx_pcr *pcr = host->pcr;
78 u16 i;
79 u8 *ptr;
80
81
82 rtsx_pci_init_cmd(pcr);
83 for (i = 0xFDA0; i <= 0xFDAE; i++)
84 rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0);
85 for (i = 0xFD52; i <= 0xFD69; i++)
86 rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0);
87 rtsx_pci_send_cmd(pcr, 100);
88
89 ptr = rtsx_pci_get_cmd_data(pcr);
90 for (i = 0xFDA0; i <= 0xFDAE; i++)
91 dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++));
92 for (i = 0xFD52; i <= 0xFD69; i++)
93 dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++));
94}
95#else
96#define sd_print_debug_regs(host)
97#endif
98
99static int sd_read_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt,
100 u8 *buf, int buf_len, int timeout)
101{
102 struct rtsx_pcr *pcr = host->pcr;
103 int err, i;
104 u8 trans_mode;
105
106 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD%d\n", __func__, cmd[0] - 0x40);
107
108 if (!buf)
109 buf_len = 0;
110
111 if ((cmd[0] & 0x3F) == MMC_SEND_TUNING_BLOCK)
112 trans_mode = SD_TM_AUTO_TUNING;
113 else
114 trans_mode = SD_TM_NORMAL_READ;
115
116 rtsx_pci_init_cmd(pcr);
117
118 for (i = 0; i < 5; i++)
119 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0 + i, 0xFF, cmd[i]);
120
121 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
122 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H,
123 0xFF, (u8)(byte_cnt >> 8));
124 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
125 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
126
127 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
128 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
129 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
130 if (trans_mode != SD_TM_AUTO_TUNING)
131 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
132 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
133
134 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
135 0xFF, trans_mode | SD_TRANSFER_START);
136 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
137 SD_TRANSFER_END, SD_TRANSFER_END);
138
139 err = rtsx_pci_send_cmd(pcr, timeout);
140 if (err < 0) {
141 sd_print_debug_regs(host);
142 dev_dbg(sdmmc_dev(host),
143 "rtsx_pci_send_cmd fail (err = %d)\n", err);
144 return err;
145 }
146
147 if (buf && buf_len) {
148 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
149 if (err < 0) {
150 dev_dbg(sdmmc_dev(host),
151 "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
152 return err;
153 }
154 }
155
156 return 0;
157}
158
159static int sd_write_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt,
160 u8 *buf, int buf_len, int timeout)
161{
162 struct rtsx_pcr *pcr = host->pcr;
163 int err, i;
164 u8 trans_mode;
165
166 if (!buf)
167 buf_len = 0;
168
169 if (buf && buf_len) {
170 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
171 if (err < 0) {
172 dev_dbg(sdmmc_dev(host),
173 "rtsx_pci_write_ppbuf fail (err = %d)\n", err);
174 return err;
175 }
176 }
177
178 trans_mode = cmd ? SD_TM_AUTO_WRITE_2 : SD_TM_AUTO_WRITE_3;
179 rtsx_pci_init_cmd(pcr);
180
181 if (cmd) {
182 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d\n", __func__,
183 cmd[0] - 0x40);
184
185 for (i = 0; i < 5; i++)
186 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
187 SD_CMD0 + i, 0xFF, cmd[i]);
188 }
189
190 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
191 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H,
192 0xFF, (u8)(byte_cnt >> 8));
193 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
194 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
195
196 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
197 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
198 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
199
200 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
201 trans_mode | SD_TRANSFER_START);
202 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
203 SD_TRANSFER_END, SD_TRANSFER_END);
204
205 err = rtsx_pci_send_cmd(pcr, timeout);
206 if (err < 0) {
207 sd_print_debug_regs(host);
208 dev_dbg(sdmmc_dev(host),
209 "rtsx_pci_send_cmd fail (err = %d)\n", err);
210 return err;
211 }
212
213 return 0;
214}
215
216static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
217 struct mmc_command *cmd)
218{
219 struct rtsx_pcr *pcr = host->pcr;
220 u8 cmd_idx = (u8)cmd->opcode;
221 u32 arg = cmd->arg;
222 int err = 0;
223 int timeout = 100;
224 int i;
225 u8 *ptr;
226 int stat_idx = 0;
227 u8 rsp_type;
228 int rsp_len = 5;
229 bool clock_toggled = false;
230
231 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
232 __func__, cmd_idx, arg);
233
234
235
236
237
238
239
240
241 switch (mmc_resp_type(cmd)) {
242 case MMC_RSP_NONE:
243 rsp_type = SD_RSP_TYPE_R0;
244 rsp_len = 0;
245 break;
246 case MMC_RSP_R1:
247 rsp_type = SD_RSP_TYPE_R1;
248 break;
249 case MMC_RSP_R1B:
250 rsp_type = SD_RSP_TYPE_R1b;
251 break;
252 case MMC_RSP_R2:
253 rsp_type = SD_RSP_TYPE_R2;
254 rsp_len = 16;
255 break;
256 case MMC_RSP_R3:
257 rsp_type = SD_RSP_TYPE_R3;
258 break;
259 default:
260 dev_dbg(sdmmc_dev(host), "cmd->flag is not valid\n");
261 err = -EINVAL;
262 goto out;
263 }
264
265 if (rsp_type == SD_RSP_TYPE_R1b)
266 timeout = 3000;
267
268 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
269 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
270 0xFF, SD_CLK_TOGGLE_EN);
271 if (err < 0)
272 goto out;
273
274 clock_toggled = true;
275 }
276
277 rtsx_pci_init_cmd(pcr);
278
279 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, 0x40 | cmd_idx);
280 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD1, 0xFF, (u8)(arg >> 24));
281 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD2, 0xFF, (u8)(arg >> 16));
282 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD3, 0xFF, (u8)(arg >> 8));
283 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD4, 0xFF, (u8)arg);
284
285 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
286 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
287 0x01, PINGPONG_BUFFER);
288 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
289 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
290 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
291 SD_TRANSFER_END | SD_STAT_IDLE,
292 SD_TRANSFER_END | SD_STAT_IDLE);
293
294 if (rsp_type == SD_RSP_TYPE_R2) {
295
296 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
297 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
298 stat_idx = 16;
299 } else if (rsp_type != SD_RSP_TYPE_R0) {
300
301 for (i = SD_CMD0; i <= SD_CMD4; i++)
302 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
303 stat_idx = 5;
304 }
305
306 rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
307
308 err = rtsx_pci_send_cmd(pcr, timeout);
309 if (err < 0) {
310 sd_print_debug_regs(host);
311 sd_clear_error(host);
312 dev_dbg(sdmmc_dev(host),
313 "rtsx_pci_send_cmd error (err = %d)\n", err);
314 goto out;
315 }
316
317 if (rsp_type == SD_RSP_TYPE_R0) {
318 err = 0;
319 goto out;
320 }
321
322
323 ptr = rtsx_pci_get_cmd_data(pcr) + 1;
324
325
326 if ((ptr[0] & 0xC0) != 0) {
327 err = -EILSEQ;
328 dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
329 goto out;
330 }
331
332
333 if (!(rsp_type & SD_NO_CHECK_CRC7)) {
334 if (ptr[stat_idx] & SD_CRC7_ERR) {
335 err = -EILSEQ;
336 dev_dbg(sdmmc_dev(host), "CRC7 error\n");
337 goto out;
338 }
339 }
340
341 if (rsp_type == SD_RSP_TYPE_R2) {
342 for (i = 0; i < 4; i++) {
343 cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
344 dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
345 i, cmd->resp[i]);
346 }
347 } else {
348 cmd->resp[0] = get_unaligned_be32(ptr + 1);
349 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
350 cmd->resp[0]);
351 }
352
353out:
354 cmd->error = err;
355
356 if (err && clock_toggled)
357 rtsx_pci_write_register(pcr, SD_BUS_STAT,
358 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
359}
360
361static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
362{
363 struct rtsx_pcr *pcr = host->pcr;
364 struct mmc_host *mmc = host->mmc;
365 struct mmc_card *card = mmc->card;
366 struct mmc_data *data = mrq->data;
367 int uhs = mmc_sd_card_uhs(card);
368 int read = (data->flags & MMC_DATA_READ) ? 1 : 0;
369 u8 cfg2, trans_mode;
370 int err;
371 size_t data_len = data->blksz * data->blocks;
372
373 if (read) {
374 cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
375 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0;
376 trans_mode = SD_TM_AUTO_READ_3;
377 } else {
378 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
379 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
380 trans_mode = SD_TM_AUTO_WRITE_3;
381 }
382
383 if (!uhs)
384 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
385
386 rtsx_pci_init_cmd(pcr);
387
388 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0x00);
389 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, 0x02);
390 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L,
391 0xFF, (u8)data->blocks);
392 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H,
393 0xFF, (u8)(data->blocks >> 8));
394
395 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
396 DMA_DONE_INT, DMA_DONE_INT);
397 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
398 0xFF, (u8)(data_len >> 24));
399 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
400 0xFF, (u8)(data_len >> 16));
401 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
402 0xFF, (u8)(data_len >> 8));
403 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
404 if (read) {
405 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
406 0x03 | DMA_PACK_SIZE_MASK,
407 DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
408 } else {
409 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
410 0x03 | DMA_PACK_SIZE_MASK,
411 DMA_DIR_TO_CARD | DMA_EN | DMA_512);
412 }
413
414 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
415 0x01, RING_BUFFER);
416
417 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
418 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
419 trans_mode | SD_TRANSFER_START);
420 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
421 SD_TRANSFER_END, SD_TRANSFER_END);
422
423 rtsx_pci_send_cmd_no_wait(pcr);
424
425 err = rtsx_pci_transfer_data(pcr, data->sg, data->sg_len, read, 10000);
426 if (err < 0) {
427 sd_clear_error(host);
428 return err;
429 }
430
431 return 0;
432}
433
434static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host)
435{
436 rtsx_pci_write_register(host->pcr, SD_CFG1,
437 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
438}
439
440static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host)
441{
442 rtsx_pci_write_register(host->pcr, SD_CFG1,
443 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
444}
445
446static void sd_normal_rw(struct realtek_pci_sdmmc *host,
447 struct mmc_request *mrq)
448{
449 struct mmc_command *cmd = mrq->cmd;
450 struct mmc_data *data = mrq->data;
451 u8 _cmd[5], *buf;
452
453 _cmd[0] = 0x40 | (u8)cmd->opcode;
454 put_unaligned_be32(cmd->arg, (u32 *)(&_cmd[1]));
455
456 buf = kzalloc(data->blksz, GFP_NOIO);
457 if (!buf) {
458 cmd->error = -ENOMEM;
459 return;
460 }
461
462 if (data->flags & MMC_DATA_READ) {
463 if (host->initial_mode)
464 sd_disable_initial_mode(host);
465
466 cmd->error = sd_read_data(host, _cmd, (u16)data->blksz, buf,
467 data->blksz, 200);
468
469 if (host->initial_mode)
470 sd_enable_initial_mode(host);
471
472 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
473 } else {
474 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
475
476 cmd->error = sd_write_data(host, _cmd, (u16)data->blksz, buf,
477 data->blksz, 200);
478 }
479
480 kfree(buf);
481}
482
483static int sd_change_phase(struct realtek_pci_sdmmc *host,
484 u8 sample_point, bool rx)
485{
486 struct rtsx_pcr *pcr = host->pcr;
487 int err;
488
489 dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n",
490 __func__, rx ? "RX" : "TX", sample_point);
491
492 rtsx_pci_init_cmd(pcr);
493
494 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
495 if (rx)
496 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
497 SD_VPRX_CTL, 0x1F, sample_point);
498 else
499 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
500 SD_VPTX_CTL, 0x1F, sample_point);
501 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
502 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
503 PHASE_NOT_RESET, PHASE_NOT_RESET);
504 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0);
505 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
506
507 err = rtsx_pci_send_cmd(pcr, 100);
508 if (err < 0)
509 return err;
510
511 return 0;
512}
513
514static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map)
515{
516 struct timing_phase_path path[MAX_PHASE + 1];
517 int i, j, cont_path_cnt;
518 int new_block, max_len, final_path_idx;
519 u8 final_phase = 0xFF;
520
521
522 cont_path_cnt = 0;
523 new_block = 1;
524 j = 0;
525 for (i = 0; i < MAX_PHASE + 1; i++) {
526 if (phase_map & (1 << i)) {
527 if (new_block) {
528 new_block = 0;
529 j = cont_path_cnt++;
530 path[j].start = i;
531 path[j].end = i;
532 } else {
533 path[j].end = i;
534 }
535 } else {
536 new_block = 1;
537 if (cont_path_cnt) {
538
539 int idx = cont_path_cnt - 1;
540 path[idx].len =
541 path[idx].end - path[idx].start + 1;
542 path[idx].mid =
543 path[idx].start + path[idx].len / 2;
544 }
545 }
546 }
547
548 if (cont_path_cnt == 0) {
549 dev_dbg(sdmmc_dev(host), "No continuous phase path\n");
550 goto finish;
551 } else {
552
553 int idx = cont_path_cnt - 1;
554 path[idx].len = path[idx].end - path[idx].start + 1;
555 path[idx].mid = path[idx].start + path[idx].len / 2;
556 }
557
558
559 if (!path[0].start && (path[cont_path_cnt - 1].end == MAX_PHASE)) {
560
561 path[0].start = path[cont_path_cnt - 1].start - MAX_PHASE - 1;
562 path[0].len += path[cont_path_cnt - 1].len;
563 path[0].mid = path[0].start + path[0].len / 2;
564
565 if (path[0].mid < 0)
566 path[0].mid += MAX_PHASE + 1;
567 cont_path_cnt--;
568 }
569
570
571 max_len = 0;
572 final_phase = 0;
573 final_path_idx = 0;
574 for (i = 0; i < cont_path_cnt; i++) {
575 if (path[i].len > max_len) {
576 max_len = path[i].len;
577 final_phase = (u8)path[i].mid;
578 final_path_idx = i;
579 }
580
581 dev_dbg(sdmmc_dev(host), "path[%d].start = %d\n",
582 i, path[i].start);
583 dev_dbg(sdmmc_dev(host), "path[%d].end = %d\n",
584 i, path[i].end);
585 dev_dbg(sdmmc_dev(host), "path[%d].len = %d\n",
586 i, path[i].len);
587 dev_dbg(sdmmc_dev(host), "path[%d].mid = %d\n",
588 i, path[i].mid);
589 }
590
591finish:
592 dev_dbg(sdmmc_dev(host), "Final chosen phase: %d\n", final_phase);
593 return final_phase;
594}
595
596static void sd_wait_data_idle(struct realtek_pci_sdmmc *host)
597{
598 int err, i;
599 u8 val = 0;
600
601 for (i = 0; i < 100; i++) {
602 err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
603 if (val & SD_DATA_IDLE)
604 return;
605
606 udelay(100);
607 }
608}
609
610static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
611 u8 opcode, u8 sample_point)
612{
613 int err;
614 u8 cmd[5] = {0};
615
616 err = sd_change_phase(host, sample_point, true);
617 if (err < 0)
618 return err;
619
620 cmd[0] = 0x40 | opcode;
621 err = sd_read_data(host, cmd, 0x40, NULL, 0, 100);
622 if (err < 0) {
623
624 sd_wait_data_idle(host);
625 sd_clear_error(host);
626 return err;
627 }
628
629 return 0;
630}
631
632static int sd_tuning_phase(struct realtek_pci_sdmmc *host,
633 u8 opcode, u32 *phase_map)
634{
635 int err, i;
636 u32 raw_phase_map = 0;
637
638 for (i = MAX_PHASE; i >= 0; i--) {
639 err = sd_tuning_rx_cmd(host, opcode, (u8)i);
640 if (err == 0)
641 raw_phase_map |= 1 << i;
642 }
643
644 if (phase_map)
645 *phase_map = raw_phase_map;
646
647 return 0;
648}
649
650static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode)
651{
652 int err, i;
653 u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
654 u8 final_phase;
655
656 for (i = 0; i < RX_TUNING_CNT; i++) {
657 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
658 if (err < 0)
659 return err;
660
661 if (raw_phase_map[i] == 0)
662 break;
663 }
664
665 phase_map = 0xFFFFFFFF;
666 for (i = 0; i < RX_TUNING_CNT; i++) {
667 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n",
668 i, raw_phase_map[i]);
669 phase_map &= raw_phase_map[i];
670 }
671 dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map);
672
673 if (phase_map) {
674 final_phase = sd_search_final_phase(host, phase_map);
675 if (final_phase == 0xFF)
676 return -EINVAL;
677
678 err = sd_change_phase(host, final_phase, true);
679 if (err < 0)
680 return err;
681 } else {
682 return -EINVAL;
683 }
684
685 return 0;
686}
687
688static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
689{
690 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
691 struct rtsx_pcr *pcr = host->pcr;
692 struct mmc_command *cmd = mrq->cmd;
693 struct mmc_data *data = mrq->data;
694 unsigned int data_size = 0;
695 int err;
696
697 if (host->eject) {
698 cmd->error = -ENOMEDIUM;
699 goto finish;
700 }
701
702 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
703 if (err) {
704 cmd->error = err;
705 goto finish;
706 }
707
708 mutex_lock(&pcr->pcr_mutex);
709
710 rtsx_pci_start_run(pcr);
711
712 rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
713 host->initial_mode, host->double_clk, host->vpclk);
714 rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
715 rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
716 CARD_SHARE_MASK, CARD_SHARE_48_SD);
717
718 mutex_lock(&host->host_mutex);
719 host->mrq = mrq;
720 mutex_unlock(&host->host_mutex);
721
722 if (mrq->data)
723 data_size = data->blocks * data->blksz;
724
725 if (!data_size || mmc_op_multi(cmd->opcode) ||
726 (cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
727 (cmd->opcode == MMC_WRITE_BLOCK)) {
728 sd_send_cmd_get_rsp(host, cmd);
729
730 if (!cmd->error && data_size) {
731 sd_rw_multi(host, mrq);
732
733 if (mmc_op_multi(cmd->opcode) && mrq->stop)
734 sd_send_cmd_get_rsp(host, mrq->stop);
735 }
736 } else {
737 sd_normal_rw(host, mrq);
738 }
739
740 if (mrq->data) {
741 if (cmd->error || data->error)
742 data->bytes_xfered = 0;
743 else
744 data->bytes_xfered = data->blocks * data->blksz;
745 }
746
747 mutex_unlock(&pcr->pcr_mutex);
748
749finish:
750 if (cmd->error)
751 dev_dbg(sdmmc_dev(host), "cmd->error = %d\n", cmd->error);
752
753 mutex_lock(&host->host_mutex);
754 host->mrq = NULL;
755 mutex_unlock(&host->host_mutex);
756
757 mmc_request_done(mmc, mrq);
758}
759
760static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
761 unsigned char bus_width)
762{
763 int err = 0;
764 u8 width[] = {
765 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
766 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
767 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
768 };
769
770 if (bus_width <= MMC_BUS_WIDTH_8)
771 err = rtsx_pci_write_register(host->pcr, SD_CFG1,
772 0x03, width[bus_width]);
773
774 return err;
775}
776
777static int sd_power_on(struct realtek_pci_sdmmc *host)
778{
779 struct rtsx_pcr *pcr = host->pcr;
780 int err;
781
782 if (host->power_state == SDMMC_POWER_ON)
783 return 0;
784
785 rtsx_pci_init_cmd(pcr);
786 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
787 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
788 CARD_SHARE_MASK, CARD_SHARE_48_SD);
789 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
790 SD_CLK_EN, SD_CLK_EN);
791 err = rtsx_pci_send_cmd(pcr, 100);
792 if (err < 0)
793 return err;
794
795 err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
796 if (err < 0)
797 return err;
798
799 err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
800 if (err < 0)
801 return err;
802
803 err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
804 if (err < 0)
805 return err;
806
807 host->power_state = SDMMC_POWER_ON;
808 return 0;
809}
810
811static int sd_power_off(struct realtek_pci_sdmmc *host)
812{
813 struct rtsx_pcr *pcr = host->pcr;
814 int err;
815
816 host->power_state = SDMMC_POWER_OFF;
817
818 rtsx_pci_init_cmd(pcr);
819
820 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
821 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
822
823 err = rtsx_pci_send_cmd(pcr, 100);
824 if (err < 0)
825 return err;
826
827 err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
828 if (err < 0)
829 return err;
830
831 return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
832}
833
834static int sd_set_power_mode(struct realtek_pci_sdmmc *host,
835 unsigned char power_mode)
836{
837 int err;
838
839 if (power_mode == MMC_POWER_OFF)
840 err = sd_power_off(host);
841 else
842 err = sd_power_on(host);
843
844 return err;
845}
846
847static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing)
848{
849 struct rtsx_pcr *pcr = host->pcr;
850 int err = 0;
851
852 rtsx_pci_init_cmd(pcr);
853
854 switch (timing) {
855 case MMC_TIMING_UHS_SDR104:
856 case MMC_TIMING_UHS_SDR50:
857 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
858 0x0C | SD_ASYNC_FIFO_NOT_RST,
859 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
860 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
861 CLK_LOW_FREQ, CLK_LOW_FREQ);
862 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
863 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
864 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
865 break;
866
867 case MMC_TIMING_UHS_DDR50:
868 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
869 0x0C | SD_ASYNC_FIFO_NOT_RST,
870 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
871 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
872 CLK_LOW_FREQ, CLK_LOW_FREQ);
873 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
874 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
875 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
876 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
877 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
878 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
879 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
880 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
881 break;
882
883 case MMC_TIMING_MMC_HS:
884 case MMC_TIMING_SD_HS:
885 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
886 0x0C, SD_20_MODE);
887 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
888 CLK_LOW_FREQ, CLK_LOW_FREQ);
889 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
890 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
891 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
892 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
893 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
894 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
895 SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
896 break;
897
898 default:
899 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
900 SD_CFG1, 0x0C, SD_20_MODE);
901 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
902 CLK_LOW_FREQ, CLK_LOW_FREQ);
903 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
904 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
905 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
906 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
907 SD_PUSH_POINT_CTL, 0xFF, 0);
908 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
909 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
910 break;
911 }
912
913 err = rtsx_pci_send_cmd(pcr, 100);
914
915 return err;
916}
917
918static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
919{
920 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
921 struct rtsx_pcr *pcr = host->pcr;
922
923 if (host->eject)
924 return;
925
926 if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))
927 return;
928
929 mutex_lock(&pcr->pcr_mutex);
930
931 rtsx_pci_start_run(pcr);
932
933 sd_set_bus_width(host, ios->bus_width);
934 sd_set_power_mode(host, ios->power_mode);
935 sd_set_timing(host, ios->timing);
936
937 host->vpclk = false;
938 host->double_clk = true;
939
940 switch (ios->timing) {
941 case MMC_TIMING_UHS_SDR104:
942 case MMC_TIMING_UHS_SDR50:
943 host->ssc_depth = RTSX_SSC_DEPTH_2M;
944 host->vpclk = true;
945 host->double_clk = false;
946 break;
947 case MMC_TIMING_UHS_DDR50:
948 case MMC_TIMING_UHS_SDR25:
949 host->ssc_depth = RTSX_SSC_DEPTH_1M;
950 break;
951 default:
952 host->ssc_depth = RTSX_SSC_DEPTH_500K;
953 break;
954 }
955
956 host->initial_mode = (ios->clock <= 1000000) ? true : false;
957
958 host->clock = ios->clock;
959 rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
960 host->initial_mode, host->double_clk, host->vpclk);
961
962 mutex_unlock(&pcr->pcr_mutex);
963}
964
965static int sdmmc_get_ro(struct mmc_host *mmc)
966{
967 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
968 struct rtsx_pcr *pcr = host->pcr;
969 int ro = 0;
970 u32 val;
971
972 if (host->eject)
973 return -ENOMEDIUM;
974
975 mutex_lock(&pcr->pcr_mutex);
976
977 rtsx_pci_start_run(pcr);
978
979
980 val = rtsx_pci_readl(pcr, RTSX_BIPR);
981 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
982 if (val & SD_WRITE_PROTECT)
983 ro = 1;
984
985 mutex_unlock(&pcr->pcr_mutex);
986
987 return ro;
988}
989
990static int sdmmc_get_cd(struct mmc_host *mmc)
991{
992 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
993 struct rtsx_pcr *pcr = host->pcr;
994 int cd = 0;
995 u32 val;
996
997 if (host->eject)
998 return -ENOMEDIUM;
999
1000 mutex_lock(&pcr->pcr_mutex);
1001
1002 rtsx_pci_start_run(pcr);
1003
1004
1005 val = rtsx_pci_card_exist(pcr);
1006 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1007 if (val & SD_EXIST)
1008 cd = 1;
1009
1010 mutex_unlock(&pcr->pcr_mutex);
1011
1012 return cd;
1013}
1014
1015static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host)
1016{
1017 struct rtsx_pcr *pcr = host->pcr;
1018 int err;
1019 u8 stat;
1020
1021
1022
1023
1024
1025 mdelay(1);
1026
1027
1028
1029
1030
1031 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1032 if (err < 0)
1033 return err;
1034
1035 if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1036 SD_DAT1_STATUS | SD_DAT0_STATUS))
1037 return -EINVAL;
1038
1039
1040 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1041 0xFF, SD_CLK_FORCE_STOP);
1042 if (err < 0)
1043 return err;
1044
1045 return 0;
1046}
1047
1048static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host)
1049{
1050 struct rtsx_pcr *pcr = host->pcr;
1051 int err;
1052 u8 stat, mask, val;
1053
1054
1055 msleep(50);
1056
1057
1058 err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1059 if (err < 0)
1060 return err;
1061
1062
1063
1064
1065 msleep(20);
1066
1067
1068 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1069 if (err < 0)
1070 return err;
1071
1072 mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1073 SD_DAT1_STATUS | SD_DAT0_STATUS;
1074 val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1075 SD_DAT1_STATUS | SD_DAT0_STATUS;
1076 if ((stat & mask) != val) {
1077 dev_dbg(sdmmc_dev(host),
1078 "%s: SD_BUS_STAT = 0x%x\n", __func__, stat);
1079 rtsx_pci_write_register(pcr, SD_BUS_STAT,
1080 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1081 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1082 return -EINVAL;
1083 }
1084
1085 return 0;
1086}
1087
1088static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1089{
1090 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1091 struct rtsx_pcr *pcr = host->pcr;
1092 int err = 0;
1093 u8 voltage;
1094
1095 dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1096 __func__, ios->signal_voltage);
1097
1098 if (host->eject)
1099 return -ENOMEDIUM;
1100
1101 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1102 if (err)
1103 return err;
1104
1105 mutex_lock(&pcr->pcr_mutex);
1106
1107 rtsx_pci_start_run(pcr);
1108
1109 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1110 voltage = OUTPUT_3V3;
1111 else
1112 voltage = OUTPUT_1V8;
1113
1114 if (voltage == OUTPUT_1V8) {
1115 err = sd_wait_voltage_stable_1(host);
1116 if (err < 0)
1117 goto out;
1118 }
1119
1120 err = rtsx_pci_switch_output_voltage(pcr, voltage);
1121 if (err < 0)
1122 goto out;
1123
1124 if (voltage == OUTPUT_1V8) {
1125 err = sd_wait_voltage_stable_2(host);
1126 if (err < 0)
1127 goto out;
1128 }
1129
1130out:
1131
1132 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1133 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1134
1135 mutex_unlock(&pcr->pcr_mutex);
1136
1137 return err;
1138}
1139
1140static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1141{
1142 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1143 struct rtsx_pcr *pcr = host->pcr;
1144 int err = 0;
1145
1146 if (host->eject)
1147 return -ENOMEDIUM;
1148
1149 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1150 if (err)
1151 return err;
1152
1153 mutex_lock(&pcr->pcr_mutex);
1154
1155 rtsx_pci_start_run(pcr);
1156
1157
1158 switch (mmc->ios.timing) {
1159 case MMC_TIMING_UHS_SDR104:
1160 err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false);
1161 break;
1162
1163 case MMC_TIMING_UHS_SDR50:
1164 err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false);
1165 break;
1166
1167 case MMC_TIMING_UHS_DDR50:
1168 err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false);
1169 break;
1170
1171 default:
1172 err = 0;
1173 }
1174
1175 if (err)
1176 goto out;
1177
1178
1179 if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
1180 (mmc->ios.timing == MMC_TIMING_UHS_SDR50))
1181 err = sd_tuning_rx(host, opcode);
1182 else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
1183 err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true);
1184
1185out:
1186 mutex_unlock(&pcr->pcr_mutex);
1187
1188 return err;
1189}
1190
1191static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
1192 .request = sdmmc_request,
1193 .set_ios = sdmmc_set_ios,
1194 .get_ro = sdmmc_get_ro,
1195 .get_cd = sdmmc_get_cd,
1196 .start_signal_voltage_switch = sdmmc_switch_voltage,
1197 .execute_tuning = sdmmc_execute_tuning,
1198};
1199
1200#ifdef CONFIG_PM
1201static int rtsx_pci_sdmmc_suspend(struct platform_device *pdev,
1202 pm_message_t state)
1203{
1204 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1205 struct mmc_host *mmc = host->mmc;
1206 int err;
1207
1208 dev_dbg(sdmmc_dev(host), "--> %s\n", __func__);
1209
1210 err = mmc_suspend_host(mmc);
1211 if (err)
1212 return err;
1213
1214 return 0;
1215}
1216
1217static int rtsx_pci_sdmmc_resume(struct platform_device *pdev)
1218{
1219 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1220 struct mmc_host *mmc = host->mmc;
1221
1222 dev_dbg(sdmmc_dev(host), "--> %s\n", __func__);
1223
1224 return mmc_resume_host(mmc);
1225}
1226#else
1227#define rtsx_pci_sdmmc_suspend NULL
1228#define rtsx_pci_sdmmc_resume NULL
1229#endif
1230
1231static void init_extra_caps(struct realtek_pci_sdmmc *host)
1232{
1233 struct mmc_host *mmc = host->mmc;
1234 struct rtsx_pcr *pcr = host->pcr;
1235
1236 dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1237
1238 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1239 mmc->caps |= MMC_CAP_UHS_SDR50;
1240 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1241 mmc->caps |= MMC_CAP_UHS_SDR104;
1242 if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1243 mmc->caps |= MMC_CAP_UHS_DDR50;
1244 if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1245 mmc->caps |= MMC_CAP_1_8V_DDR;
1246 if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1247 mmc->caps |= MMC_CAP_8_BIT_DATA;
1248}
1249
1250static void realtek_init_host(struct realtek_pci_sdmmc *host)
1251{
1252 struct mmc_host *mmc = host->mmc;
1253
1254 mmc->f_min = 250000;
1255 mmc->f_max = 208000000;
1256 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1257 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1258 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1259 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
1260 mmc->max_current_330 = 400;
1261 mmc->max_current_180 = 800;
1262 mmc->ops = &realtek_pci_sdmmc_ops;
1263
1264 init_extra_caps(host);
1265
1266 mmc->max_segs = 256;
1267 mmc->max_seg_size = 65536;
1268 mmc->max_blk_size = 512;
1269 mmc->max_blk_count = 65535;
1270 mmc->max_req_size = 524288;
1271}
1272
1273static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev)
1274{
1275 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1276
1277 mmc_detect_change(host->mmc, 0);
1278}
1279
1280static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1281{
1282 struct mmc_host *mmc;
1283 struct realtek_pci_sdmmc *host;
1284 struct rtsx_pcr *pcr;
1285 struct pcr_handle *handle = pdev->dev.platform_data;
1286
1287 if (!handle)
1288 return -ENXIO;
1289
1290 pcr = handle->pcr;
1291 if (!pcr)
1292 return -ENXIO;
1293
1294 dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n");
1295
1296 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1297 if (!mmc)
1298 return -ENOMEM;
1299
1300 host = mmc_priv(mmc);
1301 host->pcr = pcr;
1302 host->mmc = mmc;
1303 host->pdev = pdev;
1304 host->power_state = SDMMC_POWER_OFF;
1305 platform_set_drvdata(pdev, host);
1306 pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1307 pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1308
1309 mutex_init(&host->host_mutex);
1310
1311 realtek_init_host(host);
1312
1313 mmc_add_host(mmc);
1314
1315 return 0;
1316}
1317
1318static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1319{
1320 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1321 struct rtsx_pcr *pcr;
1322 struct mmc_host *mmc;
1323
1324 if (!host)
1325 return 0;
1326
1327 pcr = host->pcr;
1328 pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1329 pcr->slots[RTSX_SD_CARD].card_event = NULL;
1330 mmc = host->mmc;
1331 host->eject = true;
1332
1333 mutex_lock(&host->host_mutex);
1334 if (host->mrq) {
1335 dev_dbg(&(pdev->dev),
1336 "%s: Controller removed during transfer\n",
1337 mmc_hostname(mmc));
1338
1339 rtsx_pci_complete_unfinished_transfer(pcr);
1340
1341 host->mrq->cmd->error = -ENOMEDIUM;
1342 if (host->mrq->stop)
1343 host->mrq->stop->error = -ENOMEDIUM;
1344 mmc_request_done(mmc, host->mrq);
1345 }
1346 mutex_unlock(&host->host_mutex);
1347
1348 mmc_remove_host(mmc);
1349 mmc_free_host(mmc);
1350
1351 dev_dbg(&(pdev->dev),
1352 ": Realtek PCI-E SDMMC controller has been removed\n");
1353
1354 return 0;
1355}
1356
1357static struct platform_device_id rtsx_pci_sdmmc_ids[] = {
1358 {
1359 .name = DRV_NAME_RTSX_PCI_SDMMC,
1360 }, {
1361
1362 }
1363};
1364MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids);
1365
1366static struct platform_driver rtsx_pci_sdmmc_driver = {
1367 .probe = rtsx_pci_sdmmc_drv_probe,
1368 .remove = rtsx_pci_sdmmc_drv_remove,
1369 .id_table = rtsx_pci_sdmmc_ids,
1370 .suspend = rtsx_pci_sdmmc_suspend,
1371 .resume = rtsx_pci_sdmmc_resume,
1372 .driver = {
1373 .owner = THIS_MODULE,
1374 .name = DRV_NAME_RTSX_PCI_SDMMC,
1375 },
1376};
1377module_platform_driver(rtsx_pci_sdmmc_driver);
1378
1379MODULE_LICENSE("GPL");
1380MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1381MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");
1382
