linux/drivers/mtd/onenand/samsung.h
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   1/*
   2 * linux/arch/arm/plat-s3c/include/plat/regs-onenand.h
   3 *
   4 *  Copyright (C) 2008-2010 Samsung Electronics
   5 *  Kyungmin Park <kyungmin.park@samsung.com>
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License version 2 as
   9 * published by the Free Software Foundation.
  10 */
  11#ifndef __SAMSUNG_ONENAND_H__
  12#define __SAMSUNG_ONENAND_H__
  13
  14/*
  15 * OneNAND Controller
  16 */
  17#define MEM_CFG_OFFSET          0x0000
  18#define BURST_LEN_OFFSET        0x0010
  19#define MEM_RESET_OFFSET        0x0020
  20#define INT_ERR_STAT_OFFSET     0x0030
  21#define INT_ERR_MASK_OFFSET     0x0040
  22#define INT_ERR_ACK_OFFSET      0x0050
  23#define ECC_ERR_STAT_OFFSET     0x0060
  24#define MANUFACT_ID_OFFSET      0x0070
  25#define DEVICE_ID_OFFSET        0x0080
  26#define DATA_BUF_SIZE_OFFSET    0x0090
  27#define BOOT_BUF_SIZE_OFFSET    0x00A0
  28#define BUF_AMOUNT_OFFSET       0x00B0
  29#define TECH_OFFSET             0x00C0
  30#define FBA_WIDTH_OFFSET        0x00D0
  31#define FPA_WIDTH_OFFSET        0x00E0
  32#define FSA_WIDTH_OFFSET        0x00F0
  33#define TRANS_SPARE_OFFSET      0x0140
  34#define DBS_DFS_WIDTH_OFFSET    0x0160
  35#define INT_PIN_ENABLE_OFFSET   0x01A0
  36#define ACC_CLOCK_OFFSET        0x01C0
  37#define FLASH_VER_ID_OFFSET     0x01F0
  38#define FLASH_AUX_CNTRL_OFFSET  0x0300          /* s3c64xx only */
  39
  40#define ONENAND_MEM_RESET_HOT   0x3
  41#define ONENAND_MEM_RESET_COLD  0x2
  42#define ONENAND_MEM_RESET_WARM  0x1
  43
  44#define CACHE_OP_ERR            (1 << 13)
  45#define RST_CMP                 (1 << 12)
  46#define RDY_ACT                 (1 << 11)
  47#define INT_ACT                 (1 << 10)
  48#define UNSUP_CMD               (1 << 9)
  49#define LOCKED_BLK              (1 << 8)
  50#define BLK_RW_CMP              (1 << 7)
  51#define ERS_CMP                 (1 << 6)
  52#define PGM_CMP                 (1 << 5)
  53#define LOAD_CMP                (1 << 4)
  54#define ERS_FAIL                (1 << 3)
  55#define PGM_FAIL                (1 << 2)
  56#define INT_TO                  (1 << 1)
  57#define LD_FAIL_ECC_ERR         (1 << 0)
  58
  59#define TSRF                    (1 << 0)
  60
  61#endif
  62