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22#include <linux/netdevice.h>
23#include <linux/can.h>
24#include <linux/can/dev.h>
25#include <linux/can/error.h>
26#include <linux/can/led.h>
27#include <linux/clk.h>
28#include <linux/delay.h>
29#include <linux/if_arp.h>
30#include <linux/if_ether.h>
31#include <linux/interrupt.h>
32#include <linux/io.h>
33#include <linux/kernel.h>
34#include <linux/list.h>
35#include <linux/module.h>
36#include <linux/of.h>
37#include <linux/of_device.h>
38#include <linux/platform_device.h>
39#include <linux/regulator/consumer.h>
40
41#define DRV_NAME "flexcan"
42
43
44#define FLEXCAN_NAPI_WEIGHT (8 + 2)
45
46
47#define FLEXCAN_MCR_MDIS BIT(31)
48#define FLEXCAN_MCR_FRZ BIT(30)
49#define FLEXCAN_MCR_FEN BIT(29)
50#define FLEXCAN_MCR_HALT BIT(28)
51#define FLEXCAN_MCR_NOT_RDY BIT(27)
52#define FLEXCAN_MCR_WAK_MSK BIT(26)
53#define FLEXCAN_MCR_SOFTRST BIT(25)
54#define FLEXCAN_MCR_FRZ_ACK BIT(24)
55#define FLEXCAN_MCR_SUPV BIT(23)
56#define FLEXCAN_MCR_SLF_WAK BIT(22)
57#define FLEXCAN_MCR_WRN_EN BIT(21)
58#define FLEXCAN_MCR_LPM_ACK BIT(20)
59#define FLEXCAN_MCR_WAK_SRC BIT(19)
60#define FLEXCAN_MCR_DOZE BIT(18)
61#define FLEXCAN_MCR_SRX_DIS BIT(17)
62#define FLEXCAN_MCR_BCC BIT(16)
63#define FLEXCAN_MCR_LPRIO_EN BIT(13)
64#define FLEXCAN_MCR_AEN BIT(12)
65#define FLEXCAN_MCR_MAXMB(x) ((x) & 0x1f)
66#define FLEXCAN_MCR_IDAM_A (0 << 8)
67#define FLEXCAN_MCR_IDAM_B (1 << 8)
68#define FLEXCAN_MCR_IDAM_C (2 << 8)
69#define FLEXCAN_MCR_IDAM_D (3 << 8)
70
71
72#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
73#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
74#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
75#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
76#define FLEXCAN_CTRL_BOFF_MSK BIT(15)
77#define FLEXCAN_CTRL_ERR_MSK BIT(14)
78#define FLEXCAN_CTRL_CLK_SRC BIT(13)
79#define FLEXCAN_CTRL_LPB BIT(12)
80#define FLEXCAN_CTRL_TWRN_MSK BIT(11)
81#define FLEXCAN_CTRL_RWRN_MSK BIT(10)
82#define FLEXCAN_CTRL_SMP BIT(7)
83#define FLEXCAN_CTRL_BOFF_REC BIT(6)
84#define FLEXCAN_CTRL_TSYN BIT(5)
85#define FLEXCAN_CTRL_LBUF BIT(4)
86#define FLEXCAN_CTRL_LOM BIT(3)
87#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
88#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
89#define FLEXCAN_CTRL_ERR_STATE \
90 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
91 FLEXCAN_CTRL_BOFF_MSK)
92#define FLEXCAN_CTRL_ERR_ALL \
93 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
94
95
96#define FLEXCAN_ESR_TWRN_INT BIT(17)
97#define FLEXCAN_ESR_RWRN_INT BIT(16)
98#define FLEXCAN_ESR_BIT1_ERR BIT(15)
99#define FLEXCAN_ESR_BIT0_ERR BIT(14)
100#define FLEXCAN_ESR_ACK_ERR BIT(13)
101#define FLEXCAN_ESR_CRC_ERR BIT(12)
102#define FLEXCAN_ESR_FRM_ERR BIT(11)
103#define FLEXCAN_ESR_STF_ERR BIT(10)
104#define FLEXCAN_ESR_TX_WRN BIT(9)
105#define FLEXCAN_ESR_RX_WRN BIT(8)
106#define FLEXCAN_ESR_IDLE BIT(7)
107#define FLEXCAN_ESR_TXRX BIT(6)
108#define FLEXCAN_EST_FLT_CONF_SHIFT (4)
109#define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
110#define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
111#define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
112#define FLEXCAN_ESR_BOFF_INT BIT(2)
113#define FLEXCAN_ESR_ERR_INT BIT(1)
114#define FLEXCAN_ESR_WAK_INT BIT(0)
115#define FLEXCAN_ESR_ERR_BUS \
116 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
117 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
118 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
119#define FLEXCAN_ESR_ERR_STATE \
120 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
121#define FLEXCAN_ESR_ERR_ALL \
122 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
123#define FLEXCAN_ESR_ALL_INT \
124 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
125 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
126
127
128#define FLEXCAN_TX_BUF_ID 8
129#define FLEXCAN_IFLAG_BUF(x) BIT(x)
130#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
131#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
132#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
133#define FLEXCAN_IFLAG_DEFAULT \
134 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \
135 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
136
137
138#define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24)
139#define FLEXCAN_MB_CNT_SRR BIT(22)
140#define FLEXCAN_MB_CNT_IDE BIT(21)
141#define FLEXCAN_MB_CNT_RTR BIT(20)
142#define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
143#define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
144
145#define FLEXCAN_MB_CODE_MASK (0xf0ffffff)
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161#define FLEXCAN_HAS_V10_FEATURES BIT(1)
162#define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2)
163
164
165struct flexcan_mb {
166 u32 can_ctrl;
167 u32 can_id;
168 u32 data[2];
169};
170
171
172struct flexcan_regs {
173 u32 mcr;
174 u32 ctrl;
175 u32 timer;
176 u32 _reserved1;
177 u32 rxgmask;
178 u32 rx14mask;
179 u32 rx15mask;
180 u32 ecr;
181 u32 esr;
182 u32 imask2;
183 u32 imask1;
184 u32 iflag2;
185 u32 iflag1;
186 u32 crl2;
187 u32 esr2;
188 u32 imeur;
189 u32 lrfr;
190 u32 crcr;
191 u32 rxfgmask;
192 u32 rxfir;
193 u32 _reserved3[12];
194 struct flexcan_mb cantxfg[64];
195};
196
197struct flexcan_devtype_data {
198 u32 features;
199};
200
201struct flexcan_priv {
202 struct can_priv can;
203 struct net_device *dev;
204 struct napi_struct napi;
205
206 void __iomem *base;
207 u32 reg_esr;
208 u32 reg_ctrl_default;
209
210 struct clk *clk_ipg;
211 struct clk *clk_per;
212 struct flexcan_platform_data *pdata;
213 const struct flexcan_devtype_data *devtype_data;
214 struct regulator *reg_xceiver;
215};
216
217static struct flexcan_devtype_data fsl_p1010_devtype_data = {
218 .features = FLEXCAN_HAS_BROKEN_ERR_STATE,
219};
220static struct flexcan_devtype_data fsl_imx28_devtype_data;
221static struct flexcan_devtype_data fsl_imx6q_devtype_data = {
222 .features = FLEXCAN_HAS_V10_FEATURES,
223};
224
225static const struct can_bittiming_const flexcan_bittiming_const = {
226 .name = DRV_NAME,
227 .tseg1_min = 4,
228 .tseg1_max = 16,
229 .tseg2_min = 2,
230 .tseg2_max = 8,
231 .sjw_max = 4,
232 .brp_min = 1,
233 .brp_max = 256,
234 .brp_inc = 1,
235};
236
237
238
239
240#if defined(__BIG_ENDIAN)
241static inline u32 flexcan_read(void __iomem *addr)
242{
243 return in_be32(addr);
244}
245
246static inline void flexcan_write(u32 val, void __iomem *addr)
247{
248 out_be32(addr, val);
249}
250#else
251static inline u32 flexcan_read(void __iomem *addr)
252{
253 return readl(addr);
254}
255
256static inline void flexcan_write(u32 val, void __iomem *addr)
257{
258 writel(val, addr);
259}
260#endif
261
262static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv,
263 u32 reg_esr)
264{
265 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
266 (reg_esr & FLEXCAN_ESR_ERR_BUS);
267}
268
269static inline void flexcan_chip_enable(struct flexcan_priv *priv)
270{
271 struct flexcan_regs __iomem *regs = priv->base;
272 u32 reg;
273
274 reg = flexcan_read(®s->mcr);
275 reg &= ~FLEXCAN_MCR_MDIS;
276 flexcan_write(reg, ®s->mcr);
277
278 udelay(10);
279}
280
281static inline void flexcan_chip_disable(struct flexcan_priv *priv)
282{
283 struct flexcan_regs __iomem *regs = priv->base;
284 u32 reg;
285
286 reg = flexcan_read(®s->mcr);
287 reg |= FLEXCAN_MCR_MDIS;
288 flexcan_write(reg, ®s->mcr);
289}
290
291static int flexcan_get_berr_counter(const struct net_device *dev,
292 struct can_berr_counter *bec)
293{
294 const struct flexcan_priv *priv = netdev_priv(dev);
295 struct flexcan_regs __iomem *regs = priv->base;
296 u32 reg = flexcan_read(®s->ecr);
297
298 bec->txerr = (reg >> 0) & 0xff;
299 bec->rxerr = (reg >> 8) & 0xff;
300
301 return 0;
302}
303
304static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
305{
306 const struct flexcan_priv *priv = netdev_priv(dev);
307 struct flexcan_regs __iomem *regs = priv->base;
308 struct can_frame *cf = (struct can_frame *)skb->data;
309 u32 can_id;
310 u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16);
311
312 if (can_dropped_invalid_skb(dev, skb))
313 return NETDEV_TX_OK;
314
315 netif_stop_queue(dev);
316
317 if (cf->can_id & CAN_EFF_FLAG) {
318 can_id = cf->can_id & CAN_EFF_MASK;
319 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
320 } else {
321 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
322 }
323
324 if (cf->can_id & CAN_RTR_FLAG)
325 ctrl |= FLEXCAN_MB_CNT_RTR;
326
327 if (cf->can_dlc > 0) {
328 u32 data = be32_to_cpup((__be32 *)&cf->data[0]);
329 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[0]);
330 }
331 if (cf->can_dlc > 3) {
332 u32 data = be32_to_cpup((__be32 *)&cf->data[4]);
333 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[1]);
334 }
335
336 can_put_echo_skb(skb, dev, 0);
337
338 flexcan_write(can_id, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
339 flexcan_write(ctrl, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
340
341 return NETDEV_TX_OK;
342}
343
344static void do_bus_err(struct net_device *dev,
345 struct can_frame *cf, u32 reg_esr)
346{
347 struct flexcan_priv *priv = netdev_priv(dev);
348 int rx_errors = 0, tx_errors = 0;
349
350 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
351
352 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
353 netdev_dbg(dev, "BIT1_ERR irq\n");
354 cf->data[2] |= CAN_ERR_PROT_BIT1;
355 tx_errors = 1;
356 }
357 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
358 netdev_dbg(dev, "BIT0_ERR irq\n");
359 cf->data[2] |= CAN_ERR_PROT_BIT0;
360 tx_errors = 1;
361 }
362 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
363 netdev_dbg(dev, "ACK_ERR irq\n");
364 cf->can_id |= CAN_ERR_ACK;
365 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
366 tx_errors = 1;
367 }
368 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
369 netdev_dbg(dev, "CRC_ERR irq\n");
370 cf->data[2] |= CAN_ERR_PROT_BIT;
371 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
372 rx_errors = 1;
373 }
374 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
375 netdev_dbg(dev, "FRM_ERR irq\n");
376 cf->data[2] |= CAN_ERR_PROT_FORM;
377 rx_errors = 1;
378 }
379 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
380 netdev_dbg(dev, "STF_ERR irq\n");
381 cf->data[2] |= CAN_ERR_PROT_STUFF;
382 rx_errors = 1;
383 }
384
385 priv->can.can_stats.bus_error++;
386 if (rx_errors)
387 dev->stats.rx_errors++;
388 if (tx_errors)
389 dev->stats.tx_errors++;
390}
391
392static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr)
393{
394 struct sk_buff *skb;
395 struct can_frame *cf;
396
397 skb = alloc_can_err_skb(dev, &cf);
398 if (unlikely(!skb))
399 return 0;
400
401 do_bus_err(dev, cf, reg_esr);
402 netif_receive_skb(skb);
403
404 dev->stats.rx_packets++;
405 dev->stats.rx_bytes += cf->can_dlc;
406
407 return 1;
408}
409
410static void do_state(struct net_device *dev,
411 struct can_frame *cf, enum can_state new_state)
412{
413 struct flexcan_priv *priv = netdev_priv(dev);
414 struct can_berr_counter bec;
415
416 flexcan_get_berr_counter(dev, &bec);
417
418 switch (priv->can.state) {
419 case CAN_STATE_ERROR_ACTIVE:
420
421
422
423
424
425 if (new_state >= CAN_STATE_ERROR_WARNING &&
426 new_state <= CAN_STATE_BUS_OFF) {
427 netdev_dbg(dev, "Error Warning IRQ\n");
428 priv->can.can_stats.error_warning++;
429
430 cf->can_id |= CAN_ERR_CRTL;
431 cf->data[1] = (bec.txerr > bec.rxerr) ?
432 CAN_ERR_CRTL_TX_WARNING :
433 CAN_ERR_CRTL_RX_WARNING;
434 }
435 case CAN_STATE_ERROR_WARNING:
436
437
438
439
440
441 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
442 new_state <= CAN_STATE_BUS_OFF) {
443 netdev_dbg(dev, "Error Passive IRQ\n");
444 priv->can.can_stats.error_passive++;
445
446 cf->can_id |= CAN_ERR_CRTL;
447 cf->data[1] = (bec.txerr > bec.rxerr) ?
448 CAN_ERR_CRTL_TX_PASSIVE :
449 CAN_ERR_CRTL_RX_PASSIVE;
450 }
451 break;
452 case CAN_STATE_BUS_OFF:
453 netdev_err(dev, "BUG! "
454 "hardware recovered automatically from BUS_OFF\n");
455 break;
456 default:
457 break;
458 }
459
460
461 switch (new_state) {
462 case CAN_STATE_ERROR_ACTIVE:
463 netdev_dbg(dev, "Error Active\n");
464 cf->can_id |= CAN_ERR_PROT;
465 cf->data[2] = CAN_ERR_PROT_ACTIVE;
466 break;
467 case CAN_STATE_BUS_OFF:
468 cf->can_id |= CAN_ERR_BUSOFF;
469 can_bus_off(dev);
470 break;
471 default:
472 break;
473 }
474}
475
476static int flexcan_poll_state(struct net_device *dev, u32 reg_esr)
477{
478 struct flexcan_priv *priv = netdev_priv(dev);
479 struct sk_buff *skb;
480 struct can_frame *cf;
481 enum can_state new_state;
482 int flt;
483
484 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
485 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
486 if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN |
487 FLEXCAN_ESR_RX_WRN))))
488 new_state = CAN_STATE_ERROR_ACTIVE;
489 else
490 new_state = CAN_STATE_ERROR_WARNING;
491 } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE))
492 new_state = CAN_STATE_ERROR_PASSIVE;
493 else
494 new_state = CAN_STATE_BUS_OFF;
495
496
497 if (likely(new_state == priv->can.state))
498 return 0;
499
500 skb = alloc_can_err_skb(dev, &cf);
501 if (unlikely(!skb))
502 return 0;
503
504 do_state(dev, cf, new_state);
505 priv->can.state = new_state;
506 netif_receive_skb(skb);
507
508 dev->stats.rx_packets++;
509 dev->stats.rx_bytes += cf->can_dlc;
510
511 return 1;
512}
513
514static void flexcan_read_fifo(const struct net_device *dev,
515 struct can_frame *cf)
516{
517 const struct flexcan_priv *priv = netdev_priv(dev);
518 struct flexcan_regs __iomem *regs = priv->base;
519 struct flexcan_mb __iomem *mb = ®s->cantxfg[0];
520 u32 reg_ctrl, reg_id;
521
522 reg_ctrl = flexcan_read(&mb->can_ctrl);
523 reg_id = flexcan_read(&mb->can_id);
524 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
525 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
526 else
527 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
528
529 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
530 cf->can_id |= CAN_RTR_FLAG;
531 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
532
533 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
534 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
535
536
537 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
538 flexcan_read(®s->timer);
539}
540
541static int flexcan_read_frame(struct net_device *dev)
542{
543 struct net_device_stats *stats = &dev->stats;
544 struct can_frame *cf;
545 struct sk_buff *skb;
546
547 skb = alloc_can_skb(dev, &cf);
548 if (unlikely(!skb)) {
549 stats->rx_dropped++;
550 return 0;
551 }
552
553 flexcan_read_fifo(dev, cf);
554 netif_receive_skb(skb);
555
556 stats->rx_packets++;
557 stats->rx_bytes += cf->can_dlc;
558
559 can_led_event(dev, CAN_LED_EVENT_RX);
560
561 return 1;
562}
563
564static int flexcan_poll(struct napi_struct *napi, int quota)
565{
566 struct net_device *dev = napi->dev;
567 const struct flexcan_priv *priv = netdev_priv(dev);
568 struct flexcan_regs __iomem *regs = priv->base;
569 u32 reg_iflag1, reg_esr;
570 int work_done = 0;
571
572
573
574
575
576 reg_esr = flexcan_read(®s->esr) | priv->reg_esr;
577
578
579 work_done += flexcan_poll_state(dev, reg_esr);
580
581
582 reg_iflag1 = flexcan_read(®s->iflag1);
583 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
584 work_done < quota) {
585 work_done += flexcan_read_frame(dev);
586 reg_iflag1 = flexcan_read(®s->iflag1);
587 }
588
589
590 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota)
591 work_done += flexcan_poll_bus_err(dev, reg_esr);
592
593 if (work_done < quota) {
594 napi_complete(napi);
595
596 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1);
597 flexcan_write(priv->reg_ctrl_default, ®s->ctrl);
598 }
599
600 return work_done;
601}
602
603static irqreturn_t flexcan_irq(int irq, void *dev_id)
604{
605 struct net_device *dev = dev_id;
606 struct net_device_stats *stats = &dev->stats;
607 struct flexcan_priv *priv = netdev_priv(dev);
608 struct flexcan_regs __iomem *regs = priv->base;
609 u32 reg_iflag1, reg_esr;
610
611 reg_iflag1 = flexcan_read(®s->iflag1);
612 reg_esr = flexcan_read(®s->esr);
613
614 if (reg_esr & FLEXCAN_ESR_ALL_INT)
615 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr);
616
617
618
619
620
621
622
623 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) ||
624 (reg_esr & FLEXCAN_ESR_ERR_STATE) ||
625 flexcan_has_and_handle_berr(priv, reg_esr)) {
626
627
628
629
630 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
631 flexcan_write(FLEXCAN_IFLAG_DEFAULT &
632 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->imask1);
633 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
634 ®s->ctrl);
635 napi_schedule(&priv->napi);
636 }
637
638
639 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
640 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1);
641 dev->stats.rx_over_errors++;
642 dev->stats.rx_errors++;
643 }
644
645
646 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) {
647 stats->tx_bytes += can_get_echo_skb(dev, 0);
648 stats->tx_packets++;
649 can_led_event(dev, CAN_LED_EVENT_TX);
650 flexcan_write((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1);
651 netif_wake_queue(dev);
652 }
653
654 return IRQ_HANDLED;
655}
656
657static void flexcan_set_bittiming(struct net_device *dev)
658{
659 const struct flexcan_priv *priv = netdev_priv(dev);
660 const struct can_bittiming *bt = &priv->can.bittiming;
661 struct flexcan_regs __iomem *regs = priv->base;
662 u32 reg;
663
664 reg = flexcan_read(®s->ctrl);
665 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
666 FLEXCAN_CTRL_RJW(0x3) |
667 FLEXCAN_CTRL_PSEG1(0x7) |
668 FLEXCAN_CTRL_PSEG2(0x7) |
669 FLEXCAN_CTRL_PROPSEG(0x7) |
670 FLEXCAN_CTRL_LPB |
671 FLEXCAN_CTRL_SMP |
672 FLEXCAN_CTRL_LOM);
673
674 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
675 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
676 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
677 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
678 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
679
680 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
681 reg |= FLEXCAN_CTRL_LPB;
682 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
683 reg |= FLEXCAN_CTRL_LOM;
684 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
685 reg |= FLEXCAN_CTRL_SMP;
686
687 netdev_info(dev, "writing ctrl=0x%08x\n", reg);
688 flexcan_write(reg, ®s->ctrl);
689
690
691 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
692 flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
693}
694
695
696
697
698
699
700
701static int flexcan_chip_start(struct net_device *dev)
702{
703 struct flexcan_priv *priv = netdev_priv(dev);
704 struct flexcan_regs __iomem *regs = priv->base;
705 int err;
706 u32 reg_mcr, reg_ctrl;
707
708
709 flexcan_chip_enable(priv);
710
711
712 flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
713 udelay(10);
714
715 reg_mcr = flexcan_read(®s->mcr);
716 if (reg_mcr & FLEXCAN_MCR_SOFTRST) {
717 netdev_err(dev, "Failed to softreset can module (mcr=0x%08x)\n",
718 reg_mcr);
719 err = -ENODEV;
720 goto out;
721 }
722
723 flexcan_set_bittiming(dev);
724
725
726
727
728
729
730
731
732
733
734
735
736
737 reg_mcr = flexcan_read(®s->mcr);
738 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
739 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
740 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
741 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS |
742 FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
743 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
744 flexcan_write(reg_mcr, ®s->mcr);
745
746
747
748
749
750
751
752
753
754
755
756
757
758 reg_ctrl = flexcan_read(®s->ctrl);
759 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
760 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
761 FLEXCAN_CTRL_ERR_STATE;
762
763
764
765
766
767 if (priv->devtype_data->features & FLEXCAN_HAS_BROKEN_ERR_STATE ||
768 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
769 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
770
771
772 priv->reg_ctrl_default = reg_ctrl;
773 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
774 flexcan_write(reg_ctrl, ®s->ctrl);
775
776
777 flexcan_write(FLEXCAN_MB_CNT_CODE(0x4),
778 ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
779
780
781 flexcan_write(0x0, ®s->rxgmask);
782 flexcan_write(0x0, ®s->rx14mask);
783 flexcan_write(0x0, ®s->rx15mask);
784
785 if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES)
786 flexcan_write(0x0, ®s->rxfgmask);
787
788 if (priv->reg_xceiver) {
789 err = regulator_enable(priv->reg_xceiver);
790 if (err)
791 goto out;
792 }
793
794
795 reg_mcr = flexcan_read(®s->mcr);
796 reg_mcr &= ~FLEXCAN_MCR_HALT;
797 flexcan_write(reg_mcr, ®s->mcr);
798
799 priv->can.state = CAN_STATE_ERROR_ACTIVE;
800
801
802 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1);
803
804
805 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
806 flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
807
808 return 0;
809
810 out:
811 flexcan_chip_disable(priv);
812 return err;
813}
814
815
816
817
818
819
820
821static void flexcan_chip_stop(struct net_device *dev)
822{
823 struct flexcan_priv *priv = netdev_priv(dev);
824 struct flexcan_regs __iomem *regs = priv->base;
825 u32 reg;
826
827
828 flexcan_write(0, ®s->imask1);
829
830
831 reg = flexcan_read(®s->mcr);
832 reg |= FLEXCAN_MCR_MDIS | FLEXCAN_MCR_HALT;
833 flexcan_write(reg, ®s->mcr);
834
835 if (priv->reg_xceiver)
836 regulator_disable(priv->reg_xceiver);
837 priv->can.state = CAN_STATE_STOPPED;
838
839 return;
840}
841
842static int flexcan_open(struct net_device *dev)
843{
844 struct flexcan_priv *priv = netdev_priv(dev);
845 int err;
846
847 err = clk_prepare_enable(priv->clk_ipg);
848 if (err)
849 return err;
850
851 err = clk_prepare_enable(priv->clk_per);
852 if (err)
853 goto out_disable_ipg;
854
855 err = open_candev(dev);
856 if (err)
857 goto out_disable_per;
858
859 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
860 if (err)
861 goto out_close;
862
863
864 err = flexcan_chip_start(dev);
865 if (err)
866 goto out_close;
867
868 can_led_event(dev, CAN_LED_EVENT_OPEN);
869
870 napi_enable(&priv->napi);
871 netif_start_queue(dev);
872
873 return 0;
874
875 out_close:
876 close_candev(dev);
877 out_disable_per:
878 clk_disable_unprepare(priv->clk_per);
879 out_disable_ipg:
880 clk_disable_unprepare(priv->clk_ipg);
881
882 return err;
883}
884
885static int flexcan_close(struct net_device *dev)
886{
887 struct flexcan_priv *priv = netdev_priv(dev);
888
889 netif_stop_queue(dev);
890 napi_disable(&priv->napi);
891 flexcan_chip_stop(dev);
892
893 free_irq(dev->irq, dev);
894 clk_disable_unprepare(priv->clk_per);
895 clk_disable_unprepare(priv->clk_ipg);
896
897 close_candev(dev);
898
899 can_led_event(dev, CAN_LED_EVENT_STOP);
900
901 return 0;
902}
903
904static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
905{
906 int err;
907
908 switch (mode) {
909 case CAN_MODE_START:
910 err = flexcan_chip_start(dev);
911 if (err)
912 return err;
913
914 netif_wake_queue(dev);
915 break;
916
917 default:
918 return -EOPNOTSUPP;
919 }
920
921 return 0;
922}
923
924static const struct net_device_ops flexcan_netdev_ops = {
925 .ndo_open = flexcan_open,
926 .ndo_stop = flexcan_close,
927 .ndo_start_xmit = flexcan_start_xmit,
928};
929
930static int register_flexcandev(struct net_device *dev)
931{
932 struct flexcan_priv *priv = netdev_priv(dev);
933 struct flexcan_regs __iomem *regs = priv->base;
934 u32 reg, err;
935
936 err = clk_prepare_enable(priv->clk_ipg);
937 if (err)
938 return err;
939
940 err = clk_prepare_enable(priv->clk_per);
941 if (err)
942 goto out_disable_ipg;
943
944
945 flexcan_chip_disable(priv);
946 reg = flexcan_read(®s->ctrl);
947 reg |= FLEXCAN_CTRL_CLK_SRC;
948 flexcan_write(reg, ®s->ctrl);
949
950 flexcan_chip_enable(priv);
951
952
953 reg = flexcan_read(®s->mcr);
954 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
955 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
956 flexcan_write(reg, ®s->mcr);
957
958
959
960
961
962
963 reg = flexcan_read(®s->mcr);
964 if (!(reg & FLEXCAN_MCR_FEN)) {
965 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
966 err = -ENODEV;
967 goto out_disable_per;
968 }
969
970 err = register_candev(dev);
971
972 out_disable_per:
973
974 flexcan_chip_disable(priv);
975 clk_disable_unprepare(priv->clk_per);
976 out_disable_ipg:
977 clk_disable_unprepare(priv->clk_ipg);
978
979 return err;
980}
981
982static void unregister_flexcandev(struct net_device *dev)
983{
984 unregister_candev(dev);
985}
986
987static const struct of_device_id flexcan_of_match[] = {
988 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
989 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
990 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
991 { },
992};
993MODULE_DEVICE_TABLE(of, flexcan_of_match);
994
995static const struct platform_device_id flexcan_id_table[] = {
996 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
997 { },
998};
999MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1000
1001static int flexcan_probe(struct platform_device *pdev)
1002{
1003 const struct of_device_id *of_id;
1004 const struct flexcan_devtype_data *devtype_data;
1005 struct net_device *dev;
1006 struct flexcan_priv *priv;
1007 struct resource *mem;
1008 struct clk *clk_ipg = NULL, *clk_per = NULL;
1009 void __iomem *base;
1010 int err, irq;
1011 u32 clock_freq = 0;
1012
1013 if (pdev->dev.of_node)
1014 of_property_read_u32(pdev->dev.of_node,
1015 "clock-frequency", &clock_freq);
1016
1017 if (!clock_freq) {
1018 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1019 if (IS_ERR(clk_ipg)) {
1020 dev_err(&pdev->dev, "no ipg clock defined\n");
1021 return PTR_ERR(clk_ipg);
1022 }
1023 clock_freq = clk_get_rate(clk_ipg);
1024
1025 clk_per = devm_clk_get(&pdev->dev, "per");
1026 if (IS_ERR(clk_per)) {
1027 dev_err(&pdev->dev, "no per clock defined\n");
1028 return PTR_ERR(clk_per);
1029 }
1030 }
1031
1032 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1033 irq = platform_get_irq(pdev, 0);
1034 if (irq <= 0)
1035 return -ENODEV;
1036
1037 base = devm_ioremap_resource(&pdev->dev, mem);
1038 if (IS_ERR(base))
1039 return PTR_ERR(base);
1040
1041 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1042 if (of_id) {
1043 devtype_data = of_id->data;
1044 } else if (pdev->id_entry->driver_data) {
1045 devtype_data = (struct flexcan_devtype_data *)
1046 pdev->id_entry->driver_data;
1047 } else {
1048 return -ENODEV;
1049 }
1050
1051 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1052 if (!dev)
1053 return -ENOMEM;
1054
1055 dev->netdev_ops = &flexcan_netdev_ops;
1056 dev->irq = irq;
1057 dev->flags |= IFF_ECHO;
1058
1059 priv = netdev_priv(dev);
1060 priv->can.clock.freq = clock_freq;
1061 priv->can.bittiming_const = &flexcan_bittiming_const;
1062 priv->can.do_set_mode = flexcan_set_mode;
1063 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1064 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1065 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1066 CAN_CTRLMODE_BERR_REPORTING;
1067 priv->base = base;
1068 priv->dev = dev;
1069 priv->clk_ipg = clk_ipg;
1070 priv->clk_per = clk_per;
1071 priv->pdata = pdev->dev.platform_data;
1072 priv->devtype_data = devtype_data;
1073
1074 priv->reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1075 if (IS_ERR(priv->reg_xceiver))
1076 priv->reg_xceiver = NULL;
1077
1078 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT);
1079
1080 platform_set_drvdata(pdev, dev);
1081 SET_NETDEV_DEV(dev, &pdev->dev);
1082
1083 err = register_flexcandev(dev);
1084 if (err) {
1085 dev_err(&pdev->dev, "registering netdev failed\n");
1086 goto failed_register;
1087 }
1088
1089 devm_can_led_init(dev);
1090
1091 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1092 priv->base, dev->irq);
1093
1094 return 0;
1095
1096 failed_register:
1097 free_candev(dev);
1098 return err;
1099}
1100
1101static int flexcan_remove(struct platform_device *pdev)
1102{
1103 struct net_device *dev = platform_get_drvdata(pdev);
1104
1105 unregister_flexcandev(dev);
1106
1107 free_candev(dev);
1108
1109 return 0;
1110}
1111
1112#ifdef CONFIG_PM_SLEEP
1113static int flexcan_suspend(struct device *device)
1114{
1115 struct net_device *dev = dev_get_drvdata(device);
1116 struct flexcan_priv *priv = netdev_priv(dev);
1117
1118 flexcan_chip_disable(priv);
1119
1120 if (netif_running(dev)) {
1121 netif_stop_queue(dev);
1122 netif_device_detach(dev);
1123 }
1124 priv->can.state = CAN_STATE_SLEEPING;
1125
1126 return 0;
1127}
1128
1129static int flexcan_resume(struct device *device)
1130{
1131 struct net_device *dev = dev_get_drvdata(device);
1132 struct flexcan_priv *priv = netdev_priv(dev);
1133
1134 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1135 if (netif_running(dev)) {
1136 netif_device_attach(dev);
1137 netif_start_queue(dev);
1138 }
1139 flexcan_chip_enable(priv);
1140
1141 return 0;
1142}
1143#endif
1144
1145static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume);
1146
1147static struct platform_driver flexcan_driver = {
1148 .driver = {
1149 .name = DRV_NAME,
1150 .owner = THIS_MODULE,
1151 .pm = &flexcan_pm_ops,
1152 .of_match_table = flexcan_of_match,
1153 },
1154 .probe = flexcan_probe,
1155 .remove = flexcan_remove,
1156 .id_table = flexcan_id_table,
1157};
1158
1159module_platform_driver(flexcan_driver);
1160
1161MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1162 "Marc Kleine-Budde <kernel@pengutronix.de>");
1163MODULE_LICENSE("GPL v2");
1164MODULE_DESCRIPTION("CAN port driver for flexcan based chip");
1165
