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58#include <linux/can/core.h>
59#include <linux/can/dev.h>
60#include <linux/can/led.h>
61#include <linux/can/platform/mcp251x.h>
62#include <linux/completion.h>
63#include <linux/delay.h>
64#include <linux/device.h>
65#include <linux/dma-mapping.h>
66#include <linux/freezer.h>
67#include <linux/interrupt.h>
68#include <linux/io.h>
69#include <linux/kernel.h>
70#include <linux/module.h>
71#include <linux/netdevice.h>
72#include <linux/platform_device.h>
73#include <linux/slab.h>
74#include <linux/spi/spi.h>
75#include <linux/uaccess.h>
76#include <linux/regulator/consumer.h>
77
78
79#define INSTRUCTION_WRITE 0x02
80#define INSTRUCTION_READ 0x03
81#define INSTRUCTION_BIT_MODIFY 0x05
82#define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
83#define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
84#define INSTRUCTION_RESET 0xC0
85#define RTS_TXB0 0x01
86#define RTS_TXB1 0x02
87#define RTS_TXB2 0x04
88#define INSTRUCTION_RTS(n) (0x80 | ((n) & 0x07))
89
90
91
92#define CANSTAT 0x0e
93#define CANCTRL 0x0f
94# define CANCTRL_REQOP_MASK 0xe0
95# define CANCTRL_REQOP_CONF 0x80
96# define CANCTRL_REQOP_LISTEN_ONLY 0x60
97# define CANCTRL_REQOP_LOOPBACK 0x40
98# define CANCTRL_REQOP_SLEEP 0x20
99# define CANCTRL_REQOP_NORMAL 0x00
100# define CANCTRL_OSM 0x08
101# define CANCTRL_ABAT 0x10
102#define TEC 0x1c
103#define REC 0x1d
104#define CNF1 0x2a
105# define CNF1_SJW_SHIFT 6
106#define CNF2 0x29
107# define CNF2_BTLMODE 0x80
108# define CNF2_SAM 0x40
109# define CNF2_PS1_SHIFT 3
110#define CNF3 0x28
111# define CNF3_SOF 0x08
112# define CNF3_WAKFIL 0x04
113# define CNF3_PHSEG2_MASK 0x07
114#define CANINTE 0x2b
115# define CANINTE_MERRE 0x80
116# define CANINTE_WAKIE 0x40
117# define CANINTE_ERRIE 0x20
118# define CANINTE_TX2IE 0x10
119# define CANINTE_TX1IE 0x08
120# define CANINTE_TX0IE 0x04
121# define CANINTE_RX1IE 0x02
122# define CANINTE_RX0IE 0x01
123#define CANINTF 0x2c
124# define CANINTF_MERRF 0x80
125# define CANINTF_WAKIF 0x40
126# define CANINTF_ERRIF 0x20
127# define CANINTF_TX2IF 0x10
128# define CANINTF_TX1IF 0x08
129# define CANINTF_TX0IF 0x04
130# define CANINTF_RX1IF 0x02
131# define CANINTF_RX0IF 0x01
132# define CANINTF_RX (CANINTF_RX0IF | CANINTF_RX1IF)
133# define CANINTF_TX (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)
134# define CANINTF_ERR (CANINTF_ERRIF)
135#define EFLG 0x2d
136# define EFLG_EWARN 0x01
137# define EFLG_RXWAR 0x02
138# define EFLG_TXWAR 0x04
139# define EFLG_RXEP 0x08
140# define EFLG_TXEP 0x10
141# define EFLG_TXBO 0x20
142# define EFLG_RX0OVR 0x40
143# define EFLG_RX1OVR 0x80
144#define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
145# define TXBCTRL_ABTF 0x40
146# define TXBCTRL_MLOA 0x20
147# define TXBCTRL_TXERR 0x10
148# define TXBCTRL_TXREQ 0x08
149#define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
150# define SIDH_SHIFT 3
151#define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
152# define SIDL_SID_MASK 7
153# define SIDL_SID_SHIFT 5
154# define SIDL_EXIDE_SHIFT 3
155# define SIDL_EID_SHIFT 16
156# define SIDL_EID_MASK 3
157#define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
158#define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
159#define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
160# define DLC_RTR_SHIFT 6
161#define TXBCTRL_OFF 0
162#define TXBSIDH_OFF 1
163#define TXBSIDL_OFF 2
164#define TXBEID8_OFF 3
165#define TXBEID0_OFF 4
166#define TXBDLC_OFF 5
167#define TXBDAT_OFF 6
168#define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
169# define RXBCTRL_BUKT 0x04
170# define RXBCTRL_RXM0 0x20
171# define RXBCTRL_RXM1 0x40
172#define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
173# define RXBSIDH_SHIFT 3
174#define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
175# define RXBSIDL_IDE 0x08
176# define RXBSIDL_SRR 0x10
177# define RXBSIDL_EID 3
178# define RXBSIDL_SHIFT 5
179#define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
180#define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
181#define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
182# define RXBDLC_LEN_MASK 0x0f
183# define RXBDLC_RTR 0x40
184#define RXBCTRL_OFF 0
185#define RXBSIDH_OFF 1
186#define RXBSIDL_OFF 2
187#define RXBEID8_OFF 3
188#define RXBEID0_OFF 4
189#define RXBDLC_OFF 5
190#define RXBDAT_OFF 6
191#define RXFSIDH(n) ((n) * 4)
192#define RXFSIDL(n) ((n) * 4 + 1)
193#define RXFEID8(n) ((n) * 4 + 2)
194#define RXFEID0(n) ((n) * 4 + 3)
195#define RXMSIDH(n) ((n) * 4 + 0x20)
196#define RXMSIDL(n) ((n) * 4 + 0x21)
197#define RXMEID8(n) ((n) * 4 + 0x22)
198#define RXMEID0(n) ((n) * 4 + 0x23)
199
200#define GET_BYTE(val, byte) \
201 (((val) >> ((byte) * 8)) & 0xff)
202#define SET_BYTE(val, byte) \
203 (((val) & 0xff) << ((byte) * 8))
204
205
206
207
208
209#define CAN_FRAME_MAX_DATA_LEN 8
210#define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
211#define CAN_FRAME_MAX_BITS 128
212
213#define TX_ECHO_SKB_MAX 1
214
215#define DEVICE_NAME "mcp251x"
216
217static int mcp251x_enable_dma;
218module_param(mcp251x_enable_dma, int, S_IRUGO);
219MODULE_PARM_DESC(mcp251x_enable_dma, "Enable SPI DMA. Default: 0 (Off)");
220
221static const struct can_bittiming_const mcp251x_bittiming_const = {
222 .name = DEVICE_NAME,
223 .tseg1_min = 3,
224 .tseg1_max = 16,
225 .tseg2_min = 2,
226 .tseg2_max = 8,
227 .sjw_max = 4,
228 .brp_min = 1,
229 .brp_max = 64,
230 .brp_inc = 1,
231};
232
233enum mcp251x_model {
234 CAN_MCP251X_MCP2510 = 0x2510,
235 CAN_MCP251X_MCP2515 = 0x2515,
236};
237
238struct mcp251x_priv {
239 struct can_priv can;
240 struct net_device *net;
241 struct spi_device *spi;
242 enum mcp251x_model model;
243
244 struct mutex mcp_lock;
245
246 u8 *spi_tx_buf;
247 u8 *spi_rx_buf;
248 dma_addr_t spi_tx_dma;
249 dma_addr_t spi_rx_dma;
250
251 struct sk_buff *tx_skb;
252 int tx_len;
253
254 struct workqueue_struct *wq;
255 struct work_struct tx_work;
256 struct work_struct restart_work;
257
258 int force_quit;
259 int after_suspend;
260#define AFTER_SUSPEND_UP 1
261#define AFTER_SUSPEND_DOWN 2
262#define AFTER_SUSPEND_POWER 4
263#define AFTER_SUSPEND_RESTART 8
264 int restart_tx;
265 struct regulator *power;
266 struct regulator *transceiver;
267};
268
269#define MCP251X_IS(_model) \
270static inline int mcp251x_is_##_model(struct spi_device *spi) \
271{ \
272 struct mcp251x_priv *priv = spi_get_drvdata(spi); \
273 return priv->model == CAN_MCP251X_MCP##_model; \
274}
275
276MCP251X_IS(2510);
277MCP251X_IS(2515);
278
279static void mcp251x_clean(struct net_device *net)
280{
281 struct mcp251x_priv *priv = netdev_priv(net);
282
283 if (priv->tx_skb || priv->tx_len)
284 net->stats.tx_errors++;
285 if (priv->tx_skb)
286 dev_kfree_skb(priv->tx_skb);
287 if (priv->tx_len)
288 can_free_echo_skb(priv->net, 0);
289 priv->tx_skb = NULL;
290 priv->tx_len = 0;
291}
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306static int mcp251x_spi_trans(struct spi_device *spi, int len)
307{
308 struct mcp251x_priv *priv = spi_get_drvdata(spi);
309 struct spi_transfer t = {
310 .tx_buf = priv->spi_tx_buf,
311 .rx_buf = priv->spi_rx_buf,
312 .len = len,
313 .cs_change = 0,
314 };
315 struct spi_message m;
316 int ret;
317
318 spi_message_init(&m);
319
320 if (mcp251x_enable_dma) {
321 t.tx_dma = priv->spi_tx_dma;
322 t.rx_dma = priv->spi_rx_dma;
323 m.is_dma_mapped = 1;
324 }
325
326 spi_message_add_tail(&t, &m);
327
328 ret = spi_sync(spi, &m);
329 if (ret)
330 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
331 return ret;
332}
333
334static u8 mcp251x_read_reg(struct spi_device *spi, uint8_t reg)
335{
336 struct mcp251x_priv *priv = spi_get_drvdata(spi);
337 u8 val = 0;
338
339 priv->spi_tx_buf[0] = INSTRUCTION_READ;
340 priv->spi_tx_buf[1] = reg;
341
342 mcp251x_spi_trans(spi, 3);
343 val = priv->spi_rx_buf[2];
344
345 return val;
346}
347
348static void mcp251x_read_2regs(struct spi_device *spi, uint8_t reg,
349 uint8_t *v1, uint8_t *v2)
350{
351 struct mcp251x_priv *priv = spi_get_drvdata(spi);
352
353 priv->spi_tx_buf[0] = INSTRUCTION_READ;
354 priv->spi_tx_buf[1] = reg;
355
356 mcp251x_spi_trans(spi, 4);
357
358 *v1 = priv->spi_rx_buf[2];
359 *v2 = priv->spi_rx_buf[3];
360}
361
362static void mcp251x_write_reg(struct spi_device *spi, u8 reg, uint8_t val)
363{
364 struct mcp251x_priv *priv = spi_get_drvdata(spi);
365
366 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
367 priv->spi_tx_buf[1] = reg;
368 priv->spi_tx_buf[2] = val;
369
370 mcp251x_spi_trans(spi, 3);
371}
372
373static void mcp251x_write_bits(struct spi_device *spi, u8 reg,
374 u8 mask, uint8_t val)
375{
376 struct mcp251x_priv *priv = spi_get_drvdata(spi);
377
378 priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY;
379 priv->spi_tx_buf[1] = reg;
380 priv->spi_tx_buf[2] = mask;
381 priv->spi_tx_buf[3] = val;
382
383 mcp251x_spi_trans(spi, 4);
384}
385
386static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf,
387 int len, int tx_buf_idx)
388{
389 struct mcp251x_priv *priv = spi_get_drvdata(spi);
390
391 if (mcp251x_is_2510(spi)) {
392 int i;
393
394 for (i = 1; i < TXBDAT_OFF + len; i++)
395 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i,
396 buf[i]);
397 } else {
398 memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len);
399 mcp251x_spi_trans(spi, TXBDAT_OFF + len);
400 }
401}
402
403static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame,
404 int tx_buf_idx)
405{
406 struct mcp251x_priv *priv = spi_get_drvdata(spi);
407 u32 sid, eid, exide, rtr;
408 u8 buf[SPI_TRANSFER_BUF_LEN];
409
410 exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0;
411 if (exide)
412 sid = (frame->can_id & CAN_EFF_MASK) >> 18;
413 else
414 sid = frame->can_id & CAN_SFF_MASK;
415 eid = frame->can_id & CAN_EFF_MASK;
416 rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0;
417
418 buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx);
419 buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT;
420 buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) |
421 (exide << SIDL_EXIDE_SHIFT) |
422 ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK);
423 buf[TXBEID8_OFF] = GET_BYTE(eid, 1);
424 buf[TXBEID0_OFF] = GET_BYTE(eid, 0);
425 buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc;
426 memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc);
427 mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx);
428
429
430 priv->spi_tx_buf[0] = INSTRUCTION_RTS(1 << tx_buf_idx);
431 mcp251x_spi_trans(priv->spi, 1);
432}
433
434static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf,
435 int buf_idx)
436{
437 struct mcp251x_priv *priv = spi_get_drvdata(spi);
438
439 if (mcp251x_is_2510(spi)) {
440 int i, len;
441
442 for (i = 1; i < RXBDAT_OFF; i++)
443 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
444
445 len = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
446 for (; i < (RXBDAT_OFF + len); i++)
447 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
448 } else {
449 priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx);
450 mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN);
451 memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN);
452 }
453}
454
455static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx)
456{
457 struct mcp251x_priv *priv = spi_get_drvdata(spi);
458 struct sk_buff *skb;
459 struct can_frame *frame;
460 u8 buf[SPI_TRANSFER_BUF_LEN];
461
462 skb = alloc_can_skb(priv->net, &frame);
463 if (!skb) {
464 dev_err(&spi->dev, "cannot allocate RX skb\n");
465 priv->net->stats.rx_dropped++;
466 return;
467 }
468
469 mcp251x_hw_rx_frame(spi, buf, buf_idx);
470 if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) {
471
472 frame->can_id = CAN_EFF_FLAG;
473 frame->can_id |=
474
475 SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) |
476 SET_BYTE(buf[RXBEID8_OFF], 1) |
477 SET_BYTE(buf[RXBEID0_OFF], 0) |
478
479 (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
480 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18);
481
482 if (buf[RXBDLC_OFF] & RXBDLC_RTR)
483 frame->can_id |= CAN_RTR_FLAG;
484 } else {
485
486 frame->can_id =
487 (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
488 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT);
489 if (buf[RXBSIDL_OFF] & RXBSIDL_SRR)
490 frame->can_id |= CAN_RTR_FLAG;
491 }
492
493 frame->can_dlc = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
494 memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc);
495
496 priv->net->stats.rx_packets++;
497 priv->net->stats.rx_bytes += frame->can_dlc;
498
499 can_led_event(priv->net, CAN_LED_EVENT_RX);
500
501 netif_rx_ni(skb);
502}
503
504static void mcp251x_hw_sleep(struct spi_device *spi)
505{
506 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
507}
508
509static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb,
510 struct net_device *net)
511{
512 struct mcp251x_priv *priv = netdev_priv(net);
513 struct spi_device *spi = priv->spi;
514
515 if (priv->tx_skb || priv->tx_len) {
516 dev_warn(&spi->dev, "hard_xmit called while tx busy\n");
517 return NETDEV_TX_BUSY;
518 }
519
520 if (can_dropped_invalid_skb(net, skb))
521 return NETDEV_TX_OK;
522
523 netif_stop_queue(net);
524 priv->tx_skb = skb;
525 queue_work(priv->wq, &priv->tx_work);
526
527 return NETDEV_TX_OK;
528}
529
530static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode)
531{
532 struct mcp251x_priv *priv = netdev_priv(net);
533
534 switch (mode) {
535 case CAN_MODE_START:
536 mcp251x_clean(net);
537
538 priv->can.state = CAN_STATE_ERROR_ACTIVE;
539 priv->restart_tx = 1;
540 if (priv->can.restart_ms == 0)
541 priv->after_suspend = AFTER_SUSPEND_RESTART;
542 queue_work(priv->wq, &priv->restart_work);
543 break;
544 default:
545 return -EOPNOTSUPP;
546 }
547
548 return 0;
549}
550
551static int mcp251x_set_normal_mode(struct spi_device *spi)
552{
553 struct mcp251x_priv *priv = spi_get_drvdata(spi);
554 unsigned long timeout;
555
556
557 mcp251x_write_reg(spi, CANINTE,
558 CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE |
559 CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE);
560
561 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
562
563 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK);
564 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
565
566 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY);
567 } else {
568
569 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL);
570
571
572 timeout = jiffies + HZ;
573 while (mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) {
574 schedule();
575 if (time_after(jiffies, timeout)) {
576 dev_err(&spi->dev, "MCP251x didn't"
577 " enter in normal mode\n");
578 return -EBUSY;
579 }
580 }
581 }
582 priv->can.state = CAN_STATE_ERROR_ACTIVE;
583 return 0;
584}
585
586static int mcp251x_do_set_bittiming(struct net_device *net)
587{
588 struct mcp251x_priv *priv = netdev_priv(net);
589 struct can_bittiming *bt = &priv->can.bittiming;
590 struct spi_device *spi = priv->spi;
591
592 mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) |
593 (bt->brp - 1));
594 mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE |
595 (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
596 CNF2_SAM : 0) |
597 ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) |
598 (bt->prop_seg - 1));
599 mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK,
600 (bt->phase_seg2 - 1));
601 dev_info(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n",
602 mcp251x_read_reg(spi, CNF1),
603 mcp251x_read_reg(spi, CNF2),
604 mcp251x_read_reg(spi, CNF3));
605
606 return 0;
607}
608
609static int mcp251x_setup(struct net_device *net, struct mcp251x_priv *priv,
610 struct spi_device *spi)
611{
612 mcp251x_do_set_bittiming(net);
613
614 mcp251x_write_reg(spi, RXBCTRL(0),
615 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1);
616 mcp251x_write_reg(spi, RXBCTRL(1),
617 RXBCTRL_RXM0 | RXBCTRL_RXM1);
618 return 0;
619}
620
621static int mcp251x_hw_reset(struct spi_device *spi)
622{
623 struct mcp251x_priv *priv = spi_get_drvdata(spi);
624 int ret;
625 unsigned long timeout;
626
627 priv->spi_tx_buf[0] = INSTRUCTION_RESET;
628 ret = spi_write(spi, priv->spi_tx_buf, 1);
629 if (ret) {
630 dev_err(&spi->dev, "reset failed: ret = %d\n", ret);
631 return -EIO;
632 }
633
634
635 timeout = jiffies + HZ;
636 mdelay(10);
637 while ((mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK)
638 != CANCTRL_REQOP_CONF) {
639 schedule();
640 if (time_after(jiffies, timeout)) {
641 dev_err(&spi->dev, "MCP251x didn't"
642 " enter in conf mode after reset\n");
643 return -EBUSY;
644 }
645 }
646 return 0;
647}
648
649static int mcp251x_hw_probe(struct spi_device *spi)
650{
651 int st1, st2;
652
653 mcp251x_hw_reset(spi);
654
655
656
657
658
659
660
661 st1 = mcp251x_read_reg(spi, CANSTAT) & 0xEE;
662 st2 = mcp251x_read_reg(spi, CANCTRL) & 0x17;
663
664 dev_dbg(&spi->dev, "CANSTAT 0x%02x CANCTRL 0x%02x\n", st1, st2);
665
666
667 return (st1 == 0x80 && st2 == 0x07) ? 1 : 0;
668}
669
670static int mcp251x_power_enable(struct regulator *reg, int enable)
671{
672 if (IS_ERR(reg))
673 return 0;
674
675 if (enable)
676 return regulator_enable(reg);
677 else
678 return regulator_disable(reg);
679}
680
681static void mcp251x_open_clean(struct net_device *net)
682{
683 struct mcp251x_priv *priv = netdev_priv(net);
684 struct spi_device *spi = priv->spi;
685
686 free_irq(spi->irq, priv);
687 mcp251x_hw_sleep(spi);
688 mcp251x_power_enable(priv->transceiver, 0);
689 close_candev(net);
690}
691
692static int mcp251x_stop(struct net_device *net)
693{
694 struct mcp251x_priv *priv = netdev_priv(net);
695 struct spi_device *spi = priv->spi;
696
697 close_candev(net);
698
699 priv->force_quit = 1;
700 free_irq(spi->irq, priv);
701 destroy_workqueue(priv->wq);
702 priv->wq = NULL;
703
704 mutex_lock(&priv->mcp_lock);
705
706
707 mcp251x_write_reg(spi, CANINTE, 0x00);
708 mcp251x_write_reg(spi, CANINTF, 0x00);
709
710 mcp251x_write_reg(spi, TXBCTRL(0), 0);
711 mcp251x_clean(net);
712
713 mcp251x_hw_sleep(spi);
714
715 mcp251x_power_enable(priv->transceiver, 0);
716
717 priv->can.state = CAN_STATE_STOPPED;
718
719 mutex_unlock(&priv->mcp_lock);
720
721 can_led_event(net, CAN_LED_EVENT_STOP);
722
723 return 0;
724}
725
726static void mcp251x_error_skb(struct net_device *net, int can_id, int data1)
727{
728 struct sk_buff *skb;
729 struct can_frame *frame;
730
731 skb = alloc_can_err_skb(net, &frame);
732 if (skb) {
733 frame->can_id |= can_id;
734 frame->data[1] = data1;
735 netif_rx_ni(skb);
736 } else {
737 netdev_err(net, "cannot allocate error skb\n");
738 }
739}
740
741static void mcp251x_tx_work_handler(struct work_struct *ws)
742{
743 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
744 tx_work);
745 struct spi_device *spi = priv->spi;
746 struct net_device *net = priv->net;
747 struct can_frame *frame;
748
749 mutex_lock(&priv->mcp_lock);
750 if (priv->tx_skb) {
751 if (priv->can.state == CAN_STATE_BUS_OFF) {
752 mcp251x_clean(net);
753 } else {
754 frame = (struct can_frame *)priv->tx_skb->data;
755
756 if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN)
757 frame->can_dlc = CAN_FRAME_MAX_DATA_LEN;
758 mcp251x_hw_tx(spi, frame, 0);
759 priv->tx_len = 1 + frame->can_dlc;
760 can_put_echo_skb(priv->tx_skb, net, 0);
761 priv->tx_skb = NULL;
762 }
763 }
764 mutex_unlock(&priv->mcp_lock);
765}
766
767static void mcp251x_restart_work_handler(struct work_struct *ws)
768{
769 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
770 restart_work);
771 struct spi_device *spi = priv->spi;
772 struct net_device *net = priv->net;
773
774 mutex_lock(&priv->mcp_lock);
775 if (priv->after_suspend) {
776 mdelay(10);
777 mcp251x_hw_reset(spi);
778 mcp251x_setup(net, priv, spi);
779 if (priv->after_suspend & AFTER_SUSPEND_RESTART) {
780 mcp251x_set_normal_mode(spi);
781 } else if (priv->after_suspend & AFTER_SUSPEND_UP) {
782 netif_device_attach(net);
783 mcp251x_clean(net);
784 mcp251x_set_normal_mode(spi);
785 netif_wake_queue(net);
786 } else {
787 mcp251x_hw_sleep(spi);
788 }
789 priv->after_suspend = 0;
790 priv->force_quit = 0;
791 }
792
793 if (priv->restart_tx) {
794 priv->restart_tx = 0;
795 mcp251x_write_reg(spi, TXBCTRL(0), 0);
796 mcp251x_clean(net);
797 netif_wake_queue(net);
798 mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0);
799 }
800 mutex_unlock(&priv->mcp_lock);
801}
802
803static irqreturn_t mcp251x_can_ist(int irq, void *dev_id)
804{
805 struct mcp251x_priv *priv = dev_id;
806 struct spi_device *spi = priv->spi;
807 struct net_device *net = priv->net;
808
809 mutex_lock(&priv->mcp_lock);
810 while (!priv->force_quit) {
811 enum can_state new_state;
812 u8 intf, eflag;
813 u8 clear_intf = 0;
814 int can_id = 0, data1 = 0;
815
816 mcp251x_read_2regs(spi, CANINTF, &intf, &eflag);
817
818
819 intf &= CANINTF_RX | CANINTF_TX | CANINTF_ERR;
820
821
822 if (intf & CANINTF_RX0IF) {
823 mcp251x_hw_rx(spi, 0);
824
825
826
827
828 if (mcp251x_is_2510(spi))
829 mcp251x_write_bits(spi, CANINTF, CANINTF_RX0IF, 0x00);
830 }
831
832
833 if (intf & CANINTF_RX1IF) {
834 mcp251x_hw_rx(spi, 1);
835
836 if (mcp251x_is_2510(spi))
837 clear_intf |= CANINTF_RX1IF;
838 }
839
840
841 if (intf & (CANINTF_ERR | CANINTF_TX))
842 clear_intf |= intf & (CANINTF_ERR | CANINTF_TX);
843 if (clear_intf)
844 mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00);
845
846 if (eflag)
847 mcp251x_write_bits(spi, EFLG, eflag, 0x00);
848
849
850 if (eflag & EFLG_TXBO) {
851 new_state = CAN_STATE_BUS_OFF;
852 can_id |= CAN_ERR_BUSOFF;
853 } else if (eflag & EFLG_TXEP) {
854 new_state = CAN_STATE_ERROR_PASSIVE;
855 can_id |= CAN_ERR_CRTL;
856 data1 |= CAN_ERR_CRTL_TX_PASSIVE;
857 } else if (eflag & EFLG_RXEP) {
858 new_state = CAN_STATE_ERROR_PASSIVE;
859 can_id |= CAN_ERR_CRTL;
860 data1 |= CAN_ERR_CRTL_RX_PASSIVE;
861 } else if (eflag & EFLG_TXWAR) {
862 new_state = CAN_STATE_ERROR_WARNING;
863 can_id |= CAN_ERR_CRTL;
864 data1 |= CAN_ERR_CRTL_TX_WARNING;
865 } else if (eflag & EFLG_RXWAR) {
866 new_state = CAN_STATE_ERROR_WARNING;
867 can_id |= CAN_ERR_CRTL;
868 data1 |= CAN_ERR_CRTL_RX_WARNING;
869 } else {
870 new_state = CAN_STATE_ERROR_ACTIVE;
871 }
872
873
874 switch (priv->can.state) {
875 case CAN_STATE_ERROR_ACTIVE:
876 if (new_state >= CAN_STATE_ERROR_WARNING &&
877 new_state <= CAN_STATE_BUS_OFF)
878 priv->can.can_stats.error_warning++;
879 case CAN_STATE_ERROR_WARNING:
880 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
881 new_state <= CAN_STATE_BUS_OFF)
882 priv->can.can_stats.error_passive++;
883 break;
884 default:
885 break;
886 }
887 priv->can.state = new_state;
888
889 if (intf & CANINTF_ERRIF) {
890
891 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) {
892 if (eflag & EFLG_RX0OVR) {
893 net->stats.rx_over_errors++;
894 net->stats.rx_errors++;
895 }
896 if (eflag & EFLG_RX1OVR) {
897 net->stats.rx_over_errors++;
898 net->stats.rx_errors++;
899 }
900 can_id |= CAN_ERR_CRTL;
901 data1 |= CAN_ERR_CRTL_RX_OVERFLOW;
902 }
903 mcp251x_error_skb(net, can_id, data1);
904 }
905
906 if (priv->can.state == CAN_STATE_BUS_OFF) {
907 if (priv->can.restart_ms == 0) {
908 priv->force_quit = 1;
909 can_bus_off(net);
910 mcp251x_hw_sleep(spi);
911 break;
912 }
913 }
914
915 if (intf == 0)
916 break;
917
918 if (intf & CANINTF_TX) {
919 net->stats.tx_packets++;
920 net->stats.tx_bytes += priv->tx_len - 1;
921 can_led_event(net, CAN_LED_EVENT_TX);
922 if (priv->tx_len) {
923 can_get_echo_skb(net, 0);
924 priv->tx_len = 0;
925 }
926 netif_wake_queue(net);
927 }
928
929 }
930 mutex_unlock(&priv->mcp_lock);
931 return IRQ_HANDLED;
932}
933
934static int mcp251x_open(struct net_device *net)
935{
936 struct mcp251x_priv *priv = netdev_priv(net);
937 struct spi_device *spi = priv->spi;
938 unsigned long flags = IRQF_ONESHOT | IRQF_TRIGGER_FALLING;
939 int ret;
940
941 ret = open_candev(net);
942 if (ret) {
943 dev_err(&spi->dev, "unable to set initial baudrate!\n");
944 return ret;
945 }
946
947 mutex_lock(&priv->mcp_lock);
948 mcp251x_power_enable(priv->transceiver, 1);
949
950 priv->force_quit = 0;
951 priv->tx_skb = NULL;
952 priv->tx_len = 0;
953
954 ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist,
955 flags, DEVICE_NAME, priv);
956 if (ret) {
957 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
958 mcp251x_power_enable(priv->transceiver, 0);
959 close_candev(net);
960 goto open_unlock;
961 }
962
963 priv->wq = create_freezable_workqueue("mcp251x_wq");
964 INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler);
965 INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler);
966
967 ret = mcp251x_hw_reset(spi);
968 if (ret) {
969 mcp251x_open_clean(net);
970 goto open_unlock;
971 }
972 ret = mcp251x_setup(net, priv, spi);
973 if (ret) {
974 mcp251x_open_clean(net);
975 goto open_unlock;
976 }
977 ret = mcp251x_set_normal_mode(spi);
978 if (ret) {
979 mcp251x_open_clean(net);
980 goto open_unlock;
981 }
982
983 can_led_event(net, CAN_LED_EVENT_OPEN);
984
985 netif_wake_queue(net);
986
987open_unlock:
988 mutex_unlock(&priv->mcp_lock);
989 return ret;
990}
991
992static const struct net_device_ops mcp251x_netdev_ops = {
993 .ndo_open = mcp251x_open,
994 .ndo_stop = mcp251x_stop,
995 .ndo_start_xmit = mcp251x_hard_start_xmit,
996};
997
998static int mcp251x_can_probe(struct spi_device *spi)
999{
1000 struct net_device *net;
1001 struct mcp251x_priv *priv;
1002 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1003 int ret = -ENODEV;
1004
1005 if (!pdata)
1006
1007 goto error_out;
1008
1009
1010 net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX);
1011 if (!net) {
1012 ret = -ENOMEM;
1013 goto error_alloc;
1014 }
1015
1016 net->netdev_ops = &mcp251x_netdev_ops;
1017 net->flags |= IFF_ECHO;
1018
1019 priv = netdev_priv(net);
1020 priv->can.bittiming_const = &mcp251x_bittiming_const;
1021 priv->can.do_set_mode = mcp251x_do_set_mode;
1022 priv->can.clock.freq = pdata->oscillator_frequency / 2;
1023 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
1024 CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY;
1025 priv->model = spi_get_device_id(spi)->driver_data;
1026 priv->net = net;
1027
1028 priv->power = devm_regulator_get(&spi->dev, "vdd");
1029 priv->transceiver = devm_regulator_get(&spi->dev, "xceiver");
1030 if ((PTR_ERR(priv->power) == -EPROBE_DEFER) ||
1031 (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) {
1032 ret = -EPROBE_DEFER;
1033 goto error_power;
1034 }
1035
1036 ret = mcp251x_power_enable(priv->power, 1);
1037 if (ret)
1038 goto error_power;
1039
1040 spi_set_drvdata(spi, priv);
1041
1042 priv->spi = spi;
1043 mutex_init(&priv->mcp_lock);
1044
1045
1046 if (mcp251x_enable_dma) {
1047 spi->dev.coherent_dma_mask = ~0;
1048
1049
1050
1051
1052
1053 priv->spi_tx_buf = dma_alloc_coherent(&spi->dev,
1054 PAGE_SIZE,
1055 &priv->spi_tx_dma,
1056 GFP_DMA);
1057
1058 if (priv->spi_tx_buf) {
1059 priv->spi_rx_buf = (priv->spi_tx_buf + (PAGE_SIZE / 2));
1060 priv->spi_rx_dma = (dma_addr_t)(priv->spi_tx_dma +
1061 (PAGE_SIZE / 2));
1062 } else {
1063
1064 mcp251x_enable_dma = 0;
1065 }
1066 }
1067
1068
1069 if (!mcp251x_enable_dma) {
1070 priv->spi_tx_buf = kmalloc(SPI_TRANSFER_BUF_LEN, GFP_KERNEL);
1071 if (!priv->spi_tx_buf) {
1072 ret = -ENOMEM;
1073 goto error_tx_buf;
1074 }
1075 priv->spi_rx_buf = kmalloc(SPI_TRANSFER_BUF_LEN, GFP_KERNEL);
1076 if (!priv->spi_rx_buf) {
1077 ret = -ENOMEM;
1078 goto error_rx_buf;
1079 }
1080 }
1081
1082 SET_NETDEV_DEV(net, &spi->dev);
1083
1084
1085 spi->mode = spi->mode ? : SPI_MODE_0;
1086 if (mcp251x_is_2510(spi))
1087 spi->max_speed_hz = spi->max_speed_hz ? : 5 * 1000 * 1000;
1088 else
1089 spi->max_speed_hz = spi->max_speed_hz ? : 10 * 1000 * 1000;
1090 spi->bits_per_word = 8;
1091 spi_setup(spi);
1092
1093
1094 if (!mcp251x_hw_probe(spi)) {
1095 ret = -ENODEV;
1096 goto error_probe;
1097 }
1098 mcp251x_hw_sleep(spi);
1099
1100 ret = register_candev(net);
1101 if (ret)
1102 goto error_probe;
1103
1104 devm_can_led_init(net);
1105
1106 dev_info(&spi->dev, "probed\n");
1107
1108 return ret;
1109
1110error_probe:
1111 if (!mcp251x_enable_dma)
1112 kfree(priv->spi_rx_buf);
1113error_rx_buf:
1114 if (!mcp251x_enable_dma)
1115 kfree(priv->spi_tx_buf);
1116error_tx_buf:
1117 if (mcp251x_enable_dma)
1118 dma_free_coherent(&spi->dev, PAGE_SIZE,
1119 priv->spi_tx_buf, priv->spi_tx_dma);
1120 mcp251x_power_enable(priv->power, 0);
1121error_power:
1122 free_candev(net);
1123error_alloc:
1124 dev_err(&spi->dev, "probe failed\n");
1125error_out:
1126 return ret;
1127}
1128
1129static int mcp251x_can_remove(struct spi_device *spi)
1130{
1131 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1132 struct net_device *net = priv->net;
1133
1134 unregister_candev(net);
1135
1136 if (mcp251x_enable_dma) {
1137 dma_free_coherent(&spi->dev, PAGE_SIZE,
1138 priv->spi_tx_buf, priv->spi_tx_dma);
1139 } else {
1140 kfree(priv->spi_tx_buf);
1141 kfree(priv->spi_rx_buf);
1142 }
1143
1144 mcp251x_power_enable(priv->power, 0);
1145
1146 free_candev(net);
1147
1148 return 0;
1149}
1150
1151#ifdef CONFIG_PM_SLEEP
1152
1153static int mcp251x_can_suspend(struct device *dev)
1154{
1155 struct spi_device *spi = to_spi_device(dev);
1156 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1157 struct net_device *net = priv->net;
1158
1159 priv->force_quit = 1;
1160 disable_irq(spi->irq);
1161
1162
1163
1164
1165 if (netif_running(net)) {
1166 netif_device_detach(net);
1167
1168 mcp251x_hw_sleep(spi);
1169 mcp251x_power_enable(priv->transceiver, 0);
1170 priv->after_suspend = AFTER_SUSPEND_UP;
1171 } else {
1172 priv->after_suspend = AFTER_SUSPEND_DOWN;
1173 }
1174
1175 if (!IS_ERR(priv->power)) {
1176 regulator_disable(priv->power);
1177 priv->after_suspend |= AFTER_SUSPEND_POWER;
1178 }
1179
1180 return 0;
1181}
1182
1183static int mcp251x_can_resume(struct device *dev)
1184{
1185 struct spi_device *spi = to_spi_device(dev);
1186 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1187
1188 if (priv->after_suspend & AFTER_SUSPEND_POWER) {
1189 mcp251x_power_enable(priv->power, 1);
1190 queue_work(priv->wq, &priv->restart_work);
1191 } else {
1192 if (priv->after_suspend & AFTER_SUSPEND_UP) {
1193 mcp251x_power_enable(priv->transceiver, 1);
1194 queue_work(priv->wq, &priv->restart_work);
1195 } else {
1196 priv->after_suspend = 0;
1197 }
1198 }
1199 priv->force_quit = 0;
1200 enable_irq(spi->irq);
1201 return 0;
1202}
1203#endif
1204
1205static SIMPLE_DEV_PM_OPS(mcp251x_can_pm_ops, mcp251x_can_suspend,
1206 mcp251x_can_resume);
1207
1208static const struct spi_device_id mcp251x_id_table[] = {
1209 { "mcp2510", CAN_MCP251X_MCP2510 },
1210 { "mcp2515", CAN_MCP251X_MCP2515 },
1211 { },
1212};
1213
1214MODULE_DEVICE_TABLE(spi, mcp251x_id_table);
1215
1216static struct spi_driver mcp251x_can_driver = {
1217 .driver = {
1218 .name = DEVICE_NAME,
1219 .owner = THIS_MODULE,
1220 .pm = &mcp251x_can_pm_ops,
1221 },
1222
1223 .id_table = mcp251x_id_table,
1224 .probe = mcp251x_can_probe,
1225 .remove = mcp251x_can_remove,
1226};
1227module_spi_driver(mcp251x_can_driver);
1228
1229MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
1230 "Christian Pellegrin <chripell@evolware.org>");
1231MODULE_DESCRIPTION("Microchip 251x CAN driver");
1232MODULE_LICENSE("GPL v2");
1233
