LXR linux/drivers/net/ethernet/brocade/bna/bna_hw

   1/*
   2 * Linux network driver for Brocade Converged Network Adapter.
   3 *
   4 * This program is free software; you can redistribute it and/or modify it
   5 * under the terms of the GNU General Public License (GPL) Version 2 as
   6 * published by the Free Software Foundation
   7 *
   8 * This program is distributed in the hope that it will be useful, but
   9 * WITHOUT ANY WARRANTY; without even the implied warranty of
  10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11 * General Public License for more details.
  12 */
  13/*
  14 * Copyright (c) 2005-2011 Brocade Communications Systems, Inc.
  15 * All rights reserved
  16 * www.brocade.com
  17 */
  18
  19/* File for interrupt macros and functions */
  20
  21#ifndef __BNA_HW_DEFS_H__
  22#define __BNA_HW_DEFS_H__
  23
  24#include "bfi_reg.h"
  25
  26/* SW imposed limits */
  27
  28#define BFI_ENET_DEF_TXQ                1
  29#define BFI_ENET_DEF_RXP                1
  30#define BFI_ENET_DEF_UCAM               1
  31#define BFI_ENET_DEF_RITSZ              1
  32
  33#define BFI_ENET_MAX_MCAM               256
  34
  35#define BFI_INVALID_RID                 -1
  36
  37#define BFI_IBIDX_SIZE                  4
  38
  39#define BFI_VLAN_WORD_SHIFT             5       /* 32 bits */
  40#define BFI_VLAN_WORD_MASK              0x1F
  41#define BFI_VLAN_BLOCK_SHIFT            9       /* 512 bits */
  42#define BFI_VLAN_BMASK_ALL              0xFF
  43
  44#define BFI_COALESCING_TIMER_UNIT       5       /* 5us */
  45#define BFI_MAX_COALESCING_TIMEO        0xFF    /* in 5us units */
  46#define BFI_MAX_INTERPKT_COUNT          0xFF
  47#define BFI_MAX_INTERPKT_TIMEO          0xF     /* in 0.5us units */
  48#define BFI_TX_COALESCING_TIMEO         20      /* 20 * 5 = 100us */
  49#define BFI_TX_INTERPKT_COUNT           12      /* Pkt Cnt = 12 */
  50#define BFI_TX_INTERPKT_TIMEO           15      /* 15 * 0.5 = 7.5us */
  51#define BFI_RX_COALESCING_TIMEO         12      /* 12 * 5 = 60us */
  52#define BFI_RX_INTERPKT_COUNT           6       /* Pkt Cnt = 6 */
  53#define BFI_RX_INTERPKT_TIMEO           3       /* 3 * 0.5 = 1.5us */
  54
  55#define BFI_TXQ_WI_SIZE                 64      /* bytes */
  56#define BFI_RXQ_WI_SIZE                 8       /* bytes */
  57#define BFI_CQ_WI_SIZE                  16      /* bytes */
  58#define BFI_TX_MAX_WRR_QUOTA            0xFFF
  59
  60#define BFI_TX_MAX_VECTORS_PER_WI       4
  61#define BFI_TX_MAX_VECTORS_PER_PKT      0xFF
  62#define BFI_TX_MAX_DATA_PER_VECTOR      0xFFFF
  63#define BFI_TX_MAX_DATA_PER_PKT         0xFFFFFF
  64
  65/* Small Q buffer size */
  66#define BFI_SMALL_RXBUF_SIZE            128
  67
  68#define BFI_TX_MAX_PRIO                 8
  69#define BFI_TX_PRIO_MAP_ALL             0xFF
  70
  71/*
  72 *
  73 * Register definitions and macros
  74 *
  75 */
  76
  77#define BNA_PCI_REG_CT_ADDRSZ           (0x40000)
  78
  79#define ct_reg_addr_init(_bna, _pcidev)                                 \
  80{                                                                       \
  81        struct bna_reg_offset reg_offset[] =                            \
  82        {{HOSTFN0_INT_STATUS, HOSTFN0_INT_MSK},                         \
  83         {HOSTFN1_INT_STATUS, HOSTFN1_INT_MSK},                         \
  84         {HOSTFN2_INT_STATUS, HOSTFN2_INT_MSK},                         \
  85         {HOSTFN3_INT_STATUS, HOSTFN3_INT_MSK} };                       \
  86                                                                        \
  87        (_bna)->regs.fn_int_status = (_pcidev)->pci_bar_kva +           \
  88                                reg_offset[(_pcidev)->pci_func].fn_int_status;\
  89        (_bna)->regs.fn_int_mask = (_pcidev)->pci_bar_kva +             \
  90                                reg_offset[(_pcidev)->pci_func].fn_int_mask;\
  91}
  92
  93#define ct_bit_defn_init(_bna, _pcidev)                                 \
  94{                                                                       \
  95        (_bna)->bits.mbox_status_bits = (__HFN_INT_MBOX_LPU0 |          \
  96                                        __HFN_INT_MBOX_LPU1);           \
  97        (_bna)->bits.mbox_mask_bits = (__HFN_INT_MBOX_LPU0 |            \
  98                                        __HFN_INT_MBOX_LPU1);           \
  99        (_bna)->bits.error_status_bits = (__HFN_INT_ERR_MASK);          \
 100        (_bna)->bits.error_mask_bits = (__HFN_INT_ERR_MASK);            \
 101        (_bna)->bits.halt_status_bits = __HFN_INT_LL_HALT;              \
 102        (_bna)->bits.halt_mask_bits = __HFN_INT_LL_HALT;                \
 103}
 104
 105#define ct2_reg_addr_init(_bna, _pcidev)                                \
 106{                                                                       \
 107        (_bna)->regs.fn_int_status = (_pcidev)->pci_bar_kva +           \
 108                                CT2_HOSTFN_INT_STATUS;                  \
 109        (_bna)->regs.fn_int_mask = (_pcidev)->pci_bar_kva +             \
 110                                CT2_HOSTFN_INTR_MASK;                   \
 111}
 112
 113#define ct2_bit_defn_init(_bna, _pcidev)                                \
 114{                                                                       \
 115        (_bna)->bits.mbox_status_bits = (__HFN_INT_MBOX_LPU0_CT2 |      \
 116                                        __HFN_INT_MBOX_LPU1_CT2);       \
 117        (_bna)->bits.mbox_mask_bits = (__HFN_INT_MBOX_LPU0_CT2 |        \
 118                                        __HFN_INT_MBOX_LPU1_CT2);       \
 119        (_bna)->bits.error_status_bits = (__HFN_INT_ERR_MASK_CT2);      \
 120        (_bna)->bits.error_mask_bits = (__HFN_INT_ERR_MASK_CT2);        \
 121        (_bna)->bits.halt_status_bits = __HFN_INT_CPQ_HALT_CT2;         \
 122        (_bna)->bits.halt_mask_bits = __HFN_INT_CPQ_HALT_CT2;           \
 123}
 124
 125#define bna_reg_addr_init(_bna, _pcidev)                                \
 126{                                                                       \
 127        switch ((_pcidev)->device_id) {                                 \
 128        case PCI_DEVICE_ID_BROCADE_CT:                                  \
 129                ct_reg_addr_init((_bna), (_pcidev));                    \
 130                ct_bit_defn_init((_bna), (_pcidev));                    \
 131                break;                                                  \
 132        case BFA_PCI_DEVICE_ID_CT2:                                     \
 133                ct2_reg_addr_init((_bna), (_pcidev));                   \
 134                ct2_bit_defn_init((_bna), (_pcidev));                   \
 135                break;                                                  \
 136        }                                                               \
 137}
 138
 139#define bna_port_id_get(_bna) ((_bna)->ioceth.ioc.port_id)
 140
 141/*  Interrupt related bits, flags and macros  */
 142
 143#define IB_STATUS_BITS          0x0000ffff
 144
 145#define BNA_IS_MBOX_INTR(_bna, _intr_status)                            \
 146        ((_intr_status) & (_bna)->bits.mbox_status_bits)
 147
 148#define BNA_IS_HALT_INTR(_bna, _intr_status)                            \
 149        ((_intr_status) & (_bna)->bits.halt_status_bits)
 150
 151#define BNA_IS_ERR_INTR(_bna, _intr_status)     \
 152        ((_intr_status) & (_bna)->bits.error_status_bits)
 153
 154#define BNA_IS_MBOX_ERR_INTR(_bna, _intr_status)        \
 155        (BNA_IS_MBOX_INTR(_bna, _intr_status) |         \
 156        BNA_IS_ERR_INTR(_bna, _intr_status))
 157
 158#define BNA_IS_INTX_DATA_INTR(_intr_status)             \
 159                ((_intr_status) & IB_STATUS_BITS)
 160
 161#define bna_halt_clear(_bna)                                            \
 162do {                                                                    \
 163        u32 init_halt;                                          \
 164        init_halt = readl((_bna)->ioceth.ioc.ioc_regs.ll_halt); \
 165        init_halt &= ~__FW_INIT_HALT_P;                                 \
 166        writel(init_halt, (_bna)->ioceth.ioc.ioc_regs.ll_halt); \
 167        init_halt = readl((_bna)->ioceth.ioc.ioc_regs.ll_halt); \
 168} while (0)
 169
 170#define bna_intx_disable(_bna, _cur_mask)                               \
 171{                                                                       \
 172        (_cur_mask) = readl((_bna)->regs.fn_int_mask);          \
 173        writel(0xffffffff, (_bna)->regs.fn_int_mask);           \
 174}
 175
 176#define bna_intx_enable(bna, new_mask)                                  \
 177        writel((new_mask), (bna)->regs.fn_int_mask)
 178#define bna_mbox_intr_disable(bna)                                      \
 179do {                                                                    \
 180        u32 mask;                                                       \
 181        mask = readl((bna)->regs.fn_int_mask);                          \
 182        writel((mask | (bna)->bits.mbox_mask_bits |                     \
 183                (bna)->bits.error_mask_bits), (bna)->regs.fn_int_mask); \
 184        mask = readl((bna)->regs.fn_int_mask);                          \
 185} while (0)
 186
 187#define bna_mbox_intr_enable(bna)                                       \
 188do {                                                                    \
 189        u32 mask;                                                       \
 190        mask = readl((bna)->regs.fn_int_mask);                          \
 191        writel((mask & ~((bna)->bits.mbox_mask_bits |                   \
 192                (bna)->bits.error_mask_bits)), (bna)->regs.fn_int_mask);\
 193        mask = readl((bna)->regs.fn_int_mask);                          \
 194} while (0)
 195
 196#define bna_intr_status_get(_bna, _status)                              \
 197{                                                                       \
 198        (_status) = readl((_bna)->regs.fn_int_status);                  \
 199        if (_status) {                                                  \
 200                writel(((_status) & ~(_bna)->bits.mbox_status_bits),    \
 201                        (_bna)->regs.fn_int_status);                    \
 202        }                                                               \
 203}
 204
 205/*
 206 * MAX ACK EVENTS : No. of acks that can be accumulated in driver,
 207 * before acking to h/w. The no. of bits is 16 in the doorbell register,
 208 * however we keep this limited to 15 bits.
 209 * This is because around the edge of 64K boundary (16 bits), one
 210 * single poll can make the accumulated ACK counter cross the 64K boundary,
 211 * causing problems, when we try to ack with a value greater than 64K.
 212 * 15 bits (32K) should  be large enough to accumulate, anyways, and the max.
 213 * acked events to h/w can be (32K + max poll weight) (currently 64).
 214 */
 215#define BNA_IB_MAX_ACK_EVENTS           (1 << 15)
 216
 217/* These macros build the data portion of the TxQ/RxQ doorbell */
 218#define BNA_DOORBELL_Q_PRD_IDX(_pi)     (0x80000000 | (_pi))
 219#define BNA_DOORBELL_Q_STOP             (0x40000000)
 220
 221/* These macros build the data portion of the IB doorbell */
 222#define BNA_DOORBELL_IB_INT_ACK(_timeout, _events)                      \
 223        (0x80000000 | ((_timeout) << 16) | (_events))
 224#define BNA_DOORBELL_IB_INT_DISABLE     (0x40000000)
 225
 226/* Set the coalescing timer for the given ib */
 227#define bna_ib_coalescing_timer_set(_i_dbell, _cls_timer)               \
 228        ((_i_dbell)->doorbell_ack = BNA_DOORBELL_IB_INT_ACK((_cls_timer), 0));
 229
 230/* Acks 'events' # of events for a given ib while disabling interrupts */
 231#define bna_ib_ack_disable_irq(_i_dbell, _events)                       \
 232        (writel(BNA_DOORBELL_IB_INT_ACK(0, (_events)), \
 233                (_i_dbell)->doorbell_addr));
 234
 235/* Acks 'events' # of events for a given ib */
 236#define bna_ib_ack(_i_dbell, _events)                                   \
 237        (writel(((_i_dbell)->doorbell_ack | (_events)), \
 238                (_i_dbell)->doorbell_addr));
 239
 240#define bna_ib_start(_bna, _ib, _is_regular)                            \
 241{                                                                       \
 242        u32 intx_mask;                                          \
 243        struct bna_ib *ib = _ib;                                        \
 244        if ((ib->intr_type == BNA_INTR_T_INTX)) {                       \
 245                bna_intx_disable((_bna), intx_mask);                    \
 246                intx_mask &= ~(ib->intr_vector);                        \
 247                bna_intx_enable((_bna), intx_mask);                     \
 248        }                                                               \
 249        bna_ib_coalescing_timer_set(&ib->door_bell,                     \
 250                        ib->coalescing_timeo);                          \
 251        if (_is_regular)                                                \
 252                bna_ib_ack(&ib->door_bell, 0);                          \
 253}
 254
 255#define bna_ib_stop(_bna, _ib)                                          \
 256{                                                                       \
 257        u32 intx_mask;                                          \
 258        struct bna_ib *ib = _ib;                                        \
 259        writel(BNA_DOORBELL_IB_INT_DISABLE,                             \
 260                ib->door_bell.doorbell_addr);                           \
 261        if (ib->intr_type == BNA_INTR_T_INTX) {                         \
 262                bna_intx_disable((_bna), intx_mask);                    \
 263                intx_mask |= ib->intr_vector;                           \
 264                bna_intx_enable((_bna), intx_mask);                     \
 265        }                                                               \
 266}
 267
 268#define bna_txq_prod_indx_doorbell(_tcb)                                \
 269        (writel(BNA_DOORBELL_Q_PRD_IDX((_tcb)->producer_index), \
 270                (_tcb)->q_dbell));
 271
 272#define bna_rxq_prod_indx_doorbell(_rcb)                                \
 273        (writel(BNA_DOORBELL_Q_PRD_IDX((_rcb)->producer_index), \
 274                (_rcb)->q_dbell));
 275
 276/* TxQ, RxQ, CQ related bits, offsets, macros */
 277
 278/* TxQ Entry Opcodes */
 279#define BNA_TXQ_WI_SEND                 (0x402) /* Single Frame Transmission */
 280#define BNA_TXQ_WI_SEND_LSO             (0x403) /* Multi-Frame Transmission */
 281#define BNA_TXQ_WI_EXTENSION            (0x104) /* Extension WI */
 282
 283/* TxQ Entry Control Flags */
 284#define BNA_TXQ_WI_CF_FCOE_CRC          (1 << 8)
 285#define BNA_TXQ_WI_CF_IPID_MODE         (1 << 5)
 286#define BNA_TXQ_WI_CF_INS_PRIO          (1 << 4)
 287#define BNA_TXQ_WI_CF_INS_VLAN          (1 << 3)
 288#define BNA_TXQ_WI_CF_UDP_CKSUM         (1 << 2)
 289#define BNA_TXQ_WI_CF_TCP_CKSUM         (1 << 1)
 290#define BNA_TXQ_WI_CF_IP_CKSUM          (1 << 0)
 291
 292#define BNA_TXQ_WI_L4_HDR_N_OFFSET(_hdr_size, _offset) \
 293                (((_hdr_size) << 10) | ((_offset) & 0x3FF))
 294
 295/*
 296 * Completion Q defines
 297 */
 298/* CQ Entry Flags */
 299#define BNA_CQ_EF_MAC_ERROR     (1 <<  0)
 300#define BNA_CQ_EF_FCS_ERROR     (1 <<  1)
 301#define BNA_CQ_EF_TOO_LONG      (1 <<  2)
 302#define BNA_CQ_EF_FC_CRC_OK     (1 <<  3)
 303
 304#define BNA_CQ_EF_RSVD1         (1 <<  4)
 305#define BNA_CQ_EF_L4_CKSUM_OK   (1 <<  5)
 306#define BNA_CQ_EF_L3_CKSUM_OK   (1 <<  6)
 307#define BNA_CQ_EF_HDS_HEADER    (1 <<  7)
 308
 309#define BNA_CQ_EF_UDP           (1 <<  8)
 310#define BNA_CQ_EF_TCP           (1 <<  9)
 311#define BNA_CQ_EF_IP_OPTIONS    (1 << 10)
 312#define BNA_CQ_EF_IPV6          (1 << 11)
 313
 314#define BNA_CQ_EF_IPV4          (1 << 12)
 315#define BNA_CQ_EF_VLAN          (1 << 13)
 316#define BNA_CQ_EF_RSS           (1 << 14)
 317#define BNA_CQ_EF_RSVD2         (1 << 15)
 318
 319#define BNA_CQ_EF_MCAST_MATCH   (1 << 16)
 320#define BNA_CQ_EF_MCAST         (1 << 17)
 321#define BNA_CQ_EF_BCAST         (1 << 18)
 322#define BNA_CQ_EF_REMOTE        (1 << 19)
 323
 324#define BNA_CQ_EF_LOCAL         (1 << 20)
 325
 326/* Data structures */
 327
 328struct bna_reg_offset {
 329        u32 fn_int_status;
 330        u32 fn_int_mask;
 331};
 332
 333struct bna_bit_defn {
 334        u32 mbox_status_bits;
 335        u32 mbox_mask_bits;
 336        u32 error_status_bits;
 337        u32 error_mask_bits;
 338        u32 halt_status_bits;
 339        u32 halt_mask_bits;
 340};
 341
 342struct bna_reg {
 343        void __iomem *fn_int_status;
 344        void __iomem *fn_int_mask;
 345};
 346
 347/* TxQ Vector (a.k.a. Tx-Buffer Descriptor) */
 348struct bna_dma_addr {
 349        u32             msb;
 350        u32             lsb;
 351};
 352
 353struct bna_txq_wi_vector {
 354        u16             reserved;
 355        u16             length;         /* Only 14 LSB are valid */
 356        struct bna_dma_addr host_addr; /* Tx-Buf DMA addr */
 357};
 358
 359/*  TxQ Entry Structure
 360 *
 361 *  BEWARE:  Load values into this structure with correct endianess.
 362 */
 363struct bna_txq_entry {
 364        union {
 365                struct {
 366                        u8 reserved;
 367                        u8 num_vectors; /* number of vectors present */
 368                        u16 opcode; /* Either */
 369                                                    /* BNA_TXQ_WI_SEND or */
 370                                                    /* BNA_TXQ_WI_SEND_LSO */
 371                        u16 flags; /* OR of all the flags */
 372                        u16 l4_hdr_size_n_offset;
 373                        u16 vlan_tag;
 374                        u16 lso_mss;    /* Only 14 LSB are valid */
 375                        u32 frame_length;       /* Only 24 LSB are valid */
 376                } wi;
 377
 378                struct {
 379                        u16 reserved;
 380                        u16 opcode; /* Must be */
 381                                                    /* BNA_TXQ_WI_EXTENSION */
 382                        u32 reserved2[3];       /* Place holder for */
 383                                                /* removed vector (12 bytes) */
 384                } wi_ext;
 385        } hdr;
 386        struct bna_txq_wi_vector vector[4];
 387};
 388
 389/* RxQ Entry Structure */
 390struct bna_rxq_entry {          /* Rx-Buffer */
 391        struct bna_dma_addr host_addr; /* Rx-Buffer DMA address */
 392};
 393
 394/* CQ Entry Structure */
 395struct bna_cq_entry {
 396        u32 flags;
 397        u16 vlan_tag;
 398        u16 length;
 399        u32 rss_hash;
 400        u8 valid;
 401        u8 reserved1;
 402        u8 reserved2;
 403        u8 rxq_id;
 404};
 405
 406#endif /* __BNA_HW_DEFS_H__ */
 407