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35#ifndef __CXGB4_H__
36#define __CXGB4_H__
37
38#include "t4_hw.h"
39
40#include <linux/bitops.h>
41#include <linux/cache.h>
42#include <linux/interrupt.h>
43#include <linux/list.h>
44#include <linux/netdevice.h>
45#include <linux/pci.h>
46#include <linux/spinlock.h>
47#include <linux/timer.h>
48#include <linux/vmalloc.h>
49#include <asm/io.h>
50#include "cxgb4_uld.h"
51#include "t4_hw.h"
52
53#define FW_VERSION_MAJOR 1
54#define FW_VERSION_MINOR 4
55#define FW_VERSION_MICRO 0
56
57#define FW_VERSION_MAJOR_T5 0
58#define FW_VERSION_MINOR_T5 0
59#define FW_VERSION_MICRO_T5 0
60
61#define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
62
63enum {
64 MAX_NPORTS = 4,
65 SERNUM_LEN = 24,
66 EC_LEN = 16,
67 ID_LEN = 16,
68};
69
70enum {
71 MEM_EDC0,
72 MEM_EDC1,
73 MEM_MC,
74 MEM_MC0 = MEM_MC,
75 MEM_MC1
76};
77
78enum {
79 MEMWIN0_APERTURE = 2048,
80 MEMWIN0_BASE = 0x1b800,
81 MEMWIN1_APERTURE = 32768,
82 MEMWIN1_BASE = 0x28000,
83 MEMWIN1_BASE_T5 = 0x52000,
84 MEMWIN2_APERTURE = 65536,
85 MEMWIN2_BASE = 0x30000,
86 MEMWIN2_BASE_T5 = 0x54000,
87};
88
89enum dev_master {
90 MASTER_CANT,
91 MASTER_MAY,
92 MASTER_MUST
93};
94
95enum dev_state {
96 DEV_STATE_UNINIT,
97 DEV_STATE_INIT,
98 DEV_STATE_ERR
99};
100
101enum {
102 PAUSE_RX = 1 << 0,
103 PAUSE_TX = 1 << 1,
104 PAUSE_AUTONEG = 1 << 2
105};
106
107struct port_stats {
108 u64 tx_octets;
109 u64 tx_frames;
110 u64 tx_bcast_frames;
111 u64 tx_mcast_frames;
112 u64 tx_ucast_frames;
113 u64 tx_error_frames;
114
115 u64 tx_frames_64;
116 u64 tx_frames_65_127;
117 u64 tx_frames_128_255;
118 u64 tx_frames_256_511;
119 u64 tx_frames_512_1023;
120 u64 tx_frames_1024_1518;
121 u64 tx_frames_1519_max;
122
123 u64 tx_drop;
124 u64 tx_pause;
125 u64 tx_ppp0;
126 u64 tx_ppp1;
127 u64 tx_ppp2;
128 u64 tx_ppp3;
129 u64 tx_ppp4;
130 u64 tx_ppp5;
131 u64 tx_ppp6;
132 u64 tx_ppp7;
133
134 u64 rx_octets;
135 u64 rx_frames;
136 u64 rx_bcast_frames;
137 u64 rx_mcast_frames;
138 u64 rx_ucast_frames;
139 u64 rx_too_long;
140 u64 rx_jabber;
141 u64 rx_fcs_err;
142 u64 rx_len_err;
143 u64 rx_symbol_err;
144 u64 rx_runt;
145
146 u64 rx_frames_64;
147 u64 rx_frames_65_127;
148 u64 rx_frames_128_255;
149 u64 rx_frames_256_511;
150 u64 rx_frames_512_1023;
151 u64 rx_frames_1024_1518;
152 u64 rx_frames_1519_max;
153
154 u64 rx_pause;
155 u64 rx_ppp0;
156 u64 rx_ppp1;
157 u64 rx_ppp2;
158 u64 rx_ppp3;
159 u64 rx_ppp4;
160 u64 rx_ppp5;
161 u64 rx_ppp6;
162 u64 rx_ppp7;
163
164 u64 rx_ovflow0;
165 u64 rx_ovflow1;
166 u64 rx_ovflow2;
167 u64 rx_ovflow3;
168 u64 rx_trunc0;
169 u64 rx_trunc1;
170 u64 rx_trunc2;
171 u64 rx_trunc3;
172};
173
174struct lb_port_stats {
175 u64 octets;
176 u64 frames;
177 u64 bcast_frames;
178 u64 mcast_frames;
179 u64 ucast_frames;
180 u64 error_frames;
181
182 u64 frames_64;
183 u64 frames_65_127;
184 u64 frames_128_255;
185 u64 frames_256_511;
186 u64 frames_512_1023;
187 u64 frames_1024_1518;
188 u64 frames_1519_max;
189
190 u64 drop;
191
192 u64 ovflow0;
193 u64 ovflow1;
194 u64 ovflow2;
195 u64 ovflow3;
196 u64 trunc0;
197 u64 trunc1;
198 u64 trunc2;
199 u64 trunc3;
200};
201
202struct tp_tcp_stats {
203 u32 tcpOutRsts;
204 u64 tcpInSegs;
205 u64 tcpOutSegs;
206 u64 tcpRetransSegs;
207};
208
209struct tp_err_stats {
210 u32 macInErrs[4];
211 u32 hdrInErrs[4];
212 u32 tcpInErrs[4];
213 u32 tnlCongDrops[4];
214 u32 ofldChanDrops[4];
215 u32 tnlTxDrops[4];
216 u32 ofldVlanDrops[4];
217 u32 tcp6InErrs[4];
218 u32 ofldNoNeigh;
219 u32 ofldCongDefer;
220};
221
222struct tp_params {
223 unsigned int ntxchan;
224 unsigned int tre;
225 unsigned short tx_modq_map;
226
227
228 uint32_t dack_re;
229 unsigned short tx_modq[NCHAN];
230};
231
232struct vpd_params {
233 unsigned int cclk;
234 u8 ec[EC_LEN + 1];
235 u8 sn[SERNUM_LEN + 1];
236 u8 id[ID_LEN + 1];
237};
238
239struct pci_params {
240 unsigned char speed;
241 unsigned char width;
242};
243
244struct adapter_params {
245 struct tp_params tp;
246 struct vpd_params vpd;
247 struct pci_params pci;
248
249 unsigned int sf_size;
250 unsigned int sf_nsec;
251 unsigned int sf_fw_start;
252
253 unsigned int fw_vers;
254 unsigned int tp_vers;
255 u8 api_vers[7];
256
257 unsigned short mtus[NMTUS];
258 unsigned short a_wnd[NCCTRL_WIN];
259 unsigned short b_wnd[NCCTRL_WIN];
260
261 unsigned char nports;
262 unsigned char portvec;
263 unsigned char rev;
264 unsigned char offload;
265
266 unsigned char bypass;
267
268 unsigned int ofldq_wr_cred;
269};
270
271struct trace_params {
272 u32 data[TRACE_LEN / 4];
273 u32 mask[TRACE_LEN / 4];
274 unsigned short snap_len;
275 unsigned short min_len;
276 unsigned char skip_ofst;
277 unsigned char skip_len;
278 unsigned char invert;
279 unsigned char port;
280};
281
282struct link_config {
283 unsigned short supported;
284 unsigned short advertising;
285 unsigned short requested_speed;
286 unsigned short speed;
287 unsigned char requested_fc;
288 unsigned char fc;
289 unsigned char autoneg;
290 unsigned char link_ok;
291};
292
293#define FW_LEN16(fw_struct) FW_CMD_LEN16(sizeof(fw_struct) / 16)
294
295enum {
296 MAX_ETH_QSETS = 32,
297 MAX_OFLD_QSETS = 16,
298 MAX_CTRL_QUEUES = NCHAN,
299 MAX_RDMA_QUEUES = NCHAN,
300};
301
302enum {
303 MAX_EGRQ = 128,
304 MAX_INGQ = 64
305};
306
307struct adapter;
308struct sge_rspq;
309
310struct port_info {
311 struct adapter *adapter;
312 u16 viid;
313 s16 xact_addr_filt;
314 u16 rss_size;
315 s8 mdio_addr;
316 u8 port_type;
317 u8 mod_type;
318 u8 port_id;
319 u8 tx_chan;
320 u8 lport;
321 u8 nqsets;
322 u8 first_qset;
323 u8 rss_mode;
324 struct link_config link_cfg;
325 u16 *rss;
326};
327
328struct dentry;
329struct work_struct;
330
331enum {
332 FULL_INIT_DONE = (1 << 0),
333 USING_MSI = (1 << 1),
334 USING_MSIX = (1 << 2),
335 FW_OK = (1 << 4),
336 RSS_TNLALLLOOKUP = (1 << 5),
337 USING_SOFT_PARAMS = (1 << 6),
338 MASTER_PF = (1 << 7),
339 FW_OFLD_CONN = (1 << 9),
340};
341
342struct rx_sw_desc;
343
344struct sge_fl {
345 unsigned int avail;
346 unsigned int pend_cred;
347 unsigned int cidx;
348 unsigned int pidx;
349 unsigned long alloc_failed;
350 unsigned long large_alloc_failed;
351 unsigned long starving;
352
353 unsigned int cntxt_id;
354 unsigned int size;
355 struct rx_sw_desc *sdesc;
356 __be64 *desc;
357 dma_addr_t addr;
358};
359
360
361struct pkt_gl {
362 struct page_frag frags[MAX_SKB_FRAGS];
363 void *va;
364 unsigned int nfrags;
365 unsigned int tot_len;
366};
367
368typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
369 const struct pkt_gl *gl);
370
371struct sge_rspq {
372 struct napi_struct napi;
373 const __be64 *cur_desc;
374 unsigned int cidx;
375 u8 gen;
376 u8 intr_params;
377 u8 next_intr_params;
378 u8 pktcnt_idx;
379 u8 uld;
380 u8 idx;
381 int offset;
382 u16 cntxt_id;
383 u16 abs_id;
384 __be64 *desc;
385 dma_addr_t phys_addr;
386 unsigned int iqe_len;
387 unsigned int size;
388 struct adapter *adap;
389 struct net_device *netdev;
390 rspq_handler_t handler;
391};
392
393struct sge_eth_stats {
394 unsigned long pkts;
395 unsigned long lro_pkts;
396 unsigned long lro_merged;
397 unsigned long rx_cso;
398 unsigned long vlan_ex;
399 unsigned long rx_drops;
400};
401
402struct sge_eth_rxq {
403 struct sge_rspq rspq;
404 struct sge_fl fl;
405 struct sge_eth_stats stats;
406} ____cacheline_aligned_in_smp;
407
408struct sge_ofld_stats {
409 unsigned long pkts;
410 unsigned long imm;
411 unsigned long an;
412 unsigned long nomem;
413};
414
415struct sge_ofld_rxq {
416 struct sge_rspq rspq;
417 struct sge_fl fl;
418 struct sge_ofld_stats stats;
419} ____cacheline_aligned_in_smp;
420
421struct tx_desc {
422 __be64 flit[8];
423};
424
425struct tx_sw_desc;
426
427struct sge_txq {
428 unsigned int in_use;
429 unsigned int size;
430 unsigned int cidx;
431 unsigned int pidx;
432 unsigned long stops;
433 unsigned long restarts;
434 unsigned int cntxt_id;
435 struct tx_desc *desc;
436 struct tx_sw_desc *sdesc;
437 struct sge_qstat *stat;
438 dma_addr_t phys_addr;
439 spinlock_t db_lock;
440 int db_disabled;
441 unsigned short db_pidx;
442 u64 udb;
443};
444
445struct sge_eth_txq {
446 struct sge_txq q;
447 struct netdev_queue *txq;
448 unsigned long tso;
449 unsigned long tx_cso;
450 unsigned long vlan_ins;
451 unsigned long mapping_err;
452} ____cacheline_aligned_in_smp;
453
454struct sge_ofld_txq {
455 struct sge_txq q;
456 struct adapter *adap;
457 struct sk_buff_head sendq;
458 struct tasklet_struct qresume_tsk;
459 u8 full;
460 unsigned long mapping_err;
461} ____cacheline_aligned_in_smp;
462
463struct sge_ctrl_txq {
464 struct sge_txq q;
465 struct adapter *adap;
466 struct sk_buff_head sendq;
467 struct tasklet_struct qresume_tsk;
468 u8 full;
469} ____cacheline_aligned_in_smp;
470
471struct sge {
472 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
473 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS];
474 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
475
476 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
477 struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS];
478 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES];
479 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
480
481 struct sge_rspq intrq ____cacheline_aligned_in_smp;
482 spinlock_t intrq_lock;
483
484 u16 max_ethqsets;
485 u16 ethqsets;
486 u16 ethtxq_rover;
487 u16 ofldqsets;
488 u16 rdmaqs;
489 u16 ofld_rxq[MAX_OFLD_QSETS];
490 u16 rdma_rxq[NCHAN];
491 u16 timer_val[SGE_NTIMERS];
492 u8 counter_val[SGE_NCOUNTERS];
493 u32 fl_pg_order;
494 u32 stat_len;
495 u32 pktshift;
496 u32 fl_align;
497 u32 fl_starve_thres;
498 unsigned int starve_thres;
499 u8 idma_state[2];
500 unsigned int egr_start;
501 unsigned int ingr_start;
502 void *egr_map[MAX_EGRQ];
503 struct sge_rspq *ingr_map[MAX_INGQ];
504 DECLARE_BITMAP(starving_fl, MAX_EGRQ);
505 DECLARE_BITMAP(txq_maperr, MAX_EGRQ);
506 struct timer_list rx_timer;
507 struct timer_list tx_timer;
508};
509
510#define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
511#define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
512#define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++)
513
514struct l2t_data;
515
516#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
517#define CHELSIO_CHIP_VERSION(code) ((code) >> 4)
518#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
519
520#define CHELSIO_T4 0x4
521#define CHELSIO_T5 0x5
522
523enum chip_type {
524 T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 0),
525 T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
526 T4_A3 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
527 T4_FIRST_REV = T4_A1,
528 T4_LAST_REV = T4_A3,
529
530 T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
531 T5_FIRST_REV = T5_A1,
532 T5_LAST_REV = T5_A1,
533};
534
535#ifdef CONFIG_PCI_IOV
536
537
538
539
540
541#define NUM_OF_PF_WITH_SRIOV 4
542
543#endif
544
545struct adapter {
546 void __iomem *regs;
547 void __iomem *bar2;
548 struct pci_dev *pdev;
549 struct device *pdev_dev;
550 unsigned int mbox;
551 unsigned int fn;
552 unsigned int flags;
553 enum chip_type chip;
554
555 int msg_enable;
556
557 struct adapter_params params;
558 struct cxgb4_virt_res vres;
559 unsigned int swintr;
560
561 unsigned int wol;
562
563 struct {
564 unsigned short vec;
565 char desc[IFNAMSIZ + 10];
566 } msix_info[MAX_INGQ + 1];
567
568 struct sge sge;
569
570 struct net_device *port[MAX_NPORTS];
571 u8 chan_map[NCHAN];
572
573 u32 filter_mode;
574 unsigned int l2t_start;
575 unsigned int l2t_end;
576 struct l2t_data *l2t;
577 void *uld_handle[CXGB4_ULD_MAX];
578 struct list_head list_node;
579 struct list_head rcu_node;
580
581 struct tid_info tids;
582 void **tid_release_head;
583 spinlock_t tid_release_lock;
584 struct work_struct tid_release_task;
585 struct work_struct db_full_task;
586 struct work_struct db_drop_task;
587 bool tid_release_task_busy;
588
589 struct dentry *debugfs_root;
590
591 spinlock_t stats_lock;
592};
593
594
595
596#define ETHTYPE_BITWIDTH 16
597#define FRAG_BITWIDTH 1
598#define MACIDX_BITWIDTH 9
599#define FCOE_BITWIDTH 1
600#define IPORT_BITWIDTH 3
601#define MATCHTYPE_BITWIDTH 3
602#define PROTO_BITWIDTH 8
603#define TOS_BITWIDTH 8
604#define PF_BITWIDTH 8
605#define VF_BITWIDTH 8
606#define IVLAN_BITWIDTH 16
607#define OVLAN_BITWIDTH 16
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626struct ch_filter_tuple {
627
628
629
630
631
632
633 uint32_t ethtype:ETHTYPE_BITWIDTH;
634 uint32_t frag:FRAG_BITWIDTH;
635 uint32_t ivlan_vld:1;
636 uint32_t ovlan_vld:1;
637 uint32_t pfvf_vld:1;
638 uint32_t macidx:MACIDX_BITWIDTH;
639 uint32_t fcoe:FCOE_BITWIDTH;
640 uint32_t iport:IPORT_BITWIDTH;
641 uint32_t matchtype:MATCHTYPE_BITWIDTH;
642 uint32_t proto:PROTO_BITWIDTH;
643 uint32_t tos:TOS_BITWIDTH;
644 uint32_t pf:PF_BITWIDTH;
645 uint32_t vf:VF_BITWIDTH;
646 uint32_t ivlan:IVLAN_BITWIDTH;
647 uint32_t ovlan:OVLAN_BITWIDTH;
648
649
650
651
652 uint8_t lip[16];
653 uint8_t fip[16];
654 uint16_t lport;
655 uint16_t fport;
656};
657
658
659
660struct ch_filter_specification {
661
662
663 uint32_t hitcnts:1;
664 uint32_t prio:1;
665
666
667
668
669 uint32_t type:1;
670
671
672
673
674
675 uint32_t action:2;
676
677 uint32_t rpttid:1;
678
679 uint32_t dirsteer:1;
680 uint32_t iq:10;
681
682 uint32_t maskhash:1;
683 uint32_t dirsteerhash:1;
684
685
686
687
688
689
690 uint32_t eport:2;
691 uint32_t newdmac:1;
692 uint32_t newsmac:1;
693 uint32_t newvlan:2;
694 uint8_t dmac[ETH_ALEN];
695 uint8_t smac[ETH_ALEN];
696 uint16_t vlan;
697
698
699
700 struct ch_filter_tuple val;
701 struct ch_filter_tuple mask;
702};
703
704enum {
705 FILTER_PASS = 0,
706 FILTER_DROP,
707 FILTER_SWITCH
708};
709
710enum {
711 VLAN_NOCHANGE = 0,
712 VLAN_REMOVE,
713 VLAN_INSERT,
714 VLAN_REWRITE
715};
716
717static inline int is_t5(enum chip_type chip)
718{
719 return (chip >= T5_FIRST_REV && chip <= T5_LAST_REV);
720}
721
722static inline int is_t4(enum chip_type chip)
723{
724 return (chip >= T4_FIRST_REV && chip <= T4_LAST_REV);
725}
726
727static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
728{
729 return readl(adap->regs + reg_addr);
730}
731
732static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
733{
734 writel(val, adap->regs + reg_addr);
735}
736
737#ifndef readq
738static inline u64 readq(const volatile void __iomem *addr)
739{
740 return readl(addr) + ((u64)readl(addr + 4) << 32);
741}
742
743static inline void writeq(u64 val, volatile void __iomem *addr)
744{
745 writel(val, addr);
746 writel(val >> 32, addr + 4);
747}
748#endif
749
750static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
751{
752 return readq(adap->regs + reg_addr);
753}
754
755static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
756{
757 writeq(val, adap->regs + reg_addr);
758}
759
760
761
762
763
764
765
766static inline struct port_info *netdev2pinfo(const struct net_device *dev)
767{
768 return netdev_priv(dev);
769}
770
771
772
773
774
775
776
777
778static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
779{
780 return netdev_priv(adap->port[idx]);
781}
782
783
784
785
786
787
788
789static inline struct adapter *netdev2adap(const struct net_device *dev)
790{
791 return netdev2pinfo(dev)->adapter;
792}
793
794void t4_os_portmod_changed(const struct adapter *adap, int port_id);
795void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
796
797void *t4_alloc_mem(size_t size);
798
799void t4_free_sge_resources(struct adapter *adap);
800irq_handler_t t4_intr_handler(struct adapter *adap);
801netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev);
802int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
803 const struct pkt_gl *gl);
804int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
805int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
806int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
807 struct net_device *dev, int intr_idx,
808 struct sge_fl *fl, rspq_handler_t hnd);
809int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
810 struct net_device *dev, struct netdev_queue *netdevq,
811 unsigned int iqid);
812int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
813 struct net_device *dev, unsigned int iqid,
814 unsigned int cmplqid);
815int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
816 struct net_device *dev, unsigned int iqid);
817irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
818int t4_sge_init(struct adapter *adap);
819void t4_sge_start(struct adapter *adap);
820void t4_sge_stop(struct adapter *adap);
821extern int dbfifo_int_thresh;
822
823#define for_each_port(adapter, iter) \
824 for (iter = 0; iter < (adapter)->params.nports; ++iter)
825
826static inline int is_bypass(struct adapter *adap)
827{
828 return adap->params.bypass;
829}
830
831static inline int is_bypass_device(int device)
832{
833
834 switch (device) {
835 case 0x440b:
836 case 0x440c:
837 return 1;
838 default:
839 return 0;
840 }
841}
842
843static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
844{
845 return adap->params.vpd.cclk / 1000;
846}
847
848static inline unsigned int us_to_core_ticks(const struct adapter *adap,
849 unsigned int us)
850{
851 return (us * adap->params.vpd.cclk) / 1000;
852}
853
854static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
855 unsigned int ticks)
856{
857
858 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
859 adapter->params.vpd.cclk);
860}
861
862void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
863 u32 val);
864
865int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
866 void *rpl, bool sleep_ok);
867
868static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
869 int size, void *rpl)
870{
871 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
872}
873
874static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
875 int size, void *rpl)
876{
877 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
878}
879
880void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
881 unsigned int data_reg, const u32 *vals,
882 unsigned int nregs, unsigned int start_idx);
883void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
884 unsigned int data_reg, u32 *vals, unsigned int nregs,
885 unsigned int start_idx);
886
887struct fw_filter_wr;
888
889void t4_intr_enable(struct adapter *adapter);
890void t4_intr_disable(struct adapter *adapter);
891int t4_slow_intr_handler(struct adapter *adapter);
892
893int t4_wait_dev_ready(struct adapter *adap);
894int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
895 struct link_config *lc);
896int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
897int t4_memory_write(struct adapter *adap, int mtype, u32 addr, u32 len,
898 __be32 *buf);
899int t4_seeprom_wp(struct adapter *adapter, bool enable);
900int get_vpd_params(struct adapter *adapter, struct vpd_params *p);
901int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
902unsigned int t4_flash_cfg_addr(struct adapter *adapter);
903int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
904int t4_check_fw_version(struct adapter *adapter);
905int t4_prep_adapter(struct adapter *adapter);
906int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
907void t4_fatal_err(struct adapter *adapter);
908int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
909 int start, int n, const u16 *rspq, unsigned int nrspq);
910int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
911 unsigned int flags);
912int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
913 u64 *parity);
914int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
915 u64 *parity);
916
917void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
918void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
919void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
920 unsigned int mask, unsigned int val);
921void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
922 struct tp_tcp_stats *v6);
923void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
924 const unsigned short *alpha, const unsigned short *beta);
925
926void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
927
928void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
929 const u8 *addr);
930int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
931 u64 mask0, u64 mask1, unsigned int crc, bool enable);
932
933int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
934 enum dev_master master, enum dev_state *state);
935int t4_fw_bye(struct adapter *adap, unsigned int mbox);
936int t4_early_init(struct adapter *adap, unsigned int mbox);
937int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
938int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force);
939int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset);
940int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
941 const u8 *fw_data, unsigned int size, int force);
942int t4_fw_config_file(struct adapter *adap, unsigned int mbox,
943 unsigned int mtype, unsigned int maddr,
944 u32 *finiver, u32 *finicsum, u32 *cfcsum);
945int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
946 unsigned int cache_line_size);
947int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
948int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
949 unsigned int vf, unsigned int nparams, const u32 *params,
950 u32 *val);
951int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
952 unsigned int vf, unsigned int nparams, const u32 *params,
953 const u32 *val);
954int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
955 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
956 unsigned int rxqi, unsigned int rxq, unsigned int tc,
957 unsigned int vi, unsigned int cmask, unsigned int pmask,
958 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
959int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
960 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
961 unsigned int *rss_size);
962int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
963 int mtu, int promisc, int all_multi, int bcast, int vlanex,
964 bool sleep_ok);
965int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
966 unsigned int viid, bool free, unsigned int naddr,
967 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
968int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
969 int idx, const u8 *addr, bool persist, bool add_smt);
970int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
971 bool ucast, u64 vec, bool sleep_ok);
972int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
973 bool rx_en, bool tx_en);
974int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
975 unsigned int nblinks);
976int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
977 unsigned int mmd, unsigned int reg, u16 *valp);
978int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
979 unsigned int mmd, unsigned int reg, u16 val);
980int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
981 unsigned int vf, unsigned int iqtype, unsigned int iqid,
982 unsigned int fl0id, unsigned int fl1id);
983int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
984 unsigned int vf, unsigned int eqid);
985int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
986 unsigned int vf, unsigned int eqid);
987int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
988 unsigned int vf, unsigned int eqid);
989int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
990void t4_db_full(struct adapter *adapter);
991void t4_db_dropped(struct adapter *adapter);
992int t4_mem_win_read_len(struct adapter *adap, u32 addr, __be32 *data, int len);
993int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
994 u32 addr, u32 val);
995#endif
996