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18#ifndef BE_H
19#define BE_H
20
21#include <linux/pci.h>
22#include <linux/etherdevice.h>
23#include <linux/delay.h>
24#include <net/tcp.h>
25#include <net/ip.h>
26#include <net/ipv6.h>
27#include <linux/if_vlan.h>
28#include <linux/workqueue.h>
29#include <linux/interrupt.h>
30#include <linux/firmware.h>
31#include <linux/slab.h>
32#include <linux/u64_stats_sync.h>
33
34#include "be_hw.h"
35#include "be_roce.h"
36
37#define DRV_VER "4.9.134.0u"
38#define DRV_NAME "be2net"
39#define BE_NAME "Emulex BladeEngine2"
40#define BE3_NAME "Emulex BladeEngine3"
41#define OC_NAME "Emulex OneConnect"
42#define OC_NAME_BE OC_NAME "(be3)"
43#define OC_NAME_LANCER OC_NAME "(Lancer)"
44#define OC_NAME_SH OC_NAME "(Skyhawk)"
45#define DRV_DESC "Emulex OneConnect 10Gbps NIC Driver"
46
47#define BE_VENDOR_ID 0x19a2
48#define EMULEX_VENDOR_ID 0x10df
49#define BE_DEVICE_ID1 0x211
50#define BE_DEVICE_ID2 0x221
51#define OC_DEVICE_ID1 0x700
52#define OC_DEVICE_ID2 0x710
53#define OC_DEVICE_ID3 0xe220
54#define OC_DEVICE_ID4 0xe228
55#define OC_DEVICE_ID5 0x720
56#define OC_DEVICE_ID6 0x728
57#define OC_SUBSYS_DEVICE_ID1 0xE602
58#define OC_SUBSYS_DEVICE_ID2 0xE642
59#define OC_SUBSYS_DEVICE_ID3 0xE612
60#define OC_SUBSYS_DEVICE_ID4 0xE652
61
62static inline char *nic_name(struct pci_dev *pdev)
63{
64 switch (pdev->device) {
65 case OC_DEVICE_ID1:
66 return OC_NAME;
67 case OC_DEVICE_ID2:
68 return OC_NAME_BE;
69 case OC_DEVICE_ID3:
70 case OC_DEVICE_ID4:
71 return OC_NAME_LANCER;
72 case BE_DEVICE_ID2:
73 return BE3_NAME;
74 case OC_DEVICE_ID5:
75 case OC_DEVICE_ID6:
76 return OC_NAME_SH;
77 default:
78 return BE_NAME;
79 }
80}
81
82
83#define BE_HDR_LEN ((u16) 64)
84
85#define BE_RX_SKB_ALLOC_SIZE (BE_HDR_LEN + 64)
86
87#define BE_MAX_JUMBO_FRAME_SIZE 9018
88#define BE_MIN_MTU 256
89
90#define BE_NUM_VLANS_SUPPORTED 64
91#define BE_UMC_NUM_VLANS_SUPPORTED 15
92#define BE_MAX_EQD 96u
93#define BE_MAX_TX_FRAG_COUNT 30
94
95#define EVNT_Q_LEN 1024
96#define TX_Q_LEN 2048
97#define TX_CQ_LEN 1024
98#define RX_Q_LEN 1024
99#define RX_CQ_LEN 1024
100#define MCC_Q_LEN 128
101#define MCC_CQ_LEN 256
102
103#define BE2_MAX_RSS_QS 4
104#define BE3_MAX_RSS_QS 16
105#define BE3_MAX_TX_QS 16
106#define BE3_MAX_EVT_QS 16
107
108#define MAX_RX_QS 32
109#define MAX_EVT_QS 32
110#define MAX_TX_QS 32
111
112#define MAX_ROCE_EQS 5
113#define MAX_MSIX_VECTORS 32
114#define MIN_MSIX_VECTORS 1
115#define BE_TX_BUDGET 256
116#define BE_NAPI_WEIGHT 64
117#define MAX_RX_POST BE_NAPI_WEIGHT
118#define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST)
119
120#define MAX_VFS 30
121#define FW_VER_LEN 32
122
123struct be_dma_mem {
124 void *va;
125 dma_addr_t dma;
126 u32 size;
127};
128
129struct be_queue_info {
130 struct be_dma_mem dma_mem;
131 u16 len;
132 u16 entry_size;
133 u16 id;
134 u16 tail, head;
135 bool created;
136 atomic_t used;
137};
138
139static inline u32 MODULO(u16 val, u16 limit)
140{
141 BUG_ON(limit & (limit - 1));
142 return val & (limit - 1);
143}
144
145static inline void index_adv(u16 *index, u16 val, u16 limit)
146{
147 *index = MODULO((*index + val), limit);
148}
149
150static inline void index_inc(u16 *index, u16 limit)
151{
152 *index = MODULO((*index + 1), limit);
153}
154
155static inline void *queue_head_node(struct be_queue_info *q)
156{
157 return q->dma_mem.va + q->head * q->entry_size;
158}
159
160static inline void *queue_tail_node(struct be_queue_info *q)
161{
162 return q->dma_mem.va + q->tail * q->entry_size;
163}
164
165static inline void *queue_index_node(struct be_queue_info *q, u16 index)
166{
167 return q->dma_mem.va + index * q->entry_size;
168}
169
170static inline void queue_head_inc(struct be_queue_info *q)
171{
172 index_inc(&q->head, q->len);
173}
174
175static inline void index_dec(u16 *index, u16 limit)
176{
177 *index = MODULO((*index - 1), limit);
178}
179
180static inline void queue_tail_inc(struct be_queue_info *q)
181{
182 index_inc(&q->tail, q->len);
183}
184
185struct be_eq_obj {
186 struct be_queue_info q;
187 char desc[32];
188
189
190 bool enable_aic;
191 u32 min_eqd;
192 u32 max_eqd;
193 u32 eqd;
194 u32 cur_eqd;
195
196 u8 idx;
197 u8 msix_idx;
198 u16 tx_budget;
199 u16 spurious_intr;
200 struct napi_struct napi;
201 struct be_adapter *adapter;
202} ____cacheline_aligned_in_smp;
203
204struct be_mcc_obj {
205 struct be_queue_info q;
206 struct be_queue_info cq;
207 bool rearm_cq;
208};
209
210struct be_tx_stats {
211 u64 tx_bytes;
212 u64 tx_pkts;
213 u64 tx_reqs;
214 u64 tx_wrbs;
215 u64 tx_compl;
216 ulong tx_jiffies;
217 u32 tx_stops;
218 struct u64_stats_sync sync;
219 struct u64_stats_sync sync_compl;
220};
221
222struct be_tx_obj {
223 u32 db_offset;
224 struct be_queue_info q;
225 struct be_queue_info cq;
226
227 struct sk_buff *sent_skb_list[TX_Q_LEN];
228 struct be_tx_stats stats;
229} ____cacheline_aligned_in_smp;
230
231
232struct be_rx_page_info {
233 struct page *page;
234 DEFINE_DMA_UNMAP_ADDR(bus);
235 u16 page_offset;
236 bool last_page_user;
237};
238
239struct be_rx_stats {
240 u64 rx_bytes;
241 u64 rx_pkts;
242 u64 rx_pkts_prev;
243 ulong rx_jiffies;
244 u32 rx_drops_no_skbs;
245 u32 rx_drops_no_frags;
246 u32 rx_post_fail;
247 u32 rx_compl;
248 u32 rx_mcast_pkts;
249 u32 rx_compl_err;
250 u32 rx_pps;
251 struct u64_stats_sync sync;
252};
253
254struct be_rx_compl_info {
255 u32 rss_hash;
256 u16 vlan_tag;
257 u16 pkt_size;
258 u16 rxq_idx;
259 u16 port;
260 u8 vlanf;
261 u8 num_rcvd;
262 u8 err;
263 u8 ipf;
264 u8 tcpf;
265 u8 udpf;
266 u8 ip_csum;
267 u8 l4_csum;
268 u8 ipv6;
269 u8 vtm;
270 u8 pkt_type;
271 u8 ip_frag;
272};
273
274struct be_rx_obj {
275 struct be_adapter *adapter;
276 struct be_queue_info q;
277 struct be_queue_info cq;
278 struct be_rx_compl_info rxcp;
279 struct be_rx_page_info page_info_tbl[RX_Q_LEN];
280 struct be_rx_stats stats;
281 u8 rss_id;
282 bool rx_post_starved;
283} ____cacheline_aligned_in_smp;
284
285struct be_drv_stats {
286 u32 be_on_die_temperature;
287 u32 eth_red_drops;
288 u32 rx_drops_no_pbuf;
289 u32 rx_drops_no_txpb;
290 u32 rx_drops_no_erx_descr;
291 u32 rx_drops_no_tpre_descr;
292 u32 rx_drops_too_many_frags;
293 u32 forwarded_packets;
294 u32 rx_drops_mtu;
295 u32 rx_crc_errors;
296 u32 rx_alignment_symbol_errors;
297 u32 rx_pause_frames;
298 u32 rx_priority_pause_frames;
299 u32 rx_control_frames;
300 u32 rx_in_range_errors;
301 u32 rx_out_range_errors;
302 u32 rx_frame_too_long;
303 u32 rx_address_filtered;
304 u32 rx_dropped_too_small;
305 u32 rx_dropped_too_short;
306 u32 rx_dropped_header_too_small;
307 u32 rx_dropped_tcp_length;
308 u32 rx_dropped_runt;
309 u32 rx_ip_checksum_errs;
310 u32 rx_tcp_checksum_errs;
311 u32 rx_udp_checksum_errs;
312 u32 tx_pauseframes;
313 u32 tx_priority_pauseframes;
314 u32 tx_controlframes;
315 u32 rxpp_fifo_overflow_drop;
316 u32 rx_input_fifo_overflow_drop;
317 u32 pmem_fifo_overflow_drop;
318 u32 jabber_events;
319};
320
321struct be_vf_cfg {
322 unsigned char mac_addr[ETH_ALEN];
323 int if_handle;
324 int pmac_id;
325 u16 def_vid;
326 u16 vlan_tag;
327 u32 tx_rate;
328};
329
330enum vf_state {
331 ENABLED = 0,
332 ASSIGNED = 1
333};
334
335#define BE_FLAGS_LINK_STATUS_INIT 1
336#define BE_FLAGS_WORKER_SCHEDULED (1 << 3)
337#define BE_FLAGS_VLAN_PROMISC (1 << 4)
338#define BE_FLAGS_NAPI_ENABLED (1 << 9)
339#define BE_UC_PMAC_COUNT 30
340#define BE_VF_UC_PMAC_COUNT 2
341#define BE_FLAGS_QNQ_ASYNC_EVT_RCVD (1 << 11)
342
343
344#define LANCER_INITIATE_FW_DUMP 0x1
345
346struct phy_info {
347 u8 transceiver;
348 u8 autoneg;
349 u8 fc_autoneg;
350 u8 port_type;
351 u16 phy_type;
352 u16 interface_type;
353 u32 misc_params;
354 u16 auto_speeds_supported;
355 u16 fixed_speeds_supported;
356 int link_speed;
357 u32 dac_cable_len;
358 u32 advertising;
359 u32 supported;
360};
361
362struct be_resources {
363 u16 max_vfs;
364 u16 max_mcast_mac;
365 u16 max_tx_qs;
366 u16 max_rss_qs;
367 u16 max_rx_qs;
368 u16 max_uc_mac;
369 u16 max_vlans;
370 u16 max_evt_qs;
371 u32 if_cap_flags;
372};
373
374struct be_adapter {
375 struct pci_dev *pdev;
376 struct net_device *netdev;
377
378 u8 __iomem *csr;
379 u8 __iomem *db;
380
381 struct mutex mbox_lock;
382 struct be_dma_mem mbox_mem;
383
384
385 struct be_dma_mem mbox_mem_alloced;
386
387 struct be_mcc_obj mcc_obj;
388 spinlock_t mcc_lock;
389 spinlock_t mcc_cq_lock;
390
391 u16 cfg_num_qs;
392 u16 num_evt_qs;
393 u16 num_msix_vec;
394 struct be_eq_obj eq_obj[MAX_EVT_QS];
395 struct msix_entry msix_entries[MAX_MSIX_VECTORS];
396 bool isr_registered;
397
398
399 u16 num_tx_qs;
400 struct be_tx_obj tx_obj[MAX_TX_QS];
401
402
403 u16 num_rx_qs;
404 struct be_rx_obj rx_obj[MAX_RX_QS];
405 u32 big_page_size;
406
407 struct be_drv_stats drv_stats;
408 u16 vlans_added;
409 u8 vlan_tag[VLAN_N_VID];
410 u8 vlan_prio_bmap;
411 u16 recommended_prio;
412 struct be_dma_mem rx_filter;
413
414 struct be_dma_mem stats_cmd;
415
416 struct delayed_work work;
417 u16 work_counter;
418
419 struct delayed_work func_recovery_work;
420 u32 flags;
421 u32 cmd_privileges;
422
423 char fw_ver[FW_VER_LEN];
424 char fw_on_flash[FW_VER_LEN];
425 int if_handle;
426 u32 *pmac_id;
427 u32 beacon_state;
428
429 bool eeh_error;
430 bool fw_timeout;
431 bool hw_error;
432
433 u32 port_num;
434 bool promiscuous;
435 u32 function_mode;
436 u32 function_caps;
437 u32 rx_fc;
438 u32 tx_fc;
439 bool stats_cmd_sent;
440 u32 if_type;
441 struct {
442 u32 size;
443 u32 total_size;
444 u64 io_addr;
445 } roce_db;
446 u32 num_msix_roce_vec;
447 struct ocrdma_dev *ocrdma_dev;
448 struct list_head entry;
449
450 u32 flash_status;
451 struct completion flash_compl;
452
453 struct be_resources res;
454 u16 num_vfs;
455 u8 virtfn;
456 struct be_vf_cfg *vf_cfg;
457 bool be3_native;
458 u32 sli_family;
459 u8 hba_port_num;
460 u16 pvid;
461 struct phy_info phy;
462 u8 wol_cap;
463 bool wol;
464 u32 uc_macs;
465 u16 asic_rev;
466 u16 qnq_vid;
467 u32 msg_enable;
468 int be_get_temp_freq;
469 u8 pf_number;
470 u64 rss_flags;
471};
472
473#define be_physfn(adapter) (!adapter->virtfn)
474#define sriov_enabled(adapter) (adapter->num_vfs > 0)
475#define sriov_want(adapter) (be_max_vfs(adapter) && num_vfs && \
476 be_physfn(adapter))
477#define for_all_vfs(adapter, vf_cfg, i) \
478 for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs; \
479 i++, vf_cfg++)
480
481#define ON 1
482#define OFF 0
483
484#define be_max_vlans(adapter) (adapter->res.max_vlans)
485#define be_max_uc(adapter) (adapter->res.max_uc_mac)
486#define be_max_mc(adapter) (adapter->res.max_mcast_mac)
487#define be_max_vfs(adapter) (adapter->res.max_vfs)
488#define be_max_rss(adapter) (adapter->res.max_rss_qs)
489#define be_max_txqs(adapter) (adapter->res.max_tx_qs)
490#define be_max_prio_txqs(adapter) (adapter->res.max_prio_tx_qs)
491#define be_max_rxqs(adapter) (adapter->res.max_rx_qs)
492#define be_max_eqs(adapter) (adapter->res.max_evt_qs)
493#define be_if_cap_flags(adapter) (adapter->res.if_cap_flags)
494
495static inline u16 be_max_qs(struct be_adapter *adapter)
496{
497
498 u16 num = max_t(u16, be_max_rss(adapter), 1);
499
500 num = min(num, be_max_eqs(adapter));
501 return min_t(u16, num, num_online_cpus());
502}
503
504#define lancer_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID3 || \
505 adapter->pdev->device == OC_DEVICE_ID4)
506
507#define skyhawk_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID5 || \
508 adapter->pdev->device == OC_DEVICE_ID6)
509
510#define BE3_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID2 || \
511 adapter->pdev->device == OC_DEVICE_ID2)
512
513#define BE2_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID1 || \
514 adapter->pdev->device == OC_DEVICE_ID1)
515
516#define BEx_chip(adapter) (BE3_chip(adapter) || BE2_chip(adapter))
517
518#define be_roce_supported(adapter) (skyhawk_chip(adapter) && \
519 (adapter->function_mode & RDMA_ENABLED))
520
521extern const struct ethtool_ops be_ethtool_ops;
522
523#define msix_enabled(adapter) (adapter->num_msix_vec > 0)
524#define num_irqs(adapter) (msix_enabled(adapter) ? \
525 adapter->num_msix_vec : 1)
526#define tx_stats(txo) (&(txo)->stats)
527#define rx_stats(rxo) (&(rxo)->stats)
528
529
530#define default_rxo(adpt) (&adpt->rx_obj[adpt->num_rx_qs - 1])
531
532#define for_all_rx_queues(adapter, rxo, i) \
533 for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \
534 i++, rxo++)
535
536
537#define for_all_rss_queues(adapter, rxo, i) \
538 for (i = 0, rxo = &adapter->rx_obj[i]; i < (adapter->num_rx_qs - 1);\
539 i++, rxo++)
540
541#define for_all_tx_queues(adapter, txo, i) \
542 for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs; \
543 i++, txo++)
544
545#define for_all_evt_queues(adapter, eqo, i) \
546 for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \
547 i++, eqo++)
548
549#define is_mcc_eqo(eqo) (eqo->idx == 0)
550#define mcc_eqo(adapter) (&adapter->eq_obj[0])
551
552#define PAGE_SHIFT_4K 12
553#define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
554
555
556#define PAGES_4K_SPANNED(_address, size) \
557 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
558 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
559
560
561#define AMAP_BIT_OFFSET(_struct, field) \
562 (((size_t)&(((_struct *)0)->field))%32)
563
564
565static inline u32 amap_mask(u32 bitsize)
566{
567 return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
568}
569
570static inline void
571amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
572{
573 u32 *dw = (u32 *) ptr + dw_offset;
574 *dw &= ~(mask << offset);
575 *dw |= (mask & value) << offset;
576}
577
578#define AMAP_SET_BITS(_struct, field, ptr, val) \
579 amap_set(ptr, \
580 offsetof(_struct, field)/32, \
581 amap_mask(sizeof(((_struct *)0)->field)), \
582 AMAP_BIT_OFFSET(_struct, field), \
583 val)
584
585static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
586{
587 u32 *dw = (u32 *) ptr;
588 return mask & (*(dw + dw_offset) >> offset);
589}
590
591#define AMAP_GET_BITS(_struct, field, ptr) \
592 amap_get(ptr, \
593 offsetof(_struct, field)/32, \
594 amap_mask(sizeof(((_struct *)0)->field)), \
595 AMAP_BIT_OFFSET(_struct, field))
596
597#define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len)
598#define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len)
599static inline void swap_dws(void *wrb, int len)
600{
601#ifdef __BIG_ENDIAN
602 u32 *dw = wrb;
603 BUG_ON(len % 4);
604 do {
605 *dw = cpu_to_le32(*dw);
606 dw++;
607 len -= 4;
608 } while (len);
609#endif
610}
611
612static inline u8 is_tcp_pkt(struct sk_buff *skb)
613{
614 u8 val = 0;
615
616 if (ip_hdr(skb)->version == 4)
617 val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
618 else if (ip_hdr(skb)->version == 6)
619 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);
620
621 return val;
622}
623
624static inline u8 is_udp_pkt(struct sk_buff *skb)
625{
626 u8 val = 0;
627
628 if (ip_hdr(skb)->version == 4)
629 val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
630 else if (ip_hdr(skb)->version == 6)
631 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);
632
633 return val;
634}
635
636static inline bool is_ipv4_pkt(struct sk_buff *skb)
637{
638 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
639}
640
641static inline void be_vf_eth_addr_generate(struct be_adapter *adapter, u8 *mac)
642{
643 u32 addr;
644
645 addr = jhash(adapter->netdev->dev_addr, ETH_ALEN, 0);
646
647 mac[5] = (u8)(addr & 0xFF);
648 mac[4] = (u8)((addr >> 8) & 0xFF);
649 mac[3] = (u8)((addr >> 16) & 0xFF);
650
651 memcpy(mac, adapter->netdev->dev_addr, 3);
652}
653
654static inline bool be_multi_rxq(const struct be_adapter *adapter)
655{
656 return adapter->num_rx_qs > 1;
657}
658
659static inline bool be_error(struct be_adapter *adapter)
660{
661 return adapter->eeh_error || adapter->hw_error || adapter->fw_timeout;
662}
663
664static inline bool be_hw_error(struct be_adapter *adapter)
665{
666 return adapter->eeh_error || adapter->hw_error;
667}
668
669static inline void be_clear_all_error(struct be_adapter *adapter)
670{
671 adapter->eeh_error = false;
672 adapter->hw_error = false;
673 adapter->fw_timeout = false;
674}
675
676static inline bool be_is_wol_excluded(struct be_adapter *adapter)
677{
678 struct pci_dev *pdev = adapter->pdev;
679
680 if (!be_physfn(adapter))
681 return true;
682
683 switch (pdev->subsystem_device) {
684 case OC_SUBSYS_DEVICE_ID1:
685 case OC_SUBSYS_DEVICE_ID2:
686 case OC_SUBSYS_DEVICE_ID3:
687 case OC_SUBSYS_DEVICE_ID4:
688 return true;
689 default:
690 return false;
691 }
692}
693
694static inline int qnq_async_evt_rcvd(struct be_adapter *adapter)
695{
696 return adapter->flags & BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
697}
698
699extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm,
700 u16 num_popped);
701extern void be_link_status_update(struct be_adapter *adapter, u8 link_status);
702extern void be_parse_stats(struct be_adapter *adapter);
703extern int be_load_fw(struct be_adapter *adapter, u8 *func);
704extern bool be_is_wol_supported(struct be_adapter *adapter);
705extern bool be_pause_supported(struct be_adapter *adapter);
706extern u32 be_get_fw_log_level(struct be_adapter *adapter);
707int be_update_queues(struct be_adapter *adapter);
708int be_poll(struct napi_struct *napi, int budget);
709
710
711
712
713extern void be_roce_dev_add(struct be_adapter *);
714extern void be_roce_dev_remove(struct be_adapter *);
715
716
717
718
719extern void be_roce_dev_open(struct be_adapter *);
720extern void be_roce_dev_close(struct be_adapter *);
721
722#endif
723