1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23#ifndef __GIANFAR_H
24#define __GIANFAR_H
25
26#include <linux/kernel.h>
27#include <linux/sched.h>
28#include <linux/string.h>
29#include <linux/errno.h>
30#include <linux/slab.h>
31#include <linux/interrupt.h>
32#include <linux/init.h>
33#include <linux/delay.h>
34#include <linux/netdevice.h>
35#include <linux/etherdevice.h>
36#include <linux/skbuff.h>
37#include <linux/spinlock.h>
38#include <linux/mm.h>
39#include <linux/mii.h>
40#include <linux/phy.h>
41
42#include <asm/io.h>
43#include <asm/irq.h>
44#include <asm/uaccess.h>
45#include <linux/module.h>
46#include <linux/crc32.h>
47#include <linux/workqueue.h>
48#include <linux/ethtool.h>
49
50struct ethtool_flow_spec_container {
51 struct ethtool_rx_flow_spec fs;
52 struct list_head list;
53};
54
55struct ethtool_rx_list {
56 struct list_head list;
57 unsigned int count;
58};
59
60
61#define GFAR_DEV_WEIGHT 64
62
63
64#define GMAC_FCB_LEN 8
65
66
67#define GMAC_TXPAL_LEN 16
68
69
70#define DEFAULT_PADDING 2
71
72
73#define RXBUF_ALIGNMENT 64
74
75
76
77
78#define INCREMENTAL_BUFFER_SIZE 512
79
80#define PHY_INIT_TIMEOUT 100000
81
82#define DRV_NAME "gfar-enet"
83extern const char gfar_driver_version[];
84
85
86#define MAX_TX_QS 0x8
87#define MAX_RX_QS 0x8
88
89
90#define MAXGROUPS 0x2
91
92
93#define DEFAULT_TX_RING_SIZE 256
94#define DEFAULT_RX_RING_SIZE 256
95
96#define GFAR_RX_MAX_RING_SIZE 256
97#define GFAR_TX_MAX_RING_SIZE 256
98
99#define GFAR_MAX_FIFO_THRESHOLD 511
100#define GFAR_MAX_FIFO_STARVE 511
101#define GFAR_MAX_FIFO_STARVE_OFF 511
102
103#define DEFAULT_RX_BUFFER_SIZE 1536
104#define TX_RING_MOD_MASK(size) (size-1)
105#define RX_RING_MOD_MASK(size) (size-1)
106#define JUMBO_BUFFER_SIZE 9728
107#define JUMBO_FRAME_SIZE 9600
108
109#define DEFAULT_FIFO_TX_THR 0x100
110#define DEFAULT_FIFO_TX_STARVE 0x40
111#define DEFAULT_FIFO_TX_STARVE_OFF 0x80
112#define DEFAULT_BD_STASH 1
113#define DEFAULT_STASH_LENGTH 96
114#define DEFAULT_STASH_INDEX 0
115
116
117#define GFAR_EM_NUM 15
118
119
120
121
122
123
124
125
126
127
128
129#define GFAR_GBIT_TIME 512
130#define GFAR_100_TIME 2560
131#define GFAR_10_TIME 25600
132
133#define DEFAULT_TX_COALESCE 1
134#define DEFAULT_TXCOUNT 16
135#define DEFAULT_TXTIME 21
136
137#define DEFAULT_RXTIME 21
138
139#define DEFAULT_RX_COALESCE 0
140#define DEFAULT_RXCOUNT 0
141
142#define GFAR_SUPPORTED (SUPPORTED_10baseT_Half \
143 | SUPPORTED_10baseT_Full \
144 | SUPPORTED_100baseT_Half \
145 | SUPPORTED_100baseT_Full \
146 | SUPPORTED_Autoneg \
147 | SUPPORTED_MII)
148
149#define GFAR_SUPPORTED_GBIT (SUPPORTED_1000baseT_Full \
150 | SUPPORTED_Pause \
151 | SUPPORTED_Asym_Pause)
152
153
154#define MII_TBICON 0x11
155
156
157#define TBICON_CLK_SELECT 0x0020
158
159
160#define MACCFG1_SOFT_RESET 0x80000000
161#define MACCFG1_RESET_RX_MC 0x00080000
162#define MACCFG1_RESET_TX_MC 0x00040000
163#define MACCFG1_RESET_RX_FUN 0x00020000
164#define MACCFG1_RESET_TX_FUN 0x00010000
165#define MACCFG1_LOOPBACK 0x00000100
166#define MACCFG1_RX_FLOW 0x00000020
167#define MACCFG1_TX_FLOW 0x00000010
168#define MACCFG1_SYNCD_RX_EN 0x00000008
169#define MACCFG1_RX_EN 0x00000004
170#define MACCFG1_SYNCD_TX_EN 0x00000002
171#define MACCFG1_TX_EN 0x00000001
172
173#define MACCFG2_INIT_SETTINGS 0x00007205
174#define MACCFG2_FULL_DUPLEX 0x00000001
175#define MACCFG2_IF 0x00000300
176#define MACCFG2_MII 0x00000100
177#define MACCFG2_GMII 0x00000200
178#define MACCFG2_HUGEFRAME 0x00000020
179#define MACCFG2_LENGTHCHECK 0x00000010
180#define MACCFG2_MPEN 0x00000008
181
182#define ECNTRL_FIFM 0x00008000
183#define ECNTRL_INIT_SETTINGS 0x00001000
184#define ECNTRL_TBI_MODE 0x00000020
185#define ECNTRL_REDUCED_MODE 0x00000010
186#define ECNTRL_R100 0x00000008
187#define ECNTRL_REDUCED_MII_MODE 0x00000004
188#define ECNTRL_SGMII_MODE 0x00000002
189
190#define MRBLR_INIT_SETTINGS DEFAULT_RX_BUFFER_SIZE
191
192#define MINFLR_INIT_SETTINGS 0x00000040
193
194
195#define TQUEUE_EN0 0x00008000
196#define TQUEUE_EN1 0x00004000
197#define TQUEUE_EN2 0x00002000
198#define TQUEUE_EN3 0x00001000
199#define TQUEUE_EN4 0x00000800
200#define TQUEUE_EN5 0x00000400
201#define TQUEUE_EN6 0x00000200
202#define TQUEUE_EN7 0x00000100
203#define TQUEUE_EN_ALL 0x0000FF00
204
205#define TR03WT_WT0_MASK 0xFF000000
206#define TR03WT_WT1_MASK 0x00FF0000
207#define TR03WT_WT2_MASK 0x0000FF00
208#define TR03WT_WT3_MASK 0x000000FF
209
210#define TR47WT_WT4_MASK 0xFF000000
211#define TR47WT_WT5_MASK 0x00FF0000
212#define TR47WT_WT6_MASK 0x0000FF00
213#define TR47WT_WT7_MASK 0x000000FF
214
215
216#define RQUEUE_EX0 0x00800000
217#define RQUEUE_EX1 0x00400000
218#define RQUEUE_EX2 0x00200000
219#define RQUEUE_EX3 0x00100000
220#define RQUEUE_EX4 0x00080000
221#define RQUEUE_EX5 0x00040000
222#define RQUEUE_EX6 0x00020000
223#define RQUEUE_EX7 0x00010000
224#define RQUEUE_EX_ALL 0x00FF0000
225
226#define RQUEUE_EN0 0x00000080
227#define RQUEUE_EN1 0x00000040
228#define RQUEUE_EN2 0x00000020
229#define RQUEUE_EN3 0x00000010
230#define RQUEUE_EN4 0x00000008
231#define RQUEUE_EN5 0x00000004
232#define RQUEUE_EN6 0x00000002
233#define RQUEUE_EN7 0x00000001
234#define RQUEUE_EN_ALL 0x000000FF
235
236
237#define DMACTRL_INIT_SETTINGS 0x000000c3
238#define DMACTRL_GRS 0x00000010
239#define DMACTRL_GTS 0x00000008
240
241#define TSTAT_CLEAR_THALT_ALL 0xFF000000
242#define TSTAT_CLEAR_THALT 0x80000000
243#define TSTAT_CLEAR_THALT0 0x80000000
244#define TSTAT_CLEAR_THALT1 0x40000000
245#define TSTAT_CLEAR_THALT2 0x20000000
246#define TSTAT_CLEAR_THALT3 0x10000000
247#define TSTAT_CLEAR_THALT4 0x08000000
248#define TSTAT_CLEAR_THALT5 0x04000000
249#define TSTAT_CLEAR_THALT6 0x02000000
250#define TSTAT_CLEAR_THALT7 0x01000000
251
252
253#define IC_ICEN 0x80000000
254#define IC_ICFT_MASK 0x1fe00000
255#define IC_ICFT_SHIFT 21
256#define mk_ic_icft(x) \
257 (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK)
258#define IC_ICTT_MASK 0x0000ffff
259#define mk_ic_ictt(x) (x&IC_ICTT_MASK)
260
261#define mk_ic_value(count, time) (IC_ICEN | \
262 mk_ic_icft(count) | \
263 mk_ic_ictt(time))
264#define get_icft_value(ic) (((unsigned long)ic & IC_ICFT_MASK) >> \
265 IC_ICFT_SHIFT)
266#define get_ictt_value(ic) ((unsigned long)ic & IC_ICTT_MASK)
267
268#define DEFAULT_TXIC mk_ic_value(DEFAULT_TXCOUNT, DEFAULT_TXTIME)
269#define DEFAULT_RXIC mk_ic_value(DEFAULT_RXCOUNT, DEFAULT_RXTIME)
270
271#define skip_bd(bdp, stride, base, ring_size) ({ \
272 typeof(bdp) new_bd = (bdp) + (stride); \
273 (new_bd >= (base) + (ring_size)) ? (new_bd - (ring_size)) : new_bd; })
274
275#define next_bd(bdp, base, ring_size) skip_bd(bdp, 1, base, ring_size)
276
277#define RCTRL_TS_ENABLE 0x01000000
278#define RCTRL_PAL_MASK 0x001f0000
279#define RCTRL_VLEX 0x00002000
280#define RCTRL_FILREN 0x00001000
281#define RCTRL_GHTX 0x00000400
282#define RCTRL_IPCSEN 0x00000200
283#define RCTRL_TUCSEN 0x00000100
284#define RCTRL_PRSDEP_MASK 0x000000c0
285#define RCTRL_PRSDEP_INIT 0x000000c0
286#define RCTRL_PRSFM 0x00000020
287#define RCTRL_PROM 0x00000008
288#define RCTRL_EMEN 0x00000002
289#define RCTRL_REQ_PARSER (RCTRL_VLEX | RCTRL_IPCSEN | \
290 RCTRL_TUCSEN | RCTRL_FILREN)
291#define RCTRL_CHECKSUMMING (RCTRL_IPCSEN | RCTRL_TUCSEN | \
292 RCTRL_PRSDEP_INIT)
293#define RCTRL_EXTHASH (RCTRL_GHTX)
294#define RCTRL_VLAN (RCTRL_PRSDEP_INIT)
295#define RCTRL_PADDING(x) ((x << 16) & RCTRL_PAL_MASK)
296
297
298#define RSTAT_CLEAR_RHALT 0x00800000
299#define RSTAT_CLEAR_RXF0 0x00000080
300#define RSTAT_RXF_MASK 0x000000ff
301
302#define TCTRL_IPCSEN 0x00004000
303#define TCTRL_TUCSEN 0x00002000
304#define TCTRL_VLINS 0x00001000
305#define TCTRL_THDF 0x00000800
306#define TCTRL_RFCPAUSE 0x00000010
307#define TCTRL_TFCPAUSE 0x00000008
308#define TCTRL_TXSCHED_MASK 0x00000006
309#define TCTRL_TXSCHED_INIT 0x00000000
310
311#define TCTRL_TXSCHED_PRIO 0x00000002
312
313#define TCTRL_TXSCHED_WRRS 0x00000004
314
315
316
317
318#define DEFAULT_WRRS_WEIGHT 0x18181818
319
320#define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN)
321
322#define IEVENT_INIT_CLEAR 0xffffffff
323#define IEVENT_BABR 0x80000000
324#define IEVENT_RXC 0x40000000
325#define IEVENT_BSY 0x20000000
326#define IEVENT_EBERR 0x10000000
327#define IEVENT_MSRO 0x04000000
328#define IEVENT_GTSC 0x02000000
329#define IEVENT_BABT 0x01000000
330#define IEVENT_TXC 0x00800000
331#define IEVENT_TXE 0x00400000
332#define IEVENT_TXB 0x00200000
333#define IEVENT_TXF 0x00100000
334#define IEVENT_LC 0x00040000
335#define IEVENT_CRL 0x00020000
336#define IEVENT_XFUN 0x00010000
337#define IEVENT_RXB0 0x00008000
338#define IEVENT_MAG 0x00000800
339#define IEVENT_GRSC 0x00000100
340#define IEVENT_RXF0 0x00000080
341#define IEVENT_FIR 0x00000008
342#define IEVENT_FIQ 0x00000004
343#define IEVENT_DPE 0x00000002
344#define IEVENT_PERR 0x00000001
345#define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0 | IEVENT_BSY)
346#define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF)
347#define IEVENT_RTX_MASK (IEVENT_RX_MASK | IEVENT_TX_MASK)
348#define IEVENT_ERR_MASK \
349(IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \
350 IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \
351 | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR \
352 | IEVENT_MAG | IEVENT_BABR)
353
354#define IMASK_INIT_CLEAR 0x00000000
355#define IMASK_BABR 0x80000000
356#define IMASK_RXC 0x40000000
357#define IMASK_BSY 0x20000000
358#define IMASK_EBERR 0x10000000
359#define IMASK_MSRO 0x04000000
360#define IMASK_GTSC 0x02000000
361#define IMASK_BABT 0x01000000
362#define IMASK_TXC 0x00800000
363#define IMASK_TXEEN 0x00400000
364#define IMASK_TXBEN 0x00200000
365#define IMASK_TXFEN 0x00100000
366#define IMASK_LC 0x00040000
367#define IMASK_CRL 0x00020000
368#define IMASK_XFUN 0x00010000
369#define IMASK_RXB0 0x00008000
370#define IMASK_MAG 0x00000800
371#define IMASK_GRSC 0x00000100
372#define IMASK_RXFEN0 0x00000080
373#define IMASK_FIR 0x00000008
374#define IMASK_FIQ 0x00000004
375#define IMASK_DPE 0x00000002
376#define IMASK_PERR 0x00000001
377#define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \
378 IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \
379 IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \
380 | IMASK_PERR)
381#define IMASK_RTX_DISABLED ((~(IMASK_RXFEN0 | IMASK_TXFEN | IMASK_BSY)) \
382 & IMASK_DEFAULT)
383
384
385#define FIFO_TX_THR_MASK 0x01ff
386#define FIFO_TX_STARVE_MASK 0x01ff
387#define FIFO_TX_STARVE_OFF_MASK 0x01ff
388
389
390
391
392#define ATTR_BDSTASH 0x00000800
393
394#define ATTR_BUFSTASH 0x00004000
395
396#define ATTR_SNOOPING 0x000000c0
397#define ATTR_INIT_SETTINGS ATTR_SNOOPING
398
399#define ATTRELI_INIT_SETTINGS 0x0
400#define ATTRELI_EL_MASK 0x3fff0000
401#define ATTRELI_EL(x) (x << 16)
402#define ATTRELI_EI_MASK 0x00003fff
403#define ATTRELI_EI(x) (x)
404
405#define BD_LFLAG(flags) ((flags) << 16)
406#define BD_LENGTH_MASK 0x0000ffff
407
408#define FPR_FILER_MASK 0xFFFFFFFF
409#define MAX_FILER_IDX 0xFF
410
411
412
413#define DEFAULT_RIR0 0x05397700
414
415
416#define RQFCR_GPI 0x80000000
417#define RQFCR_HASHTBL_Q 0x00000000
418#define RQFCR_HASHTBL_0 0x00020000
419#define RQFCR_HASHTBL_1 0x00040000
420#define RQFCR_HASHTBL_2 0x00060000
421#define RQFCR_HASHTBL_3 0x00080000
422#define RQFCR_HASH 0x00010000
423#define RQFCR_QUEUE 0x0000FC00
424#define RQFCR_CLE 0x00000200
425#define RQFCR_RJE 0x00000100
426#define RQFCR_AND 0x00000080
427#define RQFCR_CMP_EXACT 0x00000000
428#define RQFCR_CMP_MATCH 0x00000020
429#define RQFCR_CMP_NOEXACT 0x00000040
430#define RQFCR_CMP_NOMATCH 0x00000060
431
432
433#define RQFCR_PID_MASK 0x00000000
434#define RQFCR_PID_PARSE 0x00000001
435#define RQFCR_PID_ARB 0x00000002
436#define RQFCR_PID_DAH 0x00000003
437#define RQFCR_PID_DAL 0x00000004
438#define RQFCR_PID_SAH 0x00000005
439#define RQFCR_PID_SAL 0x00000006
440#define RQFCR_PID_ETY 0x00000007
441#define RQFCR_PID_VID 0x00000008
442#define RQFCR_PID_PRI 0x00000009
443#define RQFCR_PID_TOS 0x0000000A
444#define RQFCR_PID_L4P 0x0000000B
445#define RQFCR_PID_DIA 0x0000000C
446#define RQFCR_PID_SIA 0x0000000D
447#define RQFCR_PID_DPT 0x0000000E
448#define RQFCR_PID_SPT 0x0000000F
449
450
451#define RQFPR_HDR_GE_512 0x00200000
452#define RQFPR_LERR 0x00100000
453#define RQFPR_RAR 0x00080000
454#define RQFPR_RARQ 0x00040000
455#define RQFPR_AR 0x00020000
456#define RQFPR_ARQ 0x00010000
457#define RQFPR_EBC 0x00008000
458#define RQFPR_VLN 0x00004000
459#define RQFPR_CFI 0x00002000
460#define RQFPR_JUM 0x00001000
461#define RQFPR_IPF 0x00000800
462#define RQFPR_FIF 0x00000400
463#define RQFPR_IPV4 0x00000200
464#define RQFPR_IPV6 0x00000100
465#define RQFPR_ICC 0x00000080
466#define RQFPR_ICV 0x00000040
467#define RQFPR_TCP 0x00000020
468#define RQFPR_UDP 0x00000010
469#define RQFPR_TUC 0x00000008
470#define RQFPR_TUV 0x00000004
471#define RQFPR_PER 0x00000002
472#define RQFPR_EER 0x00000001
473
474
475#define TXBD_READY 0x8000
476#define TXBD_PADCRC 0x4000
477#define TXBD_WRAP 0x2000
478#define TXBD_INTERRUPT 0x1000
479#define TXBD_LAST 0x0800
480#define TXBD_CRC 0x0400
481#define TXBD_DEF 0x0200
482#define TXBD_HUGEFRAME 0x0080
483#define TXBD_LATECOLLISION 0x0080
484#define TXBD_RETRYLIMIT 0x0040
485#define TXBD_RETRYCOUNTMASK 0x003c
486#define TXBD_UNDERRUN 0x0002
487#define TXBD_TOE 0x0002
488
489
490#define TXFCB_VLN 0x80
491#define TXFCB_IP 0x40
492#define TXFCB_IP6 0x20
493#define TXFCB_TUP 0x10
494#define TXFCB_UDP 0x08
495#define TXFCB_CIP 0x04
496#define TXFCB_CTU 0x02
497#define TXFCB_NPH 0x01
498#define TXFCB_DEFAULT (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH)
499
500
501#define RXBD_EMPTY 0x8000
502#define RXBD_RO1 0x4000
503#define RXBD_WRAP 0x2000
504#define RXBD_INTERRUPT 0x1000
505#define RXBD_LAST 0x0800
506#define RXBD_FIRST 0x0400
507#define RXBD_MISS 0x0100
508#define RXBD_BROADCAST 0x0080
509#define RXBD_MULTICAST 0x0040
510#define RXBD_LARGE 0x0020
511#define RXBD_NONOCTET 0x0010
512#define RXBD_SHORT 0x0008
513#define RXBD_CRCERR 0x0004
514#define RXBD_OVERRUN 0x0002
515#define RXBD_TRUNCATED 0x0001
516#define RXBD_STATS 0x01ff
517#define RXBD_ERR (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET \
518 | RXBD_CRCERR | RXBD_OVERRUN \
519 | RXBD_TRUNCATED)
520
521
522#define RXFCB_VLN 0x8000
523#define RXFCB_IP 0x4000
524#define RXFCB_IP6 0x2000
525#define RXFCB_TUP 0x1000
526#define RXFCB_CIP 0x0800
527#define RXFCB_CTU 0x0400
528#define RXFCB_EIP 0x0200
529#define RXFCB_ETU 0x0100
530#define RXFCB_CSUM_MASK 0x0f00
531#define RXFCB_PERR_MASK 0x000c
532#define RXFCB_PERR_BADL3 0x0008
533
534#define GFAR_INT_NAME_MAX (IFNAMSIZ + 6)
535
536struct txbd8
537{
538 union {
539 struct {
540 u16 status;
541 u16 length;
542 };
543 u32 lstatus;
544 };
545 u32 bufPtr;
546};
547
548struct txfcb {
549 u8 flags;
550 u8 ptp;
551 u8 l4os;
552 u8 l3os;
553 u16 phcs;
554 u16 vlctl;
555};
556
557struct rxbd8
558{
559 union {
560 struct {
561 u16 status;
562 u16 length;
563 };
564 u32 lstatus;
565 };
566 u32 bufPtr;
567};
568
569struct rxfcb {
570 u16 flags;
571 u8 rq;
572 u8 pro;
573 u16 reserved;
574 u16 vlctl;
575};
576
577struct gianfar_skb_cb {
578 unsigned int bytes_sent;
579};
580
581#define GFAR_CB(skb) ((struct gianfar_skb_cb *)((skb)->cb))
582
583struct rmon_mib
584{
585 u32 tr64;
586 u32 tr127;
587 u32 tr255;
588 u32 tr511;
589 u32 tr1k;
590 u32 trmax;
591 u32 trmgv;
592 u32 rbyt;
593 u32 rpkt;
594 u32 rfcs;
595 u32 rmca;
596 u32 rbca;
597 u32 rxcf;
598 u32 rxpf;
599 u32 rxuo;
600 u32 raln;
601 u32 rflr;
602 u32 rcde;
603 u32 rcse;
604 u32 rund;
605 u32 rovr;
606 u32 rfrg;
607 u32 rjbr;
608 u32 rdrp;
609 u32 tbyt;
610 u32 tpkt;
611 u32 tmca;
612 u32 tbca;
613 u32 txpf;
614 u32 tdfr;
615 u32 tedf;
616 u32 tscl;
617 u32 tmcl;
618 u32 tlcl;
619 u32 txcl;
620 u32 tncl;
621 u8 res1[4];
622 u32 tdrp;
623 u32 tjbr;
624 u32 tfcs;
625 u32 txcf;
626 u32 tovr;
627 u32 tund;
628 u32 tfrg;
629 u32 car1;
630 u32 car2;
631 u32 cam1;
632 u32 cam2;
633};
634
635struct gfar_extra_stats {
636 atomic64_t rx_large;
637 atomic64_t rx_short;
638 atomic64_t rx_nonoctet;
639 atomic64_t rx_crcerr;
640 atomic64_t rx_overrun;
641 atomic64_t rx_bsy;
642 atomic64_t rx_babr;
643 atomic64_t rx_trunc;
644 atomic64_t eberr;
645 atomic64_t tx_babt;
646 atomic64_t tx_underrun;
647 atomic64_t rx_skbmissing;
648 atomic64_t tx_timeout;
649};
650
651#define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32))
652#define GFAR_EXTRA_STATS_LEN \
653 (sizeof(struct gfar_extra_stats)/sizeof(atomic64_t))
654
655
656#define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN)
657
658struct gfar {
659 u32 tsec_id;
660 u32 tsec_id2;
661 u8 res1[8];
662 u32 ievent;
663 u32 imask;
664 u32 edis;
665 u32 emapg;
666 u32 ecntrl;
667 u32 minflr;
668 u32 ptv;
669 u32 dmactrl;
670 u32 tbipa;
671 u8 res2[28];
672 u32 fifo_rx_pause;
673
674 u32 fifo_rx_pause_shutoff;
675
676 u32 fifo_rx_alarm;
677
678 u32 fifo_rx_alarm_shutoff;
679
680 u8 res3[44];
681 u32 fifo_tx_thr;
682 u8 res4[8];
683 u32 fifo_tx_starve;
684 u32 fifo_tx_starve_shutoff;
685 u8 res5[96];
686 u32 tctrl;
687 u32 tstat;
688 u32 dfvlan;
689 u32 tbdlen;
690 u32 txic;
691 u32 tqueue;
692 u8 res7[40];
693 u32 tr03wt;
694 u32 tr47wt;
695 u8 res8[52];
696 u32 tbdbph;
697 u8 res9a[4];
698 u32 tbptr0;
699 u8 res9b[4];
700 u32 tbptr1;
701 u8 res9c[4];
702 u32 tbptr2;
703 u8 res9d[4];
704 u32 tbptr3;
705 u8 res9e[4];
706 u32 tbptr4;
707 u8 res9f[4];
708 u32 tbptr5;
709 u8 res9g[4];
710 u32 tbptr6;
711 u8 res9h[4];
712 u32 tbptr7;
713 u8 res9[64];
714 u32 tbaseh;
715 u32 tbase0;
716 u8 res10a[4];
717 u32 tbase1;
718 u8 res10b[4];
719 u32 tbase2;
720 u8 res10c[4];
721 u32 tbase3;
722 u8 res10d[4];
723 u32 tbase4;
724 u8 res10e[4];
725 u32 tbase5;
726 u8 res10f[4];
727 u32 tbase6;
728 u8 res10g[4];
729 u32 tbase7;
730 u8 res10[192];
731 u32 rctrl;
732 u32 rstat;
733 u8 res12[8];
734 u32 rxic;
735 u32 rqueue;
736 u32 rir0;
737 u32 rir1;
738 u32 rir2;
739 u32 rir3;
740 u8 res13[8];
741 u32 rbifx;
742 u32 rqfar;
743 u32 rqfcr;
744 u32 rqfpr;
745 u32 mrblr;
746 u8 res14[56];
747 u32 rbdbph;
748 u8 res15a[4];
749 u32 rbptr0;
750 u8 res15b[4];
751 u32 rbptr1;
752 u8 res15c[4];
753 u32 rbptr2;
754 u8 res15d[4];
755 u32 rbptr3;
756 u8 res15e[4];
757 u32 rbptr4;
758 u8 res15f[4];
759 u32 rbptr5;
760 u8 res15g[4];
761 u32 rbptr6;
762 u8 res15h[4];
763 u32 rbptr7;
764 u8 res16[64];
765 u32 rbaseh;
766 u32 rbase0;
767 u8 res17a[4];
768 u32 rbase1;
769 u8 res17b[4];
770 u32 rbase2;
771 u8 res17c[4];
772 u32 rbase3;
773 u8 res17d[4];
774 u32 rbase4;
775 u8 res17e[4];
776 u32 rbase5;
777 u8 res17f[4];
778 u32 rbase6;
779 u8 res17g[4];
780 u32 rbase7;
781 u8 res17[192];
782 u32 maccfg1;
783 u32 maccfg2;
784 u32 ipgifg;
785 u32 hafdup;
786 u32 maxfrm;
787 u8 res18[12];
788 u8 gfar_mii_regs[24];
789 u32 ifctrl;
790 u32 ifstat;
791 u32 macstnaddr1;
792 u32 macstnaddr2;
793 u32 mac01addr1;
794 u32 mac01addr2;
795 u32 mac02addr1;
796 u32 mac02addr2;
797 u32 mac03addr1;
798 u32 mac03addr2;
799 u32 mac04addr1;
800 u32 mac04addr2;
801 u32 mac05addr1;
802 u32 mac05addr2;
803 u32 mac06addr1;
804 u32 mac06addr2;
805 u32 mac07addr1;
806 u32 mac07addr2;
807 u32 mac08addr1;
808 u32 mac08addr2;
809 u32 mac09addr1;
810 u32 mac09addr2;
811 u32 mac10addr1;
812 u32 mac10addr2;
813 u32 mac11addr1;
814 u32 mac11addr2;
815 u32 mac12addr1;
816 u32 mac12addr2;
817 u32 mac13addr1;
818 u32 mac13addr2;
819 u32 mac14addr1;
820 u32 mac14addr2;
821 u32 mac15addr1;
822 u32 mac15addr2;
823 u8 res20[192];
824 struct rmon_mib rmon;
825 u32 rrej;
826 u8 res21[188];
827 u32 igaddr0;
828 u32 igaddr1;
829 u32 igaddr2;
830 u32 igaddr3;
831 u32 igaddr4;
832 u32 igaddr5;
833 u32 igaddr6;
834 u32 igaddr7;
835 u8 res22[96];
836 u32 gaddr0;
837 u32 gaddr1;
838 u32 gaddr2;
839 u32 gaddr3;
840 u32 gaddr4;
841 u32 gaddr5;
842 u32 gaddr6;
843 u32 gaddr7;
844 u8 res23a[352];
845 u32 fifocfg;
846 u8 res23b[252];
847 u8 res23c[248];
848 u32 attr;
849 u32 attreli;
850 u8 res24[688];
851 u32 isrg0;
852 u32 isrg1;
853 u32 isrg2;
854 u32 isrg3;
855 u8 res25[16];
856 u32 rxic0;
857 u32 rxic1;
858 u32 rxic2;
859 u32 rxic3;
860 u32 rxic4;
861 u32 rxic5;
862 u32 rxic6;
863 u32 rxic7;
864 u8 res26[32];
865 u32 txic0;
866 u32 txic1;
867 u32 txic2;
868 u32 txic3;
869 u32 txic4;
870 u32 txic5;
871 u32 txic6;
872 u32 txic7;
873 u8 res27[208];
874};
875
876
877#define FSL_GIANFAR_DEV_HAS_GIGABIT 0x00000001
878#define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002
879#define FSL_GIANFAR_DEV_HAS_RMON 0x00000004
880#define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008
881#define FSL_GIANFAR_DEV_HAS_CSUM 0x00000010
882#define FSL_GIANFAR_DEV_HAS_VLAN 0x00000020
883#define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH 0x00000040
884#define FSL_GIANFAR_DEV_HAS_PADDING 0x00000080
885#define FSL_GIANFAR_DEV_HAS_MAGIC_PACKET 0x00000100
886#define FSL_GIANFAR_DEV_HAS_BD_STASHING 0x00000200
887#define FSL_GIANFAR_DEV_HAS_BUF_STASHING 0x00000400
888#define FSL_GIANFAR_DEV_HAS_TIMER 0x00000800
889
890#if (MAXGROUPS == 2)
891#define DEFAULT_MAPPING 0xAA
892#else
893#define DEFAULT_MAPPING 0xFF
894#endif
895
896#define ISRG_SHIFT_TX 0x10
897#define ISRG_SHIFT_RX 0x18
898
899
900
901
902
903
904enum {
905 SQ_SG_MODE = 0,
906 MQ_MG_MODE
907};
908
909
910
911
912struct tx_q_stats {
913 unsigned long tx_packets;
914 unsigned long tx_bytes;
915};
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937struct gfar_priv_tx_q {
938
939 spinlock_t txlock __attribute__ ((aligned (SMP_CACHE_BYTES)));
940 struct txbd8 *tx_bd_base;
941 struct txbd8 *cur_tx;
942 unsigned int num_txbdfree;
943 unsigned short skb_curtx;
944 unsigned short tx_ring_size;
945 struct tx_q_stats stats;
946 struct gfar_priv_grp *grp;
947
948 struct net_device *dev;
949 struct sk_buff **tx_skbuff;
950 struct txbd8 *dirty_tx;
951 unsigned short skb_dirtytx;
952 unsigned short qindex;
953
954 unsigned int txcoalescing;
955 unsigned long txic;
956 dma_addr_t tx_bd_dma_base;
957};
958
959
960
961
962struct rx_q_stats {
963 unsigned long rx_packets;
964 unsigned long rx_bytes;
965 unsigned long rx_dropped;
966};
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982struct gfar_priv_rx_q {
983 spinlock_t rxlock __attribute__ ((aligned (SMP_CACHE_BYTES)));
984 struct sk_buff ** rx_skbuff;
985 dma_addr_t rx_bd_dma_base;
986 struct rxbd8 *rx_bd_base;
987 struct rxbd8 *cur_rx;
988 struct net_device *dev;
989 struct gfar_priv_grp *grp;
990 struct rx_q_stats stats;
991 u16 skb_currx;
992 u16 qindex;
993 unsigned int rx_ring_size;
994
995 unsigned char rxcoalescing;
996 unsigned long rxic;
997};
998
999enum gfar_irqinfo_id {
1000 GFAR_TX = 0,
1001 GFAR_RX = 1,
1002 GFAR_ER = 2,
1003 GFAR_NUM_IRQS = 3
1004};
1005
1006struct gfar_irqinfo {
1007 unsigned int irq;
1008 char name[GFAR_INT_NAME_MAX];
1009};
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019struct gfar_priv_grp {
1020 spinlock_t grplock __attribute__ ((aligned (SMP_CACHE_BYTES)));
1021 struct napi_struct napi;
1022 struct gfar_private *priv;
1023 struct gfar __iomem *regs;
1024 unsigned int rstat;
1025 unsigned long num_rx_queues;
1026 unsigned long rx_bit_map;
1027
1028 unsigned int tstat;
1029 unsigned long num_tx_queues;
1030 unsigned long tx_bit_map;
1031
1032 struct gfar_irqinfo *irqinfo[GFAR_NUM_IRQS];
1033};
1034
1035#define gfar_irq(grp, ID) \
1036 ((grp)->irqinfo[GFAR_##ID])
1037
1038enum gfar_errata {
1039 GFAR_ERRATA_74 = 0x01,
1040 GFAR_ERRATA_76 = 0x02,
1041 GFAR_ERRATA_A002 = 0x04,
1042 GFAR_ERRATA_12 = 0x08,
1043};
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054struct gfar_private {
1055 unsigned int num_rx_queues;
1056
1057 struct device *dev;
1058 struct net_device *ndev;
1059 enum gfar_errata errata;
1060 unsigned int rx_buffer_size;
1061
1062 u16 uses_rxfcb;
1063 u16 padding;
1064
1065
1066 int hwts_rx_en;
1067 int hwts_tx_en;
1068
1069 struct gfar_priv_tx_q *tx_queue[MAX_TX_QS];
1070 struct gfar_priv_rx_q *rx_queue[MAX_RX_QS];
1071 struct gfar_priv_grp gfargrp[MAXGROUPS];
1072
1073 u32 device_flags;
1074
1075 unsigned int mode;
1076 unsigned int num_tx_queues;
1077 unsigned int num_grps;
1078
1079
1080 struct gfar_extra_stats extra_stats;
1081
1082
1083 phy_interface_t interface;
1084 struct device_node *phy_node;
1085 struct device_node *tbi_node;
1086 struct phy_device *phydev;
1087 struct mii_bus *mii_bus;
1088 int oldspeed;
1089 int oldduplex;
1090 int oldlink;
1091
1092
1093 spinlock_t bflock;
1094
1095 uint32_t msg_enable;
1096
1097 struct work_struct reset_task;
1098
1099 struct platform_device *ofdev;
1100 unsigned char
1101 extended_hash:1,
1102 bd_stash_en:1,
1103 rx_filer_enable:1,
1104
1105 wol_en:1,
1106
1107 prio_sched_en:1,
1108
1109 pause_aneg_en:1,
1110 tx_pause_en:1,
1111 rx_pause_en:1;
1112
1113
1114 unsigned int total_tx_ring_size;
1115 unsigned int total_rx_ring_size;
1116
1117
1118 unsigned int rx_stash_size;
1119 unsigned int rx_stash_index;
1120
1121 u32 cur_filer_idx;
1122
1123
1124 struct ethtool_rx_list rx_list;
1125 struct mutex rx_queue_access;
1126
1127
1128 u32 __iomem *hash_regs[16];
1129 int hash_width;
1130
1131
1132 unsigned int fifo_threshold;
1133 unsigned int fifo_starve;
1134 unsigned int fifo_starve_off;
1135
1136
1137 unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
1138 unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
1139};
1140
1141
1142static inline int gfar_has_errata(struct gfar_private *priv,
1143 enum gfar_errata err)
1144{
1145 return priv->errata & err;
1146}
1147
1148static inline u32 gfar_read(unsigned __iomem *addr)
1149{
1150 u32 val;
1151 val = ioread32be(addr);
1152 return val;
1153}
1154
1155static inline void gfar_write(unsigned __iomem *addr, u32 val)
1156{
1157 iowrite32be(val, addr);
1158}
1159
1160static inline void gfar_write_filer(struct gfar_private *priv,
1161 unsigned int far, unsigned int fcr, unsigned int fpr)
1162{
1163 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1164
1165 gfar_write(®s->rqfar, far);
1166 gfar_write(®s->rqfcr, fcr);
1167 gfar_write(®s->rqfpr, fpr);
1168}
1169
1170static inline void gfar_read_filer(struct gfar_private *priv,
1171 unsigned int far, unsigned int *fcr, unsigned int *fpr)
1172{
1173 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1174
1175 gfar_write(®s->rqfar, far);
1176 *fcr = gfar_read(®s->rqfcr);
1177 *fpr = gfar_read(®s->rqfpr);
1178}
1179
1180extern void lock_rx_qs(struct gfar_private *priv);
1181extern void lock_tx_qs(struct gfar_private *priv);
1182extern void unlock_rx_qs(struct gfar_private *priv);
1183extern void unlock_tx_qs(struct gfar_private *priv);
1184extern irqreturn_t gfar_receive(int irq, void *dev_id);
1185extern int startup_gfar(struct net_device *dev);
1186extern void stop_gfar(struct net_device *dev);
1187extern void gfar_halt(struct net_device *dev);
1188extern void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev,
1189 int enable, u32 regnum, u32 read);
1190extern void gfar_configure_coalescing_all(struct gfar_private *priv);
1191void gfar_init_sysfs(struct net_device *dev);
1192int gfar_set_features(struct net_device *dev, netdev_features_t features);
1193extern void gfar_check_rx_parser_mode(struct gfar_private *priv);
1194extern void gfar_vlan_mode(struct net_device *dev, netdev_features_t features);
1195
1196extern const struct ethtool_ops gfar_ethtool_ops;
1197
1198#define MAX_FILER_CACHE_IDX (2*(MAX_FILER_IDX))
1199
1200#define RQFCR_PID_PRI_MASK 0xFFFFFFF8
1201#define RQFCR_PID_L4P_MASK 0xFFFFFF00
1202#define RQFCR_PID_VID_MASK 0xFFFFF000
1203#define RQFCR_PID_PORT_MASK 0xFFFF0000
1204#define RQFCR_PID_MAC_MASK 0xFF000000
1205
1206struct gfar_mask_entry {
1207 unsigned int mask;
1208 unsigned int start;
1209 unsigned int end;
1210 unsigned int block;
1211};
1212
1213
1214struct gfar_filer_entry {
1215 u32 ctrl;
1216 u32 prop;
1217};
1218
1219
1220
1221struct filer_table {
1222 u32 index;
1223 struct gfar_filer_entry fe[MAX_FILER_CACHE_IDX + 20];
1224};
1225
1226
1227extern int gfar_phc_index;
1228
1229#endif
1230