LXR linux/drivers/net/ethernet/intel/igb/igb.h

   1/*******************************************************************************
   2
   3  Intel(R) Gigabit Ethernet Linux driver
   4  Copyright(c) 2007-2013 Intel Corporation.
   5
   6  This program is free software; you can redistribute it and/or modify it
   7  under the terms and conditions of the GNU General Public License,
   8  version 2, as published by the Free Software Foundation.
   9
  10  This program is distributed in the hope it will be useful, but WITHOUT
  11  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  more details.
  14
  15  You should have received a copy of the GNU General Public License along with
  16  this program; if not, write to the Free Software Foundation, Inc.,
  17  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19  The full GNU General Public License is included in this distribution in
  20  the file called "COPYING".
  21
  22  Contact Information:
  23  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26*******************************************************************************/
  27
  28
  29/* Linux PRO/1000 Ethernet Driver main header file */
  30
  31#ifndef _IGB_H_
  32#define _IGB_H_
  33
  34#include "e1000_mac.h"
  35#include "e1000_82575.h"
  36
  37#include <linux/clocksource.h>
  38#include <linux/net_tstamp.h>
  39#include <linux/ptp_clock_kernel.h>
  40#include <linux/bitops.h>
  41#include <linux/if_vlan.h>
  42#include <linux/i2c.h>
  43#include <linux/i2c-algo-bit.h>
  44
  45struct igb_adapter;
  46
  47#define E1000_PCS_CFG_IGN_SD    1
  48
  49/* Interrupt defines */
  50#define IGB_START_ITR           648 /* ~6000 ints/sec */
  51#define IGB_4K_ITR              980
  52#define IGB_20K_ITR             196
  53#define IGB_70K_ITR             56
  54
  55/* TX/RX descriptor defines */
  56#define IGB_DEFAULT_TXD         256
  57#define IGB_DEFAULT_TX_WORK     128
  58#define IGB_MIN_TXD             80
  59#define IGB_MAX_TXD             4096
  60
  61#define IGB_DEFAULT_RXD         256
  62#define IGB_MIN_RXD             80
  63#define IGB_MAX_RXD             4096
  64
  65#define IGB_DEFAULT_ITR         3 /* dynamic */
  66#define IGB_MAX_ITR_USECS       10000
  67#define IGB_MIN_ITR_USECS       10
  68#define NON_Q_VECTORS           1
  69#define MAX_Q_VECTORS           8
  70
  71/* Transmit and receive queues */
  72#define IGB_MAX_RX_QUEUES       8
  73#define IGB_MAX_RX_QUEUES_82575 4
  74#define IGB_MAX_RX_QUEUES_I211  2
  75#define IGB_MAX_TX_QUEUES       8
  76#define IGB_MAX_VF_MC_ENTRIES   30
  77#define IGB_MAX_VF_FUNCTIONS    8
  78#define IGB_MAX_VFTA_ENTRIES    128
  79#define IGB_82576_VF_DEV_ID     0x10CA
  80#define IGB_I350_VF_DEV_ID      0x1520
  81
  82/* NVM version defines */
  83#define IGB_MAJOR_MASK          0xF000
  84#define IGB_MINOR_MASK          0x0FF0
  85#define IGB_BUILD_MASK          0x000F
  86#define IGB_COMB_VER_MASK       0x00FF
  87#define IGB_MAJOR_SHIFT         12
  88#define IGB_MINOR_SHIFT         4
  89#define IGB_COMB_VER_SHFT       8
  90#define IGB_NVM_VER_INVALID     0xFFFF
  91#define IGB_ETRACK_SHIFT        16
  92#define NVM_ETRACK_WORD         0x0042
  93#define NVM_COMB_VER_OFF        0x0083
  94#define NVM_COMB_VER_PTR        0x003d
  95
  96struct vf_data_storage {
  97        unsigned char vf_mac_addresses[ETH_ALEN];
  98        u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
  99        u16 num_vf_mc_hashes;
 100        u16 vlans_enabled;
 101        u32 flags;
 102        unsigned long last_nack;
 103        u16 pf_vlan; /* When set, guest VLAN config not allowed. */
 104        u16 pf_qos;
 105        u16 tx_rate;
 106        bool spoofchk_enabled;
 107};
 108
 109#define IGB_VF_FLAG_CTS            0x00000001 /* VF is clear to send data */
 110#define IGB_VF_FLAG_UNI_PROMISC    0x00000002 /* VF has unicast promisc */
 111#define IGB_VF_FLAG_MULTI_PROMISC  0x00000004 /* VF has multicast promisc */
 112#define IGB_VF_FLAG_PF_SET_MAC     0x00000008 /* PF has set MAC address */
 113
 114/* RX descriptor control thresholds.
 115 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
 116 *           descriptors available in its onboard memory.
 117 *           Setting this to 0 disables RX descriptor prefetch.
 118 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
 119 *           available in host memory.
 120 *           If PTHRESH is 0, this should also be 0.
 121 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
 122 *           descriptors until either it has this many to write back, or the
 123 *           ITR timer expires.
 124 */
 125#define IGB_RX_PTHRESH  ((hw->mac.type == e1000_i354) ? 12 : 8)
 126#define IGB_RX_HTHRESH  8
 127#define IGB_TX_PTHRESH  ((hw->mac.type == e1000_i354) ? 20 : 8)
 128#define IGB_TX_HTHRESH  1
 129#define IGB_RX_WTHRESH  ((hw->mac.type == e1000_82576 && \
 130                          adapter->msix_entries) ? 1 : 4)
 131#define IGB_TX_WTHRESH  ((hw->mac.type == e1000_82576 && \
 132                          adapter->msix_entries) ? 1 : 16)
 133
 134/* this is the size past which hardware will drop packets when setting LPE=0 */
 135#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
 136
 137/* Supported Rx Buffer Sizes */
 138#define IGB_RXBUFFER_256        256
 139#define IGB_RXBUFFER_2048       2048
 140#define IGB_RX_HDR_LEN          IGB_RXBUFFER_256
 141#define IGB_RX_BUFSZ            IGB_RXBUFFER_2048
 142
 143/* How many Rx Buffers do we bundle into one write to the hardware ? */
 144#define IGB_RX_BUFFER_WRITE     16 /* Must be power of 2 */
 145
 146#define AUTO_ALL_MODES          0
 147#define IGB_EEPROM_APME         0x0400
 148
 149#ifndef IGB_MASTER_SLAVE
 150/* Switch to override PHY master/slave setting */
 151#define IGB_MASTER_SLAVE        e1000_ms_hw_default
 152#endif
 153
 154#define IGB_MNG_VLAN_NONE       -1
 155
 156enum igb_tx_flags {
 157        /* cmd_type flags */
 158        IGB_TX_FLAGS_VLAN       = 0x01,
 159        IGB_TX_FLAGS_TSO        = 0x02,
 160        IGB_TX_FLAGS_TSTAMP     = 0x04,
 161
 162        /* olinfo flags */
 163        IGB_TX_FLAGS_IPV4       = 0x10,
 164        IGB_TX_FLAGS_CSUM       = 0x20,
 165};
 166
 167/* VLAN info */
 168#define IGB_TX_FLAGS_VLAN_MASK  0xffff0000
 169#define IGB_TX_FLAGS_VLAN_SHIFT 16
 170
 171/* The largest size we can write to the descriptor is 65535.  In order to
 172 * maintain a power of two alignment we have to limit ourselves to 32K.
 173 */
 174#define IGB_MAX_TXD_PWR 15
 175#define IGB_MAX_DATA_PER_TXD    (1 << IGB_MAX_TXD_PWR)
 176
 177/* Tx Descriptors needed, worst case */
 178#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGB_MAX_DATA_PER_TXD)
 179#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
 180
 181/* EEPROM byte offsets */
 182#define IGB_SFF_8472_SWAP               0x5C
 183#define IGB_SFF_8472_COMP               0x5E
 184
 185/* Bitmasks */
 186#define IGB_SFF_ADDRESSING_MODE         0x4
 187#define IGB_SFF_8472_UNSUP              0x00
 188
 189/* wrapper around a pointer to a socket buffer,
 190 * so a DMA handle can be stored along with the buffer
 191 */
 192struct igb_tx_buffer {
 193        union e1000_adv_tx_desc *next_to_watch;
 194        unsigned long time_stamp;
 195        struct sk_buff *skb;
 196        unsigned int bytecount;
 197        u16 gso_segs;
 198        __be16 protocol;
 199        DEFINE_DMA_UNMAP_ADDR(dma);
 200        DEFINE_DMA_UNMAP_LEN(len);
 201        u32 tx_flags;
 202};
 203
 204struct igb_rx_buffer {
 205        dma_addr_t dma;
 206        struct page *page;
 207        unsigned int page_offset;
 208};
 209
 210struct igb_tx_queue_stats {
 211        u64 packets;
 212        u64 bytes;
 213        u64 restart_queue;
 214        u64 restart_queue2;
 215};
 216
 217struct igb_rx_queue_stats {
 218        u64 packets;
 219        u64 bytes;
 220        u64 drops;
 221        u64 csum_err;
 222        u64 alloc_failed;
 223};
 224
 225struct igb_ring_container {
 226        struct igb_ring *ring;          /* pointer to linked list of rings */
 227        unsigned int total_bytes;       /* total bytes processed this int */
 228        unsigned int total_packets;     /* total packets processed this int */
 229        u16 work_limit;                 /* total work allowed per interrupt */
 230        u8 count;                       /* total number of rings in vector */
 231        u8 itr;                         /* current ITR setting for ring */
 232};
 233
 234struct igb_ring {
 235        struct igb_q_vector *q_vector;  /* backlink to q_vector */
 236        struct net_device *netdev;      /* back pointer to net_device */
 237        struct device *dev;             /* device pointer for dma mapping */
 238        union {                         /* array of buffer info structs */
 239                struct igb_tx_buffer *tx_buffer_info;
 240                struct igb_rx_buffer *rx_buffer_info;
 241        };
 242        unsigned long last_rx_timestamp;
 243        void *desc;                     /* descriptor ring memory */
 244        unsigned long flags;            /* ring specific flags */
 245        void __iomem *tail;             /* pointer to ring tail register */
 246        dma_addr_t dma;                 /* phys address of the ring */
 247        unsigned int  size;             /* length of desc. ring in bytes */
 248
 249        u16 count;                      /* number of desc. in the ring */
 250        u8 queue_index;                 /* logical index of the ring*/
 251        u8 reg_idx;                     /* physical index of the ring */
 252
 253        /* everything past this point are written often */
 254        u16 next_to_clean;
 255        u16 next_to_use;
 256        u16 next_to_alloc;
 257
 258        union {
 259                /* TX */
 260                struct {
 261                        struct igb_tx_queue_stats tx_stats;
 262                        struct u64_stats_sync tx_syncp;
 263                        struct u64_stats_sync tx_syncp2;
 264                };
 265                /* RX */
 266                struct {
 267                        struct sk_buff *skb;
 268                        struct igb_rx_queue_stats rx_stats;
 269                        struct u64_stats_sync rx_syncp;
 270                };
 271        };
 272} ____cacheline_internodealigned_in_smp;
 273
 274struct igb_q_vector {
 275        struct igb_adapter *adapter;    /* backlink */
 276        int cpu;                        /* CPU for DCA */
 277        u32 eims_value;                 /* EIMS mask value */
 278
 279        u16 itr_val;
 280        u8 set_itr;
 281        void __iomem *itr_register;
 282
 283        struct igb_ring_container rx, tx;
 284
 285        struct napi_struct napi;
 286        struct rcu_head rcu;    /* to avoid race with update stats on free */
 287        char name[IFNAMSIZ + 9];
 288
 289        /* for dynamic allocation of rings associated with this q_vector */
 290        struct igb_ring ring[0] ____cacheline_internodealigned_in_smp;
 291};
 292
 293enum e1000_ring_flags_t {
 294        IGB_RING_FLAG_RX_SCTP_CSUM,
 295        IGB_RING_FLAG_RX_LB_VLAN_BSWAP,
 296        IGB_RING_FLAG_TX_CTX_IDX,
 297        IGB_RING_FLAG_TX_DETECT_HANG
 298};
 299
 300#define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)
 301
 302#define IGB_RX_DESC(R, i)       \
 303        (&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
 304#define IGB_TX_DESC(R, i)       \
 305        (&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
 306#define IGB_TX_CTXTDESC(R, i)   \
 307        (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))
 308
 309/* igb_test_staterr - tests bits within Rx descriptor status and error fields */
 310static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc,
 311                                      const u32 stat_err_bits)
 312{
 313        return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
 314}
 315
 316/* igb_desc_unused - calculate if we have unused descriptors */
 317static inline int igb_desc_unused(struct igb_ring *ring)
 318{
 319        if (ring->next_to_clean > ring->next_to_use)
 320                return ring->next_to_clean - ring->next_to_use - 1;
 321
 322        return ring->count + ring->next_to_clean - ring->next_to_use - 1;
 323}
 324
 325#ifdef CONFIG_IGB_HWMON
 326
 327#define IGB_HWMON_TYPE_LOC      0
 328#define IGB_HWMON_TYPE_TEMP     1
 329#define IGB_HWMON_TYPE_CAUTION  2
 330#define IGB_HWMON_TYPE_MAX      3
 331
 332struct hwmon_attr {
 333        struct device_attribute dev_attr;
 334        struct e1000_hw *hw;
 335        struct e1000_thermal_diode_data *sensor;
 336        char name[12];
 337        };
 338
 339struct hwmon_buff {
 340        struct device *device;
 341        struct hwmon_attr *hwmon_list;
 342        unsigned int n_hwmon;
 343        };
 344#endif
 345
 346#define IGB_RETA_SIZE   128
 347
 348/* board specific private data structure */
 349struct igb_adapter {
 350        unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 351
 352        struct net_device *netdev;
 353
 354        unsigned long state;
 355        unsigned int flags;
 356
 357        unsigned int num_q_vectors;
 358        struct msix_entry *msix_entries;
 359
 360        /* Interrupt Throttle Rate */
 361        u32 rx_itr_setting;
 362        u32 tx_itr_setting;
 363        u16 tx_itr;
 364        u16 rx_itr;
 365
 366        /* TX */
 367        u16 tx_work_limit;
 368        u32 tx_timeout_count;
 369        int num_tx_queues;
 370        struct igb_ring *tx_ring[16];
 371
 372        /* RX */
 373        int num_rx_queues;
 374        struct igb_ring *rx_ring[16];
 375
 376        u32 max_frame_size;
 377        u32 min_frame_size;
 378
 379        struct timer_list watchdog_timer;
 380        struct timer_list phy_info_timer;
 381
 382        u16 mng_vlan_id;
 383        u32 bd_number;
 384        u32 wol;
 385        u32 en_mng_pt;
 386        u16 link_speed;
 387        u16 link_duplex;
 388
 389        struct work_struct reset_task;
 390        struct work_struct watchdog_task;
 391        bool fc_autoneg;
 392        u8  tx_timeout_factor;
 393        struct timer_list blink_timer;
 394        unsigned long led_status;
 395
 396        /* OS defined structs */
 397        struct pci_dev *pdev;
 398
 399        spinlock_t stats64_lock;
 400        struct rtnl_link_stats64 stats64;
 401
 402        /* structs defined in e1000_hw.h */
 403        struct e1000_hw hw;
 404        struct e1000_hw_stats stats;
 405        struct e1000_phy_info phy_info;
 406        struct e1000_phy_stats phy_stats;
 407
 408        u32 test_icr;
 409        struct igb_ring test_tx_ring;
 410        struct igb_ring test_rx_ring;
 411
 412        int msg_enable;
 413
 414        struct igb_q_vector *q_vector[MAX_Q_VECTORS];
 415        u32 eims_enable_mask;
 416        u32 eims_other;
 417
 418        /* to not mess up cache alignment, always add to the bottom */
 419        u16 tx_ring_count;
 420        u16 rx_ring_count;
 421        unsigned int vfs_allocated_count;
 422        struct vf_data_storage *vf_data;
 423        int vf_rate_link_speed;
 424        u32 rss_queues;
 425        u32 wvbr;
 426        u32 *shadow_vfta;
 427
 428        struct ptp_clock *ptp_clock;
 429        struct ptp_clock_info ptp_caps;
 430        struct delayed_work ptp_overflow_work;
 431        struct work_struct ptp_tx_work;
 432        struct sk_buff *ptp_tx_skb;
 433        unsigned long ptp_tx_start;
 434        unsigned long last_rx_ptp_check;
 435        spinlock_t tmreg_lock;
 436        struct cyclecounter cc;
 437        struct timecounter tc;
 438        u32 tx_hwtstamp_timeouts;
 439        u32 rx_hwtstamp_cleared;
 440
 441        char fw_version[32];
 442#ifdef CONFIG_IGB_HWMON
 443        struct hwmon_buff igb_hwmon_buff;
 444        bool ets;
 445#endif
 446        struct i2c_algo_bit_data i2c_algo;
 447        struct i2c_adapter i2c_adap;
 448        struct i2c_client *i2c_client;
 449        u32 rss_indir_tbl_init;
 450        u8 rss_indir_tbl[IGB_RETA_SIZE];
 451
 452        unsigned long link_check_timeout;
 453};
 454
 455#define IGB_FLAG_HAS_MSI                (1 << 0)
 456#define IGB_FLAG_DCA_ENABLED            (1 << 1)
 457#define IGB_FLAG_QUAD_PORT_A            (1 << 2)
 458#define IGB_FLAG_QUEUE_PAIRS            (1 << 3)
 459#define IGB_FLAG_DMAC                   (1 << 4)
 460#define IGB_FLAG_PTP                    (1 << 5)
 461#define IGB_FLAG_RSS_FIELD_IPV4_UDP     (1 << 6)
 462#define IGB_FLAG_RSS_FIELD_IPV6_UDP     (1 << 7)
 463#define IGB_FLAG_WOL_SUPPORTED          (1 << 8)
 464#define IGB_FLAG_NEED_LINK_UPDATE       (1 << 9)
 465
 466/* DMA Coalescing defines */
 467#define IGB_MIN_TXPBSIZE        20408
 468#define IGB_TX_BUF_4096         4096
 469#define IGB_DMCTLX_DCFLUSH_DIS  0x80000000  /* Disable DMA Coal Flush */
 470
 471#define IGB_82576_TSYNC_SHIFT   19
 472#define IGB_TS_HDR_LEN          16
 473enum e1000_state_t {
 474        __IGB_TESTING,
 475        __IGB_RESETTING,
 476        __IGB_DOWN
 477};
 478
 479enum igb_boards {
 480        board_82575,
 481};
 482
 483extern char igb_driver_name[];
 484extern char igb_driver_version[];
 485
 486extern int igb_up(struct igb_adapter *);
 487extern void igb_down(struct igb_adapter *);
 488extern void igb_reinit_locked(struct igb_adapter *);
 489extern void igb_reset(struct igb_adapter *);
 490extern void igb_write_rss_indir_tbl(struct igb_adapter *);
 491extern int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
 492extern int igb_setup_tx_resources(struct igb_ring *);
 493extern int igb_setup_rx_resources(struct igb_ring *);
 494extern void igb_free_tx_resources(struct igb_ring *);
 495extern void igb_free_rx_resources(struct igb_ring *);
 496extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
 497extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
 498extern void igb_setup_tctl(struct igb_adapter *);
 499extern void igb_setup_rctl(struct igb_adapter *);
 500extern netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *);
 501extern void igb_unmap_and_free_tx_resource(struct igb_ring *,
 502                                           struct igb_tx_buffer *);
 503extern void igb_alloc_rx_buffers(struct igb_ring *, u16);
 504extern void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *);
 505extern bool igb_has_link(struct igb_adapter *adapter);
 506extern void igb_set_ethtool_ops(struct net_device *);
 507extern void igb_power_up_link(struct igb_adapter *);
 508extern void igb_set_fw_version(struct igb_adapter *);
 509extern void igb_ptp_init(struct igb_adapter *adapter);
 510extern void igb_ptp_stop(struct igb_adapter *adapter);
 511extern void igb_ptp_reset(struct igb_adapter *adapter);
 512extern void igb_ptp_tx_work(struct work_struct *work);
 513extern void igb_ptp_rx_hang(struct igb_adapter *adapter);
 514extern void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter);
 515extern void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector,
 516                                struct sk_buff *skb);
 517extern void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector,
 518                                unsigned char *va,
 519                                struct sk_buff *skb);
 520static inline void igb_ptp_rx_hwtstamp(struct igb_ring *rx_ring,
 521                                       union e1000_adv_rx_desc *rx_desc,
 522                                       struct sk_buff *skb)
 523{
 524        if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
 525            !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
 526                igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
 527
 528        /* Update the last_rx_timestamp timer in order to enable watchdog check
 529         * for error case of latched timestamp on a dropped packet.
 530         */
 531        rx_ring->last_rx_timestamp = jiffies;
 532}
 533
 534extern int igb_ptp_hwtstamp_ioctl(struct net_device *netdev,
 535                                  struct ifreq *ifr, int cmd);
 536#ifdef CONFIG_IGB_HWMON
 537extern void igb_sysfs_exit(struct igb_adapter *adapter);
 538extern int igb_sysfs_init(struct igb_adapter *adapter);
 539#endif
 540static inline s32 igb_reset_phy(struct e1000_hw *hw)
 541{
 542        if (hw->phy.ops.reset)
 543                return hw->phy.ops.reset(hw);
 544
 545        return 0;
 546}
 547
 548static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
 549{
 550        if (hw->phy.ops.read_reg)
 551                return hw->phy.ops.read_reg(hw, offset, data);
 552
 553        return 0;
 554}
 555
 556static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
 557{
 558        if (hw->phy.ops.write_reg)
 559                return hw->phy.ops.write_reg(hw, offset, data);
 560
 561        return 0;
 562}
 563
 564static inline s32 igb_get_phy_info(struct e1000_hw *hw)
 565{
 566        if (hw->phy.ops.get_phy_info)
 567                return hw->phy.ops.get_phy_info(hw);
 568
 569        return 0;
 570}
 571
 572static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring)
 573{
 574        return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
 575}
 576
 577#endif /* _IGB_H_ */
 578