LXR linux/drivers/net/ethernet/intel/ixgbe/ixgbe

   1/*******************************************************************************
   2
   3  Intel 10 Gigabit PCI Express Linux driver
   4  Copyright(c) 1999 - 2013 Intel Corporation.
   5
   6  This program is free software; you can redistribute it and/or modify it
   7  under the terms and conditions of the GNU General Public License,
   8  version 2, as published by the Free Software Foundation.
   9
  10  This program is distributed in the hope it will be useful, but WITHOUT
  11  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  more details.
  14
  15  You should have received a copy of the GNU General Public License along with
  16  this program; if not, write to the Free Software Foundation, Inc.,
  17  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19  The full GNU General Public License is included in this distribution in
  20  the file called "COPYING".
  21
  22  Contact Information:
  23  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26*******************************************************************************/
  27
  28#ifndef _IXGBE_PHY_H_
  29#define _IXGBE_PHY_H_
  30
  31#include "ixgbe_type.h"
  32#define IXGBE_I2C_EEPROM_DEV_ADDR    0xA0
  33#define IXGBE_I2C_EEPROM_DEV_ADDR2   0xA2
  34
  35/* EEPROM byte offsets */
  36#define IXGBE_SFF_IDENTIFIER            0x0
  37#define IXGBE_SFF_IDENTIFIER_SFP        0x3
  38#define IXGBE_SFF_VENDOR_OUI_BYTE0      0x25
  39#define IXGBE_SFF_VENDOR_OUI_BYTE1      0x26
  40#define IXGBE_SFF_VENDOR_OUI_BYTE2      0x27
  41#define IXGBE_SFF_1GBE_COMP_CODES       0x6
  42#define IXGBE_SFF_10GBE_COMP_CODES      0x3
  43#define IXGBE_SFF_CABLE_TECHNOLOGY      0x8
  44#define IXGBE_SFF_CABLE_SPEC_COMP       0x3C
  45#define IXGBE_SFF_SFF_8472_SWAP         0x5C
  46#define IXGBE_SFF_SFF_8472_COMP         0x5E
  47#define IXGBE_SFF_SFF_8472_OSCB         0x6E
  48#define IXGBE_SFF_SFF_8472_ESCB         0x76
  49#define IXGBE_SFF_IDENTIFIER_QSFP_PLUS  0xD
  50#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0 0xA5
  51#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1 0xA6
  52#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2 0xA7
  53#define IXGBE_SFF_QSFP_CONNECTOR        0x82
  54#define IXGBE_SFF_QSFP_10GBE_COMP       0x83
  55#define IXGBE_SFF_QSFP_1GBE_COMP        0x86
  56#define IXGBE_SFF_QSFP_CABLE_LENGTH     0x92
  57#define IXGBE_SFF_QSFP_DEVICE_TECH      0x93
  58
  59/* Bitmasks */
  60#define IXGBE_SFF_DA_PASSIVE_CABLE           0x4
  61#define IXGBE_SFF_DA_ACTIVE_CABLE            0x8
  62#define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING    0x4
  63#define IXGBE_SFF_1GBASESX_CAPABLE           0x1
  64#define IXGBE_SFF_1GBASELX_CAPABLE           0x2
  65#define IXGBE_SFF_1GBASET_CAPABLE            0x8
  66#define IXGBE_SFF_10GBASESR_CAPABLE          0x10
  67#define IXGBE_SFF_10GBASELR_CAPABLE          0x20
  68#define IXGBE_SFF_SOFT_RS_SELECT_MASK   0x8
  69#define IXGBE_SFF_SOFT_RS_SELECT_10G    0x8
  70#define IXGBE_SFF_SOFT_RS_SELECT_1G     0x0
  71#define IXGBE_SFF_ADDRESSING_MODE            0x4
  72#define IXGBE_SFF_QSFP_DA_ACTIVE_CABLE       0x1
  73#define IXGBE_SFF_QSFP_DA_PASSIVE_CABLE      0x8
  74#define IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE  0x23
  75#define IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL   0x0
  76#define IXGBE_I2C_EEPROM_READ_MASK           0x100
  77#define IXGBE_I2C_EEPROM_STATUS_MASK         0x3
  78#define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0
  79#define IXGBE_I2C_EEPROM_STATUS_PASS         0x1
  80#define IXGBE_I2C_EEPROM_STATUS_FAIL         0x2
  81#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS  0x3
  82
  83/* Flow control defines */
  84#define IXGBE_TAF_SYM_PAUSE                  0x400
  85#define IXGBE_TAF_ASM_PAUSE                  0x800
  86
  87/* Bit-shift macros */
  88#define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT    24
  89#define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT    16
  90#define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT    8
  91
  92/* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
  93#define IXGBE_SFF_VENDOR_OUI_TYCO     0x00407600
  94#define IXGBE_SFF_VENDOR_OUI_FTL      0x00906500
  95#define IXGBE_SFF_VENDOR_OUI_AVAGO    0x00176A00
  96#define IXGBE_SFF_VENDOR_OUI_INTEL    0x001B2100
  97
  98/* I2C SDA and SCL timing parameters for standard mode */
  99#define IXGBE_I2C_T_HD_STA  4
 100#define IXGBE_I2C_T_LOW     5
 101#define IXGBE_I2C_T_HIGH    4
 102#define IXGBE_I2C_T_SU_STA  5
 103#define IXGBE_I2C_T_HD_DATA 5
 104#define IXGBE_I2C_T_SU_DATA 1
 105#define IXGBE_I2C_T_RISE    1
 106#define IXGBE_I2C_T_FALL    1
 107#define IXGBE_I2C_T_SU_STO  4
 108#define IXGBE_I2C_T_BUF     5
 109
 110#define IXGBE_TN_LASI_STATUS_REG        0x9005
 111#define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
 112
 113/* SFP+ SFF-8472 Compliance code */
 114#define IXGBE_SFF_SFF_8472_UNSUP      0x00
 115
 116s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
 117s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
 118s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
 119s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 120                               u32 device_type, u16 *phy_data);
 121s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 122                                u32 device_type, u16 phy_data);
 123s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 124                           u32 device_type, u16 *phy_data);
 125s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 126                            u32 device_type, u16 phy_data);
 127s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
 128s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 129                                       ixgbe_link_speed speed,
 130                                       bool autoneg_wait_to_complete);
 131s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 132                                               ixgbe_link_speed *speed,
 133                                               bool *autoneg);
 134
 135/* PHY specific */
 136s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
 137                             ixgbe_link_speed *speed,
 138                             bool *link_up);
 139s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);
 140s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
 141                                       u16 *firmware_version);
 142s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
 143                                           u16 *firmware_version);
 144
 145s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
 146s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw);
 147s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
 148s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
 149s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
 150                                        u16 *list_offset,
 151                                        u16 *data_offset);
 152s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);
 153s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
 154                                u8 dev_addr, u8 *data);
 155s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
 156                                 u8 dev_addr, u8 data);
 157s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
 158                                  u8 *eeprom_data);
 159s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
 160                                   u8 *sff8472_data);
 161s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
 162                                   u8 eeprom_data);
 163#endif /* _IXGBE_PHY_H_ */
 164