LXR linux/drivers/net/ethernet/oki-semi/pch_gbe/pch

   1/*
   2 * Copyright (C) 1999 - 2010 Intel Corporation.
   3 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
   4 *
   5 * This code was derived from the Intel e1000e Linux driver.
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License as published by
   9 * the Free Software Foundation; version 2 of the License.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, write to the Free Software
  18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  19 */
  20
  21#ifndef _PCH_GBE_H_
  22#define _PCH_GBE_H_
  23
  24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  25
  26#include <linux/mii.h>
  27#include <linux/delay.h>
  28#include <linux/pci.h>
  29#include <linux/netdevice.h>
  30#include <linux/etherdevice.h>
  31#include <linux/ethtool.h>
  32#include <linux/vmalloc.h>
  33#include <net/ip.h>
  34#include <net/tcp.h>
  35#include <net/udp.h>
  36
  37/**
  38 * pch_gbe_regs_mac_adr - Structure holding values of mac address registers
  39 * @high        Denotes the 1st to 4th byte from the initial of MAC address
  40 * @low         Denotes the 5th to 6th byte from the initial of MAC address
  41 */
  42struct pch_gbe_regs_mac_adr {
  43        u32 high;
  44        u32 low;
  45};
  46/**
  47 * pch_udc_regs - Structure holding values of MAC registers
  48 */
  49struct pch_gbe_regs {
  50        u32 INT_ST;
  51        u32 INT_EN;
  52        u32 MODE;
  53        u32 RESET;
  54        u32 TCPIP_ACC;
  55        u32 EX_LIST;
  56        u32 INT_ST_HOLD;
  57        u32 PHY_INT_CTRL;
  58        u32 MAC_RX_EN;
  59        u32 RX_FCTRL;
  60        u32 PAUSE_REQ;
  61        u32 RX_MODE;
  62        u32 TX_MODE;
  63        u32 RX_FIFO_ST;
  64        u32 TX_FIFO_ST;
  65        u32 TX_FID;
  66        u32 TX_RESULT;
  67        u32 PAUSE_PKT1;
  68        u32 PAUSE_PKT2;
  69        u32 PAUSE_PKT3;
  70        u32 PAUSE_PKT4;
  71        u32 PAUSE_PKT5;
  72        u32 reserve[2];
  73        struct pch_gbe_regs_mac_adr mac_adr[16];
  74        u32 ADDR_MASK;
  75        u32 MIIM;
  76        u32 MAC_ADDR_LOAD;
  77        u32 RGMII_ST;
  78        u32 RGMII_CTRL;
  79        u32 reserve3[3];
  80        u32 DMA_CTRL;
  81        u32 reserve4[3];
  82        u32 RX_DSC_BASE;
  83        u32 RX_DSC_SIZE;
  84        u32 RX_DSC_HW_P;
  85        u32 RX_DSC_HW_P_HLD;
  86        u32 RX_DSC_SW_P;
  87        u32 reserve5[3];
  88        u32 TX_DSC_BASE;
  89        u32 TX_DSC_SIZE;
  90        u32 TX_DSC_HW_P;
  91        u32 TX_DSC_HW_P_HLD;
  92        u32 TX_DSC_SW_P;
  93        u32 reserve6[3];
  94        u32 RX_DMA_ST;
  95        u32 TX_DMA_ST;
  96        u32 reserve7[2];
  97        u32 WOL_ST;
  98        u32 WOL_CTRL;
  99        u32 WOL_ADDR_MASK;
 100};
 101
 102/* Interrupt Status */
 103/* Interrupt Status Hold */
 104/* Interrupt Enable */
 105#define PCH_GBE_INT_RX_DMA_CMPLT  0x00000001 /* Receive DMA Transfer Complete */
 106#define PCH_GBE_INT_RX_VALID      0x00000002 /* MAC Normal Receive Complete */
 107#define PCH_GBE_INT_RX_FRAME_ERR  0x00000004 /* Receive frame error */
 108#define PCH_GBE_INT_RX_FIFO_ERR   0x00000008 /* Receive FIFO Overflow */
 109#define PCH_GBE_INT_RX_DMA_ERR    0x00000010 /* Receive DMA Transfer Error */
 110#define PCH_GBE_INT_RX_DSC_EMP    0x00000020 /* Receive Descriptor Empty */
 111#define PCH_GBE_INT_TX_CMPLT      0x00000100 /* MAC Transmission Complete */
 112#define PCH_GBE_INT_TX_DMA_CMPLT  0x00000200 /* DMA Transfer Complete */
 113#define PCH_GBE_INT_TX_FIFO_ERR   0x00000400 /* Transmission FIFO underflow. */
 114#define PCH_GBE_INT_TX_DMA_ERR    0x00000800 /* Transmission DMA Error */
 115#define PCH_GBE_INT_PAUSE_CMPLT   0x00001000 /* Pause Transmission complete */
 116#define PCH_GBE_INT_MIIM_CMPLT    0x00010000 /* MIIM I/F Read completion */
 117#define PCH_GBE_INT_PHY_INT       0x00100000 /* Interruption from PHY */
 118#define PCH_GBE_INT_WOL_DET       0x01000000 /* Wake On LAN Event detection. */
 119#define PCH_GBE_INT_TCPIP_ERR     0x10000000 /* TCP/IP Accelerator Error */
 120
 121/* Mode */
 122#define PCH_GBE_MODE_MII_ETHER      0x00000000  /* GIGA Ethernet Mode [MII] */
 123#define PCH_GBE_MODE_GMII_ETHER     0x80000000  /* GIGA Ethernet Mode [GMII] */
 124#define PCH_GBE_MODE_HALF_DUPLEX    0x00000000  /* Duplex Mode [half duplex] */
 125#define PCH_GBE_MODE_FULL_DUPLEX    0x40000000  /* Duplex Mode [full duplex] */
 126#define PCH_GBE_MODE_FR_BST         0x04000000  /* Frame bursting is done */
 127
 128/* Reset */
 129#define PCH_GBE_ALL_RST         0x80000000  /* All reset */
 130#define PCH_GBE_TX_RST          0x00008000  /* TX MAC, TX FIFO, TX DMA reset */
 131#define PCH_GBE_RX_RST          0x00004000  /* RX MAC, RX FIFO, RX DMA reset */
 132
 133/* TCP/IP Accelerator Control */
 134#define PCH_GBE_EX_LIST_EN      0x00000008  /* External List Enable */
 135#define PCH_GBE_RX_TCPIPACC_OFF 0x00000004  /* RX TCP/IP ACC Disabled */
 136#define PCH_GBE_TX_TCPIPACC_EN  0x00000002  /* TX TCP/IP ACC Enable */
 137#define PCH_GBE_RX_TCPIPACC_EN  0x00000001  /* RX TCP/IP ACC Enable */
 138
 139/* MAC RX Enable */
 140#define PCH_GBE_MRE_MAC_RX_EN   0x00000001      /* MAC Receive Enable */
 141
 142/* RX Flow Control */
 143#define PCH_GBE_FL_CTRL_EN      0x80000000  /* Pause packet is enabled */
 144
 145/* Pause Packet Request */
 146#define PCH_GBE_PS_PKT_RQ       0x80000000  /* Pause packet Request */
 147
 148/* RX Mode */
 149#define PCH_GBE_ADD_FIL_EN      0x80000000  /* Address Filtering Enable */
 150/* Multicast Filtering Enable */
 151#define PCH_GBE_MLT_FIL_EN      0x40000000
 152/* Receive Almost Empty Threshold */
 153#define PCH_GBE_RH_ALM_EMP_4    0x00000000      /* 4 words */
 154#define PCH_GBE_RH_ALM_EMP_8    0x00004000      /* 8 words */
 155#define PCH_GBE_RH_ALM_EMP_16   0x00008000      /* 16 words */
 156#define PCH_GBE_RH_ALM_EMP_32   0x0000C000      /* 32 words */
 157/* Receive Almost Full Threshold */
 158#define PCH_GBE_RH_ALM_FULL_4   0x00000000      /* 4 words */
 159#define PCH_GBE_RH_ALM_FULL_8   0x00001000      /* 8 words */
 160#define PCH_GBE_RH_ALM_FULL_16  0x00002000      /* 16 words */
 161#define PCH_GBE_RH_ALM_FULL_32  0x00003000      /* 32 words */
 162/* RX FIFO Read Triger Threshold */
 163#define PCH_GBE_RH_RD_TRG_4     0x00000000      /* 4 words */
 164#define PCH_GBE_RH_RD_TRG_8     0x00000200      /* 8 words */
 165#define PCH_GBE_RH_RD_TRG_16    0x00000400      /* 16 words */
 166#define PCH_GBE_RH_RD_TRG_32    0x00000600      /* 32 words */
 167#define PCH_GBE_RH_RD_TRG_64    0x00000800      /* 64 words */
 168#define PCH_GBE_RH_RD_TRG_128   0x00000A00      /* 128 words */
 169#define PCH_GBE_RH_RD_TRG_256   0x00000C00      /* 256 words */
 170#define PCH_GBE_RH_RD_TRG_512   0x00000E00      /* 512 words */
 171
 172/* Receive Descriptor bit definitions */
 173#define PCH_GBE_RXD_ACC_STAT_BCAST          0x00000400
 174#define PCH_GBE_RXD_ACC_STAT_MCAST          0x00000200
 175#define PCH_GBE_RXD_ACC_STAT_UCAST          0x00000100
 176#define PCH_GBE_RXD_ACC_STAT_TCPIPOK        0x000000C0
 177#define PCH_GBE_RXD_ACC_STAT_IPOK           0x00000080
 178#define PCH_GBE_RXD_ACC_STAT_TCPOK          0x00000040
 179#define PCH_GBE_RXD_ACC_STAT_IP6ERR         0x00000020
 180#define PCH_GBE_RXD_ACC_STAT_OFLIST         0x00000010
 181#define PCH_GBE_RXD_ACC_STAT_TYPEIP         0x00000008
 182#define PCH_GBE_RXD_ACC_STAT_MACL           0x00000004
 183#define PCH_GBE_RXD_ACC_STAT_PPPOE          0x00000002
 184#define PCH_GBE_RXD_ACC_STAT_VTAGT          0x00000001
 185#define PCH_GBE_RXD_GMAC_STAT_PAUSE         0x0200
 186#define PCH_GBE_RXD_GMAC_STAT_MARBR         0x0100
 187#define PCH_GBE_RXD_GMAC_STAT_MARMLT        0x0080
 188#define PCH_GBE_RXD_GMAC_STAT_MARIND        0x0040
 189#define PCH_GBE_RXD_GMAC_STAT_MARNOTMT      0x0020
 190#define PCH_GBE_RXD_GMAC_STAT_TLONG         0x0010
 191#define PCH_GBE_RXD_GMAC_STAT_TSHRT         0x0008
 192#define PCH_GBE_RXD_GMAC_STAT_NOTOCTAL      0x0004
 193#define PCH_GBE_RXD_GMAC_STAT_NBLERR        0x0002
 194#define PCH_GBE_RXD_GMAC_STAT_CRCERR        0x0001
 195
 196/* Transmit Descriptor bit definitions */
 197#define PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF      0x0008
 198#define PCH_GBE_TXD_CTRL_ITAG               0x0004
 199#define PCH_GBE_TXD_CTRL_ICRC               0x0002
 200#define PCH_GBE_TXD_CTRL_APAD               0x0001
 201#define PCH_GBE_TXD_WORDS_SHIFT             2
 202#define PCH_GBE_TXD_GMAC_STAT_CMPLT         0x2000
 203#define PCH_GBE_TXD_GMAC_STAT_ABT           0x1000
 204#define PCH_GBE_TXD_GMAC_STAT_EXCOL         0x0800
 205#define PCH_GBE_TXD_GMAC_STAT_SNGCOL        0x0400
 206#define PCH_GBE_TXD_GMAC_STAT_MLTCOL        0x0200
 207#define PCH_GBE_TXD_GMAC_STAT_CRSER         0x0100
 208#define PCH_GBE_TXD_GMAC_STAT_TLNG          0x0080
 209#define PCH_GBE_TXD_GMAC_STAT_TSHRT         0x0040
 210#define PCH_GBE_TXD_GMAC_STAT_LTCOL         0x0020
 211#define PCH_GBE_TXD_GMAC_STAT_TFUNDFLW      0x0010
 212#define PCH_GBE_TXD_GMAC_STAT_RTYCNT_MASK   0x000F
 213
 214/* TX Mode */
 215#define PCH_GBE_TM_NO_RTRY     0x80000000 /* No Retransmission */
 216#define PCH_GBE_TM_LONG_PKT    0x40000000 /* Long Packt TX Enable */
 217#define PCH_GBE_TM_ST_AND_FD   0x20000000 /* Stare and Forward */
 218#define PCH_GBE_TM_SHORT_PKT   0x10000000 /* Short Packet TX Enable */
 219#define PCH_GBE_TM_LTCOL_RETX  0x08000000 /* Retransmission at Late Collision */
 220/* Frame Start Threshold */
 221#define PCH_GBE_TM_TH_TX_STRT_4    0x00000000    /* 4 words */
 222#define PCH_GBE_TM_TH_TX_STRT_8    0x00004000    /* 8 words */
 223#define PCH_GBE_TM_TH_TX_STRT_16   0x00008000    /* 16 words */
 224#define PCH_GBE_TM_TH_TX_STRT_32   0x0000C000    /* 32 words */
 225/* Transmit Almost Empty Threshold */
 226#define PCH_GBE_TM_TH_ALM_EMP_4    0x00000000    /* 4 words */
 227#define PCH_GBE_TM_TH_ALM_EMP_8    0x00000800    /* 8 words */
 228#define PCH_GBE_TM_TH_ALM_EMP_16   0x00001000    /* 16 words */
 229#define PCH_GBE_TM_TH_ALM_EMP_32   0x00001800    /* 32 words */
 230#define PCH_GBE_TM_TH_ALM_EMP_64   0x00002000    /* 64 words */
 231#define PCH_GBE_TM_TH_ALM_EMP_128  0x00002800    /* 128 words */
 232#define PCH_GBE_TM_TH_ALM_EMP_256  0x00003000    /* 256 words */
 233#define PCH_GBE_TM_TH_ALM_EMP_512  0x00003800    /* 512 words */
 234/* Transmit Almost Full Threshold */
 235#define PCH_GBE_TM_TH_ALM_FULL_4   0x00000000    /* 4 words */
 236#define PCH_GBE_TM_TH_ALM_FULL_8   0x00000200    /* 8 words */
 237#define PCH_GBE_TM_TH_ALM_FULL_16  0x00000400    /* 16 words */
 238#define PCH_GBE_TM_TH_ALM_FULL_32  0x00000600    /* 32 words */
 239
 240/* RX FIFO Status */
 241#define PCH_GBE_RF_ALM_FULL     0x80000000  /* RX FIFO is almost full. */
 242#define PCH_GBE_RF_ALM_EMP      0x40000000  /* RX FIFO is almost empty. */
 243#define PCH_GBE_RF_RD_TRG       0x20000000  /* Become more than RH_RD_TRG. */
 244#define PCH_GBE_RF_STRWD        0x1FFE0000  /* The word count of RX FIFO. */
 245#define PCH_GBE_RF_RCVING       0x00010000  /* Stored in RX FIFO. */
 246
 247/* MAC Address Mask */
 248#define PCH_GBE_BUSY                0x80000000
 249
 250/* MIIM  */
 251#define PCH_GBE_MIIM_OPER_WRITE     0x04000000
 252#define PCH_GBE_MIIM_OPER_READ      0x00000000
 253#define PCH_GBE_MIIM_OPER_READY     0x04000000
 254#define PCH_GBE_MIIM_PHY_ADDR_SHIFT 21
 255#define PCH_GBE_MIIM_REG_ADDR_SHIFT 16
 256
 257/* RGMII Status */
 258#define PCH_GBE_LINK_UP             0x80000008
 259#define PCH_GBE_RXC_SPEED_MSK       0x00000006
 260#define PCH_GBE_RXC_SPEED_2_5M      0x00000000    /* 2.5MHz */
 261#define PCH_GBE_RXC_SPEED_25M       0x00000002    /* 25MHz  */
 262#define PCH_GBE_RXC_SPEED_125M      0x00000004    /* 100MHz */
 263#define PCH_GBE_DUPLEX_FULL         0x00000001
 264
 265/* RGMII Control */
 266#define PCH_GBE_CRS_SEL             0x00000010
 267#define PCH_GBE_RGMII_RATE_125M     0x00000000
 268#define PCH_GBE_RGMII_RATE_25M      0x00000008
 269#define PCH_GBE_RGMII_RATE_2_5M     0x0000000C
 270#define PCH_GBE_RGMII_MODE_GMII     0x00000000
 271#define PCH_GBE_RGMII_MODE_RGMII    0x00000002
 272#define PCH_GBE_CHIP_TYPE_EXTERNAL  0x00000000
 273#define PCH_GBE_CHIP_TYPE_INTERNAL  0x00000001
 274
 275/* DMA Control */
 276#define PCH_GBE_RX_DMA_EN       0x00000002   /* Enables Receive DMA */
 277#define PCH_GBE_TX_DMA_EN       0x00000001   /* Enables Transmission DMA */
 278
 279/* RX DMA STATUS */
 280#define PCH_GBE_IDLE_CHECK       0xFFFFFFFE
 281
 282/* Wake On LAN Status */
 283#define PCH_GBE_WLS_BR          0x00000008 /* Broadcas Address */
 284#define PCH_GBE_WLS_MLT         0x00000004 /* Multicast Address */
 285
 286/* The Frame registered in Address Recognizer */
 287#define PCH_GBE_WLS_IND         0x00000002
 288#define PCH_GBE_WLS_MP          0x00000001 /* Magic packet Address */
 289
 290/* Wake On LAN Control */
 291#define PCH_GBE_WLC_WOL_MODE    0x00010000
 292#define PCH_GBE_WLC_IGN_TLONG   0x00000100
 293#define PCH_GBE_WLC_IGN_TSHRT   0x00000080
 294#define PCH_GBE_WLC_IGN_OCTER   0x00000040
 295#define PCH_GBE_WLC_IGN_NBLER   0x00000020
 296#define PCH_GBE_WLC_IGN_CRCER   0x00000010
 297#define PCH_GBE_WLC_BR          0x00000008
 298#define PCH_GBE_WLC_MLT         0x00000004
 299#define PCH_GBE_WLC_IND         0x00000002
 300#define PCH_GBE_WLC_MP          0x00000001
 301
 302/* Wake On LAN Address Mask */
 303#define PCH_GBE_WLA_BUSY        0x80000000
 304
 305
 306
 307/* TX/RX descriptor defines */
 308#define PCH_GBE_MAX_TXD                     4096
 309#define PCH_GBE_DEFAULT_TXD                  256
 310#define PCH_GBE_MIN_TXD                        8
 311#define PCH_GBE_MAX_RXD                     4096
 312#define PCH_GBE_DEFAULT_RXD                  256
 313#define PCH_GBE_MIN_RXD                        8
 314
 315/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
 316#define PCH_GBE_TX_DESC_MULTIPLE               8
 317#define PCH_GBE_RX_DESC_MULTIPLE               8
 318
 319/* Read/Write operation is done through MII Management IF */
 320#define PCH_GBE_HAL_MIIM_READ          ((u32)0x00000000)
 321#define PCH_GBE_HAL_MIIM_WRITE         ((u32)0x04000000)
 322
 323/* flow control values */
 324#define PCH_GBE_FC_NONE                 0
 325#define PCH_GBE_FC_RX_PAUSE             1
 326#define PCH_GBE_FC_TX_PAUSE             2
 327#define PCH_GBE_FC_FULL                 3
 328#define PCH_GBE_FC_DEFAULT              PCH_GBE_FC_FULL
 329
 330
 331struct pch_gbe_hw;
 332/**
 333 * struct  pch_gbe_functions - HAL APi function pointer
 334 * @get_bus_info:       for pch_gbe_hal_get_bus_info
 335 * @init_hw:            for pch_gbe_hal_init_hw
 336 * @read_phy_reg:       for pch_gbe_hal_read_phy_reg
 337 * @write_phy_reg:      for pch_gbe_hal_write_phy_reg
 338 * @reset_phy:          for pch_gbe_hal_phy_hw_reset
 339 * @sw_reset_phy:       for pch_gbe_hal_phy_sw_reset
 340 * @power_up_phy:       for pch_gbe_hal_power_up_phy
 341 * @power_down_phy:     for pch_gbe_hal_power_down_phy
 342 * @read_mac_addr:      for pch_gbe_hal_read_mac_addr
 343 */
 344struct pch_gbe_functions {
 345        void (*get_bus_info) (struct pch_gbe_hw *);
 346        s32 (*init_hw) (struct pch_gbe_hw *);
 347        s32 (*read_phy_reg) (struct pch_gbe_hw *, u32, u16 *);
 348        s32 (*write_phy_reg) (struct pch_gbe_hw *, u32, u16);
 349        void (*reset_phy) (struct pch_gbe_hw *);
 350        void (*sw_reset_phy) (struct pch_gbe_hw *);
 351        void (*power_up_phy) (struct pch_gbe_hw *hw);
 352        void (*power_down_phy) (struct pch_gbe_hw *hw);
 353        s32 (*read_mac_addr) (struct pch_gbe_hw *);
 354};
 355
 356/**
 357 * struct pch_gbe_mac_info - MAC information
 358 * @addr[6]:            Store the MAC address
 359 * @fc:                 Mode of flow control
 360 * @fc_autoneg:         Auto negotiation enable for flow control setting
 361 * @tx_fc_enable:       Enable flag of Transmit flow control
 362 * @max_frame_size:     Max transmit frame size
 363 * @min_frame_size:     Min transmit frame size
 364 * @autoneg:            Auto negotiation enable
 365 * @link_speed:         Link speed
 366 * @link_duplex:        Link duplex
 367 */
 368struct pch_gbe_mac_info {
 369        u8 addr[6];
 370        u8 fc;
 371        u8 fc_autoneg;
 372        u8 tx_fc_enable;
 373        u32 max_frame_size;
 374        u32 min_frame_size;
 375        u8 autoneg;
 376        u16 link_speed;
 377        u16 link_duplex;
 378};
 379
 380/**
 381 * struct pch_gbe_phy_info - PHY information
 382 * @addr:               PHY address
 383 * @id:                 PHY's identifier
 384 * @revision:           PHY's revision
 385 * @reset_delay_us:     HW reset delay time[us]
 386 * @autoneg_advertised: Autoneg advertised
 387 */
 388struct pch_gbe_phy_info {
 389        u32 addr;
 390        u32 id;
 391        u32 revision;
 392        u32 reset_delay_us;
 393        u16 autoneg_advertised;
 394};
 395
 396/*!
 397 * @ingroup Gigabit Ether driver Layer
 398 * @struct  pch_gbe_bus_info
 399 * @brief   Bus information
 400 */
 401struct pch_gbe_bus_info {
 402        u8 type;
 403        u8 speed;
 404        u8 width;
 405};
 406
 407/*!
 408 * @ingroup Gigabit Ether driver Layer
 409 * @struct  pch_gbe_hw
 410 * @brief   Hardware information
 411 */
 412struct pch_gbe_hw {
 413        void *back;
 414
 415        struct pch_gbe_regs  __iomem *reg;
 416        spinlock_t miim_lock;
 417
 418        const struct pch_gbe_functions *func;
 419        struct pch_gbe_mac_info mac;
 420        struct pch_gbe_phy_info phy;
 421        struct pch_gbe_bus_info bus;
 422};
 423
 424/**
 425 * struct pch_gbe_rx_desc - Receive Descriptor
 426 * @buffer_addr:        RX Frame Buffer Address
 427 * @tcp_ip_status:      TCP/IP Accelerator Status
 428 * @rx_words_eob:       RX word count and Byte position
 429 * @gbec_status:        GMAC Status
 430 * @dma_status:         DMA Status
 431 * @reserved1:          Reserved
 432 * @reserved2:          Reserved
 433 */
 434struct pch_gbe_rx_desc {
 435        u32 buffer_addr;
 436        u32 tcp_ip_status;
 437        u16 rx_words_eob;
 438        u16 gbec_status;
 439        u8 dma_status;
 440        u8 reserved1;
 441        u16 reserved2;
 442};
 443
 444/**
 445 * struct pch_gbe_tx_desc - Transmit Descriptor
 446 * @buffer_addr:        TX Frame Buffer Address
 447 * @length:             Data buffer length
 448 * @reserved1:          Reserved
 449 * @tx_words_eob:       TX word count and Byte position
 450 * @tx_frame_ctrl:      TX Frame Control
 451 * @dma_status:         DMA Status
 452 * @reserved2:          Reserved
 453 * @gbec_status:        GMAC Status
 454 */
 455struct pch_gbe_tx_desc {
 456        u32 buffer_addr;
 457        u16 length;
 458        u16 reserved1;
 459        u16 tx_words_eob;
 460        u16 tx_frame_ctrl;
 461        u8 dma_status;
 462        u8 reserved2;
 463        u16 gbec_status;
 464};
 465
 466
 467/**
 468 * struct pch_gbe_buffer - Buffer information
 469 * @skb:        pointer to a socket buffer
 470 * @dma:        DMA address
 471 * @time_stamp: time stamp
 472 * @length:     data size
 473 */
 474struct pch_gbe_buffer {
 475        struct sk_buff *skb;
 476        dma_addr_t dma;
 477        unsigned char *rx_buffer;
 478        unsigned long time_stamp;
 479        u16 length;
 480        bool mapped;
 481};
 482
 483/**
 484 * struct pch_gbe_tx_ring - tx ring information
 485 * @tx_lock:    spinlock structs
 486 * @desc:       pointer to the descriptor ring memory
 487 * @dma:        physical address of the descriptor ring
 488 * @size:       length of descriptor ring in bytes
 489 * @count:      number of descriptors in the ring
 490 * @next_to_use:        next descriptor to associate a buffer with
 491 * @next_to_clean:      next descriptor to check for DD status bit
 492 * @buffer_info:        array of buffer information structs
 493 */
 494struct pch_gbe_tx_ring {
 495        spinlock_t tx_lock;
 496        struct pch_gbe_tx_desc *desc;
 497        dma_addr_t dma;
 498        unsigned int size;
 499        unsigned int count;
 500        unsigned int next_to_use;
 501        unsigned int next_to_clean;
 502        struct pch_gbe_buffer *buffer_info;
 503};
 504
 505/**
 506 * struct pch_gbe_rx_ring - rx ring information
 507 * @desc:       pointer to the descriptor ring memory
 508 * @dma:        physical address of the descriptor ring
 509 * @size:       length of descriptor ring in bytes
 510 * @count:      number of descriptors in the ring
 511 * @next_to_use:        next descriptor to associate a buffer with
 512 * @next_to_clean:      next descriptor to check for DD status bit
 513 * @buffer_info:        array of buffer information structs
 514 */
 515struct pch_gbe_rx_ring {
 516        struct pch_gbe_rx_desc *desc;
 517        dma_addr_t dma;
 518        unsigned char *rx_buff_pool;
 519        dma_addr_t rx_buff_pool_logic;
 520        unsigned int rx_buff_pool_size;
 521        unsigned int size;
 522        unsigned int count;
 523        unsigned int next_to_use;
 524        unsigned int next_to_clean;
 525        struct pch_gbe_buffer *buffer_info;
 526};
 527
 528/**
 529 * struct pch_gbe_hw_stats - Statistics counters collected by the MAC
 530 * @rx_packets:             total packets received
 531 * @tx_packets:             total packets transmitted
 532 * @rx_bytes:               total bytes received
 533 * @tx_bytes:               total bytes transmitted
 534 * @rx_errors:              bad packets received
 535 * @tx_errors:              packet transmit problems
 536 * @rx_dropped:             no space in Linux buffers
 537 * @tx_dropped:             no space available in Linux
 538 * @multicast:              multicast packets received
 539 * @collisions:             collisions
 540 * @rx_crc_errors:          received packet with crc error
 541 * @rx_frame_errors:        received frame alignment error
 542 * @rx_alloc_buff_failed:   allocate failure of a receive buffer
 543 * @tx_length_errors:       transmit length error
 544 * @tx_aborted_errors:      transmit aborted error
 545 * @tx_carrier_errors:      transmit carrier error
 546 * @tx_timeout_count:       Number of transmit timeout
 547 * @tx_restart_count:       Number of transmit restert
 548 * @intr_rx_dsc_empty_count:    Interrupt count of receive descriptor empty
 549 * @intr_rx_frame_err_count:    Interrupt count of receive frame error
 550 * @intr_rx_fifo_err_count:     Interrupt count of receive FIFO error
 551 * @intr_rx_dma_err_count:      Interrupt count of receive DMA error
 552 * @intr_tx_fifo_err_count:     Interrupt count of transmit FIFO error
 553 * @intr_tx_dma_err_count:      Interrupt count of transmit DMA error
 554 * @intr_tcpip_err_count:       Interrupt count of TCP/IP Accelerator
 555 */
 556struct pch_gbe_hw_stats {
 557        u32 rx_packets;
 558        u32 tx_packets;
 559        u32 rx_bytes;
 560        u32 tx_bytes;
 561        u32 rx_errors;
 562        u32 tx_errors;
 563        u32 rx_dropped;
 564        u32 tx_dropped;
 565        u32 multicast;
 566        u32 collisions;
 567        u32 rx_crc_errors;
 568        u32 rx_frame_errors;
 569        u32 rx_alloc_buff_failed;
 570        u32 tx_length_errors;
 571        u32 tx_aborted_errors;
 572        u32 tx_carrier_errors;
 573        u32 tx_timeout_count;
 574        u32 tx_restart_count;
 575        u32 intr_rx_dsc_empty_count;
 576        u32 intr_rx_frame_err_count;
 577        u32 intr_rx_fifo_err_count;
 578        u32 intr_rx_dma_err_count;
 579        u32 intr_tx_fifo_err_count;
 580        u32 intr_tx_dma_err_count;
 581        u32 intr_tcpip_err_count;
 582};
 583
 584/**
 585 * struct pch_gbe_privdata - PCI Device ID driver data
 586 * @phy_tx_clk_delay:           Bool, configure the PHY TX delay in software
 587 * @phy_disable_hibernate:      Bool, disable PHY hibernation
 588 * @platform_init:              Platform initialization callback, called from
 589 *                              probe, prior to PHY initialization.
 590 */
 591struct pch_gbe_privdata {
 592        bool phy_tx_clk_delay;
 593        bool phy_disable_hibernate;
 594        int (*platform_init)(struct pci_dev *pdev);
 595};
 596
 597/**
 598 * struct pch_gbe_adapter - board specific private data structure
 599 * @stats_lock: Spinlock structure for status
 600 * @ethtool_lock:       Spinlock structure for ethtool
 601 * @irq_sem:            Semaphore for interrupt
 602 * @netdev:             Pointer of network device structure
 603 * @pdev:               Pointer of pci device structure
 604 * @polling_netdev:     Pointer of polling network device structure
 605 * @napi:               NAPI structure
 606 * @hw:                 Pointer of hardware structure
 607 * @stats:              Hardware status
 608 * @reset_task:         Reset task
 609 * @mii:                MII information structure
 610 * @watchdog_timer:     Watchdog timer list
 611 * @wake_up_evt:        Wake up event
 612 * @config_space:       Configuration space
 613 * @msg_enable:         Driver message level
 614 * @led_status:         LED status
 615 * @tx_ring:            Pointer of Tx descriptor ring structure
 616 * @rx_ring:            Pointer of Rx descriptor ring structure
 617 * @rx_buffer_len:      Receive buffer length
 618 * @tx_queue_len:       Transmit queue length
 619 * @have_msi:           PCI MSI mode flag
 620 * @pch_gbe_privdata:   PCI Device ID driver_data
 621 */
 622
 623struct pch_gbe_adapter {
 624        spinlock_t stats_lock;
 625        spinlock_t ethtool_lock;
 626        atomic_t irq_sem;
 627        struct net_device *netdev;
 628        struct pci_dev *pdev;
 629        struct net_device *polling_netdev;
 630        struct napi_struct napi;
 631        struct pch_gbe_hw hw;
 632        struct pch_gbe_hw_stats stats;
 633        struct work_struct reset_task;
 634        struct mii_if_info mii;
 635        struct timer_list watchdog_timer;
 636        u32 wake_up_evt;
 637        u32 *config_space;
 638        unsigned long led_status;
 639        struct pch_gbe_tx_ring *tx_ring;
 640        struct pch_gbe_rx_ring *rx_ring;
 641        unsigned long rx_buffer_len;
 642        unsigned long tx_queue_len;
 643        bool have_msi;
 644        bool rx_stop_flag;
 645        int hwts_tx_en;
 646        int hwts_rx_en;
 647        struct pci_dev *ptp_pdev;
 648        struct pch_gbe_privdata *pdata;
 649};
 650
 651#define pch_gbe_hw_to_adapter(hw)       container_of(hw, struct pch_gbe_adapter, hw)
 652
 653extern const char pch_driver_version[];
 654
 655/* pch_gbe_main.c */
 656extern int pch_gbe_up(struct pch_gbe_adapter *adapter);
 657extern void pch_gbe_down(struct pch_gbe_adapter *adapter);
 658extern void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter);
 659extern void pch_gbe_reset(struct pch_gbe_adapter *adapter);
 660extern int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
 661                                       struct pch_gbe_tx_ring *txdr);
 662extern int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
 663                                       struct pch_gbe_rx_ring *rxdr);
 664extern void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
 665                                       struct pch_gbe_tx_ring *tx_ring);
 666extern void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
 667                                       struct pch_gbe_rx_ring *rx_ring);
 668extern void pch_gbe_update_stats(struct pch_gbe_adapter *adapter);
 669extern u32 pch_ch_control_read(struct pci_dev *pdev);
 670extern void pch_ch_control_write(struct pci_dev *pdev, u32 val);
 671extern u32 pch_ch_event_read(struct pci_dev *pdev);
 672extern void pch_ch_event_write(struct pci_dev *pdev, u32 val);
 673extern u32 pch_src_uuid_lo_read(struct pci_dev *pdev);
 674extern u32 pch_src_uuid_hi_read(struct pci_dev *pdev);
 675extern u64 pch_rx_snap_read(struct pci_dev *pdev);
 676extern u64 pch_tx_snap_read(struct pci_dev *pdev);
 677extern int pch_set_station_address(u8 *addr, struct pci_dev *pdev);
 678
 679/* pch_gbe_param.c */
 680extern void pch_gbe_check_options(struct pch_gbe_adapter *adapter);
 681
 682/* pch_gbe_ethtool.c */
 683extern void pch_gbe_set_ethtool_ops(struct net_device *netdev);
 684
 685/* pch_gbe_mac.c */
 686extern s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw);
 687extern s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw);
 688extern u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw,
 689                                  u32 addr, u32 dir, u32 reg, u16 data);
 690#endif /* _PCH_GBE_H_ */
 691