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11#include <linux/bitops.h>
12#include <linux/delay.h>
13#include <linux/pci.h>
14#include <linux/module.h>
15#include <linux/seq_file.h>
16#include <linux/i2c.h>
17#include <linux/mii.h>
18#include <linux/slab.h>
19#include "net_driver.h"
20#include "bitfield.h"
21#include "efx.h"
22#include "nic.h"
23#include "farch_regs.h"
24#include "io.h"
25#include "phy.h"
26#include "workarounds.h"
27#include "selftest.h"
28#include "mdio_10g.h"
29
30
31
32
33
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35
36
37
38
39#define FALCON_MAC_STATS_SIZE 0x100
40
41#define XgRxOctets_offset 0x0
42#define XgRxOctets_WIDTH 48
43#define XgRxOctetsOK_offset 0x8
44#define XgRxOctetsOK_WIDTH 48
45#define XgRxPkts_offset 0x10
46#define XgRxPkts_WIDTH 32
47#define XgRxPktsOK_offset 0x14
48#define XgRxPktsOK_WIDTH 32
49#define XgRxBroadcastPkts_offset 0x18
50#define XgRxBroadcastPkts_WIDTH 32
51#define XgRxMulticastPkts_offset 0x1C
52#define XgRxMulticastPkts_WIDTH 32
53#define XgRxUnicastPkts_offset 0x20
54#define XgRxUnicastPkts_WIDTH 32
55#define XgRxUndersizePkts_offset 0x24
56#define XgRxUndersizePkts_WIDTH 32
57#define XgRxOversizePkts_offset 0x28
58#define XgRxOversizePkts_WIDTH 32
59#define XgRxJabberPkts_offset 0x2C
60#define XgRxJabberPkts_WIDTH 32
61#define XgRxUndersizeFCSerrorPkts_offset 0x30
62#define XgRxUndersizeFCSerrorPkts_WIDTH 32
63#define XgRxDropEvents_offset 0x34
64#define XgRxDropEvents_WIDTH 32
65#define XgRxFCSerrorPkts_offset 0x38
66#define XgRxFCSerrorPkts_WIDTH 32
67#define XgRxAlignError_offset 0x3C
68#define XgRxAlignError_WIDTH 32
69#define XgRxSymbolError_offset 0x40
70#define XgRxSymbolError_WIDTH 32
71#define XgRxInternalMACError_offset 0x44
72#define XgRxInternalMACError_WIDTH 32
73#define XgRxControlPkts_offset 0x48
74#define XgRxControlPkts_WIDTH 32
75#define XgRxPausePkts_offset 0x4C
76#define XgRxPausePkts_WIDTH 32
77#define XgRxPkts64Octets_offset 0x50
78#define XgRxPkts64Octets_WIDTH 32
79#define XgRxPkts65to127Octets_offset 0x54
80#define XgRxPkts65to127Octets_WIDTH 32
81#define XgRxPkts128to255Octets_offset 0x58
82#define XgRxPkts128to255Octets_WIDTH 32
83#define XgRxPkts256to511Octets_offset 0x5C
84#define XgRxPkts256to511Octets_WIDTH 32
85#define XgRxPkts512to1023Octets_offset 0x60
86#define XgRxPkts512to1023Octets_WIDTH 32
87#define XgRxPkts1024to15xxOctets_offset 0x64
88#define XgRxPkts1024to15xxOctets_WIDTH 32
89#define XgRxPkts15xxtoMaxOctets_offset 0x68
90#define XgRxPkts15xxtoMaxOctets_WIDTH 32
91#define XgRxLengthError_offset 0x6C
92#define XgRxLengthError_WIDTH 32
93#define XgTxPkts_offset 0x80
94#define XgTxPkts_WIDTH 32
95#define XgTxOctets_offset 0x88
96#define XgTxOctets_WIDTH 48
97#define XgTxMulticastPkts_offset 0x90
98#define XgTxMulticastPkts_WIDTH 32
99#define XgTxBroadcastPkts_offset 0x94
100#define XgTxBroadcastPkts_WIDTH 32
101#define XgTxUnicastPkts_offset 0x98
102#define XgTxUnicastPkts_WIDTH 32
103#define XgTxControlPkts_offset 0x9C
104#define XgTxControlPkts_WIDTH 32
105#define XgTxPausePkts_offset 0xA0
106#define XgTxPausePkts_WIDTH 32
107#define XgTxPkts64Octets_offset 0xA4
108#define XgTxPkts64Octets_WIDTH 32
109#define XgTxPkts65to127Octets_offset 0xA8
110#define XgTxPkts65to127Octets_WIDTH 32
111#define XgTxPkts128to255Octets_offset 0xAC
112#define XgTxPkts128to255Octets_WIDTH 32
113#define XgTxPkts256to511Octets_offset 0xB0
114#define XgTxPkts256to511Octets_WIDTH 32
115#define XgTxPkts512to1023Octets_offset 0xB4
116#define XgTxPkts512to1023Octets_WIDTH 32
117#define XgTxPkts1024to15xxOctets_offset 0xB8
118#define XgTxPkts1024to15xxOctets_WIDTH 32
119#define XgTxPkts1519toMaxOctets_offset 0xBC
120#define XgTxPkts1519toMaxOctets_WIDTH 32
121#define XgTxUndersizePkts_offset 0xC0
122#define XgTxUndersizePkts_WIDTH 32
123#define XgTxOversizePkts_offset 0xC4
124#define XgTxOversizePkts_WIDTH 32
125#define XgTxNonTcpUdpPkt_offset 0xC8
126#define XgTxNonTcpUdpPkt_WIDTH 16
127#define XgTxMacSrcErrPkt_offset 0xCC
128#define XgTxMacSrcErrPkt_WIDTH 16
129#define XgTxIpSrcErrPkt_offset 0xD0
130#define XgTxIpSrcErrPkt_WIDTH 16
131#define XgDmaDone_offset 0xD4
132#define XgDmaDone_WIDTH 32
133
134#define FALCON_XMAC_STATS_DMA_FLAG(efx) \
135 (*(u32 *)((efx)->stats_buffer.addr + XgDmaDone_offset))
136
137#define FALCON_DMA_STAT(ext_name, hw_name) \
138 [FALCON_STAT_ ## ext_name] = \
139 { #ext_name, \
140 \
141 hw_name ## _ ## WIDTH == 48 ? 64 : hw_name ## _ ## WIDTH, \
142 hw_name ## _ ## offset }
143#define FALCON_OTHER_STAT(ext_name) \
144 [FALCON_STAT_ ## ext_name] = { #ext_name, 0, 0 }
145
146static const struct efx_hw_stat_desc falcon_stat_desc[FALCON_STAT_COUNT] = {
147 FALCON_DMA_STAT(tx_bytes, XgTxOctets),
148 FALCON_DMA_STAT(tx_packets, XgTxPkts),
149 FALCON_DMA_STAT(tx_pause, XgTxPausePkts),
150 FALCON_DMA_STAT(tx_control, XgTxControlPkts),
151 FALCON_DMA_STAT(tx_unicast, XgTxUnicastPkts),
152 FALCON_DMA_STAT(tx_multicast, XgTxMulticastPkts),
153 FALCON_DMA_STAT(tx_broadcast, XgTxBroadcastPkts),
154 FALCON_DMA_STAT(tx_lt64, XgTxUndersizePkts),
155 FALCON_DMA_STAT(tx_64, XgTxPkts64Octets),
156 FALCON_DMA_STAT(tx_65_to_127, XgTxPkts65to127Octets),
157 FALCON_DMA_STAT(tx_128_to_255, XgTxPkts128to255Octets),
158 FALCON_DMA_STAT(tx_256_to_511, XgTxPkts256to511Octets),
159 FALCON_DMA_STAT(tx_512_to_1023, XgTxPkts512to1023Octets),
160 FALCON_DMA_STAT(tx_1024_to_15xx, XgTxPkts1024to15xxOctets),
161 FALCON_DMA_STAT(tx_15xx_to_jumbo, XgTxPkts1519toMaxOctets),
162 FALCON_DMA_STAT(tx_gtjumbo, XgTxOversizePkts),
163 FALCON_DMA_STAT(tx_non_tcpudp, XgTxNonTcpUdpPkt),
164 FALCON_DMA_STAT(tx_mac_src_error, XgTxMacSrcErrPkt),
165 FALCON_DMA_STAT(tx_ip_src_error, XgTxIpSrcErrPkt),
166 FALCON_DMA_STAT(rx_bytes, XgRxOctets),
167 FALCON_DMA_STAT(rx_good_bytes, XgRxOctetsOK),
168 FALCON_OTHER_STAT(rx_bad_bytes),
169 FALCON_DMA_STAT(rx_packets, XgRxPkts),
170 FALCON_DMA_STAT(rx_good, XgRxPktsOK),
171 FALCON_DMA_STAT(rx_bad, XgRxFCSerrorPkts),
172 FALCON_DMA_STAT(rx_pause, XgRxPausePkts),
173 FALCON_DMA_STAT(rx_control, XgRxControlPkts),
174 FALCON_DMA_STAT(rx_unicast, XgRxUnicastPkts),
175 FALCON_DMA_STAT(rx_multicast, XgRxMulticastPkts),
176 FALCON_DMA_STAT(rx_broadcast, XgRxBroadcastPkts),
177 FALCON_DMA_STAT(rx_lt64, XgRxUndersizePkts),
178 FALCON_DMA_STAT(rx_64, XgRxPkts64Octets),
179 FALCON_DMA_STAT(rx_65_to_127, XgRxPkts65to127Octets),
180 FALCON_DMA_STAT(rx_128_to_255, XgRxPkts128to255Octets),
181 FALCON_DMA_STAT(rx_256_to_511, XgRxPkts256to511Octets),
182 FALCON_DMA_STAT(rx_512_to_1023, XgRxPkts512to1023Octets),
183 FALCON_DMA_STAT(rx_1024_to_15xx, XgRxPkts1024to15xxOctets),
184 FALCON_DMA_STAT(rx_15xx_to_jumbo, XgRxPkts15xxtoMaxOctets),
185 FALCON_DMA_STAT(rx_gtjumbo, XgRxOversizePkts),
186 FALCON_DMA_STAT(rx_bad_lt64, XgRxUndersizeFCSerrorPkts),
187 FALCON_DMA_STAT(rx_bad_gtjumbo, XgRxJabberPkts),
188 FALCON_DMA_STAT(rx_overflow, XgRxDropEvents),
189 FALCON_DMA_STAT(rx_symbol_error, XgRxSymbolError),
190 FALCON_DMA_STAT(rx_align_error, XgRxAlignError),
191 FALCON_DMA_STAT(rx_length_error, XgRxLengthError),
192 FALCON_DMA_STAT(rx_internal_error, XgRxInternalMACError),
193 FALCON_OTHER_STAT(rx_nodesc_drop_cnt),
194};
195static const unsigned long falcon_stat_mask[] = {
196 [0 ... BITS_TO_LONGS(FALCON_STAT_COUNT) - 1] = ~0UL,
197};
198
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204
205#define SPI_WRSR 0x01
206#define SPI_WRITE 0x02
207#define SPI_READ 0x03
208#define SPI_WRDI 0x04
209#define SPI_RDSR 0x05
210#define SPI_WREN 0x06
211#define SPI_SST_EWSR 0x50
212
213#define SPI_STATUS_WPEN 0x80
214#define SPI_STATUS_BP2 0x10
215#define SPI_STATUS_BP1 0x08
216#define SPI_STATUS_BP0 0x04
217#define SPI_STATUS_WEN 0x02
218#define SPI_STATUS_NRDY 0x01
219
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238
239#define FALCON_NVCONFIG_END 0x400U
240#define FALCON_FLASH_BOOTCODE_START 0x8000U
241#define FALCON_EEPROM_BOOTCONFIG_START 0x800U
242#define FALCON_EEPROM_BOOTCONFIG_END 0x1800U
243
244
245struct falcon_nvconfig_board_v2 {
246 __le16 nports;
247 u8 port0_phy_addr;
248 u8 port0_phy_type;
249 u8 port1_phy_addr;
250 u8 port1_phy_type;
251 __le16 asic_sub_revision;
252 __le16 board_revision;
253} __packed;
254
255
256struct falcon_nvconfig_board_v3 {
257 __le32 spi_device_type[2];
258} __packed;
259
260
261#define SPI_DEV_TYPE_SIZE_LBN 0
262#define SPI_DEV_TYPE_SIZE_WIDTH 5
263#define SPI_DEV_TYPE_ADDR_LEN_LBN 6
264#define SPI_DEV_TYPE_ADDR_LEN_WIDTH 2
265#define SPI_DEV_TYPE_ERASE_CMD_LBN 8
266#define SPI_DEV_TYPE_ERASE_CMD_WIDTH 8
267#define SPI_DEV_TYPE_ERASE_SIZE_LBN 16
268#define SPI_DEV_TYPE_ERASE_SIZE_WIDTH 5
269#define SPI_DEV_TYPE_BLOCK_SIZE_LBN 24
270#define SPI_DEV_TYPE_BLOCK_SIZE_WIDTH 5
271#define SPI_DEV_TYPE_FIELD(type, field) \
272 (((type) >> EFX_LOW_BIT(field)) & EFX_MASK32(EFX_WIDTH(field)))
273
274#define FALCON_NVCONFIG_OFFSET 0x300
275
276#define FALCON_NVCONFIG_BOARD_MAGIC_NUM 0xFA1C
277struct falcon_nvconfig {
278 efx_oword_t ee_vpd_cfg_reg;
279 u8 mac_address[2][8];
280 efx_oword_t pcie_sd_ctl0123_reg;
281 efx_oword_t pcie_sd_ctl45_reg;
282 efx_oword_t pcie_pcs_ctl_stat_reg;
283 efx_oword_t hw_init_reg;
284 efx_oword_t nic_stat_reg;
285 efx_oword_t glb_ctl_reg;
286 efx_oword_t srm_cfg_reg;
287 efx_oword_t spare_reg;
288 __le16 board_magic_num;
289 __le16 board_struct_ver;
290 __le16 board_checksum;
291 struct falcon_nvconfig_board_v2 board_v2;
292 efx_oword_t ee_base_page_reg;
293 struct falcon_nvconfig_board_v3 board_v3;
294} __packed;
295
296
297
298static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method);
299static void falcon_reconfigure_mac_wrapper(struct efx_nic *efx);
300
301static const unsigned int
302
303
304large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
305 | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
306 | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
307
308
309default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
310 | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
311 | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
312 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
313 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
314
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320
321
322
323static void falcon_setsda(void *data, int state)
324{
325 struct efx_nic *efx = (struct efx_nic *)data;
326 efx_oword_t reg;
327
328 efx_reado(efx, ®, FR_AB_GPIO_CTL);
329 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
330 efx_writeo(efx, ®, FR_AB_GPIO_CTL);
331}
332
333static void falcon_setscl(void *data, int state)
334{
335 struct efx_nic *efx = (struct efx_nic *)data;
336 efx_oword_t reg;
337
338 efx_reado(efx, ®, FR_AB_GPIO_CTL);
339 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
340 efx_writeo(efx, ®, FR_AB_GPIO_CTL);
341}
342
343static int falcon_getsda(void *data)
344{
345 struct efx_nic *efx = (struct efx_nic *)data;
346 efx_oword_t reg;
347
348 efx_reado(efx, ®, FR_AB_GPIO_CTL);
349 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
350}
351
352static int falcon_getscl(void *data)
353{
354 struct efx_nic *efx = (struct efx_nic *)data;
355 efx_oword_t reg;
356
357 efx_reado(efx, ®, FR_AB_GPIO_CTL);
358 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
359}
360
361static const struct i2c_algo_bit_data falcon_i2c_bit_operations = {
362 .setsda = falcon_setsda,
363 .setscl = falcon_setscl,
364 .getsda = falcon_getsda,
365 .getscl = falcon_getscl,
366 .udelay = 5,
367
368 .timeout = DIV_ROUND_UP(HZ, 20),
369};
370
371static void falcon_push_irq_moderation(struct efx_channel *channel)
372{
373 efx_dword_t timer_cmd;
374 struct efx_nic *efx = channel->efx;
375
376
377 if (channel->irq_moderation) {
378 EFX_POPULATE_DWORD_2(timer_cmd,
379 FRF_AB_TC_TIMER_MODE,
380 FFE_BB_TIMER_MODE_INT_HLDOFF,
381 FRF_AB_TC_TIMER_VAL,
382 channel->irq_moderation - 1);
383 } else {
384 EFX_POPULATE_DWORD_2(timer_cmd,
385 FRF_AB_TC_TIMER_MODE,
386 FFE_BB_TIMER_MODE_DIS,
387 FRF_AB_TC_TIMER_VAL, 0);
388 }
389 BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
390 efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
391 channel->channel);
392}
393
394static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx);
395
396static void falcon_prepare_flush(struct efx_nic *efx)
397{
398 falcon_deconfigure_mac_wrapper(efx);
399
400
401
402
403 msleep(10);
404}
405
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407
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410
411
412
413
414
415
416static inline void falcon_irq_ack_a1(struct efx_nic *efx)
417{
418 efx_dword_t reg;
419
420 EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
421 efx_writed(efx, ®, FR_AA_INT_ACK_KER);
422 efx_readd(efx, ®, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
423}
424
425
426static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
427{
428 struct efx_nic *efx = dev_id;
429 efx_oword_t *int_ker = efx->irq_status.addr;
430 int syserr;
431 int queues;
432
433
434
435
436 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
437 netif_vdbg(efx, intr, efx->net_dev,
438 "IRQ %d on CPU %d not for me\n", irq,
439 raw_smp_processor_id());
440 return IRQ_NONE;
441 }
442 efx->last_irq_cpu = raw_smp_processor_id();
443 netif_vdbg(efx, intr, efx->net_dev,
444 "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
445 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
446
447 if (!likely(ACCESS_ONCE(efx->irq_soft_enabled)))
448 return IRQ_HANDLED;
449
450
451 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
452 if (unlikely(syserr))
453 return efx_farch_fatal_interrupt(efx);
454
455
456
457
458 BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH > EFX_MAX_CHANNELS);
459 queues = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_INT_Q);
460 EFX_ZERO_OWORD(*int_ker);
461 wmb();
462 falcon_irq_ack_a1(efx);
463
464 if (queues & 1)
465 efx_schedule_channel_irq(efx_get_channel(efx, 0));
466 if (queues & 2)
467 efx_schedule_channel_irq(efx_get_channel(efx, 1));
468 return IRQ_HANDLED;
469}
470
471
472
473
474
475
476
477#define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
478
479static int falcon_spi_poll(struct efx_nic *efx)
480{
481 efx_oword_t reg;
482 efx_reado(efx, ®, FR_AB_EE_SPI_HCMD);
483 return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
484}
485
486
487static int falcon_spi_wait(struct efx_nic *efx)
488{
489
490
491
492
493 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
494 int i;
495
496 for (i = 0; i < 10; i++) {
497 if (!falcon_spi_poll(efx))
498 return 0;
499 udelay(10);
500 }
501
502 for (;;) {
503 if (!falcon_spi_poll(efx))
504 return 0;
505 if (time_after_eq(jiffies, timeout)) {
506 netif_err(efx, hw, efx->net_dev,
507 "timed out waiting for SPI\n");
508 return -ETIMEDOUT;
509 }
510 schedule_timeout_uninterruptible(1);
511 }
512}
513
514static int
515falcon_spi_cmd(struct efx_nic *efx, const struct falcon_spi_device *spi,
516 unsigned int command, int address,
517 const void *in, void *out, size_t len)
518{
519 bool addressed = (address >= 0);
520 bool reading = (out != NULL);
521 efx_oword_t reg;
522 int rc;
523
524
525 if (len > FALCON_SPI_MAX_LEN)
526 return -EINVAL;
527
528
529 rc = falcon_spi_poll(efx);
530 if (rc)
531 return rc;
532
533
534 if (addressed) {
535 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
536 efx_writeo(efx, ®, FR_AB_EE_SPI_HADR);
537 }
538
539
540 if (in != NULL) {
541 memcpy(®, in, len);
542 efx_writeo(efx, ®, FR_AB_EE_SPI_HDATA);
543 }
544
545
546 EFX_POPULATE_OWORD_7(reg,
547 FRF_AB_EE_SPI_HCMD_CMD_EN, 1,
548 FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id,
549 FRF_AB_EE_SPI_HCMD_DABCNT, len,
550 FRF_AB_EE_SPI_HCMD_READ, reading,
551 FRF_AB_EE_SPI_HCMD_DUBCNT, 0,
552 FRF_AB_EE_SPI_HCMD_ADBCNT,
553 (addressed ? spi->addr_len : 0),
554 FRF_AB_EE_SPI_HCMD_ENC, command);
555 efx_writeo(efx, ®, FR_AB_EE_SPI_HCMD);
556
557
558 rc = falcon_spi_wait(efx);
559 if (rc)
560 return rc;
561
562
563 if (out != NULL) {
564 efx_reado(efx, ®, FR_AB_EE_SPI_HDATA);
565 memcpy(out, ®, len);
566 }
567
568 return 0;
569}
570
571static inline u8
572falcon_spi_munge_command(const struct falcon_spi_device *spi,
573 const u8 command, const unsigned int address)
574{
575 return command | (((address >> 8) & spi->munge_address) << 3);
576}
577
578static int
579falcon_spi_read(struct efx_nic *efx, const struct falcon_spi_device *spi,
580 loff_t start, size_t len, size_t *retlen, u8 *buffer)
581{
582 size_t block_len, pos = 0;
583 unsigned int command;
584 int rc = 0;
585
586 while (pos < len) {
587 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
588
589 command = falcon_spi_munge_command(spi, SPI_READ, start + pos);
590 rc = falcon_spi_cmd(efx, spi, command, start + pos, NULL,
591 buffer + pos, block_len);
592 if (rc)
593 break;
594 pos += block_len;
595
596
597 cond_resched();
598 if (signal_pending(current)) {
599 rc = -EINTR;
600 break;
601 }
602 }
603
604 if (retlen)
605 *retlen = pos;
606 return rc;
607}
608
609#ifdef CONFIG_SFC_MTD
610
611struct falcon_mtd_partition {
612 struct efx_mtd_partition common;
613 const struct falcon_spi_device *spi;
614 size_t offset;
615};
616
617#define to_falcon_mtd_partition(mtd) \
618 container_of(mtd, struct falcon_mtd_partition, common.mtd)
619
620static size_t
621falcon_spi_write_limit(const struct falcon_spi_device *spi, size_t start)
622{
623 return min(FALCON_SPI_MAX_LEN,
624 (spi->block_size - (start & (spi->block_size - 1))));
625}
626
627
628static int
629falcon_spi_wait_write(struct efx_nic *efx, const struct falcon_spi_device *spi)
630{
631 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
632 u8 status;
633 int rc;
634
635 for (;;) {
636 rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
637 &status, sizeof(status));
638 if (rc)
639 return rc;
640 if (!(status & SPI_STATUS_NRDY))
641 return 0;
642 if (time_after_eq(jiffies, timeout)) {
643 netif_err(efx, hw, efx->net_dev,
644 "SPI write timeout on device %d"
645 " last status=0x%02x\n",
646 spi->device_id, status);
647 return -ETIMEDOUT;
648 }
649 schedule_timeout_uninterruptible(1);
650 }
651}
652
653static int
654falcon_spi_write(struct efx_nic *efx, const struct falcon_spi_device *spi,
655 loff_t start, size_t len, size_t *retlen, const u8 *buffer)
656{
657 u8 verify_buffer[FALCON_SPI_MAX_LEN];
658 size_t block_len, pos = 0;
659 unsigned int command;
660 int rc = 0;
661
662 while (pos < len) {
663 rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
664 if (rc)
665 break;
666
667 block_len = min(len - pos,
668 falcon_spi_write_limit(spi, start + pos));
669 command = falcon_spi_munge_command(spi, SPI_WRITE, start + pos);
670 rc = falcon_spi_cmd(efx, spi, command, start + pos,
671 buffer + pos, NULL, block_len);
672 if (rc)
673 break;
674
675 rc = falcon_spi_wait_write(efx, spi);
676 if (rc)
677 break;
678
679 command = falcon_spi_munge_command(spi, SPI_READ, start + pos);
680 rc = falcon_spi_cmd(efx, spi, command, start + pos,
681 NULL, verify_buffer, block_len);
682 if (memcmp(verify_buffer, buffer + pos, block_len)) {
683 rc = -EIO;
684 break;
685 }
686
687 pos += block_len;
688
689
690 cond_resched();
691 if (signal_pending(current)) {
692 rc = -EINTR;
693 break;
694 }
695 }
696
697 if (retlen)
698 *retlen = pos;
699 return rc;
700}
701
702static int
703falcon_spi_slow_wait(struct falcon_mtd_partition *part, bool uninterruptible)
704{
705 const struct falcon_spi_device *spi = part->spi;
706 struct efx_nic *efx = part->common.mtd.priv;
707 u8 status;
708 int rc, i;
709
710
711 for (i = 0; i < 40; i++) {
712 __set_current_state(uninterruptible ?
713 TASK_UNINTERRUPTIBLE : TASK_INTERRUPTIBLE);
714 schedule_timeout(HZ / 10);
715 rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
716 &status, sizeof(status));
717 if (rc)
718 return rc;
719 if (!(status & SPI_STATUS_NRDY))
720 return 0;
721 if (signal_pending(current))
722 return -EINTR;
723 }
724 pr_err("%s: timed out waiting for %s\n",
725 part->common.name, part->common.dev_type_name);
726 return -ETIMEDOUT;
727}
728
729static int
730falcon_spi_unlock(struct efx_nic *efx, const struct falcon_spi_device *spi)
731{
732 const u8 unlock_mask = (SPI_STATUS_BP2 | SPI_STATUS_BP1 |
733 SPI_STATUS_BP0);
734 u8 status;
735 int rc;
736
737 rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
738 &status, sizeof(status));
739 if (rc)
740 return rc;
741
742 if (!(status & unlock_mask))
743 return 0;
744
745 rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
746 if (rc)
747 return rc;
748 rc = falcon_spi_cmd(efx, spi, SPI_SST_EWSR, -1, NULL, NULL, 0);
749 if (rc)
750 return rc;
751
752 status &= ~unlock_mask;
753 rc = falcon_spi_cmd(efx, spi, SPI_WRSR, -1, &status,
754 NULL, sizeof(status));
755 if (rc)
756 return rc;
757 rc = falcon_spi_wait_write(efx, spi);
758 if (rc)
759 return rc;
760
761 return 0;
762}
763
764#define FALCON_SPI_VERIFY_BUF_LEN 16
765
766static int
767falcon_spi_erase(struct falcon_mtd_partition *part, loff_t start, size_t len)
768{
769 const struct falcon_spi_device *spi = part->spi;
770 struct efx_nic *efx = part->common.mtd.priv;
771 unsigned pos, block_len;
772 u8 empty[FALCON_SPI_VERIFY_BUF_LEN];
773 u8 buffer[FALCON_SPI_VERIFY_BUF_LEN];
774 int rc;
775
776 if (len != spi->erase_size)
777 return -EINVAL;
778
779 if (spi->erase_command == 0)
780 return -EOPNOTSUPP;
781
782 rc = falcon_spi_unlock(efx, spi);
783 if (rc)
784 return rc;
785 rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
786 if (rc)
787 return rc;
788 rc = falcon_spi_cmd(efx, spi, spi->erase_command, start, NULL,
789 NULL, 0);
790 if (rc)
791 return rc;
792 rc = falcon_spi_slow_wait(part, false);
793
794
795 memset(empty, 0xff, sizeof(empty));
796 for (pos = 0; pos < len; pos += block_len) {
797 block_len = min(len - pos, sizeof(buffer));
798 rc = falcon_spi_read(efx, spi, start + pos, block_len,
799 NULL, buffer);
800 if (rc)
801 return rc;
802 if (memcmp(empty, buffer, block_len))
803 return -EIO;
804
805
806 cond_resched();
807 if (signal_pending(current))
808 return -EINTR;
809 }
810
811 return rc;
812}
813
814static void falcon_mtd_rename(struct efx_mtd_partition *part)
815{
816 struct efx_nic *efx = part->mtd.priv;
817
818 snprintf(part->name, sizeof(part->name), "%s %s",
819 efx->name, part->type_name);
820}
821
822static int falcon_mtd_read(struct mtd_info *mtd, loff_t start,
823 size_t len, size_t *retlen, u8 *buffer)
824{
825 struct falcon_mtd_partition *part = to_falcon_mtd_partition(mtd);
826 struct efx_nic *efx = mtd->priv;
827 struct falcon_nic_data *nic_data = efx->nic_data;
828 int rc;
829
830 rc = mutex_lock_interruptible(&nic_data->spi_lock);
831 if (rc)
832 return rc;
833 rc = falcon_spi_read(efx, part->spi, part->offset + start,
834 len, retlen, buffer);
835 mutex_unlock(&nic_data->spi_lock);
836 return rc;
837}
838
839static int falcon_mtd_erase(struct mtd_info *mtd, loff_t start, size_t len)
840{
841 struct falcon_mtd_partition *part = to_falcon_mtd_partition(mtd);
842 struct efx_nic *efx = mtd->priv;
843 struct falcon_nic_data *nic_data = efx->nic_data;
844 int rc;
845
846 rc = mutex_lock_interruptible(&nic_data->spi_lock);
847 if (rc)
848 return rc;
849 rc = falcon_spi_erase(part, part->offset + start, len);
850 mutex_unlock(&nic_data->spi_lock);
851 return rc;
852}
853
854static int falcon_mtd_write(struct mtd_info *mtd, loff_t start,
855 size_t len, size_t *retlen, const u8 *buffer)
856{
857 struct falcon_mtd_partition *part = to_falcon_mtd_partition(mtd);
858 struct efx_nic *efx = mtd->priv;
859 struct falcon_nic_data *nic_data = efx->nic_data;
860 int rc;
861
862 rc = mutex_lock_interruptible(&nic_data->spi_lock);
863 if (rc)
864 return rc;
865 rc = falcon_spi_write(efx, part->spi, part->offset + start,
866 len, retlen, buffer);
867 mutex_unlock(&nic_data->spi_lock);
868 return rc;
869}
870
871static int falcon_mtd_sync(struct mtd_info *mtd)
872{
873 struct falcon_mtd_partition *part = to_falcon_mtd_partition(mtd);
874 struct efx_nic *efx = mtd->priv;
875 struct falcon_nic_data *nic_data = efx->nic_data;
876 int rc;
877
878 mutex_lock(&nic_data->spi_lock);
879 rc = falcon_spi_slow_wait(part, true);
880 mutex_unlock(&nic_data->spi_lock);
881 return rc;
882}
883
884static int falcon_mtd_probe(struct efx_nic *efx)
885{
886 struct falcon_nic_data *nic_data = efx->nic_data;
887 struct falcon_mtd_partition *parts;
888 struct falcon_spi_device *spi;
889 size_t n_parts;
890 int rc = -ENODEV;
891
892 ASSERT_RTNL();
893
894
895 parts = kcalloc(2, sizeof(*parts), GFP_KERNEL);
896 if (!parts)
897 return -ENOMEM;
898 n_parts = 0;
899
900 spi = &nic_data->spi_flash;
901 if (falcon_spi_present(spi) && spi->size > FALCON_FLASH_BOOTCODE_START) {
902 parts[n_parts].spi = spi;
903 parts[n_parts].offset = FALCON_FLASH_BOOTCODE_START;
904 parts[n_parts].common.dev_type_name = "flash";
905 parts[n_parts].common.type_name = "sfc_flash_bootrom";
906 parts[n_parts].common.mtd.type = MTD_NORFLASH;
907 parts[n_parts].common.mtd.flags = MTD_CAP_NORFLASH;
908 parts[n_parts].common.mtd.size = spi->size - FALCON_FLASH_BOOTCODE_START;
909 parts[n_parts].common.mtd.erasesize = spi->erase_size;
910 n_parts++;
911 }
912
913 spi = &nic_data->spi_eeprom;
914 if (falcon_spi_present(spi) && spi->size > FALCON_EEPROM_BOOTCONFIG_START) {
915 parts[n_parts].spi = spi;
916 parts[n_parts].offset = FALCON_EEPROM_BOOTCONFIG_START;
917 parts[n_parts].common.dev_type_name = "EEPROM";
918 parts[n_parts].common.type_name = "sfc_bootconfig";
919 parts[n_parts].common.mtd.type = MTD_RAM;
920 parts[n_parts].common.mtd.flags = MTD_CAP_RAM;
921 parts[n_parts].common.mtd.size =
922 min(spi->size, FALCON_EEPROM_BOOTCONFIG_END) -
923 FALCON_EEPROM_BOOTCONFIG_START;
924 parts[n_parts].common.mtd.erasesize = spi->erase_size;
925 n_parts++;
926 }
927
928 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
929 if (rc)
930 kfree(parts);
931 return rc;
932}
933
934#endif
935
936
937
938
939
940
941
942
943
944static void falcon_setup_xaui(struct efx_nic *efx)
945{
946 efx_oword_t sdctl, txdrv;
947
948
949
950 if (efx->phy_type == PHY_TYPE_NONE)
951 return;
952
953 efx_reado(efx, &sdctl, FR_AB_XX_SD_CTL);
954 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
955 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
956 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
957 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
958 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
959 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
960 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
961 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
962 efx_writeo(efx, &sdctl, FR_AB_XX_SD_CTL);
963
964 EFX_POPULATE_OWORD_8(txdrv,
965 FRF_AB_XX_DEQD, FFE_AB_XX_TXDRV_DEQ_DEF,
966 FRF_AB_XX_DEQC, FFE_AB_XX_TXDRV_DEQ_DEF,
967 FRF_AB_XX_DEQB, FFE_AB_XX_TXDRV_DEQ_DEF,
968 FRF_AB_XX_DEQA, FFE_AB_XX_TXDRV_DEQ_DEF,
969 FRF_AB_XX_DTXD, FFE_AB_XX_TXDRV_DTX_DEF,
970 FRF_AB_XX_DTXC, FFE_AB_XX_TXDRV_DTX_DEF,
971 FRF_AB_XX_DTXB, FFE_AB_XX_TXDRV_DTX_DEF,
972 FRF_AB_XX_DTXA, FFE_AB_XX_TXDRV_DTX_DEF);
973 efx_writeo(efx, &txdrv, FR_AB_XX_TXDRV_CTL);
974}
975
976int falcon_reset_xaui(struct efx_nic *efx)
977{
978 struct falcon_nic_data *nic_data = efx->nic_data;
979 efx_oword_t reg;
980 int count;
981
982
983 WARN_ON(nic_data->stats_disable_count == 0);
984
985
986 EFX_POPULATE_OWORD_1(reg, FRF_AB_XX_RST_XX_EN, 1);
987 efx_writeo(efx, ®, FR_AB_XX_PWR_RST);
988
989
990 for (count = 0; count < 1000; count++) {
991 efx_reado(efx, ®, FR_AB_XX_PWR_RST);
992 if (EFX_OWORD_FIELD(reg, FRF_AB_XX_RST_XX_EN) == 0 &&
993 EFX_OWORD_FIELD(reg, FRF_AB_XX_SD_RST_ACT) == 0) {
994 falcon_setup_xaui(efx);
995 return 0;
996 }
997 udelay(10);
998 }
999 netif_err(efx, hw, efx->net_dev,
1000 "timed out waiting for XAUI/XGXS reset\n");
1001 return -ETIMEDOUT;
1002}
1003
1004static void falcon_ack_status_intr(struct efx_nic *efx)
1005{
1006 struct falcon_nic_data *nic_data = efx->nic_data;
1007 efx_oword_t reg;
1008
1009 if ((efx_nic_rev(efx) != EFX_REV_FALCON_B0) || LOOPBACK_INTERNAL(efx))
1010 return;
1011
1012
1013 if (!efx->link_state.up)
1014 return;
1015
1016
1017
1018 if (nic_data->xmac_poll_required)
1019 return;
1020
1021 efx_reado(efx, ®, FR_AB_XM_MGT_INT_MSK);
1022}
1023
1024static bool falcon_xgxs_link_ok(struct efx_nic *efx)
1025{
1026 efx_oword_t reg;
1027 bool align_done, link_ok = false;
1028 int sync_status;
1029
1030
1031 efx_reado(efx, ®, FR_AB_XX_CORE_STAT);
1032
1033 align_done = EFX_OWORD_FIELD(reg, FRF_AB_XX_ALIGN_DONE);
1034 sync_status = EFX_OWORD_FIELD(reg, FRF_AB_XX_SYNC_STAT);
1035 if (align_done && (sync_status == FFE_AB_XX_STAT_ALL_LANES))
1036 link_ok = true;
1037
1038
1039 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_COMMA_DET, FFE_AB_XX_STAT_ALL_LANES);
1040 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_CHAR_ERR, FFE_AB_XX_STAT_ALL_LANES);
1041 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_DISPERR, FFE_AB_XX_STAT_ALL_LANES);
1042 efx_writeo(efx, ®, FR_AB_XX_CORE_STAT);
1043
1044 return link_ok;
1045}
1046
1047static bool falcon_xmac_link_ok(struct efx_nic *efx)
1048{
1049
1050
1051
1052
1053
1054
1055 return (efx->loopback_mode == LOOPBACK_XGMII ||
1056 falcon_xgxs_link_ok(efx)) &&
1057 (!(efx->mdio.mmds & (1 << MDIO_MMD_PHYXS)) ||
1058 LOOPBACK_INTERNAL(efx) ||
1059 efx_mdio_phyxgxs_lane_sync(efx));
1060}
1061
1062static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
1063{
1064 unsigned int max_frame_len;
1065 efx_oword_t reg;
1066 bool rx_fc = !!(efx->link_state.fc & EFX_FC_RX);
1067 bool tx_fc = !!(efx->link_state.fc & EFX_FC_TX);
1068
1069
1070 EFX_POPULATE_OWORD_3(reg,
1071 FRF_AB_XM_RX_JUMBO_MODE, 1,
1072 FRF_AB_XM_TX_STAT_EN, 1,
1073 FRF_AB_XM_RX_STAT_EN, 1);
1074 efx_writeo(efx, ®, FR_AB_XM_GLB_CFG);
1075
1076
1077 EFX_POPULATE_OWORD_6(reg,
1078 FRF_AB_XM_TXEN, 1,
1079 FRF_AB_XM_TX_PRMBL, 1,
1080 FRF_AB_XM_AUTO_PAD, 1,
1081 FRF_AB_XM_TXCRC, 1,
1082 FRF_AB_XM_FCNTL, tx_fc,
1083 FRF_AB_XM_IPG, 0x3);
1084 efx_writeo(efx, ®, FR_AB_XM_TX_CFG);
1085
1086
1087 EFX_POPULATE_OWORD_5(reg,
1088 FRF_AB_XM_RXEN, 1,
1089 FRF_AB_XM_AUTO_DEPAD, 0,
1090 FRF_AB_XM_ACPT_ALL_MCAST, 1,
1091 FRF_AB_XM_ACPT_ALL_UCAST, !efx->unicast_filter,
1092 FRF_AB_XM_PASS_CRC_ERR, 1);
1093 efx_writeo(efx, ®, FR_AB_XM_RX_CFG);
1094
1095
1096 max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
1097 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_MAX_RX_FRM_SIZE, max_frame_len);
1098 efx_writeo(efx, ®, FR_AB_XM_RX_PARAM);
1099 EFX_POPULATE_OWORD_2(reg,
1100 FRF_AB_XM_MAX_TX_FRM_SIZE, max_frame_len,
1101 FRF_AB_XM_TX_JUMBO_MODE, 1);
1102 efx_writeo(efx, ®, FR_AB_XM_TX_PARAM);
1103
1104 EFX_POPULATE_OWORD_2(reg,
1105 FRF_AB_XM_PAUSE_TIME, 0xfffe,
1106 FRF_AB_XM_DIS_FCNTL, !rx_fc);
1107 efx_writeo(efx, ®, FR_AB_XM_FC);
1108
1109
1110 memcpy(®, &efx->net_dev->dev_addr[0], 4);
1111 efx_writeo(efx, ®, FR_AB_XM_ADR_LO);
1112 memcpy(®, &efx->net_dev->dev_addr[4], 2);
1113 efx_writeo(efx, ®, FR_AB_XM_ADR_HI);
1114}
1115
1116static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
1117{
1118 efx_oword_t reg;
1119 bool xgxs_loopback = (efx->loopback_mode == LOOPBACK_XGXS);
1120 bool xaui_loopback = (efx->loopback_mode == LOOPBACK_XAUI);
1121 bool xgmii_loopback = (efx->loopback_mode == LOOPBACK_XGMII);
1122 bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback;
1123
1124
1125
1126 efx_reado(efx, ®, FR_AB_XX_CORE_STAT);
1127 old_xgxs_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN);
1128 old_xgmii_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN);
1129
1130 efx_reado(efx, ®, FR_AB_XX_SD_CTL);
1131 old_xaui_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_LPBKA);
1132
1133
1134 if ((xgxs_loopback != old_xgxs_loopback) ||
1135 (xaui_loopback != old_xaui_loopback) ||
1136 (xgmii_loopback != old_xgmii_loopback))
1137 falcon_reset_xaui(efx);
1138
1139 efx_reado(efx, ®, FR_AB_XX_CORE_STAT);
1140 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_FORCE_SIG,
1141 (xgxs_loopback || xaui_loopback) ?
1142 FFE_AB_XX_FORCE_SIG_ALL_LANES : 0);
1143 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN, xgxs_loopback);
1144 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN, xgmii_loopback);
1145 efx_writeo(efx, ®, FR_AB_XX_CORE_STAT);
1146
1147 efx_reado(efx, ®, FR_AB_XX_SD_CTL);
1148 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKD, xaui_loopback);
1149 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKC, xaui_loopback);
1150 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKB, xaui_loopback);
1151 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKA, xaui_loopback);
1152 efx_writeo(efx, ®, FR_AB_XX_SD_CTL);
1153}
1154
1155
1156
1157static bool falcon_xmac_link_ok_retry(struct efx_nic *efx, int tries)
1158{
1159 bool mac_up = falcon_xmac_link_ok(efx);
1160
1161 if (LOOPBACK_MASK(efx) & LOOPBACKS_EXTERNAL(efx) & LOOPBACKS_WS ||
1162 efx_phy_mode_disabled(efx->phy_mode))
1163
1164 return mac_up;
1165
1166 falcon_stop_nic_stats(efx);
1167
1168 while (!mac_up && tries) {
1169 netif_dbg(efx, hw, efx->net_dev, "bashing xaui\n");
1170 falcon_reset_xaui(efx);
1171 udelay(200);
1172
1173 mac_up = falcon_xmac_link_ok(efx);
1174 --tries;
1175 }
1176
1177 falcon_start_nic_stats(efx);
1178
1179 return mac_up;
1180}
1181
1182static bool falcon_xmac_check_fault(struct efx_nic *efx)
1183{
1184 return !falcon_xmac_link_ok_retry(efx, 5);
1185}
1186
1187static int falcon_reconfigure_xmac(struct efx_nic *efx)
1188{
1189 struct falcon_nic_data *nic_data = efx->nic_data;
1190
1191 efx_farch_filter_sync_rx_mode(efx);
1192
1193 falcon_reconfigure_xgxs_core(efx);
1194 falcon_reconfigure_xmac_core(efx);
1195
1196 falcon_reconfigure_mac_wrapper(efx);
1197
1198 nic_data->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 5);
1199 falcon_ack_status_intr(efx);
1200
1201 return 0;
1202}
1203
1204static void falcon_poll_xmac(struct efx_nic *efx)
1205{
1206 struct falcon_nic_data *nic_data = efx->nic_data;
1207
1208
1209 if (!efx->link_state.up || !nic_data->xmac_poll_required)
1210 return;
1211
1212 nic_data->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 1);
1213 falcon_ack_status_intr(efx);
1214}
1215
1216
1217
1218
1219
1220
1221
1222
1223static void falcon_push_multicast_hash(struct efx_nic *efx)
1224{
1225 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
1226
1227 WARN_ON(!mutex_is_locked(&efx->mac_lock));
1228
1229 efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
1230 efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
1231}
1232
1233static void falcon_reset_macs(struct efx_nic *efx)
1234{
1235 struct falcon_nic_data *nic_data = efx->nic_data;
1236 efx_oword_t reg, mac_ctrl;
1237 int count;
1238
1239 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
1240
1241
1242
1243 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
1244 efx_writeo(efx, ®, FR_AB_XM_GLB_CFG);
1245
1246 for (count = 0; count < 10000; count++) {
1247 efx_reado(efx, ®, FR_AB_XM_GLB_CFG);
1248 if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
1249 0)
1250 return;
1251 udelay(10);
1252 }
1253
1254 netif_err(efx, hw, efx->net_dev,
1255 "timed out waiting for XMAC core reset\n");
1256 }
1257
1258
1259 WARN_ON(nic_data->stats_disable_count == 0);
1260
1261 efx_reado(efx, &mac_ctrl, FR_AB_MAC_CTRL);
1262 EFX_SET_OWORD_FIELD(mac_ctrl, FRF_BB_TXFIFO_DRAIN_EN, 1);
1263 efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
1264
1265 efx_reado(efx, ®, FR_AB_GLB_CTL);
1266 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
1267 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
1268 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
1269 efx_writeo(efx, ®, FR_AB_GLB_CTL);
1270
1271 count = 0;
1272 while (1) {
1273 efx_reado(efx, ®, FR_AB_GLB_CTL);
1274 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
1275 !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
1276 !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
1277 netif_dbg(efx, hw, efx->net_dev,
1278 "Completed MAC reset after %d loops\n",
1279 count);
1280 break;
1281 }
1282 if (count > 20) {
1283 netif_err(efx, hw, efx->net_dev, "MAC reset failed\n");
1284 break;
1285 }
1286 count++;
1287 udelay(10);
1288 }
1289
1290
1291
1292 efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
1293
1294 falcon_setup_xaui(efx);
1295}
1296
1297static void falcon_drain_tx_fifo(struct efx_nic *efx)
1298{
1299 efx_oword_t reg;
1300
1301 if ((efx_nic_rev(efx) < EFX_REV_FALCON_B0) ||
1302 (efx->loopback_mode != LOOPBACK_NONE))
1303 return;
1304
1305 efx_reado(efx, ®, FR_AB_MAC_CTRL);
1306
1307 if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
1308 return;
1309
1310 falcon_reset_macs(efx);
1311}
1312
1313static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1314{
1315 efx_oword_t reg;
1316
1317 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
1318 return;
1319
1320
1321 efx_reado(efx, ®, FR_AZ_RX_CFG);
1322 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
1323 efx_writeo(efx, ®, FR_AZ_RX_CFG);
1324
1325
1326 falcon_drain_tx_fifo(efx);
1327}
1328
1329static void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1330{
1331 struct efx_link_state *link_state = &efx->link_state;
1332 efx_oword_t reg;
1333 int link_speed, isolate;
1334
1335 isolate = !!ACCESS_ONCE(efx->reset_pending);
1336
1337 switch (link_state->speed) {
1338 case 10000: link_speed = 3; break;
1339 case 1000: link_speed = 2; break;
1340 case 100: link_speed = 1; break;
1341 default: link_speed = 0; break;
1342 }
1343
1344
1345
1346
1347 EFX_POPULATE_OWORD_5(reg,
1348 FRF_AB_MAC_XOFF_VAL, 0xffff ,
1349 FRF_AB_MAC_BCAD_ACPT, 1,
1350 FRF_AB_MAC_UC_PROM, !efx->unicast_filter,
1351 FRF_AB_MAC_LINK_STATUS, 1,
1352 FRF_AB_MAC_SPEED, link_speed);
1353
1354
1355 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
1356 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
1357 !link_state->up || isolate);
1358 }
1359
1360 efx_writeo(efx, ®, FR_AB_MAC_CTRL);
1361
1362
1363 falcon_push_multicast_hash(efx);
1364
1365 efx_reado(efx, ®, FR_AZ_RX_CFG);
1366
1367
1368 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
1369
1370 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1371 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, !isolate);
1372 efx_writeo(efx, ®, FR_AZ_RX_CFG);
1373}
1374
1375static void falcon_stats_request(struct efx_nic *efx)
1376{
1377 struct falcon_nic_data *nic_data = efx->nic_data;
1378 efx_oword_t reg;
1379
1380 WARN_ON(nic_data->stats_pending);
1381 WARN_ON(nic_data->stats_disable_count);
1382
1383 FALCON_XMAC_STATS_DMA_FLAG(efx) = 0;
1384 nic_data->stats_pending = true;
1385 wmb();
1386
1387
1388 EFX_POPULATE_OWORD_2(reg,
1389 FRF_AB_MAC_STAT_DMA_CMD, 1,
1390 FRF_AB_MAC_STAT_DMA_ADR,
1391 efx->stats_buffer.dma_addr);
1392 efx_writeo(efx, ®, FR_AB_MAC_STAT_DMA);
1393
1394 mod_timer(&nic_data->stats_timer, round_jiffies_up(jiffies + HZ / 2));
1395}
1396
1397static void falcon_stats_complete(struct efx_nic *efx)
1398{
1399 struct falcon_nic_data *nic_data = efx->nic_data;
1400
1401 if (!nic_data->stats_pending)
1402 return;
1403
1404 nic_data->stats_pending = false;
1405 if (FALCON_XMAC_STATS_DMA_FLAG(efx)) {
1406 rmb();
1407 efx_nic_update_stats(falcon_stat_desc, FALCON_STAT_COUNT,
1408 falcon_stat_mask, nic_data->stats,
1409 efx->stats_buffer.addr, true);
1410 } else {
1411 netif_err(efx, hw, efx->net_dev,
1412 "timed out waiting for statistics\n");
1413 }
1414}
1415
1416static void falcon_stats_timer_func(unsigned long context)
1417{
1418 struct efx_nic *efx = (struct efx_nic *)context;
1419 struct falcon_nic_data *nic_data = efx->nic_data;
1420
1421 spin_lock(&efx->stats_lock);
1422
1423 falcon_stats_complete(efx);
1424 if (nic_data->stats_disable_count == 0)
1425 falcon_stats_request(efx);
1426
1427 spin_unlock(&efx->stats_lock);
1428}
1429
1430static bool falcon_loopback_link_poll(struct efx_nic *efx)
1431{
1432 struct efx_link_state old_state = efx->link_state;
1433
1434 WARN_ON(!mutex_is_locked(&efx->mac_lock));
1435 WARN_ON(!LOOPBACK_INTERNAL(efx));
1436
1437 efx->link_state.fd = true;
1438 efx->link_state.fc = efx->wanted_fc;
1439 efx->link_state.up = true;
1440 efx->link_state.speed = 10000;
1441
1442 return !efx_link_state_equal(&efx->link_state, &old_state);
1443}
1444
1445static int falcon_reconfigure_port(struct efx_nic *efx)
1446{
1447 int rc;
1448
1449 WARN_ON(efx_nic_rev(efx) > EFX_REV_FALCON_B0);
1450
1451
1452
1453
1454
1455 if (LOOPBACK_INTERNAL(efx))
1456 falcon_loopback_link_poll(efx);
1457 else
1458 efx->phy_op->poll(efx);
1459
1460 falcon_stop_nic_stats(efx);
1461 falcon_deconfigure_mac_wrapper(efx);
1462
1463 falcon_reset_macs(efx);
1464
1465 efx->phy_op->reconfigure(efx);
1466 rc = falcon_reconfigure_xmac(efx);
1467 BUG_ON(rc);
1468
1469 falcon_start_nic_stats(efx);
1470
1471
1472 efx_link_status_changed(efx);
1473
1474 return 0;
1475}
1476
1477
1478
1479
1480
1481
1482
1483
1484static void falcon_a1_prepare_enable_fc_tx(struct efx_nic *efx)
1485{
1486
1487 efx_schedule_reset(efx, RESET_TYPE_INVISIBLE);
1488}
1489
1490static void falcon_b0_prepare_enable_fc_tx(struct efx_nic *efx)
1491{
1492
1493 falcon_stop_nic_stats(efx);
1494 falcon_drain_tx_fifo(efx);
1495 falcon_reconfigure_xmac(efx);
1496 falcon_start_nic_stats(efx);
1497}
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507static int falcon_gmii_wait(struct efx_nic *efx)
1508{
1509 efx_oword_t md_stat;
1510 int count;
1511
1512
1513 for (count = 0; count < 5000; count++) {
1514 efx_reado(efx, &md_stat, FR_AB_MD_STAT);
1515 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
1516 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
1517 EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
1518 netif_err(efx, hw, efx->net_dev,
1519 "error from GMII access "
1520 EFX_OWORD_FMT"\n",
1521 EFX_OWORD_VAL(md_stat));
1522 return -EIO;
1523 }
1524 return 0;
1525 }
1526 udelay(10);
1527 }
1528 netif_err(efx, hw, efx->net_dev, "timed out waiting for GMII\n");
1529 return -ETIMEDOUT;
1530}
1531
1532
1533static int falcon_mdio_write(struct net_device *net_dev,
1534 int prtad, int devad, u16 addr, u16 value)
1535{
1536 struct efx_nic *efx = netdev_priv(net_dev);
1537 struct falcon_nic_data *nic_data = efx->nic_data;
1538 efx_oword_t reg;
1539 int rc;
1540
1541 netif_vdbg(efx, hw, efx->net_dev,
1542 "writing MDIO %d register %d.%d with 0x%04x\n",
1543 prtad, devad, addr, value);
1544
1545 mutex_lock(&nic_data->mdio_lock);
1546
1547
1548 rc = falcon_gmii_wait(efx);
1549 if (rc)
1550 goto out;
1551
1552
1553 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
1554 efx_writeo(efx, ®, FR_AB_MD_PHY_ADR);
1555
1556 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
1557 FRF_AB_MD_DEV_ADR, devad);
1558 efx_writeo(efx, ®, FR_AB_MD_ID);
1559
1560
1561 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
1562 efx_writeo(efx, ®, FR_AB_MD_TXD);
1563
1564 EFX_POPULATE_OWORD_2(reg,
1565 FRF_AB_MD_WRC, 1,
1566 FRF_AB_MD_GC, 0);
1567 efx_writeo(efx, ®, FR_AB_MD_CS);
1568
1569
1570 rc = falcon_gmii_wait(efx);
1571 if (rc) {
1572
1573 EFX_POPULATE_OWORD_2(reg,
1574 FRF_AB_MD_WRC, 0,
1575 FRF_AB_MD_GC, 1);
1576 efx_writeo(efx, ®, FR_AB_MD_CS);
1577 udelay(10);
1578 }
1579
1580out:
1581 mutex_unlock(&nic_data->mdio_lock);
1582 return rc;
1583}
1584
1585
1586static int falcon_mdio_read(struct net_device *net_dev,
1587 int prtad, int devad, u16 addr)
1588{
1589 struct efx_nic *efx = netdev_priv(net_dev);
1590 struct falcon_nic_data *nic_data = efx->nic_data;
1591 efx_oword_t reg;
1592 int rc;
1593
1594 mutex_lock(&nic_data->mdio_lock);
1595
1596
1597 rc = falcon_gmii_wait(efx);
1598 if (rc)
1599 goto out;
1600
1601 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
1602 efx_writeo(efx, ®, FR_AB_MD_PHY_ADR);
1603
1604 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
1605 FRF_AB_MD_DEV_ADR, devad);
1606 efx_writeo(efx, ®, FR_AB_MD_ID);
1607
1608
1609 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
1610 efx_writeo(efx, ®, FR_AB_MD_CS);
1611
1612
1613 rc = falcon_gmii_wait(efx);
1614 if (rc == 0) {
1615 efx_reado(efx, ®, FR_AB_MD_RXD);
1616 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
1617 netif_vdbg(efx, hw, efx->net_dev,
1618 "read from MDIO %d register %d.%d, got %04x\n",
1619 prtad, devad, addr, rc);
1620 } else {
1621
1622 EFX_POPULATE_OWORD_2(reg,
1623 FRF_AB_MD_RIC, 0,
1624 FRF_AB_MD_GC, 1);
1625 efx_writeo(efx, ®, FR_AB_MD_CS);
1626
1627 netif_dbg(efx, hw, efx->net_dev,
1628 "read from MDIO %d register %d.%d, got error %d\n",
1629 prtad, devad, addr, rc);
1630 }
1631
1632out:
1633 mutex_unlock(&nic_data->mdio_lock);
1634 return rc;
1635}
1636
1637
1638static int falcon_probe_port(struct efx_nic *efx)
1639{
1640 struct falcon_nic_data *nic_data = efx->nic_data;
1641 int rc;
1642
1643 switch (efx->phy_type) {
1644 case PHY_TYPE_SFX7101:
1645 efx->phy_op = &falcon_sfx7101_phy_ops;
1646 break;
1647 case PHY_TYPE_QT2022C2:
1648 case PHY_TYPE_QT2025C:
1649 efx->phy_op = &falcon_qt202x_phy_ops;
1650 break;
1651 case PHY_TYPE_TXC43128:
1652 efx->phy_op = &falcon_txc_phy_ops;
1653 break;
1654 default:
1655 netif_err(efx, probe, efx->net_dev, "Unknown PHY type %d\n",
1656 efx->phy_type);
1657 return -ENODEV;
1658 }
1659
1660
1661 mutex_init(&nic_data->mdio_lock);
1662 efx->mdio.mdio_read = falcon_mdio_read;
1663 efx->mdio.mdio_write = falcon_mdio_write;
1664 rc = efx->phy_op->probe(efx);
1665 if (rc != 0)
1666 return rc;
1667
1668
1669 efx->link_state.speed = 10000;
1670 efx->link_state.fd = true;
1671
1672
1673 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1674 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
1675 else
1676 efx->wanted_fc = EFX_FC_RX;
1677 if (efx->mdio.mmds & MDIO_DEVS_AN)
1678 efx->wanted_fc |= EFX_FC_AUTO;
1679
1680
1681 rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
1682 FALCON_MAC_STATS_SIZE, GFP_KERNEL);
1683 if (rc)
1684 return rc;
1685 netif_dbg(efx, probe, efx->net_dev,
1686 "stats buffer at %llx (virt %p phys %llx)\n",
1687 (u64)efx->stats_buffer.dma_addr,
1688 efx->stats_buffer.addr,
1689 (u64)virt_to_phys(efx->stats_buffer.addr));
1690
1691 return 0;
1692}
1693
1694static void falcon_remove_port(struct efx_nic *efx)
1695{
1696 efx->phy_op->remove(efx);
1697 efx_nic_free_buffer(efx, &efx->stats_buffer);
1698}
1699
1700
1701static bool
1702falcon_handle_global_event(struct efx_channel *channel, efx_qword_t *event)
1703{
1704 struct efx_nic *efx = channel->efx;
1705 struct falcon_nic_data *nic_data = efx->nic_data;
1706
1707 if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) ||
1708 EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) ||
1709 EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR))
1710
1711 return true;
1712
1713 if ((efx_nic_rev(efx) == EFX_REV_FALCON_B0) &&
1714 EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) {
1715 nic_data->xmac_poll_required = true;
1716 return true;
1717 }
1718
1719 if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1 ?
1720 EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) :
1721 EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) {
1722 netif_err(efx, rx_err, efx->net_dev,
1723 "channel %d seen global RX_RESET event. Resetting.\n",
1724 channel->channel);
1725
1726 atomic_inc(&efx->rx_reset);
1727 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
1728 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
1729 return true;
1730 }
1731
1732 return false;
1733}
1734
1735
1736
1737
1738
1739
1740
1741static int
1742falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
1743{
1744 struct falcon_nic_data *nic_data = efx->nic_data;
1745 struct falcon_nvconfig *nvconfig;
1746 struct falcon_spi_device *spi;
1747 void *region;
1748 int rc, magic_num, struct_ver;
1749 __le16 *word, *limit;
1750 u32 csum;
1751
1752 if (falcon_spi_present(&nic_data->spi_flash))
1753 spi = &nic_data->spi_flash;
1754 else if (falcon_spi_present(&nic_data->spi_eeprom))
1755 spi = &nic_data->spi_eeprom;
1756 else
1757 return -EINVAL;
1758
1759 region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
1760 if (!region)
1761 return -ENOMEM;
1762 nvconfig = region + FALCON_NVCONFIG_OFFSET;
1763
1764 mutex_lock(&nic_data->spi_lock);
1765 rc = falcon_spi_read(efx, spi, 0, FALCON_NVCONFIG_END, NULL, region);
1766 mutex_unlock(&nic_data->spi_lock);
1767 if (rc) {
1768 netif_err(efx, hw, efx->net_dev, "Failed to read %s\n",
1769 falcon_spi_present(&nic_data->spi_flash) ?
1770 "flash" : "EEPROM");
1771 rc = -EIO;
1772 goto out;
1773 }
1774
1775 magic_num = le16_to_cpu(nvconfig->board_magic_num);
1776 struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
1777
1778 rc = -EINVAL;
1779 if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) {
1780 netif_err(efx, hw, efx->net_dev,
1781 "NVRAM bad magic 0x%x\n", magic_num);
1782 goto out;
1783 }
1784 if (struct_ver < 2) {
1785 netif_err(efx, hw, efx->net_dev,
1786 "NVRAM has ancient version 0x%x\n", struct_ver);
1787 goto out;
1788 } else if (struct_ver < 4) {
1789 word = &nvconfig->board_magic_num;
1790 limit = (__le16 *) (nvconfig + 1);
1791 } else {
1792 word = region;
1793 limit = region + FALCON_NVCONFIG_END;
1794 }
1795 for (csum = 0; word < limit; ++word)
1796 csum += le16_to_cpu(*word);
1797
1798 if (~csum & 0xffff) {
1799 netif_err(efx, hw, efx->net_dev,
1800 "NVRAM has incorrect checksum\n");
1801 goto out;
1802 }
1803
1804 rc = 0;
1805 if (nvconfig_out)
1806 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
1807
1808 out:
1809 kfree(region);
1810 return rc;
1811}
1812
1813static int falcon_test_nvram(struct efx_nic *efx)
1814{
1815 return falcon_read_nvram(efx, NULL);
1816}
1817
1818static const struct efx_farch_register_test falcon_b0_register_tests[] = {
1819 { FR_AZ_ADR_REGION,
1820 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
1821 { FR_AZ_RX_CFG,
1822 EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
1823 { FR_AZ_TX_CFG,
1824 EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
1825 { FR_AZ_TX_RESERVED,
1826 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
1827 { FR_AB_MAC_CTRL,
1828 EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
1829 { FR_AZ_SRM_TX_DC_CFG,
1830 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
1831 { FR_AZ_RX_DC_CFG,
1832 EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
1833 { FR_AZ_RX_DC_PF_WM,
1834 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
1835 { FR_BZ_DP_CTRL,
1836 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
1837 { FR_AB_GM_CFG2,
1838 EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
1839 { FR_AB_GMF_CFG0,
1840 EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
1841 { FR_AB_XM_GLB_CFG,
1842 EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
1843 { FR_AB_XM_TX_CFG,
1844 EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
1845 { FR_AB_XM_RX_CFG,
1846 EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
1847 { FR_AB_XM_RX_PARAM,
1848 EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
1849 { FR_AB_XM_FC,
1850 EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
1851 { FR_AB_XM_ADR_LO,
1852 EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
1853 { FR_AB_XX_SD_CTL,
1854 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
1855};
1856
1857static int
1858falcon_b0_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
1859{
1860 enum reset_type reset_method = RESET_TYPE_INVISIBLE;
1861 int rc, rc2;
1862
1863 mutex_lock(&efx->mac_lock);
1864 if (efx->loopback_modes) {
1865
1866
1867 if (efx->loopback_modes & (1 << LOOPBACK_XGMII))
1868 efx->loopback_mode = LOOPBACK_XGMII;
1869 else
1870 efx->loopback_mode = __ffs(efx->loopback_modes);
1871 }
1872 __efx_reconfigure_port(efx);
1873 mutex_unlock(&efx->mac_lock);
1874
1875 efx_reset_down(efx, reset_method);
1876
1877 tests->registers =
1878 efx_farch_test_registers(efx, falcon_b0_register_tests,
1879 ARRAY_SIZE(falcon_b0_register_tests))
1880 ? -1 : 1;
1881
1882 rc = falcon_reset_hw(efx, reset_method);
1883 rc2 = efx_reset_up(efx, reset_method, rc == 0);
1884 return rc ? rc : rc2;
1885}
1886
1887
1888
1889
1890
1891
1892
1893
1894static enum reset_type falcon_map_reset_reason(enum reset_type reason)
1895{
1896 switch (reason) {
1897 case RESET_TYPE_RX_RECOVERY:
1898 case RESET_TYPE_DMA_ERROR:
1899 case RESET_TYPE_TX_SKIP:
1900
1901
1902
1903 return RESET_TYPE_INVISIBLE;
1904 default:
1905 return RESET_TYPE_ALL;
1906 }
1907}
1908
1909static int falcon_map_reset_flags(u32 *flags)
1910{
1911 enum {
1912 FALCON_RESET_INVISIBLE = (ETH_RESET_DMA | ETH_RESET_FILTER |
1913 ETH_RESET_OFFLOAD | ETH_RESET_MAC),
1914 FALCON_RESET_ALL = FALCON_RESET_INVISIBLE | ETH_RESET_PHY,
1915 FALCON_RESET_WORLD = FALCON_RESET_ALL | ETH_RESET_IRQ,
1916 };
1917
1918 if ((*flags & FALCON_RESET_WORLD) == FALCON_RESET_WORLD) {
1919 *flags &= ~FALCON_RESET_WORLD;
1920 return RESET_TYPE_WORLD;
1921 }
1922
1923 if ((*flags & FALCON_RESET_ALL) == FALCON_RESET_ALL) {
1924 *flags &= ~FALCON_RESET_ALL;
1925 return RESET_TYPE_ALL;
1926 }
1927
1928 if ((*flags & FALCON_RESET_INVISIBLE) == FALCON_RESET_INVISIBLE) {
1929 *flags &= ~FALCON_RESET_INVISIBLE;
1930 return RESET_TYPE_INVISIBLE;
1931 }
1932
1933 return -EINVAL;
1934}
1935
1936
1937
1938static int __falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
1939{
1940 struct falcon_nic_data *nic_data = efx->nic_data;
1941 efx_oword_t glb_ctl_reg_ker;
1942 int rc;
1943
1944 netif_dbg(efx, hw, efx->net_dev, "performing %s hardware reset\n",
1945 RESET_TYPE(method));
1946
1947
1948 if (method == RESET_TYPE_WORLD) {
1949 rc = pci_save_state(efx->pci_dev);
1950 if (rc) {
1951 netif_err(efx, drv, efx->net_dev,
1952 "failed to backup PCI state of primary "
1953 "function prior to hardware reset\n");
1954 goto fail1;
1955 }
1956 if (efx_nic_is_dual_func(efx)) {
1957 rc = pci_save_state(nic_data->pci_dev2);
1958 if (rc) {
1959 netif_err(efx, drv, efx->net_dev,
1960 "failed to backup PCI state of "
1961 "secondary function prior to "
1962 "hardware reset\n");
1963 goto fail2;
1964 }
1965 }
1966
1967 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
1968 FRF_AB_EXT_PHY_RST_DUR,
1969 FFE_AB_EXT_PHY_RST_DUR_10240US,
1970 FRF_AB_SWRST, 1);
1971 } else {
1972 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
1973
1974 FRF_AB_EXT_PHY_RST_CTL,
1975 method == RESET_TYPE_INVISIBLE,
1976
1977 FRF_AB_PCIE_CORE_RST_CTL, 1,
1978 FRF_AB_PCIE_NSTKY_RST_CTL, 1,
1979 FRF_AB_PCIE_SD_RST_CTL, 1,
1980 FRF_AB_EE_RST_CTL, 1,
1981 FRF_AB_EXT_PHY_RST_DUR,
1982 FFE_AB_EXT_PHY_RST_DUR_10240US,
1983 FRF_AB_SWRST, 1);
1984 }
1985 efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
1986
1987 netif_dbg(efx, hw, efx->net_dev, "waiting for hardware reset\n");
1988 schedule_timeout_uninterruptible(HZ / 20);
1989
1990
1991 if (method == RESET_TYPE_WORLD) {
1992 if (efx_nic_is_dual_func(efx))
1993 pci_restore_state(nic_data->pci_dev2);
1994 pci_restore_state(efx->pci_dev);
1995 netif_dbg(efx, drv, efx->net_dev,
1996 "successfully restored PCI config\n");
1997 }
1998
1999
2000 efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2001 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
2002 rc = -ETIMEDOUT;
2003 netif_err(efx, hw, efx->net_dev,
2004 "timed out waiting for hardware reset\n");
2005 goto fail3;
2006 }
2007 netif_dbg(efx, hw, efx->net_dev, "hardware reset complete\n");
2008
2009 return 0;
2010
2011
2012fail2:
2013 pci_restore_state(efx->pci_dev);
2014fail1:
2015fail3:
2016 return rc;
2017}
2018
2019static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2020{
2021 struct falcon_nic_data *nic_data = efx->nic_data;
2022 int rc;
2023
2024 mutex_lock(&nic_data->spi_lock);
2025 rc = __falcon_reset_hw(efx, method);
2026 mutex_unlock(&nic_data->spi_lock);
2027
2028 return rc;
2029}
2030
2031static void falcon_monitor(struct efx_nic *efx)
2032{
2033 bool link_changed;
2034 int rc;
2035
2036 BUG_ON(!mutex_is_locked(&efx->mac_lock));
2037
2038 rc = falcon_board(efx)->type->monitor(efx);
2039 if (rc) {
2040 netif_err(efx, hw, efx->net_dev,
2041 "Board sensor %s; shutting down PHY\n",
2042 (rc == -ERANGE) ? "reported fault" : "failed");
2043 efx->phy_mode |= PHY_MODE_LOW_POWER;
2044 rc = __efx_reconfigure_port(efx);
2045 WARN_ON(rc);
2046 }
2047
2048 if (LOOPBACK_INTERNAL(efx))
2049 link_changed = falcon_loopback_link_poll(efx);
2050 else
2051 link_changed = efx->phy_op->poll(efx);
2052
2053 if (link_changed) {
2054 falcon_stop_nic_stats(efx);
2055 falcon_deconfigure_mac_wrapper(efx);
2056
2057 falcon_reset_macs(efx);
2058 rc = falcon_reconfigure_xmac(efx);
2059 BUG_ON(rc);
2060
2061 falcon_start_nic_stats(efx);
2062
2063 efx_link_status_changed(efx);
2064 }
2065
2066 falcon_poll_xmac(efx);
2067}
2068
2069
2070
2071
2072static int falcon_reset_sram(struct efx_nic *efx)
2073{
2074 efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2075 int count;
2076
2077
2078 efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2079 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
2080 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
2081 efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2082
2083
2084 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2085 FRF_AZ_SRM_INIT_EN, 1,
2086 FRF_AZ_SRM_NB_SZ, 0);
2087 efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2088
2089
2090 count = 0;
2091 do {
2092 netif_dbg(efx, hw, efx->net_dev,
2093 "waiting for SRAM reset (attempt %d)...\n", count);
2094
2095
2096 schedule_timeout_uninterruptible(HZ / 50);
2097
2098
2099 efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2100 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
2101 netif_dbg(efx, hw, efx->net_dev,
2102 "SRAM reset complete\n");
2103
2104 return 0;
2105 }
2106 } while (++count < 20);
2107
2108 netif_err(efx, hw, efx->net_dev, "timed out waiting for SRAM reset\n");
2109 return -ETIMEDOUT;
2110}
2111
2112static void falcon_spi_device_init(struct efx_nic *efx,
2113 struct falcon_spi_device *spi_device,
2114 unsigned int device_id, u32 device_type)
2115{
2116 if (device_type != 0) {
2117 spi_device->device_id = device_id;
2118 spi_device->size =
2119 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
2120 spi_device->addr_len =
2121 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
2122 spi_device->munge_address = (spi_device->size == 1 << 9 &&
2123 spi_device->addr_len == 1);
2124 spi_device->erase_command =
2125 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
2126 spi_device->erase_size =
2127 1 << SPI_DEV_TYPE_FIELD(device_type,
2128 SPI_DEV_TYPE_ERASE_SIZE);
2129 spi_device->block_size =
2130 1 << SPI_DEV_TYPE_FIELD(device_type,
2131 SPI_DEV_TYPE_BLOCK_SIZE);
2132 } else {
2133 spi_device->size = 0;
2134 }
2135}
2136
2137
2138static int falcon_probe_nvconfig(struct efx_nic *efx)
2139{
2140 struct falcon_nic_data *nic_data = efx->nic_data;
2141 struct falcon_nvconfig *nvconfig;
2142 int rc;
2143
2144 nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
2145 if (!nvconfig)
2146 return -ENOMEM;
2147
2148 rc = falcon_read_nvram(efx, nvconfig);
2149 if (rc)
2150 goto out;
2151
2152 efx->phy_type = nvconfig->board_v2.port0_phy_type;
2153 efx->mdio.prtad = nvconfig->board_v2.port0_phy_addr;
2154
2155 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
2156 falcon_spi_device_init(
2157 efx, &nic_data->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
2158 le32_to_cpu(nvconfig->board_v3
2159 .spi_device_type[FFE_AB_SPI_DEVICE_FLASH]));
2160 falcon_spi_device_init(
2161 efx, &nic_data->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
2162 le32_to_cpu(nvconfig->board_v3
2163 .spi_device_type[FFE_AB_SPI_DEVICE_EEPROM]));
2164 }
2165
2166
2167 memcpy(efx->net_dev->perm_addr, nvconfig->mac_address[0], ETH_ALEN);
2168
2169 netif_dbg(efx, probe, efx->net_dev, "PHY is %d phy_id %d\n",
2170 efx->phy_type, efx->mdio.prtad);
2171
2172 rc = falcon_probe_board(efx,
2173 le16_to_cpu(nvconfig->board_v2.board_revision));
2174out:
2175 kfree(nvconfig);
2176 return rc;
2177}
2178
2179static int falcon_dimension_resources(struct efx_nic *efx)
2180{
2181 efx->rx_dc_base = 0x20000;
2182 efx->tx_dc_base = 0x26000;
2183 return 0;
2184}
2185
2186
2187static void falcon_probe_spi_devices(struct efx_nic *efx)
2188{
2189 struct falcon_nic_data *nic_data = efx->nic_data;
2190 efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
2191 int boot_dev;
2192
2193 efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
2194 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2195 efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2196
2197 if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
2198 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
2199 FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM);
2200 netif_dbg(efx, probe, efx->net_dev, "Booted from %s\n",
2201 boot_dev == FFE_AB_SPI_DEVICE_FLASH ?
2202 "flash" : "EEPROM");
2203 } else {
2204
2205
2206 boot_dev = -1;
2207 netif_dbg(efx, probe, efx->net_dev,
2208 "Booted from internal ASIC settings;"
2209 " setting SPI config\n");
2210 EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0,
2211
2212 FRF_AB_EE_SF_CLOCK_DIV, 7,
2213
2214 FRF_AB_EE_EE_CLOCK_DIV, 63);
2215 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2216 }
2217
2218 mutex_init(&nic_data->spi_lock);
2219
2220 if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
2221 falcon_spi_device_init(efx, &nic_data->spi_flash,
2222 FFE_AB_SPI_DEVICE_FLASH,
2223 default_flash_type);
2224 if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
2225 falcon_spi_device_init(efx, &nic_data->spi_eeprom,
2226 FFE_AB_SPI_DEVICE_EEPROM,
2227 large_eeprom_type);
2228}
2229
2230static unsigned int falcon_a1_mem_map_size(struct efx_nic *efx)
2231{
2232 return 0x20000;
2233}
2234
2235static unsigned int falcon_b0_mem_map_size(struct efx_nic *efx)
2236{
2237
2238
2239
2240 return FR_BZ_RX_INDIRECTION_TBL +
2241 FR_BZ_RX_INDIRECTION_TBL_STEP * FR_BZ_RX_INDIRECTION_TBL_ROWS;
2242}
2243
2244static int falcon_probe_nic(struct efx_nic *efx)
2245{
2246 struct falcon_nic_data *nic_data;
2247 struct falcon_board *board;
2248 int rc;
2249
2250
2251 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
2252 if (!nic_data)
2253 return -ENOMEM;
2254 efx->nic_data = nic_data;
2255
2256 rc = -ENODEV;
2257
2258 if (efx_farch_fpga_ver(efx) != 0) {
2259 netif_err(efx, probe, efx->net_dev,
2260 "Falcon FPGA not supported\n");
2261 goto fail1;
2262 }
2263
2264 if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
2265 efx_oword_t nic_stat;
2266 struct pci_dev *dev;
2267 u8 pci_rev = efx->pci_dev->revision;
2268
2269 if ((pci_rev == 0xff) || (pci_rev == 0)) {
2270 netif_err(efx, probe, efx->net_dev,
2271 "Falcon rev A0 not supported\n");
2272 goto fail1;
2273 }
2274 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2275 if (EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) == 0) {
2276 netif_err(efx, probe, efx->net_dev,
2277 "Falcon rev A1 1G not supported\n");
2278 goto fail1;
2279 }
2280 if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) {
2281 netif_err(efx, probe, efx->net_dev,
2282 "Falcon rev A1 PCI-X not supported\n");
2283 goto fail1;
2284 }
2285
2286 dev = pci_dev_get(efx->pci_dev);
2287 while ((dev = pci_get_device(PCI_VENDOR_ID_SOLARFLARE,
2288 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1,
2289 dev))) {
2290 if (dev->bus == efx->pci_dev->bus &&
2291 dev->devfn == efx->pci_dev->devfn + 1) {
2292 nic_data->pci_dev2 = dev;
2293 break;
2294 }
2295 }
2296 if (!nic_data->pci_dev2) {
2297 netif_err(efx, probe, efx->net_dev,
2298 "failed to find secondary function\n");
2299 rc = -ENODEV;
2300 goto fail2;
2301 }
2302 }
2303
2304
2305 rc = __falcon_reset_hw(efx, RESET_TYPE_ALL);
2306 if (rc) {
2307 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
2308 goto fail3;
2309 }
2310
2311
2312 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t),
2313 GFP_KERNEL);
2314 if (rc)
2315 goto fail4;
2316 BUG_ON(efx->irq_status.dma_addr & 0x0f);
2317
2318 netif_dbg(efx, probe, efx->net_dev,
2319 "INT_KER at %llx (virt %p phys %llx)\n",
2320 (u64)efx->irq_status.dma_addr,
2321 efx->irq_status.addr,
2322 (u64)virt_to_phys(efx->irq_status.addr));
2323
2324 falcon_probe_spi_devices(efx);
2325
2326
2327 rc = falcon_probe_nvconfig(efx);
2328 if (rc) {
2329 if (rc == -EINVAL)
2330 netif_err(efx, probe, efx->net_dev, "NVRAM is invalid\n");
2331 goto fail5;
2332 }
2333
2334 efx->max_channels = (efx_nic_rev(efx) <= EFX_REV_FALCON_A1 ? 4 :
2335 EFX_MAX_CHANNELS);
2336 efx->timer_quantum_ns = 4968;
2337
2338
2339 board = falcon_board(efx);
2340 board->i2c_adap.owner = THIS_MODULE;
2341 board->i2c_data = falcon_i2c_bit_operations;
2342 board->i2c_data.data = efx;
2343 board->i2c_adap.algo_data = &board->i2c_data;
2344 board->i2c_adap.dev.parent = &efx->pci_dev->dev;
2345 strlcpy(board->i2c_adap.name, "SFC4000 GPIO",
2346 sizeof(board->i2c_adap.name));
2347 rc = i2c_bit_add_bus(&board->i2c_adap);
2348 if (rc)
2349 goto fail5;
2350
2351 rc = falcon_board(efx)->type->init(efx);
2352 if (rc) {
2353 netif_err(efx, probe, efx->net_dev,
2354 "failed to initialise board\n");
2355 goto fail6;
2356 }
2357
2358 nic_data->stats_disable_count = 1;
2359 setup_timer(&nic_data->stats_timer, &falcon_stats_timer_func,
2360 (unsigned long)efx);
2361
2362 return 0;
2363
2364 fail6:
2365 i2c_del_adapter(&board->i2c_adap);
2366 memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
2367 fail5:
2368 efx_nic_free_buffer(efx, &efx->irq_status);
2369 fail4:
2370 fail3:
2371 if (nic_data->pci_dev2) {
2372 pci_dev_put(nic_data->pci_dev2);
2373 nic_data->pci_dev2 = NULL;
2374 }
2375 fail2:
2376 fail1:
2377 kfree(efx->nic_data);
2378 return rc;
2379}
2380
2381static void falcon_init_rx_cfg(struct efx_nic *efx)
2382{
2383
2384 const unsigned ctrl_xon_thr = 20;
2385 const unsigned ctrl_xoff_thr = 25;
2386 efx_oword_t reg;
2387
2388 efx_reado(efx, ®, FR_AZ_RX_CFG);
2389 if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
2390
2391
2392
2393
2394
2395
2396 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
2397 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
2398 (3 * 4096) >> 5);
2399 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, 512 >> 8);
2400 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, 2048 >> 8);
2401 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
2402 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
2403 } else {
2404
2405 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
2406 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
2407 EFX_RX_USR_BUF_SIZE >> 5);
2408
2409 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, 27648 >> 8);
2410 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, 54272 >> 8);
2411 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
2412 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
2413 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
2414
2415
2416
2417
2418 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_INSRT_HDR, 1);
2419 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_ALG, 1);
2420 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_IP_HASH, 1);
2421 }
2422
2423
2424 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
2425 efx_writeo(efx, ®, FR_AZ_RX_CFG);
2426}
2427
2428
2429
2430
2431
2432static int falcon_init_nic(struct efx_nic *efx)
2433{
2434 efx_oword_t temp;
2435 int rc;
2436
2437
2438 efx_reado(efx, &temp, FR_AB_NIC_STAT);
2439 EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
2440 efx_writeo(efx, &temp, FR_AB_NIC_STAT);
2441
2442 rc = falcon_reset_sram(efx);
2443 if (rc)
2444 return rc;
2445
2446
2447
2448
2449 if (EFX_WORKAROUND_5129(efx)) {
2450 efx_reado(efx, &temp, FR_AZ_CSR_SPARE);
2451 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
2452 efx_writeo(efx, &temp, FR_AZ_CSR_SPARE);
2453 }
2454
2455 if (EFX_WORKAROUND_7244(efx)) {
2456 efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
2457 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
2458 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
2459 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
2460 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
2461 efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
2462 }
2463
2464
2465
2466
2467
2468 efx_reado(efx, &temp, FR_AA_RX_SELF_RST);
2469 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
2470 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
2471 if (EFX_WORKAROUND_5583(efx))
2472 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
2473 efx_writeo(efx, &temp, FR_AA_RX_SELF_RST);
2474
2475
2476
2477
2478 efx_reado(efx, &temp, FR_AZ_TX_CFG);
2479 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
2480 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
2481
2482 falcon_init_rx_cfg(efx);
2483
2484 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
2485
2486 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
2487 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
2488
2489
2490 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
2491 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
2492 }
2493
2494 efx_farch_init_common(efx);
2495
2496 return 0;
2497}
2498
2499static void falcon_remove_nic(struct efx_nic *efx)
2500{
2501 struct falcon_nic_data *nic_data = efx->nic_data;
2502 struct falcon_board *board = falcon_board(efx);
2503
2504 board->type->fini(efx);
2505
2506
2507 i2c_del_adapter(&board->i2c_adap);
2508 memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
2509
2510 efx_nic_free_buffer(efx, &efx->irq_status);
2511
2512 __falcon_reset_hw(efx, RESET_TYPE_ALL);
2513
2514
2515 if (nic_data->pci_dev2) {
2516 pci_dev_put(nic_data->pci_dev2);
2517 nic_data->pci_dev2 = NULL;
2518 }
2519
2520
2521 kfree(efx->nic_data);
2522 efx->nic_data = NULL;
2523}
2524
2525static size_t falcon_describe_nic_stats(struct efx_nic *efx, u8 *names)
2526{
2527 return efx_nic_describe_stats(falcon_stat_desc, FALCON_STAT_COUNT,
2528 falcon_stat_mask, names);
2529}
2530
2531static size_t falcon_update_nic_stats(struct efx_nic *efx, u64 *full_stats,
2532 struct rtnl_link_stats64 *core_stats)
2533{
2534 struct falcon_nic_data *nic_data = efx->nic_data;
2535 u64 *stats = nic_data->stats;
2536 efx_oword_t cnt;
2537
2538 if (!nic_data->stats_disable_count) {
2539 efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
2540 stats[FALCON_STAT_rx_nodesc_drop_cnt] +=
2541 EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
2542
2543 if (nic_data->stats_pending &&
2544 FALCON_XMAC_STATS_DMA_FLAG(efx)) {
2545 nic_data->stats_pending = false;
2546 rmb();
2547 efx_nic_update_stats(
2548 falcon_stat_desc, FALCON_STAT_COUNT,
2549 falcon_stat_mask,
2550 stats, efx->stats_buffer.addr, true);
2551 }
2552
2553
2554 efx_update_diff_stat(&stats[FALCON_STAT_rx_bad_bytes],
2555 stats[FALCON_STAT_rx_bytes] -
2556 stats[FALCON_STAT_rx_good_bytes] -
2557 stats[FALCON_STAT_rx_control] * 64);
2558 }
2559
2560 if (full_stats)
2561 memcpy(full_stats, stats, sizeof(u64) * FALCON_STAT_COUNT);
2562
2563 if (core_stats) {
2564 core_stats->rx_packets = stats[FALCON_STAT_rx_packets];
2565 core_stats->tx_packets = stats[FALCON_STAT_tx_packets];
2566 core_stats->rx_bytes = stats[FALCON_STAT_rx_bytes];
2567 core_stats->tx_bytes = stats[FALCON_STAT_tx_bytes];
2568 core_stats->rx_dropped = stats[FALCON_STAT_rx_nodesc_drop_cnt];
2569 core_stats->multicast = stats[FALCON_STAT_rx_multicast];
2570 core_stats->rx_length_errors =
2571 stats[FALCON_STAT_rx_gtjumbo] +
2572 stats[FALCON_STAT_rx_length_error];
2573 core_stats->rx_crc_errors = stats[FALCON_STAT_rx_bad];
2574 core_stats->rx_frame_errors = stats[FALCON_STAT_rx_align_error];
2575 core_stats->rx_fifo_errors = stats[FALCON_STAT_rx_overflow];
2576
2577 core_stats->rx_errors = (core_stats->rx_length_errors +
2578 core_stats->rx_crc_errors +
2579 core_stats->rx_frame_errors +
2580 stats[FALCON_STAT_rx_symbol_error]);
2581 }
2582
2583 return FALCON_STAT_COUNT;
2584}
2585
2586void falcon_start_nic_stats(struct efx_nic *efx)
2587{
2588 struct falcon_nic_data *nic_data = efx->nic_data;
2589
2590 spin_lock_bh(&efx->stats_lock);
2591 if (--nic_data->stats_disable_count == 0)
2592 falcon_stats_request(efx);
2593 spin_unlock_bh(&efx->stats_lock);
2594}
2595
2596void falcon_stop_nic_stats(struct efx_nic *efx)
2597{
2598 struct falcon_nic_data *nic_data = efx->nic_data;
2599 int i;
2600
2601 might_sleep();
2602
2603 spin_lock_bh(&efx->stats_lock);
2604 ++nic_data->stats_disable_count;
2605 spin_unlock_bh(&efx->stats_lock);
2606
2607 del_timer_sync(&nic_data->stats_timer);
2608
2609
2610
2611 for (i = 0; i < 4 && nic_data->stats_pending; i++) {
2612 if (FALCON_XMAC_STATS_DMA_FLAG(efx))
2613 break;
2614 msleep(1);
2615 }
2616
2617 spin_lock_bh(&efx->stats_lock);
2618 falcon_stats_complete(efx);
2619 spin_unlock_bh(&efx->stats_lock);
2620}
2621
2622static void falcon_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
2623{
2624 falcon_board(efx)->type->set_id_led(efx, mode);
2625}
2626
2627
2628
2629
2630
2631
2632
2633
2634static void falcon_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
2635{
2636 wol->supported = 0;
2637 wol->wolopts = 0;
2638 memset(&wol->sopass, 0, sizeof(wol->sopass));
2639}
2640
2641static int falcon_set_wol(struct efx_nic *efx, u32 type)
2642{
2643 if (type != 0)
2644 return -EINVAL;
2645 return 0;
2646}
2647
2648
2649
2650
2651
2652
2653
2654
2655const struct efx_nic_type falcon_a1_nic_type = {
2656 .mem_map_size = falcon_a1_mem_map_size,
2657 .probe = falcon_probe_nic,
2658 .remove = falcon_remove_nic,
2659 .init = falcon_init_nic,
2660 .dimension_resources = falcon_dimension_resources,
2661 .fini = falcon_irq_ack_a1,
2662 .monitor = falcon_monitor,
2663 .map_reset_reason = falcon_map_reset_reason,
2664 .map_reset_flags = falcon_map_reset_flags,
2665 .reset = falcon_reset_hw,
2666 .probe_port = falcon_probe_port,
2667 .remove_port = falcon_remove_port,
2668 .handle_global_event = falcon_handle_global_event,
2669 .fini_dmaq = efx_farch_fini_dmaq,
2670 .prepare_flush = falcon_prepare_flush,
2671 .finish_flush = efx_port_dummy_op_void,
2672 .describe_stats = falcon_describe_nic_stats,
2673 .update_stats = falcon_update_nic_stats,
2674 .start_stats = falcon_start_nic_stats,
2675 .stop_stats = falcon_stop_nic_stats,
2676 .set_id_led = falcon_set_id_led,
2677 .push_irq_moderation = falcon_push_irq_moderation,
2678 .reconfigure_port = falcon_reconfigure_port,
2679 .prepare_enable_fc_tx = falcon_a1_prepare_enable_fc_tx,
2680 .reconfigure_mac = falcon_reconfigure_xmac,
2681 .check_mac_fault = falcon_xmac_check_fault,
2682 .get_wol = falcon_get_wol,
2683 .set_wol = falcon_set_wol,
2684 .resume_wol = efx_port_dummy_op_void,
2685 .test_nvram = falcon_test_nvram,
2686 .irq_enable_master = efx_farch_irq_enable_master,
2687 .irq_test_generate = efx_farch_irq_test_generate,
2688 .irq_disable_non_ev = efx_farch_irq_disable_master,
2689 .irq_handle_msi = efx_farch_msi_interrupt,
2690 .irq_handle_legacy = falcon_legacy_interrupt_a1,
2691 .tx_probe = efx_farch_tx_probe,
2692 .tx_init = efx_farch_tx_init,
2693 .tx_remove = efx_farch_tx_remove,
2694 .tx_write = efx_farch_tx_write,
2695 .rx_push_indir_table = efx_farch_rx_push_indir_table,
2696 .rx_probe = efx_farch_rx_probe,
2697 .rx_init = efx_farch_rx_init,
2698 .rx_remove = efx_farch_rx_remove,
2699 .rx_write = efx_farch_rx_write,
2700 .rx_defer_refill = efx_farch_rx_defer_refill,
2701 .ev_probe = efx_farch_ev_probe,
2702 .ev_init = efx_farch_ev_init,
2703 .ev_fini = efx_farch_ev_fini,
2704 .ev_remove = efx_farch_ev_remove,
2705 .ev_process = efx_farch_ev_process,
2706 .ev_read_ack = efx_farch_ev_read_ack,
2707 .ev_test_generate = efx_farch_ev_test_generate,
2708
2709
2710
2711
2712
2713 .filter_table_probe = efx_farch_filter_table_probe,
2714 .filter_table_restore = efx_farch_filter_table_restore,
2715 .filter_table_remove = efx_farch_filter_table_remove,
2716 .filter_insert = efx_farch_filter_insert,
2717 .filter_remove_safe = efx_farch_filter_remove_safe,
2718 .filter_get_safe = efx_farch_filter_get_safe,
2719 .filter_clear_rx = efx_farch_filter_clear_rx,
2720 .filter_count_rx_used = efx_farch_filter_count_rx_used,
2721 .filter_get_rx_id_limit = efx_farch_filter_get_rx_id_limit,
2722 .filter_get_rx_ids = efx_farch_filter_get_rx_ids,
2723
2724#ifdef CONFIG_SFC_MTD
2725 .mtd_probe = falcon_mtd_probe,
2726 .mtd_rename = falcon_mtd_rename,
2727 .mtd_read = falcon_mtd_read,
2728 .mtd_erase = falcon_mtd_erase,
2729 .mtd_write = falcon_mtd_write,
2730 .mtd_sync = falcon_mtd_sync,
2731#endif
2732
2733 .revision = EFX_REV_FALCON_A1,
2734 .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
2735 .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
2736 .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
2737 .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
2738 .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
2739 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
2740 .rx_buffer_padding = 0x24,
2741 .can_rx_scatter = false,
2742 .max_interrupt_mode = EFX_INT_MODE_MSI,
2743 .timer_period_max = 1 << FRF_AB_TC_TIMER_VAL_WIDTH,
2744 .offload_features = NETIF_F_IP_CSUM,
2745 .mcdi_max_ver = -1,
2746};
2747
2748const struct efx_nic_type falcon_b0_nic_type = {
2749 .mem_map_size = falcon_b0_mem_map_size,
2750 .probe = falcon_probe_nic,
2751 .remove = falcon_remove_nic,
2752 .init = falcon_init_nic,
2753 .dimension_resources = falcon_dimension_resources,
2754 .fini = efx_port_dummy_op_void,
2755 .monitor = falcon_monitor,
2756 .map_reset_reason = falcon_map_reset_reason,
2757 .map_reset_flags = falcon_map_reset_flags,
2758 .reset = falcon_reset_hw,
2759 .probe_port = falcon_probe_port,
2760 .remove_port = falcon_remove_port,
2761 .handle_global_event = falcon_handle_global_event,
2762 .fini_dmaq = efx_farch_fini_dmaq,
2763 .prepare_flush = falcon_prepare_flush,
2764 .finish_flush = efx_port_dummy_op_void,
2765 .describe_stats = falcon_describe_nic_stats,
2766 .update_stats = falcon_update_nic_stats,
2767 .start_stats = falcon_start_nic_stats,
2768 .stop_stats = falcon_stop_nic_stats,
2769 .set_id_led = falcon_set_id_led,
2770 .push_irq_moderation = falcon_push_irq_moderation,
2771 .reconfigure_port = falcon_reconfigure_port,
2772 .prepare_enable_fc_tx = falcon_b0_prepare_enable_fc_tx,
2773 .reconfigure_mac = falcon_reconfigure_xmac,
2774 .check_mac_fault = falcon_xmac_check_fault,
2775 .get_wol = falcon_get_wol,
2776 .set_wol = falcon_set_wol,
2777 .resume_wol = efx_port_dummy_op_void,
2778 .test_chip = falcon_b0_test_chip,
2779 .test_nvram = falcon_test_nvram,
2780 .irq_enable_master = efx_farch_irq_enable_master,
2781 .irq_test_generate = efx_farch_irq_test_generate,
2782 .irq_disable_non_ev = efx_farch_irq_disable_master,
2783 .irq_handle_msi = efx_farch_msi_interrupt,
2784 .irq_handle_legacy = efx_farch_legacy_interrupt,
2785 .tx_probe = efx_farch_tx_probe,
2786 .tx_init = efx_farch_tx_init,
2787 .tx_remove = efx_farch_tx_remove,
2788 .tx_write = efx_farch_tx_write,
2789 .rx_push_indir_table = efx_farch_rx_push_indir_table,
2790 .rx_probe = efx_farch_rx_probe,
2791 .rx_init = efx_farch_rx_init,
2792 .rx_remove = efx_farch_rx_remove,
2793 .rx_write = efx_farch_rx_write,
2794 .rx_defer_refill = efx_farch_rx_defer_refill,
2795 .ev_probe = efx_farch_ev_probe,
2796 .ev_init = efx_farch_ev_init,
2797 .ev_fini = efx_farch_ev_fini,
2798 .ev_remove = efx_farch_ev_remove,
2799 .ev_process = efx_farch_ev_process,
2800 .ev_read_ack = efx_farch_ev_read_ack,
2801 .ev_test_generate = efx_farch_ev_test_generate,
2802 .filter_table_probe = efx_farch_filter_table_probe,
2803 .filter_table_restore = efx_farch_filter_table_restore,
2804 .filter_table_remove = efx_farch_filter_table_remove,
2805 .filter_update_rx_scatter = efx_farch_filter_update_rx_scatter,
2806 .filter_insert = efx_farch_filter_insert,
2807 .filter_remove_safe = efx_farch_filter_remove_safe,
2808 .filter_get_safe = efx_farch_filter_get_safe,
2809 .filter_clear_rx = efx_farch_filter_clear_rx,
2810 .filter_count_rx_used = efx_farch_filter_count_rx_used,
2811 .filter_get_rx_id_limit = efx_farch_filter_get_rx_id_limit,
2812 .filter_get_rx_ids = efx_farch_filter_get_rx_ids,
2813#ifdef CONFIG_RFS_ACCEL
2814 .filter_rfs_insert = efx_farch_filter_rfs_insert,
2815 .filter_rfs_expire_one = efx_farch_filter_rfs_expire_one,
2816#endif
2817#ifdef CONFIG_SFC_MTD
2818 .mtd_probe = falcon_mtd_probe,
2819 .mtd_rename = falcon_mtd_rename,
2820 .mtd_read = falcon_mtd_read,
2821 .mtd_erase = falcon_mtd_erase,
2822 .mtd_write = falcon_mtd_write,
2823 .mtd_sync = falcon_mtd_sync,
2824#endif
2825
2826 .revision = EFX_REV_FALCON_B0,
2827 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
2828 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
2829 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
2830 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
2831 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
2832 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
2833 .rx_prefix_size = FS_BZ_RX_PREFIX_SIZE,
2834 .rx_hash_offset = FS_BZ_RX_PREFIX_HASH_OFST,
2835 .rx_buffer_padding = 0,
2836 .can_rx_scatter = true,
2837 .max_interrupt_mode = EFX_INT_MODE_MSIX,
2838 .timer_period_max = 1 << FRF_AB_TC_TIMER_VAL_WIDTH,
2839 .offload_features = NETIF_F_IP_CSUM | NETIF_F_RXHASH | NETIF_F_NTUPLE,
2840 .mcdi_max_ver = -1,
2841 .max_rx_ip_filters = FR_BZ_RX_FILTER_TBL0_ROWS,
2842};
2843
2844