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25#define DRV_VERSION "1.39"
26static const char *version = "tc35815.c:v" DRV_VERSION "\n";
27#define MODNAME "tc35815"
28
29#include <linux/module.h>
30#include <linux/kernel.h>
31#include <linux/types.h>
32#include <linux/fcntl.h>
33#include <linux/interrupt.h>
34#include <linux/ioport.h>
35#include <linux/in.h>
36#include <linux/if_vlan.h>
37#include <linux/slab.h>
38#include <linux/string.h>
39#include <linux/spinlock.h>
40#include <linux/errno.h>
41#include <linux/init.h>
42#include <linux/netdevice.h>
43#include <linux/etherdevice.h>
44#include <linux/skbuff.h>
45#include <linux/delay.h>
46#include <linux/pci.h>
47#include <linux/phy.h>
48#include <linux/workqueue.h>
49#include <linux/platform_device.h>
50#include <linux/prefetch.h>
51#include <asm/io.h>
52#include <asm/byteorder.h>
53
54enum tc35815_chiptype {
55 TC35815CF = 0,
56 TC35815_NWU,
57 TC35815_TX4939,
58};
59
60
61static const struct {
62 const char *name;
63} chip_info[] = {
64 { "TOSHIBA TC35815CF 10/100BaseTX" },
65 { "TOSHIBA TC35815 with Wake on LAN" },
66 { "TOSHIBA TC35815/TX4939" },
67};
68
69static DEFINE_PCI_DEVICE_TABLE(tc35815_pci_tbl) = {
70 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815CF), .driver_data = TC35815CF },
71 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_NWU), .driver_data = TC35815_NWU },
72 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939), .driver_data = TC35815_TX4939 },
73 {0,}
74};
75MODULE_DEVICE_TABLE(pci, tc35815_pci_tbl);
76
77
78static struct tc35815_options {
79 int speed;
80 int duplex;
81} options;
82
83
84
85
86struct tc35815_regs {
87 __u32 DMA_Ctl;
88 __u32 TxFrmPtr;
89 __u32 TxThrsh;
90 __u32 TxPollCtr;
91 __u32 BLFrmPtr;
92 __u32 RxFragSize;
93 __u32 Int_En;
94 __u32 FDA_Bas;
95 __u32 FDA_Lim;
96 __u32 Int_Src;
97 __u32 unused0[2];
98 __u32 PauseCnt;
99 __u32 RemPauCnt;
100 __u32 TxCtlFrmStat;
101 __u32 unused1;
102 __u32 MAC_Ctl;
103 __u32 CAM_Ctl;
104 __u32 Tx_Ctl;
105 __u32 Tx_Stat;
106 __u32 Rx_Ctl;
107 __u32 Rx_Stat;
108 __u32 MD_Data;
109 __u32 MD_CA;
110 __u32 CAM_Adr;
111 __u32 CAM_Data;
112 __u32 CAM_Ena;
113 __u32 PROM_Ctl;
114 __u32 PROM_Data;
115 __u32 Algn_Cnt;
116 __u32 CRC_Cnt;
117 __u32 Miss_Cnt;
118};
119
120
121
122
123
124#define DMA_RxAlign 0x00c00000
125#define DMA_RxAlign_1 0x00400000
126#define DMA_RxAlign_2 0x00800000
127#define DMA_RxAlign_3 0x00c00000
128#define DMA_M66EnStat 0x00080000
129#define DMA_IntMask 0x00040000
130#define DMA_SWIntReq 0x00020000
131#define DMA_TxWakeUp 0x00010000
132#define DMA_RxBigE 0x00008000
133#define DMA_TxBigE 0x00004000
134#define DMA_TestMode 0x00002000
135#define DMA_PowrMgmnt 0x00001000
136#define DMA_DmBurst_Mask 0x000001fc
137
138
139#define RxFrag_EnPack 0x00008000
140#define RxFrag_MinFragMask 0x00000ffc
141
142
143#define MAC_Link10 0x00008000
144#define MAC_EnMissRoll 0x00002000
145#define MAC_MissRoll 0x00000400
146#define MAC_Loop10 0x00000080
147#define MAC_Conn_Auto 0x00000000
148#define MAC_Conn_10M 0x00000020
149#define MAC_Conn_Mll 0x00000040
150#define MAC_MacLoop 0x00000010
151#define MAC_FullDup 0x00000008
152#define MAC_Reset 0x00000004
153#define MAC_HaltImm 0x00000002
154#define MAC_HaltReq 0x00000001
155
156
157#define PROM_Busy 0x00008000
158#define PROM_Read 0x00004000
159#define PROM_Write 0x00002000
160#define PROM_Erase 0x00006000
161
162
163#define PROM_Addr_Ena 0x00000030
164
165
166
167#define CAM_CompEn 0x00000010
168#define CAM_NegCAM 0x00000008
169
170#define CAM_BroadAcc 0x00000004
171#define CAM_GroupAcc 0x00000002
172#define CAM_StationAcc 0x00000001
173
174
175#define CAM_ENTRY_MAX 21
176#define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1)
177#define CAM_Ena_Bit(index) (1 << (index))
178#define CAM_ENTRY_DESTINATION 0
179#define CAM_ENTRY_SOURCE 1
180#define CAM_ENTRY_MACCTL 20
181
182
183#define Tx_En 0x00000001
184#define Tx_TxHalt 0x00000002
185#define Tx_NoPad 0x00000004
186#define Tx_NoCRC 0x00000008
187#define Tx_FBack 0x00000010
188#define Tx_EnUnder 0x00000100
189#define Tx_EnExDefer 0x00000200
190#define Tx_EnLCarr 0x00000400
191#define Tx_EnExColl 0x00000800
192#define Tx_EnLateColl 0x00001000
193#define Tx_EnTxPar 0x00002000
194#define Tx_EnComp 0x00004000
195
196
197#define Tx_TxColl_MASK 0x0000000F
198#define Tx_ExColl 0x00000010
199#define Tx_TXDefer 0x00000020
200#define Tx_Paused 0x00000040
201#define Tx_IntTx 0x00000080
202#define Tx_Under 0x00000100
203#define Tx_Defer 0x00000200
204#define Tx_NCarr 0x00000400
205#define Tx_10Stat 0x00000800
206#define Tx_LateColl 0x00001000
207#define Tx_TxPar 0x00002000
208#define Tx_Comp 0x00004000
209#define Tx_Halted 0x00008000
210#define Tx_SQErr 0x00010000
211
212
213#define Rx_EnGood 0x00004000
214#define Rx_EnRxPar 0x00002000
215#define Rx_EnLongErr 0x00000800
216#define Rx_EnOver 0x00000400
217#define Rx_EnCRCErr 0x00000200
218#define Rx_EnAlign 0x00000100
219#define Rx_IgnoreCRC 0x00000040
220#define Rx_StripCRC 0x00000010
221#define Rx_ShortEn 0x00000008
222#define Rx_LongEn 0x00000004
223#define Rx_RxHalt 0x00000002
224#define Rx_RxEn 0x00000001
225
226
227#define Rx_Halted 0x00008000
228#define Rx_Good 0x00004000
229#define Rx_RxPar 0x00002000
230#define Rx_TypePkt 0x00001000
231#define Rx_LongErr 0x00000800
232#define Rx_Over 0x00000400
233#define Rx_CRCErr 0x00000200
234#define Rx_Align 0x00000100
235#define Rx_10Stat 0x00000080
236#define Rx_IntRx 0x00000040
237#define Rx_CtlRecd 0x00000020
238#define Rx_InLenErr 0x00000010
239
240#define Rx_Stat_Mask 0x0000FFF0
241
242
243#define Int_NRAbtEn 0x00000800
244#define Int_TxCtlCmpEn 0x00000400
245#define Int_DmParErrEn 0x00000200
246#define Int_DParDEn 0x00000100
247#define Int_EarNotEn 0x00000080
248#define Int_DParErrEn 0x00000040
249#define Int_SSysErrEn 0x00000020
250#define Int_RMasAbtEn 0x00000010
251#define Int_RTargAbtEn 0x00000008
252#define Int_STargAbtEn 0x00000004
253#define Int_BLExEn 0x00000002
254#define Int_FDAExEn 0x00000001
255
256
257
258#define Int_NRabt 0x00004000
259#define Int_DmParErrStat 0x00002000
260#define Int_BLEx 0x00001000
261#define Int_FDAEx 0x00000800
262#define Int_IntNRAbt 0x00000400
263#define Int_IntCmp 0x00000200
264#define Int_IntExBD 0x00000100
265#define Int_DmParErr 0x00000080
266#define Int_IntEarNot 0x00000040
267#define Int_SWInt 0x00000020
268#define Int_IntBLEx 0x00000010
269#define Int_IntFDAEx 0x00000008
270#define Int_IntPCI 0x00000004
271#define Int_IntMacRx 0x00000002
272#define Int_IntMacTx 0x00000001
273
274
275#define MD_CA_PreSup 0x00001000
276#define MD_CA_Busy 0x00000800
277#define MD_CA_Wr 0x00000400
278
279
280
281
282
283
284
285struct FDesc {
286 volatile __u32 FDNext;
287 volatile __u32 FDSystem;
288 volatile __u32 FDStat;
289 volatile __u32 FDCtl;
290};
291
292
293struct BDesc {
294 volatile __u32 BuffData;
295 volatile __u32 BDCtl;
296};
297
298#define FD_ALIGN 16
299
300
301#define FD_FDLength_MASK 0x0000FFFF
302#define FD_BDCnt_MASK 0x001F0000
303#define FD_FrmOpt_MASK 0x7C000000
304#define FD_FrmOpt_BigEndian 0x40000000
305#define FD_FrmOpt_IntTx 0x20000000
306#define FD_FrmOpt_NoCRC 0x10000000
307#define FD_FrmOpt_NoPadding 0x08000000
308#define FD_FrmOpt_Packing 0x04000000
309#define FD_CownsFD 0x80000000
310#define FD_Next_EOL 0x00000001
311#define FD_BDCnt_SHIFT 16
312
313
314#define BD_BuffLength_MASK 0x0000FFFF
315#define BD_RxBDID_MASK 0x00FF0000
316#define BD_RxBDSeqN_MASK 0x7F000000
317#define BD_CownsBD 0x80000000
318#define BD_RxBDID_SHIFT 16
319#define BD_RxBDSeqN_SHIFT 24
320
321
322
323
324#define TX_CTL_CMD (Tx_EnTxPar | Tx_EnLateColl | \
325 Tx_EnExColl | Tx_EnLCarr | Tx_EnExDefer | Tx_EnUnder | \
326 Tx_En)
327
328#define RX_CTL_CMD (Rx_EnGood | Rx_EnRxPar | Rx_EnLongErr | Rx_EnOver \
329 | Rx_EnCRCErr | Rx_EnAlign | Rx_RxEn)
330#define INT_EN_CMD (Int_NRAbtEn | \
331 Int_DmParErrEn | Int_DParDEn | Int_DParErrEn | \
332 Int_SSysErrEn | Int_RMasAbtEn | Int_RTargAbtEn | \
333 Int_STargAbtEn | \
334 Int_BLExEn | Int_FDAExEn)
335#define DMA_CTL_CMD DMA_BURST_SIZE
336#define HAVE_DMA_RXALIGN(lp) likely((lp)->chiptype != TC35815CF)
337
338
339#define DMA_BURST_SIZE 32
340#define TX_THRESHOLD 1024
341
342#define TX_THRESHOLD_MAX 1536
343
344#define TX_THRESHOLD_KEEP_LIMIT 10
345
346
347#define FD_PAGE_NUM 4
348#define RX_BUF_NUM 128
349#define RX_FD_NUM 256
350#define TX_FD_NUM 128
351#if RX_CTL_CMD & Rx_LongEn
352#define RX_BUF_SIZE PAGE_SIZE
353#elif RX_CTL_CMD & Rx_StripCRC
354#define RX_BUF_SIZE \
355 L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + NET_IP_ALIGN)
356#else
357#define RX_BUF_SIZE \
358 L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN + NET_IP_ALIGN)
359#endif
360#define RX_FD_RESERVE (2 / 2)
361#define NAPI_WEIGHT 16
362
363struct TxFD {
364 struct FDesc fd;
365 struct BDesc bd;
366 struct BDesc unused;
367};
368
369struct RxFD {
370 struct FDesc fd;
371 struct BDesc bd[0];
372};
373
374struct FrFD {
375 struct FDesc fd;
376 struct BDesc bd[RX_BUF_NUM];
377};
378
379
380#define tc_readl(addr) ioread32(addr)
381#define tc_writel(d, addr) iowrite32(d, addr)
382
383#define TC35815_TX_TIMEOUT msecs_to_jiffies(400)
384
385
386struct tc35815_local {
387 struct pci_dev *pci_dev;
388
389 struct net_device *dev;
390 struct napi_struct napi;
391
392
393 struct {
394 int max_tx_qlen;
395 int tx_ints;
396 int rx_ints;
397 int tx_underrun;
398 } lstats;
399
400
401
402
403
404
405 spinlock_t lock;
406 spinlock_t rx_lock;
407
408 struct mii_bus *mii_bus;
409 struct phy_device *phy_dev;
410 int duplex;
411 int speed;
412 int link;
413 struct work_struct restart_work;
414
415
416
417
418
419
420
421
422
423 void *fd_buf;
424 dma_addr_t fd_buf_dma;
425 struct TxFD *tfd_base;
426 unsigned int tfd_start;
427 unsigned int tfd_end;
428 struct RxFD *rfd_base;
429 struct RxFD *rfd_limit;
430 struct RxFD *rfd_cur;
431 struct FrFD *fbl_ptr;
432 unsigned int fbl_count;
433 struct {
434 struct sk_buff *skb;
435 dma_addr_t skb_dma;
436 } tx_skbs[TX_FD_NUM], rx_skbs[RX_BUF_NUM];
437 u32 msg_enable;
438 enum tc35815_chiptype chiptype;
439};
440
441static inline dma_addr_t fd_virt_to_bus(struct tc35815_local *lp, void *virt)
442{
443 return lp->fd_buf_dma + ((u8 *)virt - (u8 *)lp->fd_buf);
444}
445#ifdef DEBUG
446static inline void *fd_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus)
447{
448 return (void *)((u8 *)lp->fd_buf + (bus - lp->fd_buf_dma));
449}
450#endif
451static struct sk_buff *alloc_rxbuf_skb(struct net_device *dev,
452 struct pci_dev *hwdev,
453 dma_addr_t *dma_handle)
454{
455 struct sk_buff *skb;
456 skb = netdev_alloc_skb(dev, RX_BUF_SIZE);
457 if (!skb)
458 return NULL;
459 *dma_handle = pci_map_single(hwdev, skb->data, RX_BUF_SIZE,
460 PCI_DMA_FROMDEVICE);
461 if (pci_dma_mapping_error(hwdev, *dma_handle)) {
462 dev_kfree_skb_any(skb);
463 return NULL;
464 }
465 skb_reserve(skb, 2);
466 return skb;
467}
468
469static void free_rxbuf_skb(struct pci_dev *hwdev, struct sk_buff *skb, dma_addr_t dma_handle)
470{
471 pci_unmap_single(hwdev, dma_handle, RX_BUF_SIZE,
472 PCI_DMA_FROMDEVICE);
473 dev_kfree_skb_any(skb);
474}
475
476
477
478static int tc35815_open(struct net_device *dev);
479static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev);
480static irqreturn_t tc35815_interrupt(int irq, void *dev_id);
481static int tc35815_rx(struct net_device *dev, int limit);
482static int tc35815_poll(struct napi_struct *napi, int budget);
483static void tc35815_txdone(struct net_device *dev);
484static int tc35815_close(struct net_device *dev);
485static struct net_device_stats *tc35815_get_stats(struct net_device *dev);
486static void tc35815_set_multicast_list(struct net_device *dev);
487static void tc35815_tx_timeout(struct net_device *dev);
488static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
489#ifdef CONFIG_NET_POLL_CONTROLLER
490static void tc35815_poll_controller(struct net_device *dev);
491#endif
492static const struct ethtool_ops tc35815_ethtool_ops;
493
494
495static void tc35815_chip_reset(struct net_device *dev);
496static void tc35815_chip_init(struct net_device *dev);
497
498#ifdef DEBUG
499static void panic_queues(struct net_device *dev);
500#endif
501
502static void tc35815_restart_work(struct work_struct *work);
503
504static int tc_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
505{
506 struct net_device *dev = bus->priv;
507 struct tc35815_regs __iomem *tr =
508 (struct tc35815_regs __iomem *)dev->base_addr;
509 unsigned long timeout = jiffies + HZ;
510
511 tc_writel(MD_CA_Busy | (mii_id << 5) | (regnum & 0x1f), &tr->MD_CA);
512 udelay(12);
513 while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
514 if (time_after(jiffies, timeout))
515 return -EIO;
516 cpu_relax();
517 }
518 return tc_readl(&tr->MD_Data) & 0xffff;
519}
520
521static int tc_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 val)
522{
523 struct net_device *dev = bus->priv;
524 struct tc35815_regs __iomem *tr =
525 (struct tc35815_regs __iomem *)dev->base_addr;
526 unsigned long timeout = jiffies + HZ;
527
528 tc_writel(val, &tr->MD_Data);
529 tc_writel(MD_CA_Busy | MD_CA_Wr | (mii_id << 5) | (regnum & 0x1f),
530 &tr->MD_CA);
531 udelay(12);
532 while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
533 if (time_after(jiffies, timeout))
534 return -EIO;
535 cpu_relax();
536 }
537 return 0;
538}
539
540static void tc_handle_link_change(struct net_device *dev)
541{
542 struct tc35815_local *lp = netdev_priv(dev);
543 struct phy_device *phydev = lp->phy_dev;
544 unsigned long flags;
545 int status_change = 0;
546
547 spin_lock_irqsave(&lp->lock, flags);
548 if (phydev->link &&
549 (lp->speed != phydev->speed || lp->duplex != phydev->duplex)) {
550 struct tc35815_regs __iomem *tr =
551 (struct tc35815_regs __iomem *)dev->base_addr;
552 u32 reg;
553
554 reg = tc_readl(&tr->MAC_Ctl);
555 reg |= MAC_HaltReq;
556 tc_writel(reg, &tr->MAC_Ctl);
557 if (phydev->duplex == DUPLEX_FULL)
558 reg |= MAC_FullDup;
559 else
560 reg &= ~MAC_FullDup;
561 tc_writel(reg, &tr->MAC_Ctl);
562 reg &= ~MAC_HaltReq;
563 tc_writel(reg, &tr->MAC_Ctl);
564
565
566
567
568
569
570
571
572
573
574 if (phydev->duplex == DUPLEX_HALF &&
575 lp->chiptype != TC35815_TX4939)
576 tc_writel(tc_readl(&tr->Tx_Ctl) | Tx_EnLCarr,
577 &tr->Tx_Ctl);
578
579 lp->speed = phydev->speed;
580 lp->duplex = phydev->duplex;
581 status_change = 1;
582 }
583
584 if (phydev->link != lp->link) {
585 if (phydev->link) {
586
587 if (dev->flags & IFF_PROMISC)
588 tc35815_set_multicast_list(dev);
589 } else {
590 lp->speed = 0;
591 lp->duplex = -1;
592 }
593 lp->link = phydev->link;
594
595 status_change = 1;
596 }
597 spin_unlock_irqrestore(&lp->lock, flags);
598
599 if (status_change && netif_msg_link(lp)) {
600 phy_print_status(phydev);
601 pr_debug("%s: MII BMCR %04x BMSR %04x LPA %04x\n",
602 dev->name,
603 phy_read(phydev, MII_BMCR),
604 phy_read(phydev, MII_BMSR),
605 phy_read(phydev, MII_LPA));
606 }
607}
608
609static int tc_mii_probe(struct net_device *dev)
610{
611 struct tc35815_local *lp = netdev_priv(dev);
612 struct phy_device *phydev = NULL;
613 int phy_addr;
614 u32 dropmask;
615
616
617 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
618 if (lp->mii_bus->phy_map[phy_addr]) {
619 if (phydev) {
620 printk(KERN_ERR "%s: multiple PHYs found\n",
621 dev->name);
622 return -EINVAL;
623 }
624 phydev = lp->mii_bus->phy_map[phy_addr];
625 break;
626 }
627 }
628
629 if (!phydev) {
630 printk(KERN_ERR "%s: no PHY found\n", dev->name);
631 return -ENODEV;
632 }
633
634
635 phydev = phy_connect(dev, dev_name(&phydev->dev),
636 &tc_handle_link_change,
637 lp->chiptype == TC35815_TX4939 ? PHY_INTERFACE_MODE_RMII : PHY_INTERFACE_MODE_MII);
638 if (IS_ERR(phydev)) {
639 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
640 return PTR_ERR(phydev);
641 }
642 printk(KERN_INFO "%s: attached PHY driver [%s] "
643 "(mii_bus:phy_addr=%s, id=%x)\n",
644 dev->name, phydev->drv->name, dev_name(&phydev->dev),
645 phydev->phy_id);
646
647
648 phydev->supported &= PHY_BASIC_FEATURES;
649 dropmask = 0;
650 if (options.speed == 10)
651 dropmask |= SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full;
652 else if (options.speed == 100)
653 dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full;
654 if (options.duplex == 1)
655 dropmask |= SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Full;
656 else if (options.duplex == 2)
657 dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_100baseT_Half;
658 phydev->supported &= ~dropmask;
659 phydev->advertising = phydev->supported;
660
661 lp->link = 0;
662 lp->speed = 0;
663 lp->duplex = -1;
664 lp->phy_dev = phydev;
665
666 return 0;
667}
668
669static int tc_mii_init(struct net_device *dev)
670{
671 struct tc35815_local *lp = netdev_priv(dev);
672 int err;
673 int i;
674
675 lp->mii_bus = mdiobus_alloc();
676 if (lp->mii_bus == NULL) {
677 err = -ENOMEM;
678 goto err_out;
679 }
680
681 lp->mii_bus->name = "tc35815_mii_bus";
682 lp->mii_bus->read = tc_mdio_read;
683 lp->mii_bus->write = tc_mdio_write;
684 snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%x",
685 (lp->pci_dev->bus->number << 8) | lp->pci_dev->devfn);
686 lp->mii_bus->priv = dev;
687 lp->mii_bus->parent = &lp->pci_dev->dev;
688 lp->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
689 if (!lp->mii_bus->irq) {
690 err = -ENOMEM;
691 goto err_out_free_mii_bus;
692 }
693
694 for (i = 0; i < PHY_MAX_ADDR; i++)
695 lp->mii_bus->irq[i] = PHY_POLL;
696
697 err = mdiobus_register(lp->mii_bus);
698 if (err)
699 goto err_out_free_mdio_irq;
700 err = tc_mii_probe(dev);
701 if (err)
702 goto err_out_unregister_bus;
703 return 0;
704
705err_out_unregister_bus:
706 mdiobus_unregister(lp->mii_bus);
707err_out_free_mdio_irq:
708 kfree(lp->mii_bus->irq);
709err_out_free_mii_bus:
710 mdiobus_free(lp->mii_bus);
711err_out:
712 return err;
713}
714
715#ifdef CONFIG_CPU_TX49XX
716
717
718
719
720
721static int tc35815_mac_match(struct device *dev, void *data)
722{
723 struct platform_device *plat_dev = to_platform_device(dev);
724 struct pci_dev *pci_dev = data;
725 unsigned int id = pci_dev->irq;
726 return !strcmp(plat_dev->name, "tc35815-mac") && plat_dev->id == id;
727}
728
729static int tc35815_read_plat_dev_addr(struct net_device *dev)
730{
731 struct tc35815_local *lp = netdev_priv(dev);
732 struct device *pd = bus_find_device(&platform_bus_type, NULL,
733 lp->pci_dev, tc35815_mac_match);
734 if (pd) {
735 if (pd->platform_data)
736 memcpy(dev->dev_addr, pd->platform_data, ETH_ALEN);
737 put_device(pd);
738 return is_valid_ether_addr(dev->dev_addr) ? 0 : -ENODEV;
739 }
740 return -ENODEV;
741}
742#else
743static int tc35815_read_plat_dev_addr(struct net_device *dev)
744{
745 return -ENODEV;
746}
747#endif
748
749static int tc35815_init_dev_addr(struct net_device *dev)
750{
751 struct tc35815_regs __iomem *tr =
752 (struct tc35815_regs __iomem *)dev->base_addr;
753 int i;
754
755 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
756 ;
757 for (i = 0; i < 6; i += 2) {
758 unsigned short data;
759 tc_writel(PROM_Busy | PROM_Read | (i / 2 + 2), &tr->PROM_Ctl);
760 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
761 ;
762 data = tc_readl(&tr->PROM_Data);
763 dev->dev_addr[i] = data & 0xff;
764 dev->dev_addr[i+1] = data >> 8;
765 }
766 if (!is_valid_ether_addr(dev->dev_addr))
767 return tc35815_read_plat_dev_addr(dev);
768 return 0;
769}
770
771static const struct net_device_ops tc35815_netdev_ops = {
772 .ndo_open = tc35815_open,
773 .ndo_stop = tc35815_close,
774 .ndo_start_xmit = tc35815_send_packet,
775 .ndo_get_stats = tc35815_get_stats,
776 .ndo_set_rx_mode = tc35815_set_multicast_list,
777 .ndo_tx_timeout = tc35815_tx_timeout,
778 .ndo_do_ioctl = tc35815_ioctl,
779 .ndo_validate_addr = eth_validate_addr,
780 .ndo_change_mtu = eth_change_mtu,
781 .ndo_set_mac_address = eth_mac_addr,
782#ifdef CONFIG_NET_POLL_CONTROLLER
783 .ndo_poll_controller = tc35815_poll_controller,
784#endif
785};
786
787static int tc35815_init_one(struct pci_dev *pdev,
788 const struct pci_device_id *ent)
789{
790 void __iomem *ioaddr = NULL;
791 struct net_device *dev;
792 struct tc35815_local *lp;
793 int rc;
794
795 static int printed_version;
796 if (!printed_version++) {
797 printk(version);
798 dev_printk(KERN_DEBUG, &pdev->dev,
799 "speed:%d duplex:%d\n",
800 options.speed, options.duplex);
801 }
802
803 if (!pdev->irq) {
804 dev_warn(&pdev->dev, "no IRQ assigned.\n");
805 return -ENODEV;
806 }
807
808
809 dev = alloc_etherdev(sizeof(*lp));
810 if (dev == NULL)
811 return -ENOMEM;
812
813 SET_NETDEV_DEV(dev, &pdev->dev);
814 lp = netdev_priv(dev);
815 lp->dev = dev;
816
817
818 rc = pcim_enable_device(pdev);
819 if (rc)
820 goto err_out;
821 rc = pcim_iomap_regions(pdev, 1 << 1, MODNAME);
822 if (rc)
823 goto err_out;
824 pci_set_master(pdev);
825 ioaddr = pcim_iomap_table(pdev)[1];
826
827
828 dev->netdev_ops = &tc35815_netdev_ops;
829 dev->ethtool_ops = &tc35815_ethtool_ops;
830 dev->watchdog_timeo = TC35815_TX_TIMEOUT;
831 netif_napi_add(dev, &lp->napi, tc35815_poll, NAPI_WEIGHT);
832
833 dev->irq = pdev->irq;
834 dev->base_addr = (unsigned long)ioaddr;
835
836 INIT_WORK(&lp->restart_work, tc35815_restart_work);
837 spin_lock_init(&lp->lock);
838 spin_lock_init(&lp->rx_lock);
839 lp->pci_dev = pdev;
840 lp->chiptype = ent->driver_data;
841
842 lp->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK;
843 pci_set_drvdata(pdev, dev);
844
845
846 tc35815_chip_reset(dev);
847
848
849 if (tc35815_init_dev_addr(dev)) {
850 dev_warn(&pdev->dev, "not valid ether addr\n");
851 eth_hw_addr_random(dev);
852 }
853
854 rc = register_netdev(dev);
855 if (rc)
856 goto err_out;
857
858 printk(KERN_INFO "%s: %s at 0x%lx, %pM, IRQ %d\n",
859 dev->name,
860 chip_info[ent->driver_data].name,
861 dev->base_addr,
862 dev->dev_addr,
863 dev->irq);
864
865 rc = tc_mii_init(dev);
866 if (rc)
867 goto err_out_unregister;
868
869 return 0;
870
871err_out_unregister:
872 unregister_netdev(dev);
873err_out:
874 free_netdev(dev);
875 return rc;
876}
877
878
879static void tc35815_remove_one(struct pci_dev *pdev)
880{
881 struct net_device *dev = pci_get_drvdata(pdev);
882 struct tc35815_local *lp = netdev_priv(dev);
883
884 phy_disconnect(lp->phy_dev);
885 mdiobus_unregister(lp->mii_bus);
886 kfree(lp->mii_bus->irq);
887 mdiobus_free(lp->mii_bus);
888 unregister_netdev(dev);
889 free_netdev(dev);
890 pci_set_drvdata(pdev, NULL);
891}
892
893static int
894tc35815_init_queues(struct net_device *dev)
895{
896 struct tc35815_local *lp = netdev_priv(dev);
897 int i;
898 unsigned long fd_addr;
899
900 if (!lp->fd_buf) {
901 BUG_ON(sizeof(struct FDesc) +
902 sizeof(struct BDesc) * RX_BUF_NUM +
903 sizeof(struct FDesc) * RX_FD_NUM +
904 sizeof(struct TxFD) * TX_FD_NUM >
905 PAGE_SIZE * FD_PAGE_NUM);
906
907 lp->fd_buf = pci_alloc_consistent(lp->pci_dev,
908 PAGE_SIZE * FD_PAGE_NUM,
909 &lp->fd_buf_dma);
910 if (!lp->fd_buf)
911 return -ENOMEM;
912 for (i = 0; i < RX_BUF_NUM; i++) {
913 lp->rx_skbs[i].skb =
914 alloc_rxbuf_skb(dev, lp->pci_dev,
915 &lp->rx_skbs[i].skb_dma);
916 if (!lp->rx_skbs[i].skb) {
917 while (--i >= 0) {
918 free_rxbuf_skb(lp->pci_dev,
919 lp->rx_skbs[i].skb,
920 lp->rx_skbs[i].skb_dma);
921 lp->rx_skbs[i].skb = NULL;
922 }
923 pci_free_consistent(lp->pci_dev,
924 PAGE_SIZE * FD_PAGE_NUM,
925 lp->fd_buf,
926 lp->fd_buf_dma);
927 lp->fd_buf = NULL;
928 return -ENOMEM;
929 }
930 }
931 printk(KERN_DEBUG "%s: FD buf %p DataBuf",
932 dev->name, lp->fd_buf);
933 printk("\n");
934 } else {
935 for (i = 0; i < FD_PAGE_NUM; i++)
936 clear_page((void *)((unsigned long)lp->fd_buf +
937 i * PAGE_SIZE));
938 }
939 fd_addr = (unsigned long)lp->fd_buf;
940
941
942 lp->rfd_base = (struct RxFD *)fd_addr;
943 fd_addr += sizeof(struct RxFD) * RX_FD_NUM;
944 for (i = 0; i < RX_FD_NUM; i++)
945 lp->rfd_base[i].fd.FDCtl = cpu_to_le32(FD_CownsFD);
946 lp->rfd_cur = lp->rfd_base;
947 lp->rfd_limit = (struct RxFD *)fd_addr - (RX_FD_RESERVE + 1);
948
949
950 lp->tfd_base = (struct TxFD *)fd_addr;
951 fd_addr += sizeof(struct TxFD) * TX_FD_NUM;
952 for (i = 0; i < TX_FD_NUM; i++) {
953 lp->tfd_base[i].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[i+1]));
954 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
955 lp->tfd_base[i].fd.FDCtl = cpu_to_le32(0);
956 }
957 lp->tfd_base[TX_FD_NUM-1].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[0]));
958 lp->tfd_start = 0;
959 lp->tfd_end = 0;
960
961
962 lp->fbl_ptr = (struct FrFD *)fd_addr;
963 lp->fbl_ptr->fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, lp->fbl_ptr));
964 lp->fbl_ptr->fd.FDCtl = cpu_to_le32(RX_BUF_NUM | FD_CownsFD);
965
966
967
968
969
970 lp->fbl_count = 0;
971 for (i = 0; i < RX_BUF_NUM; i++) {
972 if (lp->rx_skbs[i].skb) {
973 if (i != lp->fbl_count) {
974 lp->rx_skbs[lp->fbl_count].skb =
975 lp->rx_skbs[i].skb;
976 lp->rx_skbs[lp->fbl_count].skb_dma =
977 lp->rx_skbs[i].skb_dma;
978 }
979 lp->fbl_count++;
980 }
981 }
982 for (i = 0; i < RX_BUF_NUM; i++) {
983 if (i >= lp->fbl_count) {
984 lp->fbl_ptr->bd[i].BuffData = 0;
985 lp->fbl_ptr->bd[i].BDCtl = 0;
986 continue;
987 }
988 lp->fbl_ptr->bd[i].BuffData =
989 cpu_to_le32(lp->rx_skbs[i].skb_dma);
990
991 lp->fbl_ptr->bd[i].BDCtl =
992 cpu_to_le32(BD_CownsBD | (i << BD_RxBDID_SHIFT) |
993 RX_BUF_SIZE);
994 }
995
996 printk(KERN_DEBUG "%s: TxFD %p RxFD %p FrFD %p\n",
997 dev->name, lp->tfd_base, lp->rfd_base, lp->fbl_ptr);
998 return 0;
999}
1000
1001static void
1002tc35815_clear_queues(struct net_device *dev)
1003{
1004 struct tc35815_local *lp = netdev_priv(dev);
1005 int i;
1006
1007 for (i = 0; i < TX_FD_NUM; i++) {
1008 u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
1009 struct sk_buff *skb =
1010 fdsystem != 0xffffffff ?
1011 lp->tx_skbs[fdsystem].skb : NULL;
1012#ifdef DEBUG
1013 if (lp->tx_skbs[i].skb != skb) {
1014 printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
1015 panic_queues(dev);
1016 }
1017#else
1018 BUG_ON(lp->tx_skbs[i].skb != skb);
1019#endif
1020 if (skb) {
1021 pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
1022 lp->tx_skbs[i].skb = NULL;
1023 lp->tx_skbs[i].skb_dma = 0;
1024 dev_kfree_skb_any(skb);
1025 }
1026 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1027 }
1028
1029 tc35815_init_queues(dev);
1030}
1031
1032static void
1033tc35815_free_queues(struct net_device *dev)
1034{
1035 struct tc35815_local *lp = netdev_priv(dev);
1036 int i;
1037
1038 if (lp->tfd_base) {
1039 for (i = 0; i < TX_FD_NUM; i++) {
1040 u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
1041 struct sk_buff *skb =
1042 fdsystem != 0xffffffff ?
1043 lp->tx_skbs[fdsystem].skb : NULL;
1044#ifdef DEBUG
1045 if (lp->tx_skbs[i].skb != skb) {
1046 printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
1047 panic_queues(dev);
1048 }
1049#else
1050 BUG_ON(lp->tx_skbs[i].skb != skb);
1051#endif
1052 if (skb) {
1053 dev_kfree_skb(skb);
1054 pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
1055 lp->tx_skbs[i].skb = NULL;
1056 lp->tx_skbs[i].skb_dma = 0;
1057 }
1058 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1059 }
1060 }
1061
1062 lp->rfd_base = NULL;
1063 lp->rfd_limit = NULL;
1064 lp->rfd_cur = NULL;
1065 lp->fbl_ptr = NULL;
1066
1067 for (i = 0; i < RX_BUF_NUM; i++) {
1068 if (lp->rx_skbs[i].skb) {
1069 free_rxbuf_skb(lp->pci_dev, lp->rx_skbs[i].skb,
1070 lp->rx_skbs[i].skb_dma);
1071 lp->rx_skbs[i].skb = NULL;
1072 }
1073 }
1074 if (lp->fd_buf) {
1075 pci_free_consistent(lp->pci_dev, PAGE_SIZE * FD_PAGE_NUM,
1076 lp->fd_buf, lp->fd_buf_dma);
1077 lp->fd_buf = NULL;
1078 }
1079}
1080
1081static void
1082dump_txfd(struct TxFD *fd)
1083{
1084 printk("TxFD(%p): %08x %08x %08x %08x\n", fd,
1085 le32_to_cpu(fd->fd.FDNext),
1086 le32_to_cpu(fd->fd.FDSystem),
1087 le32_to_cpu(fd->fd.FDStat),
1088 le32_to_cpu(fd->fd.FDCtl));
1089 printk("BD: ");
1090 printk(" %08x %08x",
1091 le32_to_cpu(fd->bd.BuffData),
1092 le32_to_cpu(fd->bd.BDCtl));
1093 printk("\n");
1094}
1095
1096static int
1097dump_rxfd(struct RxFD *fd)
1098{
1099 int i, bd_count = (le32_to_cpu(fd->fd.FDCtl) & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1100 if (bd_count > 8)
1101 bd_count = 8;
1102 printk("RxFD(%p): %08x %08x %08x %08x\n", fd,
1103 le32_to_cpu(fd->fd.FDNext),
1104 le32_to_cpu(fd->fd.FDSystem),
1105 le32_to_cpu(fd->fd.FDStat),
1106 le32_to_cpu(fd->fd.FDCtl));
1107 if (le32_to_cpu(fd->fd.FDCtl) & FD_CownsFD)
1108 return 0;
1109 printk("BD: ");
1110 for (i = 0; i < bd_count; i++)
1111 printk(" %08x %08x",
1112 le32_to_cpu(fd->bd[i].BuffData),
1113 le32_to_cpu(fd->bd[i].BDCtl));
1114 printk("\n");
1115 return bd_count;
1116}
1117
1118#ifdef DEBUG
1119static void
1120dump_frfd(struct FrFD *fd)
1121{
1122 int i;
1123 printk("FrFD(%p): %08x %08x %08x %08x\n", fd,
1124 le32_to_cpu(fd->fd.FDNext),
1125 le32_to_cpu(fd->fd.FDSystem),
1126 le32_to_cpu(fd->fd.FDStat),
1127 le32_to_cpu(fd->fd.FDCtl));
1128 printk("BD: ");
1129 for (i = 0; i < RX_BUF_NUM; i++)
1130 printk(" %08x %08x",
1131 le32_to_cpu(fd->bd[i].BuffData),
1132 le32_to_cpu(fd->bd[i].BDCtl));
1133 printk("\n");
1134}
1135
1136static void
1137panic_queues(struct net_device *dev)
1138{
1139 struct tc35815_local *lp = netdev_priv(dev);
1140 int i;
1141
1142 printk("TxFD base %p, start %u, end %u\n",
1143 lp->tfd_base, lp->tfd_start, lp->tfd_end);
1144 printk("RxFD base %p limit %p cur %p\n",
1145 lp->rfd_base, lp->rfd_limit, lp->rfd_cur);
1146 printk("FrFD %p\n", lp->fbl_ptr);
1147 for (i = 0; i < TX_FD_NUM; i++)
1148 dump_txfd(&lp->tfd_base[i]);
1149 for (i = 0; i < RX_FD_NUM; i++) {
1150 int bd_count = dump_rxfd(&lp->rfd_base[i]);
1151 i += (bd_count + 1) / 2;
1152 }
1153 dump_frfd(lp->fbl_ptr);
1154 panic("%s: Illegal queue state.", dev->name);
1155}
1156#endif
1157
1158static void print_eth(const u8 *add)
1159{
1160 printk(KERN_DEBUG "print_eth(%p)\n", add);
1161 printk(KERN_DEBUG " %pM => %pM : %02x%02x\n",
1162 add + 6, add, add[12], add[13]);
1163}
1164
1165static int tc35815_tx_full(struct net_device *dev)
1166{
1167 struct tc35815_local *lp = netdev_priv(dev);
1168 return (lp->tfd_start + 1) % TX_FD_NUM == lp->tfd_end;
1169}
1170
1171static void tc35815_restart(struct net_device *dev)
1172{
1173 struct tc35815_local *lp = netdev_priv(dev);
1174
1175 if (lp->phy_dev) {
1176 int timeout;
1177
1178 phy_write(lp->phy_dev, MII_BMCR, BMCR_RESET);
1179 timeout = 100;
1180 while (--timeout) {
1181 if (!(phy_read(lp->phy_dev, MII_BMCR) & BMCR_RESET))
1182 break;
1183 udelay(1);
1184 }
1185 if (!timeout)
1186 printk(KERN_ERR "%s: BMCR reset failed.\n", dev->name);
1187 }
1188
1189 spin_lock_bh(&lp->rx_lock);
1190 spin_lock_irq(&lp->lock);
1191 tc35815_chip_reset(dev);
1192 tc35815_clear_queues(dev);
1193 tc35815_chip_init(dev);
1194
1195 tc35815_set_multicast_list(dev);
1196 spin_unlock_irq(&lp->lock);
1197 spin_unlock_bh(&lp->rx_lock);
1198
1199 netif_wake_queue(dev);
1200}
1201
1202static void tc35815_restart_work(struct work_struct *work)
1203{
1204 struct tc35815_local *lp =
1205 container_of(work, struct tc35815_local, restart_work);
1206 struct net_device *dev = lp->dev;
1207
1208 tc35815_restart(dev);
1209}
1210
1211static void tc35815_schedule_restart(struct net_device *dev)
1212{
1213 struct tc35815_local *lp = netdev_priv(dev);
1214 struct tc35815_regs __iomem *tr =
1215 (struct tc35815_regs __iomem *)dev->base_addr;
1216 unsigned long flags;
1217
1218
1219 spin_lock_irqsave(&lp->lock, flags);
1220 tc_writel(0, &tr->Int_En);
1221 tc_writel(tc_readl(&tr->DMA_Ctl) | DMA_IntMask, &tr->DMA_Ctl);
1222 schedule_work(&lp->restart_work);
1223 spin_unlock_irqrestore(&lp->lock, flags);
1224}
1225
1226static void tc35815_tx_timeout(struct net_device *dev)
1227{
1228 struct tc35815_regs __iomem *tr =
1229 (struct tc35815_regs __iomem *)dev->base_addr;
1230
1231 printk(KERN_WARNING "%s: transmit timed out, status %#x\n",
1232 dev->name, tc_readl(&tr->Tx_Stat));
1233
1234
1235 tc35815_schedule_restart(dev);
1236 dev->stats.tx_errors++;
1237}
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247static int
1248tc35815_open(struct net_device *dev)
1249{
1250 struct tc35815_local *lp = netdev_priv(dev);
1251
1252
1253
1254
1255
1256 if (request_irq(dev->irq, tc35815_interrupt, IRQF_SHARED,
1257 dev->name, dev))
1258 return -EAGAIN;
1259
1260 tc35815_chip_reset(dev);
1261
1262 if (tc35815_init_queues(dev) != 0) {
1263 free_irq(dev->irq, dev);
1264 return -EAGAIN;
1265 }
1266
1267 napi_enable(&lp->napi);
1268
1269
1270 spin_lock_irq(&lp->lock);
1271 tc35815_chip_init(dev);
1272 spin_unlock_irq(&lp->lock);
1273
1274 netif_carrier_off(dev);
1275
1276 phy_start(lp->phy_dev);
1277
1278
1279
1280
1281 netif_start_queue(dev);
1282
1283 return 0;
1284}
1285
1286
1287
1288
1289
1290
1291static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev)
1292{
1293 struct tc35815_local *lp = netdev_priv(dev);
1294 struct TxFD *txfd;
1295 unsigned long flags;
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311 spin_lock_irqsave(&lp->lock, flags);
1312
1313
1314 if ((lp->tfd_start + TX_FD_NUM - lp->tfd_end) % TX_FD_NUM >
1315 TX_FD_NUM / 2)
1316 tc35815_txdone(dev);
1317
1318 if (netif_msg_pktdata(lp))
1319 print_eth(skb->data);
1320#ifdef DEBUG
1321 if (lp->tx_skbs[lp->tfd_start].skb) {
1322 printk("%s: tx_skbs conflict.\n", dev->name);
1323 panic_queues(dev);
1324 }
1325#else
1326 BUG_ON(lp->tx_skbs[lp->tfd_start].skb);
1327#endif
1328 lp->tx_skbs[lp->tfd_start].skb = skb;
1329 lp->tx_skbs[lp->tfd_start].skb_dma = pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1330
1331
1332 txfd = &lp->tfd_base[lp->tfd_start];
1333 txfd->bd.BuffData = cpu_to_le32(lp->tx_skbs[lp->tfd_start].skb_dma);
1334 txfd->bd.BDCtl = cpu_to_le32(skb->len);
1335 txfd->fd.FDSystem = cpu_to_le32(lp->tfd_start);
1336 txfd->fd.FDCtl = cpu_to_le32(FD_CownsFD | (1 << FD_BDCnt_SHIFT));
1337
1338 if (lp->tfd_start == lp->tfd_end) {
1339 struct tc35815_regs __iomem *tr =
1340 (struct tc35815_regs __iomem *)dev->base_addr;
1341
1342 txfd->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
1343 txfd->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
1344 if (netif_msg_tx_queued(lp)) {
1345 printk("%s: starting TxFD.\n", dev->name);
1346 dump_txfd(txfd);
1347 }
1348 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
1349 } else {
1350 txfd->fd.FDNext &= cpu_to_le32(~FD_Next_EOL);
1351 if (netif_msg_tx_queued(lp)) {
1352 printk("%s: queueing TxFD.\n", dev->name);
1353 dump_txfd(txfd);
1354 }
1355 }
1356 lp->tfd_start = (lp->tfd_start + 1) % TX_FD_NUM;
1357
1358
1359
1360
1361
1362 if (tc35815_tx_full(dev)) {
1363 if (netif_msg_tx_queued(lp))
1364 printk(KERN_WARNING "%s: TxFD Exhausted.\n", dev->name);
1365 netif_stop_queue(dev);
1366 }
1367
1368
1369
1370
1371
1372 spin_unlock_irqrestore(&lp->lock, flags);
1373 return NETDEV_TX_OK;
1374}
1375
1376#define FATAL_ERROR_INT \
1377 (Int_IntPCI | Int_DmParErr | Int_IntNRAbt)
1378static void tc35815_fatal_error_interrupt(struct net_device *dev, u32 status)
1379{
1380 static int count;
1381 printk(KERN_WARNING "%s: Fatal Error Intterrupt (%#x):",
1382 dev->name, status);
1383 if (status & Int_IntPCI)
1384 printk(" IntPCI");
1385 if (status & Int_DmParErr)
1386 printk(" DmParErr");
1387 if (status & Int_IntNRAbt)
1388 printk(" IntNRAbt");
1389 printk("\n");
1390 if (count++ > 100)
1391 panic("%s: Too many fatal errors.", dev->name);
1392 printk(KERN_WARNING "%s: Resetting ...\n", dev->name);
1393
1394 tc35815_schedule_restart(dev);
1395}
1396
1397static int tc35815_do_interrupt(struct net_device *dev, u32 status, int limit)
1398{
1399 struct tc35815_local *lp = netdev_priv(dev);
1400 int ret = -1;
1401
1402
1403 if (status & FATAL_ERROR_INT) {
1404 tc35815_fatal_error_interrupt(dev, status);
1405 return 0;
1406 }
1407
1408 if (status & Int_IntFDAEx) {
1409 if (netif_msg_rx_err(lp))
1410 dev_warn(&dev->dev,
1411 "Free Descriptor Area Exhausted (%#x).\n",
1412 status);
1413 dev->stats.rx_dropped++;
1414 ret = 0;
1415 }
1416 if (status & Int_IntBLEx) {
1417 if (netif_msg_rx_err(lp))
1418 dev_warn(&dev->dev,
1419 "Buffer List Exhausted (%#x).\n",
1420 status);
1421 dev->stats.rx_dropped++;
1422 ret = 0;
1423 }
1424 if (status & Int_IntExBD) {
1425 if (netif_msg_rx_err(lp))
1426 dev_warn(&dev->dev,
1427 "Excessive Buffer Descriptiors (%#x).\n",
1428 status);
1429 dev->stats.rx_length_errors++;
1430 ret = 0;
1431 }
1432
1433
1434 if (status & Int_IntMacRx) {
1435
1436 ret = tc35815_rx(dev, limit);
1437 lp->lstats.rx_ints++;
1438 }
1439 if (status & Int_IntMacTx) {
1440
1441 lp->lstats.tx_ints++;
1442 spin_lock_irq(&lp->lock);
1443 tc35815_txdone(dev);
1444 spin_unlock_irq(&lp->lock);
1445 if (ret < 0)
1446 ret = 0;
1447 }
1448 return ret;
1449}
1450
1451
1452
1453
1454
1455static irqreturn_t tc35815_interrupt(int irq, void *dev_id)
1456{
1457 struct net_device *dev = dev_id;
1458 struct tc35815_local *lp = netdev_priv(dev);
1459 struct tc35815_regs __iomem *tr =
1460 (struct tc35815_regs __iomem *)dev->base_addr;
1461 u32 dmactl = tc_readl(&tr->DMA_Ctl);
1462
1463 if (!(dmactl & DMA_IntMask)) {
1464
1465 tc_writel(dmactl | DMA_IntMask, &tr->DMA_Ctl);
1466 if (napi_schedule_prep(&lp->napi))
1467 __napi_schedule(&lp->napi);
1468 else {
1469 printk(KERN_ERR "%s: interrupt taken in poll\n",
1470 dev->name);
1471 BUG();
1472 }
1473 (void)tc_readl(&tr->Int_Src);
1474 return IRQ_HANDLED;
1475 }
1476 return IRQ_NONE;
1477}
1478
1479#ifdef CONFIG_NET_POLL_CONTROLLER
1480static void tc35815_poll_controller(struct net_device *dev)
1481{
1482 disable_irq(dev->irq);
1483 tc35815_interrupt(dev->irq, dev);
1484 enable_irq(dev->irq);
1485}
1486#endif
1487
1488
1489static int
1490tc35815_rx(struct net_device *dev, int limit)
1491{
1492 struct tc35815_local *lp = netdev_priv(dev);
1493 unsigned int fdctl;
1494 int i;
1495 int received = 0;
1496
1497 while (!((fdctl = le32_to_cpu(lp->rfd_cur->fd.FDCtl)) & FD_CownsFD)) {
1498 int status = le32_to_cpu(lp->rfd_cur->fd.FDStat);
1499 int pkt_len = fdctl & FD_FDLength_MASK;
1500 int bd_count = (fdctl & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1501#ifdef DEBUG
1502 struct RxFD *next_rfd;
1503#endif
1504#if (RX_CTL_CMD & Rx_StripCRC) == 0
1505 pkt_len -= ETH_FCS_LEN;
1506#endif
1507
1508 if (netif_msg_rx_status(lp))
1509 dump_rxfd(lp->rfd_cur);
1510 if (status & Rx_Good) {
1511 struct sk_buff *skb;
1512 unsigned char *data;
1513 int cur_bd;
1514
1515 if (--limit < 0)
1516 break;
1517 BUG_ON(bd_count > 1);
1518 cur_bd = (le32_to_cpu(lp->rfd_cur->bd[0].BDCtl)
1519 & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1520#ifdef DEBUG
1521 if (cur_bd >= RX_BUF_NUM) {
1522 printk("%s: invalid BDID.\n", dev->name);
1523 panic_queues(dev);
1524 }
1525 BUG_ON(lp->rx_skbs[cur_bd].skb_dma !=
1526 (le32_to_cpu(lp->rfd_cur->bd[0].BuffData) & ~3));
1527 if (!lp->rx_skbs[cur_bd].skb) {
1528 printk("%s: NULL skb.\n", dev->name);
1529 panic_queues(dev);
1530 }
1531#else
1532 BUG_ON(cur_bd >= RX_BUF_NUM);
1533#endif
1534 skb = lp->rx_skbs[cur_bd].skb;
1535 prefetch(skb->data);
1536 lp->rx_skbs[cur_bd].skb = NULL;
1537 pci_unmap_single(lp->pci_dev,
1538 lp->rx_skbs[cur_bd].skb_dma,
1539 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1540 if (!HAVE_DMA_RXALIGN(lp) && NET_IP_ALIGN)
1541 memmove(skb->data, skb->data - NET_IP_ALIGN,
1542 pkt_len);
1543 data = skb_put(skb, pkt_len);
1544 if (netif_msg_pktdata(lp))
1545 print_eth(data);
1546 skb->protocol = eth_type_trans(skb, dev);
1547 netif_receive_skb(skb);
1548 received++;
1549 dev->stats.rx_packets++;
1550 dev->stats.rx_bytes += pkt_len;
1551 } else {
1552 dev->stats.rx_errors++;
1553 if (netif_msg_rx_err(lp))
1554 dev_info(&dev->dev, "Rx error (status %x)\n",
1555 status & Rx_Stat_Mask);
1556
1557 if ((status & Rx_LongErr) && (status & Rx_CRCErr)) {
1558 status &= ~(Rx_LongErr|Rx_CRCErr);
1559 status |= Rx_Over;
1560 }
1561 if (status & Rx_LongErr)
1562 dev->stats.rx_length_errors++;
1563 if (status & Rx_Over)
1564 dev->stats.rx_fifo_errors++;
1565 if (status & Rx_CRCErr)
1566 dev->stats.rx_crc_errors++;
1567 if (status & Rx_Align)
1568 dev->stats.rx_frame_errors++;
1569 }
1570
1571 if (bd_count > 0) {
1572
1573 int bdctl = le32_to_cpu(lp->rfd_cur->bd[bd_count - 1].BDCtl);
1574 unsigned char id =
1575 (bdctl & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1576#ifdef DEBUG
1577 if (id >= RX_BUF_NUM) {
1578 printk("%s: invalid BDID.\n", dev->name);
1579 panic_queues(dev);
1580 }
1581#else
1582 BUG_ON(id >= RX_BUF_NUM);
1583#endif
1584
1585 lp->fbl_count--;
1586 while (lp->fbl_count < RX_BUF_NUM)
1587 {
1588 unsigned char curid =
1589 (id + 1 + lp->fbl_count) % RX_BUF_NUM;
1590 struct BDesc *bd = &lp->fbl_ptr->bd[curid];
1591#ifdef DEBUG
1592 bdctl = le32_to_cpu(bd->BDCtl);
1593 if (bdctl & BD_CownsBD) {
1594 printk("%s: Freeing invalid BD.\n",
1595 dev->name);
1596 panic_queues(dev);
1597 }
1598#endif
1599
1600 if (!lp->rx_skbs[curid].skb) {
1601 lp->rx_skbs[curid].skb =
1602 alloc_rxbuf_skb(dev,
1603 lp->pci_dev,
1604 &lp->rx_skbs[curid].skb_dma);
1605 if (!lp->rx_skbs[curid].skb)
1606 break;
1607 bd->BuffData = cpu_to_le32(lp->rx_skbs[curid].skb_dma);
1608 }
1609
1610 bd->BDCtl = cpu_to_le32(BD_CownsBD |
1611 (curid << BD_RxBDID_SHIFT) |
1612 RX_BUF_SIZE);
1613 lp->fbl_count++;
1614 }
1615 }
1616
1617
1618#ifdef DEBUG
1619 next_rfd = fd_bus_to_virt(lp,
1620 le32_to_cpu(lp->rfd_cur->fd.FDNext));
1621 if (next_rfd < lp->rfd_base || next_rfd > lp->rfd_limit) {
1622 printk("%s: RxFD FDNext invalid.\n", dev->name);
1623 panic_queues(dev);
1624 }
1625#endif
1626 for (i = 0; i < (bd_count + 1) / 2 + 1; i++) {
1627
1628#ifdef DEBUG
1629 lp->rfd_cur->fd.FDNext = cpu_to_le32(0xdeaddead);
1630#else
1631 lp->rfd_cur->fd.FDNext = cpu_to_le32(FD_Next_EOL);
1632#endif
1633 lp->rfd_cur->fd.FDCtl = cpu_to_le32(FD_CownsFD);
1634 lp->rfd_cur++;
1635 }
1636 if (lp->rfd_cur > lp->rfd_limit)
1637 lp->rfd_cur = lp->rfd_base;
1638#ifdef DEBUG
1639 if (lp->rfd_cur != next_rfd)
1640 printk("rfd_cur = %p, next_rfd %p\n",
1641 lp->rfd_cur, next_rfd);
1642#endif
1643 }
1644
1645 return received;
1646}
1647
1648static int tc35815_poll(struct napi_struct *napi, int budget)
1649{
1650 struct tc35815_local *lp = container_of(napi, struct tc35815_local, napi);
1651 struct net_device *dev = lp->dev;
1652 struct tc35815_regs __iomem *tr =
1653 (struct tc35815_regs __iomem *)dev->base_addr;
1654 int received = 0, handled;
1655 u32 status;
1656
1657 spin_lock(&lp->rx_lock);
1658 status = tc_readl(&tr->Int_Src);
1659 do {
1660
1661 tc_writel(status & ~(Int_BLEx | Int_FDAEx),
1662 &tr->Int_Src);
1663
1664 handled = tc35815_do_interrupt(dev, status, budget - received);
1665 if (status & (Int_BLEx | Int_FDAEx))
1666 tc_writel(status & (Int_BLEx | Int_FDAEx),
1667 &tr->Int_Src);
1668 if (handled >= 0) {
1669 received += handled;
1670 if (received >= budget)
1671 break;
1672 }
1673 status = tc_readl(&tr->Int_Src);
1674 } while (status);
1675 spin_unlock(&lp->rx_lock);
1676
1677 if (received < budget) {
1678 napi_complete(napi);
1679
1680 tc_writel(tc_readl(&tr->DMA_Ctl) & ~DMA_IntMask, &tr->DMA_Ctl);
1681 }
1682 return received;
1683}
1684
1685#define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_NCarr|Tx_LateColl|Tx_TxPar|Tx_SQErr)
1686
1687static void
1688tc35815_check_tx_stat(struct net_device *dev, int status)
1689{
1690 struct tc35815_local *lp = netdev_priv(dev);
1691 const char *msg = NULL;
1692
1693
1694 if (status & Tx_ExColl)
1695 dev->stats.collisions += 16;
1696 if (status & Tx_TxColl_MASK)
1697 dev->stats.collisions += status & Tx_TxColl_MASK;
1698
1699
1700 if (lp->chiptype == TC35815_TX4939)
1701 status &= ~Tx_NCarr;
1702
1703 if (!lp->link || lp->duplex == DUPLEX_FULL)
1704 status &= ~Tx_NCarr;
1705
1706 if (!(status & TX_STA_ERR)) {
1707
1708 dev->stats.tx_packets++;
1709 return;
1710 }
1711
1712 dev->stats.tx_errors++;
1713 if (status & Tx_ExColl) {
1714 dev->stats.tx_aborted_errors++;
1715 msg = "Excessive Collision.";
1716 }
1717 if (status & Tx_Under) {
1718 dev->stats.tx_fifo_errors++;
1719 msg = "Tx FIFO Underrun.";
1720 if (lp->lstats.tx_underrun < TX_THRESHOLD_KEEP_LIMIT) {
1721 lp->lstats.tx_underrun++;
1722 if (lp->lstats.tx_underrun >= TX_THRESHOLD_KEEP_LIMIT) {
1723 struct tc35815_regs __iomem *tr =
1724 (struct tc35815_regs __iomem *)dev->base_addr;
1725 tc_writel(TX_THRESHOLD_MAX, &tr->TxThrsh);
1726 msg = "Tx FIFO Underrun.Change Tx threshold to max.";
1727 }
1728 }
1729 }
1730 if (status & Tx_Defer) {
1731 dev->stats.tx_fifo_errors++;
1732 msg = "Excessive Deferral.";
1733 }
1734 if (status & Tx_NCarr) {
1735 dev->stats.tx_carrier_errors++;
1736 msg = "Lost Carrier Sense.";
1737 }
1738 if (status & Tx_LateColl) {
1739 dev->stats.tx_aborted_errors++;
1740 msg = "Late Collision.";
1741 }
1742 if (status & Tx_TxPar) {
1743 dev->stats.tx_fifo_errors++;
1744 msg = "Transmit Parity Error.";
1745 }
1746 if (status & Tx_SQErr) {
1747 dev->stats.tx_heartbeat_errors++;
1748 msg = "Signal Quality Error.";
1749 }
1750 if (msg && netif_msg_tx_err(lp))
1751 printk(KERN_WARNING "%s: %s (%#x)\n", dev->name, msg, status);
1752}
1753
1754
1755
1756
1757static void
1758tc35815_txdone(struct net_device *dev)
1759{
1760 struct tc35815_local *lp = netdev_priv(dev);
1761 struct TxFD *txfd;
1762 unsigned int fdctl;
1763
1764 txfd = &lp->tfd_base[lp->tfd_end];
1765 while (lp->tfd_start != lp->tfd_end &&
1766 !((fdctl = le32_to_cpu(txfd->fd.FDCtl)) & FD_CownsFD)) {
1767 int status = le32_to_cpu(txfd->fd.FDStat);
1768 struct sk_buff *skb;
1769 unsigned long fdnext = le32_to_cpu(txfd->fd.FDNext);
1770 u32 fdsystem = le32_to_cpu(txfd->fd.FDSystem);
1771
1772 if (netif_msg_tx_done(lp)) {
1773 printk("%s: complete TxFD.\n", dev->name);
1774 dump_txfd(txfd);
1775 }
1776 tc35815_check_tx_stat(dev, status);
1777
1778 skb = fdsystem != 0xffffffff ?
1779 lp->tx_skbs[fdsystem].skb : NULL;
1780#ifdef DEBUG
1781 if (lp->tx_skbs[lp->tfd_end].skb != skb) {
1782 printk("%s: tx_skbs mismatch.\n", dev->name);
1783 panic_queues(dev);
1784 }
1785#else
1786 BUG_ON(lp->tx_skbs[lp->tfd_end].skb != skb);
1787#endif
1788 if (skb) {
1789 dev->stats.tx_bytes += skb->len;
1790 pci_unmap_single(lp->pci_dev, lp->tx_skbs[lp->tfd_end].skb_dma, skb->len, PCI_DMA_TODEVICE);
1791 lp->tx_skbs[lp->tfd_end].skb = NULL;
1792 lp->tx_skbs[lp->tfd_end].skb_dma = 0;
1793 dev_kfree_skb_any(skb);
1794 }
1795 txfd->fd.FDSystem = cpu_to_le32(0xffffffff);
1796
1797 lp->tfd_end = (lp->tfd_end + 1) % TX_FD_NUM;
1798 txfd = &lp->tfd_base[lp->tfd_end];
1799#ifdef DEBUG
1800 if ((fdnext & ~FD_Next_EOL) != fd_virt_to_bus(lp, txfd)) {
1801 printk("%s: TxFD FDNext invalid.\n", dev->name);
1802 panic_queues(dev);
1803 }
1804#endif
1805 if (fdnext & FD_Next_EOL) {
1806
1807 if (lp->tfd_end != lp->tfd_start) {
1808 struct tc35815_regs __iomem *tr =
1809 (struct tc35815_regs __iomem *)dev->base_addr;
1810 int head = (lp->tfd_start + TX_FD_NUM - 1) % TX_FD_NUM;
1811 struct TxFD *txhead = &lp->tfd_base[head];
1812 int qlen = (lp->tfd_start + TX_FD_NUM
1813 - lp->tfd_end) % TX_FD_NUM;
1814
1815#ifdef DEBUG
1816 if (!(le32_to_cpu(txfd->fd.FDCtl) & FD_CownsFD)) {
1817 printk("%s: TxFD FDCtl invalid.\n", dev->name);
1818 panic_queues(dev);
1819 }
1820#endif
1821
1822 if (lp->lstats.max_tx_qlen < qlen)
1823 lp->lstats.max_tx_qlen = qlen;
1824
1825
1826
1827 txhead->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
1828 txhead->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
1829 if (netif_msg_tx_queued(lp)) {
1830 printk("%s: start TxFD on queue.\n",
1831 dev->name);
1832 dump_txfd(txfd);
1833 }
1834 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
1835 }
1836 break;
1837 }
1838 }
1839
1840
1841
1842
1843
1844 if (netif_queue_stopped(dev) && !tc35815_tx_full(dev))
1845 netif_wake_queue(dev);
1846}
1847
1848
1849static int
1850tc35815_close(struct net_device *dev)
1851{
1852 struct tc35815_local *lp = netdev_priv(dev);
1853
1854 netif_stop_queue(dev);
1855 napi_disable(&lp->napi);
1856 if (lp->phy_dev)
1857 phy_stop(lp->phy_dev);
1858 cancel_work_sync(&lp->restart_work);
1859
1860
1861 tc35815_chip_reset(dev);
1862 free_irq(dev->irq, dev);
1863
1864 tc35815_free_queues(dev);
1865
1866 return 0;
1867
1868}
1869
1870
1871
1872
1873
1874static struct net_device_stats *tc35815_get_stats(struct net_device *dev)
1875{
1876 struct tc35815_regs __iomem *tr =
1877 (struct tc35815_regs __iomem *)dev->base_addr;
1878 if (netif_running(dev))
1879
1880 dev->stats.rx_missed_errors += tc_readl(&tr->Miss_Cnt);
1881
1882 return &dev->stats;
1883}
1884
1885static void tc35815_set_cam_entry(struct net_device *dev, int index, unsigned char *addr)
1886{
1887 struct tc35815_local *lp = netdev_priv(dev);
1888 struct tc35815_regs __iomem *tr =
1889 (struct tc35815_regs __iomem *)dev->base_addr;
1890 int cam_index = index * 6;
1891 u32 cam_data;
1892 u32 saved_addr;
1893
1894 saved_addr = tc_readl(&tr->CAM_Adr);
1895
1896 if (netif_msg_hw(lp))
1897 printk(KERN_DEBUG "%s: CAM %d: %pM\n",
1898 dev->name, index, addr);
1899 if (index & 1) {
1900
1901 tc_writel(cam_index - 2, &tr->CAM_Adr);
1902 cam_data = tc_readl(&tr->CAM_Data) & 0xffff0000;
1903 cam_data |= addr[0] << 8 | addr[1];
1904 tc_writel(cam_data, &tr->CAM_Data);
1905
1906 tc_writel(cam_index + 2, &tr->CAM_Adr);
1907 cam_data = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
1908 tc_writel(cam_data, &tr->CAM_Data);
1909 } else {
1910
1911 tc_writel(cam_index, &tr->CAM_Adr);
1912 cam_data = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1913 tc_writel(cam_data, &tr->CAM_Data);
1914
1915 tc_writel(cam_index + 4, &tr->CAM_Adr);
1916 cam_data = tc_readl(&tr->CAM_Data) & 0x0000ffff;
1917 cam_data |= addr[4] << 24 | (addr[5] << 16);
1918 tc_writel(cam_data, &tr->CAM_Data);
1919 }
1920
1921 tc_writel(saved_addr, &tr->CAM_Adr);
1922}
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932static void
1933tc35815_set_multicast_list(struct net_device *dev)
1934{
1935 struct tc35815_regs __iomem *tr =
1936 (struct tc35815_regs __iomem *)dev->base_addr;
1937
1938 if (dev->flags & IFF_PROMISC) {
1939
1940
1941 struct tc35815_local *lp = netdev_priv(dev);
1942
1943 if (!lp->link)
1944 return;
1945
1946 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc | CAM_StationAcc, &tr->CAM_Ctl);
1947 } else if ((dev->flags & IFF_ALLMULTI) ||
1948 netdev_mc_count(dev) > CAM_ENTRY_MAX - 3) {
1949
1950
1951 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc, &tr->CAM_Ctl);
1952 } else if (!netdev_mc_empty(dev)) {
1953 struct netdev_hw_addr *ha;
1954 int i;
1955 int ena_bits = CAM_Ena_Bit(CAM_ENTRY_SOURCE);
1956
1957 tc_writel(0, &tr->CAM_Ctl);
1958
1959 i = 0;
1960 netdev_for_each_mc_addr(ha, dev) {
1961
1962 tc35815_set_cam_entry(dev, i + 2, ha->addr);
1963 ena_bits |= CAM_Ena_Bit(i + 2);
1964 i++;
1965 }
1966 tc_writel(ena_bits, &tr->CAM_Ena);
1967 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
1968 } else {
1969 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
1970 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
1971 }
1972}
1973
1974static void tc35815_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1975{
1976 struct tc35815_local *lp = netdev_priv(dev);
1977
1978 strlcpy(info->driver, MODNAME, sizeof(info->driver));
1979 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1980 strlcpy(info->bus_info, pci_name(lp->pci_dev), sizeof(info->bus_info));
1981}
1982
1983static int tc35815_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1984{
1985 struct tc35815_local *lp = netdev_priv(dev);
1986
1987 if (!lp->phy_dev)
1988 return -ENODEV;
1989 return phy_ethtool_gset(lp->phy_dev, cmd);
1990}
1991
1992static int tc35815_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1993{
1994 struct tc35815_local *lp = netdev_priv(dev);
1995
1996 if (!lp->phy_dev)
1997 return -ENODEV;
1998 return phy_ethtool_sset(lp->phy_dev, cmd);
1999}
2000
2001static u32 tc35815_get_msglevel(struct net_device *dev)
2002{
2003 struct tc35815_local *lp = netdev_priv(dev);
2004 return lp->msg_enable;
2005}
2006
2007static void tc35815_set_msglevel(struct net_device *dev, u32 datum)
2008{
2009 struct tc35815_local *lp = netdev_priv(dev);
2010 lp->msg_enable = datum;
2011}
2012
2013static int tc35815_get_sset_count(struct net_device *dev, int sset)
2014{
2015 struct tc35815_local *lp = netdev_priv(dev);
2016
2017 switch (sset) {
2018 case ETH_SS_STATS:
2019 return sizeof(lp->lstats) / sizeof(int);
2020 default:
2021 return -EOPNOTSUPP;
2022 }
2023}
2024
2025static void tc35815_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2026{
2027 struct tc35815_local *lp = netdev_priv(dev);
2028 data[0] = lp->lstats.max_tx_qlen;
2029 data[1] = lp->lstats.tx_ints;
2030 data[2] = lp->lstats.rx_ints;
2031 data[3] = lp->lstats.tx_underrun;
2032}
2033
2034static struct {
2035 const char str[ETH_GSTRING_LEN];
2036} ethtool_stats_keys[] = {
2037 { "max_tx_qlen" },
2038 { "tx_ints" },
2039 { "rx_ints" },
2040 { "tx_underrun" },
2041};
2042
2043static void tc35815_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2044{
2045 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2046}
2047
2048static const struct ethtool_ops tc35815_ethtool_ops = {
2049 .get_drvinfo = tc35815_get_drvinfo,
2050 .get_settings = tc35815_get_settings,
2051 .set_settings = tc35815_set_settings,
2052 .get_link = ethtool_op_get_link,
2053 .get_msglevel = tc35815_get_msglevel,
2054 .set_msglevel = tc35815_set_msglevel,
2055 .get_strings = tc35815_get_strings,
2056 .get_sset_count = tc35815_get_sset_count,
2057 .get_ethtool_stats = tc35815_get_ethtool_stats,
2058};
2059
2060static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2061{
2062 struct tc35815_local *lp = netdev_priv(dev);
2063
2064 if (!netif_running(dev))
2065 return -EINVAL;
2066 if (!lp->phy_dev)
2067 return -ENODEV;
2068 return phy_mii_ioctl(lp->phy_dev, rq, cmd);
2069}
2070
2071static void tc35815_chip_reset(struct net_device *dev)
2072{
2073 struct tc35815_regs __iomem *tr =
2074 (struct tc35815_regs __iomem *)dev->base_addr;
2075 int i;
2076
2077 tc_writel(MAC_Reset, &tr->MAC_Ctl);
2078 udelay(4);
2079 i = 0;
2080 while (tc_readl(&tr->MAC_Ctl) & MAC_Reset) {
2081 if (i++ > 100) {
2082 printk(KERN_ERR "%s: MAC reset failed.\n", dev->name);
2083 break;
2084 }
2085 mdelay(1);
2086 }
2087 tc_writel(0, &tr->MAC_Ctl);
2088
2089
2090 tc_writel(0, &tr->DMA_Ctl);
2091 tc_writel(0, &tr->TxThrsh);
2092 tc_writel(0, &tr->TxPollCtr);
2093 tc_writel(0, &tr->RxFragSize);
2094 tc_writel(0, &tr->Int_En);
2095 tc_writel(0, &tr->FDA_Bas);
2096 tc_writel(0, &tr->FDA_Lim);
2097 tc_writel(0xffffffff, &tr->Int_Src);
2098 tc_writel(0, &tr->CAM_Ctl);
2099 tc_writel(0, &tr->Tx_Ctl);
2100 tc_writel(0, &tr->Rx_Ctl);
2101 tc_writel(0, &tr->CAM_Ena);
2102 (void)tc_readl(&tr->Miss_Cnt);
2103
2104
2105 tc_writel(DMA_TestMode, &tr->DMA_Ctl);
2106 for (i = 0; i < 0x1000; i += 4) {
2107 tc_writel(i, &tr->CAM_Adr);
2108 tc_writel(0, &tr->CAM_Data);
2109 }
2110 tc_writel(0, &tr->DMA_Ctl);
2111}
2112
2113static void tc35815_chip_init(struct net_device *dev)
2114{
2115 struct tc35815_local *lp = netdev_priv(dev);
2116 struct tc35815_regs __iomem *tr =
2117 (struct tc35815_regs __iomem *)dev->base_addr;
2118 unsigned long txctl = TX_CTL_CMD;
2119
2120
2121 tc35815_set_cam_entry(dev, CAM_ENTRY_SOURCE, dev->dev_addr);
2122
2123
2124 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
2125 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
2126
2127
2128 if (HAVE_DMA_RXALIGN(lp))
2129 tc_writel(DMA_BURST_SIZE | DMA_RxAlign_2, &tr->DMA_Ctl);
2130 else
2131 tc_writel(DMA_BURST_SIZE, &tr->DMA_Ctl);
2132 tc_writel(0, &tr->TxPollCtr);
2133 tc_writel(TX_THRESHOLD, &tr->TxThrsh);
2134 tc_writel(INT_EN_CMD, &tr->Int_En);
2135
2136
2137 tc_writel(fd_virt_to_bus(lp, lp->rfd_base), &tr->FDA_Bas);
2138 tc_writel((unsigned long)lp->rfd_limit - (unsigned long)lp->rfd_base,
2139 &tr->FDA_Lim);
2140
2141
2142
2143
2144
2145 tc_writel(fd_virt_to_bus(lp, lp->fbl_ptr), &tr->BLFrmPtr);
2146 tc_writel(RX_CTL_CMD, &tr->Rx_Ctl);
2147
2148
2149
2150 if (lp->chiptype == TC35815_TX4939)
2151 txctl &= ~Tx_EnLCarr;
2152
2153 if (!lp->phy_dev || !lp->link || lp->duplex == DUPLEX_FULL)
2154 txctl &= ~Tx_EnLCarr;
2155 tc_writel(txctl, &tr->Tx_Ctl);
2156}
2157
2158#ifdef CONFIG_PM
2159static int tc35815_suspend(struct pci_dev *pdev, pm_message_t state)
2160{
2161 struct net_device *dev = pci_get_drvdata(pdev);
2162 struct tc35815_local *lp = netdev_priv(dev);
2163 unsigned long flags;
2164
2165 pci_save_state(pdev);
2166 if (!netif_running(dev))
2167 return 0;
2168 netif_device_detach(dev);
2169 if (lp->phy_dev)
2170 phy_stop(lp->phy_dev);
2171 spin_lock_irqsave(&lp->lock, flags);
2172 tc35815_chip_reset(dev);
2173 spin_unlock_irqrestore(&lp->lock, flags);
2174 pci_set_power_state(pdev, PCI_D3hot);
2175 return 0;
2176}
2177
2178static int tc35815_resume(struct pci_dev *pdev)
2179{
2180 struct net_device *dev = pci_get_drvdata(pdev);
2181 struct tc35815_local *lp = netdev_priv(dev);
2182
2183 pci_restore_state(pdev);
2184 if (!netif_running(dev))
2185 return 0;
2186 pci_set_power_state(pdev, PCI_D0);
2187 tc35815_restart(dev);
2188 netif_carrier_off(dev);
2189 if (lp->phy_dev)
2190 phy_start(lp->phy_dev);
2191 netif_device_attach(dev);
2192 return 0;
2193}
2194#endif
2195
2196static struct pci_driver tc35815_pci_driver = {
2197 .name = MODNAME,
2198 .id_table = tc35815_pci_tbl,
2199 .probe = tc35815_init_one,
2200 .remove = tc35815_remove_one,
2201#ifdef CONFIG_PM
2202 .suspend = tc35815_suspend,
2203 .resume = tc35815_resume,
2204#endif
2205};
2206
2207module_param_named(speed, options.speed, int, 0);
2208MODULE_PARM_DESC(speed, "0:auto, 10:10Mbps, 100:100Mbps");
2209module_param_named(duplex, options.duplex, int, 0);
2210MODULE_PARM_DESC(duplex, "0:auto, 1:half, 2:full");
2211
2212module_pci_driver(tc35815_pci_driver);
2213MODULE_DESCRIPTION("TOSHIBA TC35815 PCI 10M/100M Ethernet driver");
2214MODULE_LICENSE("GPL");
2215