LXR linux/drivers/net/wan/hd64570.c

   1/*
   2 * Hitachi SCA HD64570 driver for Linux
   3 *
   4 * Copyright (C) 1998-2003 Krzysztof Halasa <khc@pm.waw.pl>
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms of version 2 of the GNU General Public License
   8 * as published by the Free Software Foundation.
   9 *
  10 * Source of information: Hitachi HD64570 SCA User's Manual
  11 *
  12 * We use the following SCA memory map:
  13 *
  14 * Packet buffer descriptor rings - starting from winbase or win0base:
  15 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #0 RX ring
  16 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #0 TX ring
  17 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #1 RX ring (if used)
  18 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #1 TX ring (if used)
  19 *
  20 * Packet data buffers - starting from winbase + buff_offset:
  21 * rx_ring_buffers * HDLC_MAX_MRU     = logical channel #0 RX buffers
  22 * tx_ring_buffers * HDLC_MAX_MRU     = logical channel #0 TX buffers
  23 * rx_ring_buffers * HDLC_MAX_MRU     = logical channel #0 RX buffers (if used)
  24 * tx_ring_buffers * HDLC_MAX_MRU     = logical channel #0 TX buffers (if used)
  25 */
  26
  27#include <linux/bitops.h>
  28#include <linux/errno.h>
  29#include <linux/fcntl.h>
  30#include <linux/hdlc.h>
  31#include <linux/in.h>
  32#include <linux/init.h>
  33#include <linux/interrupt.h>
  34#include <linux/ioport.h>
  35#include <linux/jiffies.h>
  36#include <linux/kernel.h>
  37#include <linux/module.h>
  38#include <linux/netdevice.h>
  39#include <linux/skbuff.h>
  40#include <linux/string.h>
  41#include <linux/types.h>
  42#include <asm/io.h>
  43#include <asm/uaccess.h>
  44#include "hd64570.h"
  45
  46#define get_msci(port)    (phy_node(port) ?   MSCI1_OFFSET :   MSCI0_OFFSET)
  47#define get_dmac_rx(port) (phy_node(port) ? DMAC1RX_OFFSET : DMAC0RX_OFFSET)
  48#define get_dmac_tx(port) (phy_node(port) ? DMAC1TX_OFFSET : DMAC0TX_OFFSET)
  49
  50#define SCA_INTR_MSCI(node)    (node ? 0x10 : 0x01)
  51#define SCA_INTR_DMAC_RX(node) (node ? 0x20 : 0x02)
  52#define SCA_INTR_DMAC_TX(node) (node ? 0x40 : 0x04)
  53
  54
  55static inline struct net_device *port_to_dev(port_t *port)
  56{
  57        return port->dev;
  58}
  59
  60static inline int sca_intr_status(card_t *card)
  61{
  62        u8 result = 0;
  63        u8 isr0 = sca_in(ISR0, card);
  64        u8 isr1 = sca_in(ISR1, card);
  65
  66        if (isr1 & 0x03) result |= SCA_INTR_DMAC_RX(0);
  67        if (isr1 & 0x0C) result |= SCA_INTR_DMAC_TX(0);
  68        if (isr1 & 0x30) result |= SCA_INTR_DMAC_RX(1);
  69        if (isr1 & 0xC0) result |= SCA_INTR_DMAC_TX(1);
  70        if (isr0 & 0x0F) result |= SCA_INTR_MSCI(0);
  71        if (isr0 & 0xF0) result |= SCA_INTR_MSCI(1);
  72
  73        if (!(result & SCA_INTR_DMAC_TX(0)))
  74                if (sca_in(DSR_TX(0), card) & DSR_EOM)
  75                        result |= SCA_INTR_DMAC_TX(0);
  76        if (!(result & SCA_INTR_DMAC_TX(1)))
  77                if (sca_in(DSR_TX(1), card) & DSR_EOM)
  78                        result |= SCA_INTR_DMAC_TX(1);
  79
  80        return result;
  81}
  82
  83static inline port_t* dev_to_port(struct net_device *dev)
  84{
  85        return dev_to_hdlc(dev)->priv;
  86}
  87
  88static inline u16 next_desc(port_t *port, u16 desc, int transmit)
  89{
  90        return (desc + 1) % (transmit ? port_to_card(port)->tx_ring_buffers
  91                             : port_to_card(port)->rx_ring_buffers);
  92}
  93
  94
  95static inline u16 desc_abs_number(port_t *port, u16 desc, int transmit)
  96{
  97        u16 rx_buffs = port_to_card(port)->rx_ring_buffers;
  98        u16 tx_buffs = port_to_card(port)->tx_ring_buffers;
  99
 100        desc %= (transmit ? tx_buffs : rx_buffs); // called with "X + 1" etc.
 101        return log_node(port) * (rx_buffs + tx_buffs) +
 102                transmit * rx_buffs + desc;
 103}
 104
 105
 106static inline u16 desc_offset(port_t *port, u16 desc, int transmit)
 107{
 108        /* Descriptor offset always fits in 16 bits */
 109        return desc_abs_number(port, desc, transmit) * sizeof(pkt_desc);
 110}
 111
 112
 113static inline pkt_desc __iomem *desc_address(port_t *port, u16 desc,
 114                                             int transmit)
 115{
 116#ifdef PAGE0_ALWAYS_MAPPED
 117        return (pkt_desc __iomem *)(win0base(port_to_card(port))
 118                                    + desc_offset(port, desc, transmit));
 119#else
 120        return (pkt_desc __iomem *)(winbase(port_to_card(port))
 121                                    + desc_offset(port, desc, transmit));
 122#endif
 123}
 124
 125
 126static inline u32 buffer_offset(port_t *port, u16 desc, int transmit)
 127{
 128        return port_to_card(port)->buff_offset +
 129                desc_abs_number(port, desc, transmit) * (u32)HDLC_MAX_MRU;
 130}
 131
 132
 133static inline void sca_set_carrier(port_t *port)
 134{
 135        if (!(sca_in(get_msci(port) + ST3, port_to_card(port)) & ST3_DCD)) {
 136#ifdef DEBUG_LINK
 137                printk(KERN_DEBUG "%s: sca_set_carrier on\n",
 138                       port_to_dev(port)->name);
 139#endif
 140                netif_carrier_on(port_to_dev(port));
 141        } else {
 142#ifdef DEBUG_LINK
 143                printk(KERN_DEBUG "%s: sca_set_carrier off\n",
 144                       port_to_dev(port)->name);
 145#endif
 146                netif_carrier_off(port_to_dev(port));
 147        }
 148}
 149
 150
 151static void sca_init_port(port_t *port)
 152{
 153        card_t *card = port_to_card(port);
 154        int transmit, i;
 155
 156        port->rxin = 0;
 157        port->txin = 0;
 158        port->txlast = 0;
 159
 160#ifndef PAGE0_ALWAYS_MAPPED
 161        openwin(card, 0);
 162#endif
 163
 164        for (transmit = 0; transmit < 2; transmit++) {
 165                u16 dmac = transmit ? get_dmac_tx(port) : get_dmac_rx(port);
 166                u16 buffs = transmit ? card->tx_ring_buffers
 167                        : card->rx_ring_buffers;
 168
 169                for (i = 0; i < buffs; i++) {
 170                        pkt_desc __iomem *desc = desc_address(port, i, transmit);
 171                        u16 chain_off = desc_offset(port, i + 1, transmit);
 172                        u32 buff_off = buffer_offset(port, i, transmit);
 173
 174                        writew(chain_off, &desc->cp);
 175                        writel(buff_off, &desc->bp);
 176                        writew(0, &desc->len);
 177                        writeb(0, &desc->stat);
 178                }
 179
 180                /* DMA disable - to halt state */
 181                sca_out(0, transmit ? DSR_TX(phy_node(port)) :
 182                        DSR_RX(phy_node(port)), card);
 183                /* software ABORT - to initial state */
 184                sca_out(DCR_ABORT, transmit ? DCR_TX(phy_node(port)) :
 185                        DCR_RX(phy_node(port)), card);
 186
 187                /* current desc addr */
 188                sca_out(0, dmac + CPB, card); /* pointer base */
 189                sca_outw(desc_offset(port, 0, transmit), dmac + CDAL, card);
 190                if (!transmit)
 191                        sca_outw(desc_offset(port, buffs - 1, transmit),
 192                                 dmac + EDAL, card);
 193                else
 194                        sca_outw(desc_offset(port, 0, transmit), dmac + EDAL,
 195                                 card);
 196
 197                /* clear frame end interrupt counter */
 198                sca_out(DCR_CLEAR_EOF, transmit ? DCR_TX(phy_node(port)) :
 199                        DCR_RX(phy_node(port)), card);
 200
 201                if (!transmit) { /* Receive */
 202                        /* set buffer length */
 203                        sca_outw(HDLC_MAX_MRU, dmac + BFLL, card);
 204                        /* Chain mode, Multi-frame */
 205                        sca_out(0x14, DMR_RX(phy_node(port)), card);
 206                        sca_out(DIR_EOME | DIR_BOFE, DIR_RX(phy_node(port)),
 207                                card);
 208                        /* DMA enable */
 209                        sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
 210                } else {        /* Transmit */
 211                        /* Chain mode, Multi-frame */
 212                        sca_out(0x14, DMR_TX(phy_node(port)), card);
 213                        /* enable underflow interrupts */
 214                        sca_out(DIR_BOFE, DIR_TX(phy_node(port)), card);
 215                }
 216        }
 217        sca_set_carrier(port);
 218}
 219
 220
 221#ifdef NEED_SCA_MSCI_INTR
 222/* MSCI interrupt service */
 223static inline void sca_msci_intr(port_t *port)
 224{
 225        u16 msci = get_msci(port);
 226        card_t* card = port_to_card(port);
 227        u8 stat = sca_in(msci + ST1, card); /* read MSCI ST1 status */
 228
 229        /* Reset MSCI TX underrun and CDCD status bit */
 230        sca_out(stat & (ST1_UDRN | ST1_CDCD), msci + ST1, card);
 231
 232        if (stat & ST1_UDRN) {
 233                /* TX Underrun error detected */
 234                port_to_dev(port)->stats.tx_errors++;
 235                port_to_dev(port)->stats.tx_fifo_errors++;
 236        }
 237
 238        if (stat & ST1_CDCD)
 239                sca_set_carrier(port);
 240}
 241#endif
 242
 243
 244static inline void sca_rx(card_t *card, port_t *port, pkt_desc __iomem *desc,
 245                          u16 rxin)
 246{
 247        struct net_device *dev = port_to_dev(port);
 248        struct sk_buff *skb;
 249        u16 len;
 250        u32 buff;
 251        u32 maxlen;
 252        u8 page;
 253
 254        len = readw(&desc->len);
 255        skb = dev_alloc_skb(len);
 256        if (!skb) {
 257                dev->stats.rx_dropped++;
 258                return;
 259        }
 260
 261        buff = buffer_offset(port, rxin, 0);
 262        page = buff / winsize(card);
 263        buff = buff % winsize(card);
 264        maxlen = winsize(card) - buff;
 265
 266        openwin(card, page);
 267
 268        if (len > maxlen) {
 269                memcpy_fromio(skb->data, winbase(card) + buff, maxlen);
 270                openwin(card, page + 1);
 271                memcpy_fromio(skb->data + maxlen, winbase(card), len - maxlen);
 272        } else
 273                memcpy_fromio(skb->data, winbase(card) + buff, len);
 274
 275#ifndef PAGE0_ALWAYS_MAPPED
 276        openwin(card, 0);       /* select pkt_desc table page back */
 277#endif
 278        skb_put(skb, len);
 279#ifdef DEBUG_PKT
 280        printk(KERN_DEBUG "%s RX(%i):", dev->name, skb->len);
 281        debug_frame(skb);
 282#endif
 283        dev->stats.rx_packets++;
 284        dev->stats.rx_bytes += skb->len;
 285        skb->protocol = hdlc_type_trans(skb, dev);
 286        netif_rx(skb);
 287}
 288
 289
 290/* Receive DMA interrupt service */
 291static inline void sca_rx_intr(port_t *port)
 292{
 293        struct net_device *dev = port_to_dev(port);
 294        u16 dmac = get_dmac_rx(port);
 295        card_t *card = port_to_card(port);
 296        u8 stat = sca_in(DSR_RX(phy_node(port)), card); /* read DMA Status */
 297
 298        /* Reset DSR status bits */
 299        sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
 300                DSR_RX(phy_node(port)), card);
 301
 302        if (stat & DSR_BOF)
 303                /* Dropped one or more frames */
 304                dev->stats.rx_over_errors++;
 305
 306        while (1) {
 307                u32 desc_off = desc_offset(port, port->rxin, 0);
 308                pkt_desc __iomem *desc;
 309                u32 cda = sca_inw(dmac + CDAL, card);
 310
 311                if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc)))
 312                        break;  /* No frame received */
 313
 314                desc = desc_address(port, port->rxin, 0);
 315                stat = readb(&desc->stat);
 316                if (!(stat & ST_RX_EOM))
 317                        port->rxpart = 1; /* partial frame received */
 318                else if ((stat & ST_ERROR_MASK) || port->rxpart) {
 319                        dev->stats.rx_errors++;
 320                        if (stat & ST_RX_OVERRUN)
 321                                dev->stats.rx_fifo_errors++;
 322                        else if ((stat & (ST_RX_SHORT | ST_RX_ABORT |
 323                                          ST_RX_RESBIT)) || port->rxpart)
 324                                dev->stats.rx_frame_errors++;
 325                        else if (stat & ST_RX_CRC)
 326                                dev->stats.rx_crc_errors++;
 327                        if (stat & ST_RX_EOM)
 328                                port->rxpart = 0; /* received last fragment */
 329                } else
 330                        sca_rx(card, port, desc, port->rxin);
 331
 332                /* Set new error descriptor address */
 333                sca_outw(desc_off, dmac + EDAL, card);
 334                port->rxin = next_desc(port, port->rxin, 0);
 335        }
 336
 337        /* make sure RX DMA is enabled */
 338        sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
 339}
 340
 341
 342/* Transmit DMA interrupt service */
 343static inline void sca_tx_intr(port_t *port)
 344{
 345        struct net_device *dev = port_to_dev(port);
 346        u16 dmac = get_dmac_tx(port);
 347        card_t* card = port_to_card(port);
 348        u8 stat;
 349
 350        spin_lock(&port->lock);
 351
 352        stat = sca_in(DSR_TX(phy_node(port)), card); /* read DMA Status */
 353
 354        /* Reset DSR status bits */
 355        sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
 356                DSR_TX(phy_node(port)), card);
 357
 358        while (1) {
 359                pkt_desc __iomem *desc;
 360
 361                u32 desc_off = desc_offset(port, port->txlast, 1);
 362                u32 cda = sca_inw(dmac + CDAL, card);
 363                if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc)))
 364                        break;  /* Transmitter is/will_be sending this frame */
 365
 366                desc = desc_address(port, port->txlast, 1);
 367                dev->stats.tx_packets++;
 368                dev->stats.tx_bytes += readw(&desc->len);
 369                writeb(0, &desc->stat); /* Free descriptor */
 370                port->txlast = next_desc(port, port->txlast, 1);
 371        }
 372
 373        netif_wake_queue(dev);
 374        spin_unlock(&port->lock);
 375}
 376
 377
 378static irqreturn_t sca_intr(int irq, void* dev_id)
 379{
 380        card_t *card = dev_id;
 381        int i;
 382        u8 stat;
 383        int handled = 0;
 384        u8 page = sca_get_page(card);
 385
 386        while((stat = sca_intr_status(card)) != 0) {
 387                handled = 1;
 388                for (i = 0; i < 2; i++) {
 389                        port_t *port = get_port(card, i);
 390                        if (port) {
 391                                if (stat & SCA_INTR_MSCI(i))
 392                                        sca_msci_intr(port);
 393
 394                                if (stat & SCA_INTR_DMAC_RX(i))
 395                                        sca_rx_intr(port);
 396
 397                                if (stat & SCA_INTR_DMAC_TX(i))
 398                                        sca_tx_intr(port);
 399                        }
 400                }
 401        }
 402
 403        openwin(card, page);            /* Restore original page */
 404        return IRQ_RETVAL(handled);
 405}
 406
 407
 408static void sca_set_port(port_t *port)
 409{
 410        card_t* card = port_to_card(port);
 411        u16 msci = get_msci(port);
 412        u8 md2 = sca_in(msci + MD2, card);
 413        unsigned int tmc, br = 10, brv = 1024;
 414
 415
 416        if (port->settings.clock_rate > 0) {
 417                /* Try lower br for better accuracy*/
 418                do {
 419                        br--;
 420                        brv >>= 1; /* brv = 2^9 = 512 max in specs */
 421
 422                        /* Baud Rate = CLOCK_BASE / TMC / 2^BR */
 423                        tmc = CLOCK_BASE / brv / port->settings.clock_rate;
 424                }while (br > 1 && tmc <= 128);
 425
 426                if (tmc < 1) {
 427                        tmc = 1;
 428                        br = 0; /* For baud=CLOCK_BASE we use tmc=1 br=0 */
 429                        brv = 1;
 430                } else if (tmc > 255)
 431                        tmc = 256; /* tmc=0 means 256 - low baud rates */
 432
 433                port->settings.clock_rate = CLOCK_BASE / brv / tmc;
 434        } else {
 435                br = 9; /* Minimum clock rate */
 436                tmc = 256;      /* 8bit = 0 */
 437                port->settings.clock_rate = CLOCK_BASE / (256 * 512);
 438        }
 439
 440        port->rxs = (port->rxs & ~CLK_BRG_MASK) | br;
 441        port->txs = (port->txs & ~CLK_BRG_MASK) | br;
 442        port->tmc = tmc;
 443
 444        /* baud divisor - time constant*/
 445        sca_out(port->tmc, msci + TMC, card);
 446
 447        /* Set BRG bits */
 448        sca_out(port->rxs, msci + RXS, card);
 449        sca_out(port->txs, msci + TXS, card);
 450
 451        if (port->settings.loopback)
 452                md2 |= MD2_LOOPBACK;
 453        else
 454                md2 &= ~MD2_LOOPBACK;
 455
 456        sca_out(md2, msci + MD2, card);
 457
 458}
 459
 460
 461static void sca_open(struct net_device *dev)
 462{
 463        port_t *port = dev_to_port(dev);
 464        card_t* card = port_to_card(port);
 465        u16 msci = get_msci(port);
 466        u8 md0, md2;
 467
 468        switch(port->encoding) {
 469        case ENCODING_NRZ:      md2 = MD2_NRZ;          break;
 470        case ENCODING_NRZI:     md2 = MD2_NRZI;         break;
 471        case ENCODING_FM_MARK:  md2 = MD2_FM_MARK;      break;
 472        case ENCODING_FM_SPACE: md2 = MD2_FM_SPACE;     break;
 473        default:                md2 = MD2_MANCHESTER;
 474        }
 475
 476        if (port->settings.loopback)
 477                md2 |= MD2_LOOPBACK;
 478
 479        switch(port->parity) {
 480        case PARITY_CRC16_PR0:       md0 = MD0_HDLC | MD0_CRC_16_0;  break;
 481        case PARITY_CRC16_PR1:       md0 = MD0_HDLC | MD0_CRC_16;    break;
 482        case PARITY_CRC16_PR0_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU_0; break;
 483        case PARITY_CRC16_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU;   break;
 484        default:                     md0 = MD0_HDLC | MD0_CRC_NONE;
 485        }
 486
 487        sca_out(CMD_RESET, msci + CMD, card);
 488        sca_out(md0, msci + MD0, card);
 489        sca_out(0x00, msci + MD1, card); /* no address field check */
 490        sca_out(md2, msci + MD2, card);
 491        sca_out(0x7E, msci + IDL, card); /* flag character 0x7E */
 492        sca_out(CTL_IDLE, msci + CTL, card);
 493
 494        /* Allow at least 8 bytes before requesting RX DMA operation */
 495        /* TX with higher priority and possibly with shorter transfers */
 496        sca_out(0x07, msci + RRC, card); /* +1=RXRDY/DMA activation condition*/
 497        sca_out(0x10, msci + TRC0, card); /* = TXRDY/DMA activation condition*/
 498        sca_out(0x14, msci + TRC1, card); /* +1=TXRDY/DMA deactiv condition */
 499
 500/* We're using the following interrupts:
 501   - TXINT (DMAC completed all transmisions, underrun or DCD change)
 502   - all DMA interrupts
 503*/
 504        sca_set_carrier(port);
 505
 506        /* MSCI TX INT and RX INT A IRQ enable */
 507        sca_out(IE0_TXINT | IE0_RXINTA, msci + IE0, card);
 508        sca_out(IE1_UDRN | IE1_CDCD, msci + IE1, card);
 509        sca_out(sca_in(IER0, card) | (phy_node(port) ? 0xC0 : 0x0C),
 510                IER0, card); /* TXINT and RXINT */
 511        /* enable DMA IRQ */
 512        sca_out(sca_in(IER1, card) | (phy_node(port) ? 0xF0 : 0x0F),
 513                IER1, card);
 514
 515        sca_out(port->tmc, msci + TMC, card); /* Restore registers */
 516        sca_out(port->rxs, msci + RXS, card);
 517        sca_out(port->txs, msci + TXS, card);
 518        sca_out(CMD_TX_ENABLE, msci + CMD, card);
 519        sca_out(CMD_RX_ENABLE, msci + CMD, card);
 520
 521        netif_start_queue(dev);
 522}
 523
 524
 525static void sca_close(struct net_device *dev)
 526{
 527        port_t *port = dev_to_port(dev);
 528        card_t* card = port_to_card(port);
 529
 530        /* reset channel */
 531        sca_out(CMD_RESET, get_msci(port) + CMD, port_to_card(port));
 532        /* disable MSCI interrupts */
 533        sca_out(sca_in(IER0, card) & (phy_node(port) ? 0x0F : 0xF0),
 534                IER0, card);
 535        /* disable DMA interrupts */
 536        sca_out(sca_in(IER1, card) & (phy_node(port) ? 0x0F : 0xF0),
 537                IER1, card);
 538
 539        netif_stop_queue(dev);
 540}
 541
 542
 543static int sca_attach(struct net_device *dev, unsigned short encoding,
 544                      unsigned short parity)
 545{
 546        if (encoding != ENCODING_NRZ &&
 547            encoding != ENCODING_NRZI &&
 548            encoding != ENCODING_FM_MARK &&
 549            encoding != ENCODING_FM_SPACE &&
 550            encoding != ENCODING_MANCHESTER)
 551                return -EINVAL;
 552
 553        if (parity != PARITY_NONE &&
 554            parity != PARITY_CRC16_PR0 &&
 555            parity != PARITY_CRC16_PR1 &&
 556            parity != PARITY_CRC16_PR0_CCITT &&
 557            parity != PARITY_CRC16_PR1_CCITT)
 558                return -EINVAL;
 559
 560        dev_to_port(dev)->encoding = encoding;
 561        dev_to_port(dev)->parity = parity;
 562        return 0;
 563}
 564
 565
 566#ifdef DEBUG_RINGS
 567static void sca_dump_rings(struct net_device *dev)
 568{
 569        port_t *port = dev_to_port(dev);
 570        card_t *card = port_to_card(port);
 571        u16 cnt;
 572#ifndef PAGE0_ALWAYS_MAPPED
 573        u8 page = sca_get_page(card);
 574
 575        openwin(card, 0);
 576#endif
 577
 578        printk(KERN_DEBUG "RX ring: CDA=%u EDA=%u DSR=%02X in=%u %sactive",
 579               sca_inw(get_dmac_rx(port) + CDAL, card),
 580               sca_inw(get_dmac_rx(port) + EDAL, card),
 581               sca_in(DSR_RX(phy_node(port)), card), port->rxin,
 582               sca_in(DSR_RX(phy_node(port)), card) & DSR_DE ? "" : "in");
 583        for (cnt = 0; cnt < port_to_card(port)->rx_ring_buffers; cnt++)
 584                pr_cont(" %02X", readb(&(desc_address(port, cnt, 0)->stat)));
 585        pr_cont("\n");
 586
 587        printk(KERN_DEBUG "TX ring: CDA=%u EDA=%u DSR=%02X in=%u "
 588               "last=%u %sactive",
 589               sca_inw(get_dmac_tx(port) + CDAL, card),
 590               sca_inw(get_dmac_tx(port) + EDAL, card),
 591               sca_in(DSR_TX(phy_node(port)), card), port->txin, port->txlast,
 592               sca_in(DSR_TX(phy_node(port)), card) & DSR_DE ? "" : "in");
 593
 594        for (cnt = 0; cnt < port_to_card(port)->tx_ring_buffers; cnt++)
 595                pr_cont(" %02X", readb(&(desc_address(port, cnt, 1)->stat)));
 596        pr_cont("\n");
 597
 598        printk(KERN_DEBUG "MSCI: MD: %02x %02x %02x, ST: %02x %02x %02x %02x,"
 599               " FST: %02x CST: %02x %02x\n",
 600               sca_in(get_msci(port) + MD0, card),
 601               sca_in(get_msci(port) + MD1, card),
 602               sca_in(get_msci(port) + MD2, card),
 603               sca_in(get_msci(port) + ST0, card),
 604               sca_in(get_msci(port) + ST1, card),
 605               sca_in(get_msci(port) + ST2, card),
 606               sca_in(get_msci(port) + ST3, card),
 607               sca_in(get_msci(port) + FST, card),
 608               sca_in(get_msci(port) + CST0, card),
 609               sca_in(get_msci(port) + CST1, card));
 610
 611        printk(KERN_DEBUG "ISR: %02x %02x %02x\n", sca_in(ISR0, card),
 612               sca_in(ISR1, card), sca_in(ISR2, card));
 613
 614#ifndef PAGE0_ALWAYS_MAPPED
 615        openwin(card, page); /* Restore original page */
 616#endif
 617}
 618#endif /* DEBUG_RINGS */
 619
 620
 621static netdev_tx_t sca_xmit(struct sk_buff *skb, struct net_device *dev)
 622{
 623        port_t *port = dev_to_port(dev);
 624        card_t *card = port_to_card(port);
 625        pkt_desc __iomem *desc;
 626        u32 buff, len;
 627        u8 page;
 628        u32 maxlen;
 629
 630        spin_lock_irq(&port->lock);
 631
 632        desc = desc_address(port, port->txin + 1, 1);
 633        BUG_ON(readb(&desc->stat)); /* previous xmit should stop queue */
 634
 635#ifdef DEBUG_PKT
 636        printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len);
 637        debug_frame(skb);
 638#endif
 639
 640        desc = desc_address(port, port->txin, 1);
 641        buff = buffer_offset(port, port->txin, 1);
 642        len = skb->len;
 643        page = buff / winsize(card);
 644        buff = buff % winsize(card);
 645        maxlen = winsize(card) - buff;
 646
 647        openwin(card, page);
 648        if (len > maxlen) {
 649                memcpy_toio(winbase(card) + buff, skb->data, maxlen);
 650                openwin(card, page + 1);
 651                memcpy_toio(winbase(card), skb->data + maxlen, len - maxlen);
 652        } else
 653                memcpy_toio(winbase(card) + buff, skb->data, len);
 654
 655#ifndef PAGE0_ALWAYS_MAPPED
 656        openwin(card, 0);       /* select pkt_desc table page back */
 657#endif
 658        writew(len, &desc->len);
 659        writeb(ST_TX_EOM, &desc->stat);
 660
 661        port->txin = next_desc(port, port->txin, 1);
 662        sca_outw(desc_offset(port, port->txin, 1),
 663                 get_dmac_tx(port) + EDAL, card);
 664
 665        sca_out(DSR_DE, DSR_TX(phy_node(port)), card); /* Enable TX DMA */
 666
 667        desc = desc_address(port, port->txin + 1, 1);
 668        if (readb(&desc->stat)) /* allow 1 packet gap */
 669                netif_stop_queue(dev);
 670
 671        spin_unlock_irq(&port->lock);
 672
 673        dev_kfree_skb(skb);
 674        return NETDEV_TX_OK;
 675}
 676
 677
 678#ifdef NEED_DETECT_RAM
 679static u32 sca_detect_ram(card_t *card, u8 __iomem *rambase, u32 ramsize)
 680{
 681        /* Round RAM size to 32 bits, fill from end to start */
 682        u32 i = ramsize &= ~3;
 683        u32 size = winsize(card);
 684
 685        openwin(card, (i - 4) / size); /* select last window */
 686
 687        do {
 688                i -= 4;
 689                if ((i + 4) % size == 0)
 690                        openwin(card, i / size);
 691                writel(i ^ 0x12345678, rambase + i % size);
 692        } while (i > 0);
 693
 694        for (i = 0; i < ramsize ; i += 4) {
 695                if (i % size == 0)
 696                        openwin(card, i / size);
 697
 698                if (readl(rambase + i % size) != (i ^ 0x12345678))
 699                        break;
 700        }
 701
 702        return i;
 703}
 704#endif /* NEED_DETECT_RAM */
 705
 706
 707static void sca_init(card_t *card, int wait_states)
 708{
 709        sca_out(wait_states, WCRL, card); /* Wait Control */
 710        sca_out(wait_states, WCRM, card);
 711        sca_out(wait_states, WCRH, card);
 712
 713        sca_out(0, DMER, card); /* DMA Master disable */
 714        sca_out(0x03, PCR, card); /* DMA priority */
 715        sca_out(0, DSR_RX(0), card); /* DMA disable - to halt state */
 716        sca_out(0, DSR_TX(0), card);
 717        sca_out(0, DSR_RX(1), card);
 718        sca_out(0, DSR_TX(1), card);
 719        sca_out(DMER_DME, DMER, card); /* DMA Master enable */
 720}
 721