1/* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18#ifndef _HW_H_ 19#define _HW_H_ 20 21#include "targaddrs.h" 22 23/* Supported FW version */ 24#define SUPPORTED_FW_MAJOR 1 25#define SUPPORTED_FW_MINOR 0 26#define SUPPORTED_FW_RELEASE 0 27#define SUPPORTED_FW_BUILD 629 28 29/* QCA988X 1.0 definitions */ 30#define QCA988X_HW_1_0_VERSION 0x4000002c 31#define QCA988X_HW_1_0_FW_DIR "ath10k/QCA988X/hw1.0" 32#define QCA988X_HW_1_0_FW_FILE "firmware.bin" 33#define QCA988X_HW_1_0_OTP_FILE "otp.bin" 34#define QCA988X_HW_1_0_BOARD_DATA_FILE "board.bin" 35#define QCA988X_HW_1_0_PATCH_LOAD_ADDR 0x1234 36 37/* QCA988X 2.0 definitions */ 38#define QCA988X_HW_2_0_VERSION 0x4100016c 39#define QCA988X_HW_2_0_FW_DIR "ath10k/QCA988X/hw2.0" 40#define QCA988X_HW_2_0_FW_FILE "firmware.bin" 41#define QCA988X_HW_2_0_OTP_FILE "otp.bin" 42#define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin" 43#define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234 44 45/* Known pecularities: 46 * - current FW doesn't support raw rx mode (last tested v599) 47 * - current FW dumps upon raw tx mode (last tested v599) 48 * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap 49 * - raw have FCS, nwifi doesn't 50 * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher 51 * param, llc/snap) are aligned to 4byte boundaries each */ 52enum ath10k_hw_txrx_mode { 53 ATH10K_HW_TXRX_RAW = 0, 54 ATH10K_HW_TXRX_NATIVE_WIFI = 1, 55 ATH10K_HW_TXRX_ETHERNET = 2, 56}; 57 58enum ath10k_mcast2ucast_mode { 59 ATH10K_MCAST2UCAST_DISABLED = 0, 60 ATH10K_MCAST2UCAST_ENABLED = 1, 61}; 62 63#define TARGET_NUM_VDEVS 8 64#define TARGET_NUM_PEER_AST 2 65#define TARGET_NUM_WDS_ENTRIES 32 66#define TARGET_DMA_BURST_SIZE 0 67#define TARGET_MAC_AGGR_DELIM 0 68#define TARGET_AST_SKID_LIMIT 16 69#define TARGET_NUM_PEERS 16 70#define TARGET_NUM_OFFLOAD_PEERS 0 71#define TARGET_NUM_OFFLOAD_REORDER_BUFS 0 72#define TARGET_NUM_PEER_KEYS 2 73#define TARGET_NUM_TIDS (2 * ((TARGET_NUM_PEERS) + (TARGET_NUM_VDEVS))) 74#define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 75#define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 76#define TARGET_RX_TIMEOUT_LO_PRI 100 77#define TARGET_RX_TIMEOUT_HI_PRI 40 78#define TARGET_RX_DECAP_MODE ATH10K_HW_TXRX_ETHERNET 79#define TARGET_SCAN_MAX_PENDING_REQS 4 80#define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 81#define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 82#define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 83#define TARGET_GTK_OFFLOAD_MAX_VDEV 3 84#define TARGET_NUM_MCAST_GROUPS 0 85#define TARGET_NUM_MCAST_TABLE_ELEMS 0 86#define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 87#define TARGET_TX_DBG_LOG_SIZE 1024 88#define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0 89#define TARGET_VOW_CONFIG 0 90#define TARGET_NUM_MSDU_DESC (1024 + 400) 91#define TARGET_MAX_FRAG_ENTRIES 0 92 93 94/* Number of Copy Engines supported */ 95#define CE_COUNT 8 96 97/* 98 * Total number of PCIe MSI interrupts requested for all interrupt sources. 99 * PCIe standard forces this to be a power of 2. 100 * Some Host OS's limit MSI requests that can be granted to 8 101 * so for now we abide by this limit and avoid requesting more 102 * than that. 103 */ 104#define MSI_NUM_REQUEST_LOG2 3 105#define MSI_NUM_REQUEST (1<<MSI_NUM_REQUEST_LOG2) 106 107/* 108 * Granted MSIs are assigned as follows: 109 * Firmware uses the first 110 * Remaining MSIs, if any, are used by Copy Engines 111 * This mapping is known to both Target firmware and Host software. 112 * It may be changed as long as Host and Target are kept in sync. 113 */ 114/* MSI for firmware (errors, etc.) */ 115#define MSI_ASSIGN_FW 0 116 117/* MSIs for Copy Engines */ 118#define MSI_ASSIGN_CE_INITIAL 1 119#define MSI_ASSIGN_CE_MAX 7 120 121/* as of IP3.7.1 */ 122#define RTC_STATE_V_ON 3 123 124#define RTC_STATE_COLD_RESET_MASK 0x00000400 125#define RTC_STATE_V_LSB 0 126#define RTC_STATE_V_MASK 0x00000007 127#define RTC_STATE_ADDRESS 0x0000 128#define PCIE_SOC_WAKE_V_MASK 0x00000001 129#define PCIE_SOC_WAKE_ADDRESS 0x0004 130#define PCIE_SOC_WAKE_RESET 0x00000000 131#define SOC_GLOBAL_RESET_ADDRESS 0x0008 132 133#define RTC_SOC_BASE_ADDRESS 0x00004000 134#define RTC_WMAC_BASE_ADDRESS 0x00005000 135#define MAC_COEX_BASE_ADDRESS 0x00006000 136#define BT_COEX_BASE_ADDRESS 0x00007000 137#define SOC_PCIE_BASE_ADDRESS 0x00008000 138#define SOC_CORE_BASE_ADDRESS 0x00009000 139#define WLAN_UART_BASE_ADDRESS 0x0000c000 140#define WLAN_SI_BASE_ADDRESS 0x00010000 141#define WLAN_GPIO_BASE_ADDRESS 0x00014000 142#define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000 143#define WLAN_MAC_BASE_ADDRESS 0x00020000 144#define EFUSE_BASE_ADDRESS 0x00030000 145#define FPGA_REG_BASE_ADDRESS 0x00039000 146#define WLAN_UART2_BASE_ADDRESS 0x00054c00 147#define CE_WRAPPER_BASE_ADDRESS 0x00057000 148#define CE0_BASE_ADDRESS 0x00057400 149#define CE1_BASE_ADDRESS 0x00057800 150#define CE2_BASE_ADDRESS 0x00057c00 151#define CE3_BASE_ADDRESS 0x00058000 152#define CE4_BASE_ADDRESS 0x00058400 153#define CE5_BASE_ADDRESS 0x00058800 154#define CE6_BASE_ADDRESS 0x00058c00 155#define CE7_BASE_ADDRESS 0x00059000 156#define DBI_BASE_ADDRESS 0x00060000 157#define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000 158#define PCIE_LOCAL_BASE_ADDRESS 0x00080000 159 160#define SOC_RESET_CONTROL_OFFSET 0x00000000 161#define SOC_RESET_CONTROL_SI0_RST_MASK 0x00000001 162#define SOC_CPU_CLOCK_OFFSET 0x00000020 163#define SOC_CPU_CLOCK_STANDARD_LSB 0 164#define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 165#define SOC_CLOCK_CONTROL_OFFSET 0x00000028 166#define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 167#define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4 168#define SOC_LPO_CAL_OFFSET 0x000000e0 169#define SOC_LPO_CAL_ENABLE_LSB 20 170#define SOC_LPO_CAL_ENABLE_MASK 0x00100000 171 172#define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008 173#define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004 174#define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 175#define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 176 177#define WLAN_GPIO_PIN0_ADDRESS 0x00000028 178#define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800 179#define WLAN_GPIO_PIN1_ADDRESS 0x0000002c 180#define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800 181#define WLAN_GPIO_PIN10_ADDRESS 0x00000050 182#define WLAN_GPIO_PIN11_ADDRESS 0x00000054 183#define WLAN_GPIO_PIN12_ADDRESS 0x00000058 184#define WLAN_GPIO_PIN13_ADDRESS 0x0000005c 185 186#define CLOCK_GPIO_OFFSET 0xffffffff 187#define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 188#define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 189 190#define SI_CONFIG_OFFSET 0x00000000 191#define SI_CONFIG_BIDIR_OD_DATA_LSB 18 192#define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 193#define SI_CONFIG_I2C_LSB 16 194#define SI_CONFIG_I2C_MASK 0x00010000 195#define SI_CONFIG_POS_SAMPLE_LSB 7 196#define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 197#define SI_CONFIG_INACTIVE_DATA_LSB 5 198#define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 199#define SI_CONFIG_INACTIVE_CLK_LSB 4 200#define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 201#define SI_CONFIG_DIVIDER_LSB 0 202#define SI_CONFIG_DIVIDER_MASK 0x0000000f 203#define SI_CS_OFFSET 0x00000004 204#define SI_CS_DONE_ERR_MASK 0x00000400 205#define SI_CS_DONE_INT_MASK 0x00000200 206#define SI_CS_START_LSB 8 207#define SI_CS_START_MASK 0x00000100 208#define SI_CS_RX_CNT_LSB 4 209#define SI_CS_RX_CNT_MASK 0x000000f0 210#define SI_CS_TX_CNT_LSB 0 211#define SI_CS_TX_CNT_MASK 0x0000000f 212 213#define SI_TX_DATA0_OFFSET 0x00000008 214#define SI_TX_DATA1_OFFSET 0x0000000c 215#define SI_RX_DATA0_OFFSET 0x00000010 216#define SI_RX_DATA1_OFFSET 0x00000014 217 218#define CORE_CTRL_CPU_INTR_MASK 0x00002000 219#define CORE_CTRL_ADDRESS 0x0000 220#define PCIE_INTR_ENABLE_ADDRESS 0x0008 221#define PCIE_INTR_CLR_ADDRESS 0x0014 222#define SCRATCH_3_ADDRESS 0x0030 223 224/* Firmware indications to the Host via SCRATCH_3 register. */ 225#define FW_INDICATOR_ADDRESS (SOC_CORE_BASE_ADDRESS + SCRATCH_3_ADDRESS) 226#define FW_IND_EVENT_PENDING 1 227#define FW_IND_INITIALIZED 2 228 229/* HOST_REG interrupt from firmware */ 230#define PCIE_INTR_FIRMWARE_MASK 0x00000400 231#define PCIE_INTR_CE_MASK_ALL 0x0007f800 232 233#define DRAM_BASE_ADDRESS 0x00400000 234 235#define MISSING 0 236 237#define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 238#define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 239#define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET 240#define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET 241#define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK 242#define RESET_CONTROL_MBOX_RST_MASK MISSING 243#define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK 244#define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS 245#define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS 246#define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS 247#define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK 248#define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK 249#define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS 250#define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS 251#define LOCAL_SCRATCH_OFFSET 0x18 252#define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET 253#define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET 254#define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS 255#define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS 256#define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS 257#define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS 258#define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB 259#define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK 260#define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB 261#define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK 262#define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS 263#define MBOX_BASE_ADDRESS MISSING 264#define INT_STATUS_ENABLE_ERROR_LSB MISSING 265#define INT_STATUS_ENABLE_ERROR_MASK MISSING 266#define INT_STATUS_ENABLE_CPU_LSB MISSING 267#define INT_STATUS_ENABLE_CPU_MASK MISSING 268#define INT_STATUS_ENABLE_COUNTER_LSB MISSING 269#define INT_STATUS_ENABLE_COUNTER_MASK MISSING 270#define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING 271#define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING 272#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING 273#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING 274#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING 275#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING 276#define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING 277#define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING 278#define INT_STATUS_ENABLE_ADDRESS MISSING 279#define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING 280#define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING 281#define HOST_INT_STATUS_ADDRESS MISSING 282#define CPU_INT_STATUS_ADDRESS MISSING 283#define ERROR_INT_STATUS_ADDRESS MISSING 284#define ERROR_INT_STATUS_WAKEUP_MASK MISSING 285#define ERROR_INT_STATUS_WAKEUP_LSB MISSING 286#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING 287#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING 288#define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING 289#define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING 290#define COUNT_DEC_ADDRESS MISSING 291#define HOST_INT_STATUS_CPU_MASK MISSING 292#define HOST_INT_STATUS_CPU_LSB MISSING 293#define HOST_INT_STATUS_ERROR_MASK MISSING 294#define HOST_INT_STATUS_ERROR_LSB MISSING 295#define HOST_INT_STATUS_COUNTER_MASK MISSING 296#define HOST_INT_STATUS_COUNTER_LSB MISSING 297#define RX_LOOKAHEAD_VALID_ADDRESS MISSING 298#define WINDOW_DATA_ADDRESS MISSING 299#define WINDOW_READ_ADDR_ADDRESS MISSING 300#define WINDOW_WRITE_ADDR_ADDRESS MISSING 301 302#define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) 303 304#endif /* _HW_H_ */ 305