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18#ifndef _WMI_H_
19#define _WMI_H_
20
21#include <linux/types.h>
22#include <net/mac80211.h>
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64struct wmi_cmd_hdr {
65 __le32 cmd_id;
66} __packed;
67
68#define WMI_CMD_HDR_CMD_ID_MASK 0x00FFFFFF
69#define WMI_CMD_HDR_CMD_ID_LSB 0
70#define WMI_CMD_HDR_PLT_PRIV_MASK 0xFF000000
71#define WMI_CMD_HDR_PLT_PRIV_LSB 24
72
73#define HTC_PROTOCOL_VERSION 0x0002
74#define WMI_PROTOCOL_VERSION 0x0002
75
76enum wmi_service_id {
77 WMI_SERVICE_BEACON_OFFLOAD = 0,
78 WMI_SERVICE_SCAN_OFFLOAD,
79 WMI_SERVICE_ROAM_OFFLOAD,
80 WMI_SERVICE_BCN_MISS_OFFLOAD,
81 WMI_SERVICE_STA_PWRSAVE,
82 WMI_SERVICE_STA_ADVANCED_PWRSAVE,
83 WMI_SERVICE_AP_UAPSD,
84 WMI_SERVICE_AP_DFS,
85 WMI_SERVICE_11AC,
86 WMI_SERVICE_BLOCKACK,
87 WMI_SERVICE_PHYERR,
88 WMI_SERVICE_BCN_FILTER,
89 WMI_SERVICE_RTT,
90 WMI_SERVICE_RATECTRL,
91 WMI_SERVICE_WOW,
92 WMI_SERVICE_RATECTRL_CACHE,
93 WMI_SERVICE_IRAM_TIDS,
94 WMI_SERVICE_ARPNS_OFFLOAD,
95 WMI_SERVICE_NLO,
96 WMI_SERVICE_GTK_OFFLOAD,
97 WMI_SERVICE_SCAN_SCH,
98 WMI_SERVICE_CSA_OFFLOAD,
99 WMI_SERVICE_CHATTER,
100 WMI_SERVICE_COEX_FREQAVOID,
101 WMI_SERVICE_PACKET_POWER_SAVE,
102 WMI_SERVICE_FORCE_FW_HANG,
103 WMI_SERVICE_GPIO,
104 WMI_SERVICE_STA_DTIM_PS_MODULATED_DTIM,
105 WMI_STA_UAPSD_BASIC_AUTO_TRIG,
106 WMI_STA_UAPSD_VAR_AUTO_TRIG,
107 WMI_SERVICE_STA_KEEP_ALIVE,
108 WMI_SERVICE_TX_ENCAP,
109
110 WMI_SERVICE_LAST,
111 WMI_MAX_SERVICE = 64
112};
113
114static inline char *wmi_service_name(int service_id)
115{
116 switch (service_id) {
117 case WMI_SERVICE_BEACON_OFFLOAD:
118 return "BEACON_OFFLOAD";
119 case WMI_SERVICE_SCAN_OFFLOAD:
120 return "SCAN_OFFLOAD";
121 case WMI_SERVICE_ROAM_OFFLOAD:
122 return "ROAM_OFFLOAD";
123 case WMI_SERVICE_BCN_MISS_OFFLOAD:
124 return "BCN_MISS_OFFLOAD";
125 case WMI_SERVICE_STA_PWRSAVE:
126 return "STA_PWRSAVE";
127 case WMI_SERVICE_STA_ADVANCED_PWRSAVE:
128 return "STA_ADVANCED_PWRSAVE";
129 case WMI_SERVICE_AP_UAPSD:
130 return "AP_UAPSD";
131 case WMI_SERVICE_AP_DFS:
132 return "AP_DFS";
133 case WMI_SERVICE_11AC:
134 return "11AC";
135 case WMI_SERVICE_BLOCKACK:
136 return "BLOCKACK";
137 case WMI_SERVICE_PHYERR:
138 return "PHYERR";
139 case WMI_SERVICE_BCN_FILTER:
140 return "BCN_FILTER";
141 case WMI_SERVICE_RTT:
142 return "RTT";
143 case WMI_SERVICE_RATECTRL:
144 return "RATECTRL";
145 case WMI_SERVICE_WOW:
146 return "WOW";
147 case WMI_SERVICE_RATECTRL_CACHE:
148 return "RATECTRL CACHE";
149 case WMI_SERVICE_IRAM_TIDS:
150 return "IRAM TIDS";
151 case WMI_SERVICE_ARPNS_OFFLOAD:
152 return "ARPNS_OFFLOAD";
153 case WMI_SERVICE_NLO:
154 return "NLO";
155 case WMI_SERVICE_GTK_OFFLOAD:
156 return "GTK_OFFLOAD";
157 case WMI_SERVICE_SCAN_SCH:
158 return "SCAN_SCH";
159 case WMI_SERVICE_CSA_OFFLOAD:
160 return "CSA_OFFLOAD";
161 case WMI_SERVICE_CHATTER:
162 return "CHATTER";
163 case WMI_SERVICE_COEX_FREQAVOID:
164 return "COEX_FREQAVOID";
165 case WMI_SERVICE_PACKET_POWER_SAVE:
166 return "PACKET_POWER_SAVE";
167 case WMI_SERVICE_FORCE_FW_HANG:
168 return "FORCE FW HANG";
169 case WMI_SERVICE_GPIO:
170 return "GPIO";
171 case WMI_SERVICE_STA_DTIM_PS_MODULATED_DTIM:
172 return "MODULATED DTIM";
173 case WMI_STA_UAPSD_BASIC_AUTO_TRIG:
174 return "BASIC UAPSD";
175 case WMI_STA_UAPSD_VAR_AUTO_TRIG:
176 return "VAR UAPSD";
177 case WMI_SERVICE_STA_KEEP_ALIVE:
178 return "STA KEEP ALIVE";
179 case WMI_SERVICE_TX_ENCAP:
180 return "TX ENCAP";
181 default:
182 return "UNKNOWN SERVICE\n";
183 }
184}
185
186
187#define WMI_SERVICE_BM_SIZE \
188 ((WMI_MAX_SERVICE + sizeof(u32) - 1)/sizeof(u32))
189
190
191struct wmi_mac_addr {
192 union {
193 u8 addr[6];
194 struct {
195 u32 word0;
196 u32 word1;
197 } __packed;
198 } __packed;
199} __packed;
200
201
202#define WMI_MAC_ADDR_TO_CHAR_ARRAY(pwmi_mac_addr, c_macaddr) do { \
203 (c_macaddr)[0] = ((pwmi_mac_addr)->word0) & 0xff; \
204 (c_macaddr)[1] = (((pwmi_mac_addr)->word0) >> 8) & 0xff; \
205 (c_macaddr)[2] = (((pwmi_mac_addr)->word0) >> 16) & 0xff; \
206 (c_macaddr)[3] = (((pwmi_mac_addr)->word0) >> 24) & 0xff; \
207 (c_macaddr)[4] = ((pwmi_mac_addr)->word1) & 0xff; \
208 (c_macaddr)[5] = (((pwmi_mac_addr)->word1) >> 8) & 0xff; \
209 } while (0)
210
211
212
213
214enum wmi_cmd_group {
215
216 WMI_GRP_START = 0x3,
217 WMI_GRP_SCAN = WMI_GRP_START,
218 WMI_GRP_PDEV,
219 WMI_GRP_VDEV,
220 WMI_GRP_PEER,
221 WMI_GRP_MGMT,
222 WMI_GRP_BA_NEG,
223 WMI_GRP_STA_PS,
224 WMI_GRP_DFS,
225 WMI_GRP_ROAM,
226 WMI_GRP_OFL_SCAN,
227 WMI_GRP_P2P,
228 WMI_GRP_AP_PS,
229 WMI_GRP_RATE_CTRL,
230 WMI_GRP_PROFILE,
231 WMI_GRP_SUSPEND,
232 WMI_GRP_BCN_FILTER,
233 WMI_GRP_WOW,
234 WMI_GRP_RTT,
235 WMI_GRP_SPECTRAL,
236 WMI_GRP_STATS,
237 WMI_GRP_ARP_NS_OFL,
238 WMI_GRP_NLO_OFL,
239 WMI_GRP_GTK_OFL,
240 WMI_GRP_CSA_OFL,
241 WMI_GRP_CHATTER,
242 WMI_GRP_TID_ADDBA,
243 WMI_GRP_MISC,
244 WMI_GRP_GPIO,
245};
246
247#define WMI_CMD_GRP(grp_id) (((grp_id) << 12) | 0x1)
248#define WMI_EVT_GRP_START_ID(grp_id) (((grp_id) << 12) | 0x1)
249
250
251enum wmi_cmd_id {
252 WMI_INIT_CMDID = 0x1,
253
254
255 WMI_START_SCAN_CMDID = WMI_CMD_GRP(WMI_GRP_SCAN),
256 WMI_STOP_SCAN_CMDID,
257 WMI_SCAN_CHAN_LIST_CMDID,
258 WMI_SCAN_SCH_PRIO_TBL_CMDID,
259
260
261 WMI_PDEV_SET_REGDOMAIN_CMDID = WMI_CMD_GRP(WMI_GRP_PDEV),
262 WMI_PDEV_SET_CHANNEL_CMDID,
263 WMI_PDEV_SET_PARAM_CMDID,
264 WMI_PDEV_PKTLOG_ENABLE_CMDID,
265 WMI_PDEV_PKTLOG_DISABLE_CMDID,
266 WMI_PDEV_SET_WMM_PARAMS_CMDID,
267 WMI_PDEV_SET_HT_CAP_IE_CMDID,
268 WMI_PDEV_SET_VHT_CAP_IE_CMDID,
269 WMI_PDEV_SET_DSCP_TID_MAP_CMDID,
270 WMI_PDEV_SET_QUIET_MODE_CMDID,
271 WMI_PDEV_GREEN_AP_PS_ENABLE_CMDID,
272 WMI_PDEV_GET_TPC_CONFIG_CMDID,
273 WMI_PDEV_SET_BASE_MACADDR_CMDID,
274
275
276 WMI_VDEV_CREATE_CMDID = WMI_CMD_GRP(WMI_GRP_VDEV),
277 WMI_VDEV_DELETE_CMDID,
278 WMI_VDEV_START_REQUEST_CMDID,
279 WMI_VDEV_RESTART_REQUEST_CMDID,
280 WMI_VDEV_UP_CMDID,
281 WMI_VDEV_STOP_CMDID,
282 WMI_VDEV_DOWN_CMDID,
283 WMI_VDEV_SET_PARAM_CMDID,
284 WMI_VDEV_INSTALL_KEY_CMDID,
285
286
287 WMI_PEER_CREATE_CMDID = WMI_CMD_GRP(WMI_GRP_PEER),
288 WMI_PEER_DELETE_CMDID,
289 WMI_PEER_FLUSH_TIDS_CMDID,
290 WMI_PEER_SET_PARAM_CMDID,
291 WMI_PEER_ASSOC_CMDID,
292 WMI_PEER_ADD_WDS_ENTRY_CMDID,
293 WMI_PEER_REMOVE_WDS_ENTRY_CMDID,
294 WMI_PEER_MCAST_GROUP_CMDID,
295
296
297 WMI_BCN_TX_CMDID = WMI_CMD_GRP(WMI_GRP_MGMT),
298 WMI_PDEV_SEND_BCN_CMDID,
299 WMI_BCN_TMPL_CMDID,
300 WMI_BCN_FILTER_RX_CMDID,
301 WMI_PRB_REQ_FILTER_RX_CMDID,
302 WMI_MGMT_TX_CMDID,
303 WMI_PRB_TMPL_CMDID,
304
305
306 WMI_ADDBA_CLEAR_RESP_CMDID = WMI_CMD_GRP(WMI_GRP_BA_NEG),
307 WMI_ADDBA_SEND_CMDID,
308 WMI_ADDBA_STATUS_CMDID,
309 WMI_DELBA_SEND_CMDID,
310 WMI_ADDBA_SET_RESP_CMDID,
311 WMI_SEND_SINGLEAMSDU_CMDID,
312
313
314 WMI_STA_POWERSAVE_MODE_CMDID = WMI_CMD_GRP(WMI_GRP_STA_PS),
315 WMI_STA_POWERSAVE_PARAM_CMDID,
316 WMI_STA_MIMO_PS_MODE_CMDID,
317
318
319 WMI_PDEV_DFS_ENABLE_CMDID = WMI_CMD_GRP(WMI_GRP_DFS),
320 WMI_PDEV_DFS_DISABLE_CMDID,
321
322
323 WMI_ROAM_SCAN_MODE = WMI_CMD_GRP(WMI_GRP_ROAM),
324 WMI_ROAM_SCAN_RSSI_THRESHOLD,
325 WMI_ROAM_SCAN_PERIOD,
326 WMI_ROAM_SCAN_RSSI_CHANGE_THRESHOLD,
327 WMI_ROAM_AP_PROFILE,
328
329
330 WMI_OFL_SCAN_ADD_AP_PROFILE = WMI_CMD_GRP(WMI_GRP_OFL_SCAN),
331 WMI_OFL_SCAN_REMOVE_AP_PROFILE,
332 WMI_OFL_SCAN_PERIOD,
333
334
335 WMI_P2P_DEV_SET_DEVICE_INFO = WMI_CMD_GRP(WMI_GRP_P2P),
336 WMI_P2P_DEV_SET_DISCOVERABILITY,
337 WMI_P2P_GO_SET_BEACON_IE,
338 WMI_P2P_GO_SET_PROBE_RESP_IE,
339 WMI_P2P_SET_VENDOR_IE_DATA_CMDID,
340
341
342 WMI_AP_PS_PEER_PARAM_CMDID = WMI_CMD_GRP(WMI_GRP_AP_PS),
343 WMI_AP_PS_PEER_UAPSD_COEX_CMDID,
344
345
346 WMI_PEER_RATE_RETRY_SCHED_CMDID =
347 WMI_CMD_GRP(WMI_GRP_RATE_CTRL),
348
349
350 WMI_WLAN_PROFILE_TRIGGER_CMDID = WMI_CMD_GRP(WMI_GRP_PROFILE),
351 WMI_WLAN_PROFILE_SET_HIST_INTVL_CMDID,
352 WMI_WLAN_PROFILE_GET_PROFILE_DATA_CMDID,
353 WMI_WLAN_PROFILE_ENABLE_PROFILE_ID_CMDID,
354 WMI_WLAN_PROFILE_LIST_PROFILE_ID_CMDID,
355
356
357 WMI_PDEV_SUSPEND_CMDID = WMI_CMD_GRP(WMI_GRP_SUSPEND),
358 WMI_PDEV_RESUME_CMDID,
359
360
361 WMI_ADD_BCN_FILTER_CMDID = WMI_CMD_GRP(WMI_GRP_BCN_FILTER),
362 WMI_RMV_BCN_FILTER_CMDID,
363
364
365 WMI_WOW_ADD_WAKE_PATTERN_CMDID = WMI_CMD_GRP(WMI_GRP_WOW),
366 WMI_WOW_DEL_WAKE_PATTERN_CMDID,
367 WMI_WOW_ENABLE_DISABLE_WAKE_EVENT_CMDID,
368 WMI_WOW_ENABLE_CMDID,
369 WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID,
370
371
372 WMI_RTT_MEASREQ_CMDID = WMI_CMD_GRP(WMI_GRP_RTT),
373 WMI_RTT_TSF_CMDID,
374
375
376 WMI_VDEV_SPECTRAL_SCAN_CONFIGURE_CMDID = WMI_CMD_GRP(WMI_GRP_SPECTRAL),
377 WMI_VDEV_SPECTRAL_SCAN_ENABLE_CMDID,
378
379
380 WMI_REQUEST_STATS_CMDID = WMI_CMD_GRP(WMI_GRP_STATS),
381
382
383 WMI_SET_ARP_NS_OFFLOAD_CMDID = WMI_CMD_GRP(WMI_GRP_ARP_NS_OFL),
384
385
386 WMI_NETWORK_LIST_OFFLOAD_CONFIG_CMDID = WMI_CMD_GRP(WMI_GRP_NLO_OFL),
387
388
389 WMI_GTK_OFFLOAD_CMDID = WMI_CMD_GRP(WMI_GRP_GTK_OFL),
390
391
392 WMI_CSA_OFFLOAD_ENABLE_CMDID = WMI_CMD_GRP(WMI_GRP_CSA_OFL),
393 WMI_CSA_OFFLOAD_CHANSWITCH_CMDID,
394
395
396 WMI_CHATTER_SET_MODE_CMDID = WMI_CMD_GRP(WMI_GRP_CHATTER),
397
398
399 WMI_PEER_TID_ADDBA_CMDID = WMI_CMD_GRP(WMI_GRP_TID_ADDBA),
400 WMI_PEER_TID_DELBA_CMDID,
401
402
403 WMI_STA_DTIM_PS_METHOD_CMDID,
404
405 WMI_STA_UAPSD_AUTO_TRIG_CMDID,
406
407
408
409 WMI_STA_KEEPALIVE_CMD,
410
411
412 WMI_ECHO_CMDID = WMI_CMD_GRP(WMI_GRP_MISC),
413 WMI_PDEV_UTF_CMDID,
414 WMI_DBGLOG_CFG_CMDID,
415 WMI_PDEV_QVIT_CMDID,
416 WMI_PDEV_FTM_INTG_CMDID,
417 WMI_VDEV_SET_KEEPALIVE_CMDID,
418 WMI_VDEV_GET_KEEPALIVE_CMDID,
419 WMI_FORCE_FW_HANG_CMDID,
420
421
422 WMI_GPIO_CONFIG_CMDID = WMI_CMD_GRP(WMI_GRP_GPIO),
423 WMI_GPIO_OUTPUT_CMDID,
424};
425
426enum wmi_event_id {
427 WMI_SERVICE_READY_EVENTID = 0x1,
428 WMI_READY_EVENTID,
429
430
431 WMI_SCAN_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SCAN),
432
433
434 WMI_PDEV_TPC_CONFIG_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_PDEV),
435 WMI_CHAN_INFO_EVENTID,
436 WMI_PHYERR_EVENTID,
437
438
439 WMI_VDEV_START_RESP_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_VDEV),
440 WMI_VDEV_STOPPED_EVENTID,
441 WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID,
442
443
444 WMI_PEER_STA_KICKOUT_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_PEER),
445
446
447 WMI_MGMT_RX_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_MGMT),
448 WMI_HOST_SWBA_EVENTID,
449 WMI_TBTTOFFSET_UPDATE_EVENTID,
450
451
452 WMI_TX_DELBA_COMPLETE_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_BA_NEG),
453 WMI_TX_ADDBA_COMPLETE_EVENTID,
454
455
456 WMI_ROAM_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_ROAM),
457 WMI_PROFILE_MATCH,
458
459
460 WMI_WOW_WAKEUP_HOST_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_WOW),
461
462
463 WMI_RTT_MEASUREMENT_REPORT_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_RTT),
464 WMI_TSF_MEASUREMENT_REPORT_EVENTID,
465 WMI_RTT_ERROR_REPORT_EVENTID,
466
467
468 WMI_GTK_OFFLOAD_STATUS_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_GTK_OFL),
469 WMI_GTK_REKEY_FAIL_EVENTID,
470
471
472 WMI_CSA_HANDLING_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_CSA_OFL),
473
474
475 WMI_ECHO_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_MISC),
476 WMI_PDEV_UTF_EVENTID,
477 WMI_DEBUG_MESG_EVENTID,
478 WMI_UPDATE_STATS_EVENTID,
479 WMI_DEBUG_PRINT_EVENTID,
480 WMI_DCS_INTERFERENCE_EVENTID,
481 WMI_PDEV_QVIT_EVENTID,
482 WMI_WLAN_PROFILE_DATA_EVENTID,
483 WMI_PDEV_FTM_INTG_EVENTID,
484 WMI_WLAN_FREQ_AVOID_EVENTID,
485 WMI_VDEV_GET_KEEPALIVE_EVENTID,
486
487
488 WMI_GPIO_INPUT_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_GPIO),
489};
490
491enum wmi_phy_mode {
492 MODE_11A = 0,
493 MODE_11G = 1,
494 MODE_11B = 2,
495 MODE_11GONLY = 3,
496 MODE_11NA_HT20 = 4,
497 MODE_11NG_HT20 = 5,
498 MODE_11NA_HT40 = 6,
499 MODE_11NG_HT40 = 7,
500 MODE_11AC_VHT20 = 8,
501 MODE_11AC_VHT40 = 9,
502 MODE_11AC_VHT80 = 10,
503
504 MODE_11AC_VHT20_2G = 11,
505 MODE_11AC_VHT40_2G = 12,
506 MODE_11AC_VHT80_2G = 13,
507 MODE_UNKNOWN = 14,
508 MODE_MAX = 14
509};
510
511#define WMI_CHAN_LIST_TAG 0x1
512#define WMI_SSID_LIST_TAG 0x2
513#define WMI_BSSID_LIST_TAG 0x3
514#define WMI_IE_TAG 0x4
515
516struct wmi_channel {
517 __le32 mhz;
518 __le32 band_center_freq1;
519 __le32 band_center_freq2;
520 union {
521 __le32 flags;
522 struct {
523 u8 mode;
524 } __packed;
525 } __packed;
526 union {
527 __le32 reginfo0;
528 struct {
529 u8 min_power;
530 u8 max_power;
531 u8 reg_power;
532 u8 reg_classid;
533 } __packed;
534 } __packed;
535 union {
536 __le32 reginfo1;
537 struct {
538 u8 antenna_max;
539 } __packed;
540 } __packed;
541} __packed;
542
543struct wmi_channel_arg {
544 u32 freq;
545 u32 band_center_freq1;
546 bool passive;
547 bool allow_ibss;
548 bool allow_ht;
549 bool allow_vht;
550 bool ht40plus;
551
552 u32 min_power;
553 u32 max_power;
554 u32 max_reg_power;
555 u32 max_antenna_gain;
556 u32 reg_class_id;
557 enum wmi_phy_mode mode;
558};
559
560enum wmi_channel_change_cause {
561 WMI_CHANNEL_CHANGE_CAUSE_NONE = 0,
562 WMI_CHANNEL_CHANGE_CAUSE_CSA,
563};
564
565#define WMI_CHAN_FLAG_HT40_PLUS (1 << 6)
566#define WMI_CHAN_FLAG_PASSIVE (1 << 7)
567#define WMI_CHAN_FLAG_ADHOC_ALLOWED (1 << 8)
568#define WMI_CHAN_FLAG_AP_DISABLED (1 << 9)
569#define WMI_CHAN_FLAG_DFS (1 << 10)
570#define WMI_CHAN_FLAG_ALLOW_HT (1 << 11)
571#define WMI_CHAN_FLAG_ALLOW_VHT (1 << 12)
572
573
574#define WMI_CHANNEL_CHANGE_CAUSE_CSA (1 << 13)
575
576#define WMI_MAX_SPATIAL_STREAM 3
577
578
579#define WMI_HT_CAP_ENABLED 0x0001
580#define WMI_HT_CAP_HT20_SGI 0x0002
581#define WMI_HT_CAP_DYNAMIC_SMPS 0x0004
582#define WMI_HT_CAP_TX_STBC 0x0008
583#define WMI_HT_CAP_TX_STBC_MASK_SHIFT 3
584#define WMI_HT_CAP_RX_STBC 0x0030
585#define WMI_HT_CAP_RX_STBC_MASK_SHIFT 4
586#define WMI_HT_CAP_LDPC 0x0040
587#define WMI_HT_CAP_L_SIG_TXOP_PROT 0x0080
588#define WMI_HT_CAP_MPDU_DENSITY 0x0700
589#define WMI_HT_CAP_MPDU_DENSITY_MASK_SHIFT 8
590#define WMI_HT_CAP_HT40_SGI 0x0800
591
592#define WMI_HT_CAP_DEFAULT_ALL (WMI_HT_CAP_ENABLED | \
593 WMI_HT_CAP_HT20_SGI | \
594 WMI_HT_CAP_HT40_SGI | \
595 WMI_HT_CAP_TX_STBC | \
596 WMI_HT_CAP_RX_STBC | \
597 WMI_HT_CAP_LDPC)
598
599
600
601
602
603
604
605
606
607#define WMI_VHT_CAP_MAX_MPDU_LEN_MASK 0x00000003
608#define WMI_VHT_CAP_RX_LDPC 0x00000010
609#define WMI_VHT_CAP_SGI_80MHZ 0x00000020
610#define WMI_VHT_CAP_TX_STBC 0x00000080
611#define WMI_VHT_CAP_RX_STBC_MASK 0x00000300
612#define WMI_VHT_CAP_RX_STBC_MASK_SHIFT 8
613#define WMI_VHT_CAP_MAX_AMPDU_LEN_EXP 0x03800000
614#define WMI_VHT_CAP_MAX_AMPDU_LEN_EXP_SHIFT 23
615#define WMI_VHT_CAP_RX_FIXED_ANT 0x10000000
616#define WMI_VHT_CAP_TX_FIXED_ANT 0x20000000
617
618
619#define WMI_VHT_CAP_MAX_MPDU_LEN_3839 0x00000000
620#define WMI_VHT_CAP_MAX_MPDU_LEN_7935 0x00000001
621#define WMI_VHT_CAP_MAX_MPDU_LEN_11454 0x00000002
622
623#define WMI_VHT_CAP_DEFAULT_ALL (WMI_VHT_CAP_MAX_MPDU_LEN_11454 | \
624 WMI_VHT_CAP_RX_LDPC | \
625 WMI_VHT_CAP_SGI_80MHZ | \
626 WMI_VHT_CAP_TX_STBC | \
627 WMI_VHT_CAP_RX_STBC_MASK | \
628 WMI_VHT_CAP_MAX_AMPDU_LEN_EXP | \
629 WMI_VHT_CAP_RX_FIXED_ANT | \
630 WMI_VHT_CAP_TX_FIXED_ANT)
631
632
633
634
635
636#define WMI_VHT_MAX_MCS_4_SS_MASK(r, ss) ((3 & (r)) << (((ss) - 1) << 1))
637#define WMI_VHT_MAX_SUPP_RATE_MASK 0x1fff0000
638#define WMI_VHT_MAX_SUPP_RATE_MASK_SHIFT 16
639
640enum {
641 REGDMN_MODE_11A = 0x00001,
642 REGDMN_MODE_TURBO = 0x00002,
643 REGDMN_MODE_11B = 0x00004,
644 REGDMN_MODE_PUREG = 0x00008,
645 REGDMN_MODE_11G = 0x00008,
646 REGDMN_MODE_108G = 0x00020,
647 REGDMN_MODE_108A = 0x00040,
648 REGDMN_MODE_XR = 0x00100,
649 REGDMN_MODE_11A_HALF_RATE = 0x00200,
650 REGDMN_MODE_11A_QUARTER_RATE = 0x00400,
651 REGDMN_MODE_11NG_HT20 = 0x00800,
652 REGDMN_MODE_11NA_HT20 = 0x01000,
653 REGDMN_MODE_11NG_HT40PLUS = 0x02000,
654 REGDMN_MODE_11NG_HT40MINUS = 0x04000,
655 REGDMN_MODE_11NA_HT40PLUS = 0x08000,
656 REGDMN_MODE_11NA_HT40MINUS = 0x10000,
657 REGDMN_MODE_11AC_VHT20 = 0x20000,
658 REGDMN_MODE_11AC_VHT40PLUS = 0x40000,
659 REGDMN_MODE_11AC_VHT40MINUS = 0x80000,
660 REGDMN_MODE_11AC_VHT80 = 0x100000,
661 REGDMN_MODE_ALL = 0xffffffff
662};
663
664#define REGDMN_CAP1_CHAN_HALF_RATE 0x00000001
665#define REGDMN_CAP1_CHAN_QUARTER_RATE 0x00000002
666#define REGDMN_CAP1_CHAN_HAL49GHZ 0x00000004
667
668
669#define REGDMN_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
670#define REGDMN_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
671#define REGDMN_EEPROM_EEREGCAP_EN_KK_U2 0x0100
672#define REGDMN_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
673#define REGDMN_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
674#define REGDMN_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
675
676struct hal_reg_capabilities {
677
678 __le32 eeprom_rd;
679
680 __le32 eeprom_rd_ext;
681
682 __le32 regcap1;
683
684 __le32 regcap2;
685
686 __le32 wireless_modes;
687 __le32 low_2ghz_chan;
688 __le32 high_2ghz_chan;
689 __le32 low_5ghz_chan;
690 __le32 high_5ghz_chan;
691} __packed;
692
693enum wlan_mode_capability {
694 WHAL_WLAN_11A_CAPABILITY = 0x1,
695 WHAL_WLAN_11G_CAPABILITY = 0x2,
696 WHAL_WLAN_11AG_CAPABILITY = 0x3,
697};
698
699
700struct wlan_host_mem_req {
701
702 __le32 req_id;
703
704 __le32 unit_size;
705
706
707
708
709 __le32 num_unit_info;
710
711
712
713
714
715
716
717 __le32 num_units;
718} __packed;
719
720#define WMI_SERVICE_IS_ENABLED(wmi_svc_bmap, svc_id) \
721 ((((wmi_svc_bmap)[(svc_id)/(sizeof(u32))]) & \
722 (1 << ((svc_id)%(sizeof(u32))))) != 0)
723
724
725
726
727
728
729struct wmi_service_ready_event {
730 __le32 sw_version;
731 __le32 sw_version_1;
732 __le32 abi_version;
733
734 __le32 phy_capability;
735
736 __le32 max_frag_entry;
737 __le32 wmi_service_bitmap[WMI_SERVICE_BM_SIZE];
738 __le32 num_rf_chains;
739
740
741
742
743 __le32 ht_cap_info;
744 __le32 vht_cap_info;
745 __le32 vht_supp_mcs;
746 __le32 hw_min_tx_power;
747 __le32 hw_max_tx_power;
748 struct hal_reg_capabilities hal_reg_capabilities;
749 __le32 sys_cap_info;
750 __le32 min_pkt_size_enable;
751
752
753
754
755 __le32 max_bcn_ie_size;
756
757
758
759
760
761
762 __le32 num_mem_reqs;
763 struct wlan_host_mem_req mem_reqs[1];
764} __packed;
765
766
767
768
769
770#define WLAN_INIT_STATUS_SUCCESS 0x0
771#define WLAN_GET_INIT_STATUS_REASON(status) ((status) & 0xffff)
772#define WLAN_GET_INIT_STATUS_MODULE_ID(status) (((status) >> 16) & 0xffff)
773
774#define WMI_SERVICE_READY_TIMEOUT_HZ (5*HZ)
775#define WMI_UNIFIED_READY_TIMEOUT_HZ (5*HZ)
776
777struct wmi_ready_event {
778 __le32 sw_version;
779 __le32 abi_version;
780 struct wmi_mac_addr mac_addr;
781 __le32 status;
782} __packed;
783
784struct wmi_resource_config {
785
786 __le32 num_vdevs;
787
788
789 __le32 num_peers;
790
791
792
793
794
795
796
797
798 __le32 num_offload_peers;
799
800
801 __le32 num_offload_reorder_bufs;
802
803
804 __le32 num_peer_keys;
805
806
807 __le32 num_tids;
808
809
810
811
812
813
814
815
816
817
818
819 __le32 ast_skid_limit;
820
821
822
823
824
825
826
827
828
829 __le32 tx_chain_mask;
830
831
832
833
834
835
836
837
838
839
840
841 __le32 rx_chain_mask;
842
843
844
845
846
847
848
849
850
851
852
853 __le32 rx_timeout_pri_vi;
854 __le32 rx_timeout_pri_vo;
855 __le32 rx_timeout_pri_be;
856 __le32 rx_timeout_pri_bk;
857
858
859
860
861
862
863
864
865 __le32 rx_decap_mode;
866
867
868 __le32 scan_max_pending_reqs;
869
870
871 __le32 bmiss_offload_max_vdev;
872
873
874 __le32 roam_offload_max_vdev;
875
876
877 __le32 roam_offload_max_ap_profiles;
878
879
880
881
882
883
884
885
886
887
888
889
890
891 __le32 num_mcast_groups;
892
893
894
895
896
897
898
899
900
901
902 __le32 num_mcast_table_elems;
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922 __le32 mcast2ucast_mode;
923
924
925
926
927
928
929
930
931 __le32 tx_dbg_log_size;
932
933
934 __le32 num_wds_entries;
935
936
937
938
939
940 __le32 dma_burst_size;
941
942
943
944
945
946 __le32 mac_aggr_delim;
947
948
949
950
951
952
953
954
955
956
957 __le32 rx_skip_defrag_timeout_dup_detection_check;
958
959
960
961
962
963
964 __le32 vow_config;
965
966
967 __le32 gtk_offload_max_vdev;
968
969
970 __le32 num_msdu_desc;
971
972
973
974
975
976
977
978 __le32 max_frag_entries;
979} __packed;
980
981
982struct host_memory_chunk {
983
984 __le32 req_id;
985
986 __le32 ptr;
987
988 __le32 size;
989} __packed;
990
991struct wmi_init_cmd {
992 struct wmi_resource_config resource_config;
993 __le32 num_host_mem_chunks;
994
995
996
997
998
999 struct host_memory_chunk host_mem_chunks[1];
1000} __packed;
1001
1002
1003struct wmi_chan_list {
1004 __le32 tag;
1005 __le32 num_chan;
1006 __le32 channel_list[0];
1007} __packed;
1008
1009struct wmi_bssid_list {
1010 __le32 tag;
1011 __le32 num_bssid;
1012 struct wmi_mac_addr bssid_list[0];
1013} __packed;
1014
1015struct wmi_ie_data {
1016 __le32 tag;
1017 __le32 ie_len;
1018 u8 ie_data[0];
1019} __packed;
1020
1021struct wmi_ssid {
1022 __le32 ssid_len;
1023 u8 ssid[32];
1024} __packed;
1025
1026struct wmi_ssid_list {
1027 __le32 tag;
1028 __le32 num_ssids;
1029 struct wmi_ssid ssids[0];
1030} __packed;
1031
1032
1033#define WMI_HOST_SCAN_REQUESTOR_ID_PREFIX 0xA000
1034
1035
1036
1037#define WMI_HOST_SCAN_REQ_ID_PREFIX 0xA000
1038
1039#define WLAN_SCAN_PARAMS_MAX_SSID 16
1040#define WLAN_SCAN_PARAMS_MAX_BSSID 4
1041#define WLAN_SCAN_PARAMS_MAX_IE_LEN 256
1042
1043
1044enum wmi_scan_priority {
1045 WMI_SCAN_PRIORITY_VERY_LOW = 0,
1046 WMI_SCAN_PRIORITY_LOW,
1047 WMI_SCAN_PRIORITY_MEDIUM,
1048 WMI_SCAN_PRIORITY_HIGH,
1049 WMI_SCAN_PRIORITY_VERY_HIGH,
1050 WMI_SCAN_PRIORITY_COUNT
1051};
1052
1053struct wmi_start_scan_cmd {
1054
1055 __le32 scan_id;
1056
1057 __le32 scan_req_id;
1058
1059 __le32 vdev_id;
1060
1061 __le32 scan_priority;
1062
1063 __le32 notify_scan_events;
1064
1065 __le32 dwell_time_active;
1066
1067 __le32 dwell_time_passive;
1068
1069
1070
1071
1072 __le32 min_rest_time;
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086 __le32 max_rest_time;
1087
1088
1089
1090
1091
1092
1093
1094 __le32 repeat_probe_time;
1095
1096 __le32 probe_spacing_time;
1097
1098
1099
1100
1101 __le32 idle_time;
1102
1103 __le32 max_scan_time;
1104
1105
1106
1107
1108 __le32 probe_delay;
1109
1110 __le32 scan_ctrl_flags;
1111
1112
1113 __le32 burst_duration;
1114
1115
1116
1117
1118
1119} __packed;
1120
1121struct wmi_ssid_arg {
1122 int len;
1123 const u8 *ssid;
1124};
1125
1126struct wmi_bssid_arg {
1127 const u8 *bssid;
1128};
1129
1130struct wmi_start_scan_arg {
1131 u32 scan_id;
1132 u32 scan_req_id;
1133 u32 vdev_id;
1134 u32 scan_priority;
1135 u32 notify_scan_events;
1136 u32 dwell_time_active;
1137 u32 dwell_time_passive;
1138 u32 min_rest_time;
1139 u32 max_rest_time;
1140 u32 repeat_probe_time;
1141 u32 probe_spacing_time;
1142 u32 idle_time;
1143 u32 max_scan_time;
1144 u32 probe_delay;
1145 u32 scan_ctrl_flags;
1146
1147 u32 ie_len;
1148 u32 n_channels;
1149 u32 n_ssids;
1150 u32 n_bssids;
1151
1152 u8 ie[WLAN_SCAN_PARAMS_MAX_IE_LEN];
1153 u32 channels[64];
1154 struct wmi_ssid_arg ssids[WLAN_SCAN_PARAMS_MAX_SSID];
1155 struct wmi_bssid_arg bssids[WLAN_SCAN_PARAMS_MAX_BSSID];
1156};
1157
1158
1159
1160
1161#define WMI_SCAN_FLAG_PASSIVE 0x1
1162
1163#define WMI_SCAN_ADD_BCAST_PROBE_REQ 0x2
1164
1165#define WMI_SCAN_ADD_CCK_RATES 0x4
1166
1167#define WMI_SCAN_ADD_OFDM_RATES 0x8
1168
1169#define WMI_SCAN_CHAN_STAT_EVENT 0x10
1170
1171#define WMI_SCAN_FILTER_PROBE_REQ 0x20
1172
1173#define WMI_SCAN_BYPASS_DFS_CHN 0x40
1174
1175
1176#define WMI_SCAN_CONTINUE_ON_ERROR 0x80
1177
1178
1179#define WMI_SCAN_CLASS_MASK 0xFF000000
1180
1181
1182enum wmi_stop_scan_type {
1183 WMI_SCAN_STOP_ONE = 0x00000000,
1184 WMI_SCAN_STOP_VDEV_ALL = 0x01000000,
1185 WMI_SCAN_STOP_ALL = 0x04000000,
1186};
1187
1188struct wmi_stop_scan_cmd {
1189 __le32 scan_req_id;
1190 __le32 scan_id;
1191 __le32 req_type;
1192 __le32 vdev_id;
1193} __packed;
1194
1195struct wmi_stop_scan_arg {
1196 u32 req_id;
1197 enum wmi_stop_scan_type req_type;
1198 union {
1199 u32 scan_id;
1200 u32 vdev_id;
1201 } u;
1202};
1203
1204struct wmi_scan_chan_list_cmd {
1205 __le32 num_scan_chans;
1206 struct wmi_channel chan_info[0];
1207} __packed;
1208
1209struct wmi_scan_chan_list_arg {
1210 u32 n_channels;
1211 struct wmi_channel_arg *channels;
1212};
1213
1214enum wmi_bss_filter {
1215 WMI_BSS_FILTER_NONE = 0,
1216 WMI_BSS_FILTER_ALL,
1217 WMI_BSS_FILTER_PROFILE,
1218 WMI_BSS_FILTER_ALL_BUT_PROFILE,
1219 WMI_BSS_FILTER_CURRENT_BSS,
1220 WMI_BSS_FILTER_ALL_BUT_BSS,
1221 WMI_BSS_FILTER_PROBED_SSID,
1222 WMI_BSS_FILTER_LAST_BSS,
1223};
1224
1225enum wmi_scan_event_type {
1226 WMI_SCAN_EVENT_STARTED = 0x1,
1227 WMI_SCAN_EVENT_COMPLETED = 0x2,
1228 WMI_SCAN_EVENT_BSS_CHANNEL = 0x4,
1229 WMI_SCAN_EVENT_FOREIGN_CHANNEL = 0x8,
1230 WMI_SCAN_EVENT_DEQUEUED = 0x10,
1231 WMI_SCAN_EVENT_PREEMPTED = 0x20,
1232 WMI_SCAN_EVENT_START_FAILED = 0x40,
1233 WMI_SCAN_EVENT_RESTARTED = 0x80,
1234 WMI_SCAN_EVENT_MAX = 0x8000
1235};
1236
1237enum wmi_scan_completion_reason {
1238 WMI_SCAN_REASON_COMPLETED,
1239 WMI_SCAN_REASON_CANCELLED,
1240 WMI_SCAN_REASON_PREEMPTED,
1241 WMI_SCAN_REASON_TIMEDOUT,
1242 WMI_SCAN_REASON_MAX,
1243};
1244
1245struct wmi_scan_event {
1246 __le32 event_type;
1247 __le32 reason;
1248 __le32 channel_freq;
1249 __le32 scan_req_id;
1250 __le32 scan_id;
1251 __le32 vdev_id;
1252} __packed;
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262#define WMI_MGMT_RX_HDR_HEADROOM 52
1263
1264
1265
1266
1267
1268
1269
1270
1271struct wmi_mgmt_rx_hdr {
1272 __le32 channel;
1273 __le32 snr;
1274 __le32 rate;
1275 __le32 phy_mode;
1276 __le32 buf_len;
1277 __le32 status;
1278} __packed;
1279
1280struct wmi_mgmt_rx_event {
1281 struct wmi_mgmt_rx_hdr hdr;
1282 u8 buf[0];
1283} __packed;
1284
1285#define WMI_RX_STATUS_OK 0x00
1286#define WMI_RX_STATUS_ERR_CRC 0x01
1287#define WMI_RX_STATUS_ERR_DECRYPT 0x08
1288#define WMI_RX_STATUS_ERR_MIC 0x10
1289#define WMI_RX_STATUS_ERR_KEY_CACHE_MISS 0x20
1290
1291struct wmi_single_phyerr_rx_hdr {
1292
1293 __le32 tsf_timestamp;
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303 __le16 freq1;
1304 __le16 freq2;
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314 u8 rssi_combined;
1315 u8 chan_width_mhz;
1316 u8 phy_err_code;
1317 u8 rsvd0;
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331 __le32 rssi_chain0;
1332 __le32 rssi_chain1;
1333 __le32 rssi_chain2;
1334 __le32 rssi_chain3;
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349 __le32 nf_list_1;
1350 __le32 nf_list_2;
1351
1352
1353
1354 __le32 buf_len;
1355} __packed;
1356
1357struct wmi_single_phyerr_rx_event {
1358
1359 struct wmi_single_phyerr_rx_hdr hdr;
1360
1361 u8 bufp[0];
1362} __packed;
1363
1364struct wmi_comb_phyerr_rx_hdr {
1365
1366 __le32 num_phyerr_events;
1367 __le32 tsf_l32;
1368 __le32 tsf_u32;
1369} __packed;
1370
1371struct wmi_comb_phyerr_rx_event {
1372
1373 struct wmi_comb_phyerr_rx_hdr hdr;
1374
1375
1376
1377
1378
1379 u8 bufp[0];
1380} __packed;
1381
1382struct wmi_mgmt_tx_hdr {
1383 __le32 vdev_id;
1384 struct wmi_mac_addr peer_macaddr;
1385 __le32 tx_rate;
1386 __le32 tx_power;
1387 __le32 buf_len;
1388} __packed;
1389
1390struct wmi_mgmt_tx_cmd {
1391 struct wmi_mgmt_tx_hdr hdr;
1392 u8 buf[0];
1393} __packed;
1394
1395struct wmi_echo_event {
1396 __le32 value;
1397} __packed;
1398
1399struct wmi_echo_cmd {
1400 __le32 value;
1401} __packed;
1402
1403
1404struct wmi_pdev_set_regdomain_cmd {
1405 __le32 reg_domain;
1406 __le32 reg_domain_2G;
1407 __le32 reg_domain_5G;
1408 __le32 conformance_test_limit_2G;
1409 __le32 conformance_test_limit_5G;
1410} __packed;
1411
1412
1413struct wmi_pdev_set_quiet_cmd {
1414
1415 __le32 period;
1416
1417
1418 __le32 duration;
1419
1420
1421 __le32 next_start;
1422
1423
1424 __le32 enabled;
1425} __packed;
1426
1427
1428
1429
1430
1431enum ath10k_protmode {
1432 ATH10K_PROT_NONE = 0,
1433 ATH10K_PROT_CTSONLY = 1,
1434 ATH10K_PROT_RTSCTS = 2,
1435};
1436
1437enum wmi_beacon_gen_mode {
1438 WMI_BEACON_STAGGERED_MODE = 0,
1439 WMI_BEACON_BURST_MODE = 1
1440};
1441
1442enum wmi_csa_event_ies_present_flag {
1443 WMI_CSA_IE_PRESENT = 0x00000001,
1444 WMI_XCSA_IE_PRESENT = 0x00000002,
1445 WMI_WBW_IE_PRESENT = 0x00000004,
1446 WMI_CSWARP_IE_PRESENT = 0x00000008,
1447};
1448
1449
1450struct wmi_csa_event {
1451 __le32 i_fc_dur;
1452
1453
1454 struct wmi_mac_addr i_addr1;
1455 struct wmi_mac_addr i_addr2;
1456 __le32 csa_ie[2];
1457 __le32 xcsa_ie[2];
1458 __le32 wb_ie[2];
1459 __le32 cswarp_ie;
1460 __le32 ies_present_flag;
1461} __packed;
1462
1463
1464#define PDEV_DEFAULT_STATS_UPDATE_PERIOD 500
1465#define VDEV_DEFAULT_STATS_UPDATE_PERIOD 500
1466#define PEER_DEFAULT_STATS_UPDATE_PERIOD 500
1467
1468enum wmi_pdev_param {
1469
1470 WMI_PDEV_PARAM_TX_CHAIN_MASK = 0x1,
1471
1472 WMI_PDEV_PARAM_RX_CHAIN_MASK,
1473
1474 WMI_PDEV_PARAM_TXPOWER_LIMIT2G,
1475
1476 WMI_PDEV_PARAM_TXPOWER_LIMIT5G,
1477
1478 WMI_PDEV_PARAM_TXPOWER_SCALE,
1479
1480 WMI_PDEV_PARAM_BEACON_GEN_MODE,
1481
1482 WMI_PDEV_PARAM_BEACON_TX_MODE,
1483
1484
1485
1486
1487 WMI_PDEV_PARAM_RESMGR_OFFCHAN_MODE,
1488
1489
1490
1491
1492 WMI_PDEV_PARAM_PROTECTION_MODE,
1493
1494 WMI_PDEV_PARAM_DYNAMIC_BW,
1495
1496 WMI_PDEV_PARAM_NON_AGG_SW_RETRY_TH,
1497
1498 WMI_PDEV_PARAM_AGG_SW_RETRY_TH,
1499
1500 WMI_PDEV_PARAM_STA_KICKOUT_TH,
1501
1502 WMI_PDEV_PARAM_AC_AGGRSIZE_SCALING,
1503
1504 WMI_PDEV_PARAM_LTR_ENABLE,
1505
1506 WMI_PDEV_PARAM_LTR_AC_LATENCY_BE,
1507
1508 WMI_PDEV_PARAM_LTR_AC_LATENCY_BK,
1509
1510 WMI_PDEV_PARAM_LTR_AC_LATENCY_VI,
1511
1512 WMI_PDEV_PARAM_LTR_AC_LATENCY_VO,
1513
1514 WMI_PDEV_PARAM_LTR_AC_LATENCY_TIMEOUT,
1515
1516 WMI_PDEV_PARAM_LTR_SLEEP_OVERRIDE,
1517
1518 WMI_PDEV_PARAM_LTR_RX_OVERRIDE,
1519
1520 WMI_PDEV_PARAM_LTR_TX_ACTIVITY_TIMEOUT,
1521
1522 WMI_PDEV_PARAM_L1SS_ENABLE,
1523
1524 WMI_PDEV_PARAM_DSLEEP_ENABLE,
1525
1526 WMI_PDEV_PARAM_PCIELP_TXBUF_FLUSH,
1527
1528 WMI_PDEV_PARAM_PCIELP_TXBUF_WATERMARK,
1529
1530 WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_EN,
1531
1532 WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_VALUE,
1533
1534 WMI_PDEV_PARAM_PDEV_STATS_UPDATE_PERIOD,
1535
1536 WMI_PDEV_PARAM_VDEV_STATS_UPDATE_PERIOD,
1537
1538 WMI_PDEV_PARAM_PEER_STATS_UPDATE_PERIOD,
1539
1540 WMI_PDEV_PARAM_BCNFLT_STATS_UPDATE_PERIOD,
1541
1542 WMI_PDEV_PARAM_PMF_QOS,
1543
1544 WMI_PDEV_PARAM_ARP_AC_OVERRIDE,
1545
1546 WMI_PDEV_PARAM_DCS,
1547
1548 WMI_PDEV_PARAM_ANI_ENABLE,
1549
1550 WMI_PDEV_PARAM_ANI_POLL_PERIOD,
1551
1552 WMI_PDEV_PARAM_ANI_LISTEN_PERIOD,
1553
1554 WMI_PDEV_PARAM_ANI_OFDM_LEVEL,
1555
1556 WMI_PDEV_PARAM_ANI_CCK_LEVEL,
1557
1558 WMI_PDEV_PARAM_DYNTXCHAIN,
1559
1560 WMI_PDEV_PARAM_PROXY_STA,
1561
1562 WMI_PDEV_PARAM_IDLE_PS_CONFIG,
1563
1564 WMI_PDEV_PARAM_POWER_GATING_SLEEP,
1565};
1566
1567struct wmi_pdev_set_param_cmd {
1568 __le32 param_id;
1569 __le32 param_value;
1570} __packed;
1571
1572struct wmi_pdev_get_tpc_config_cmd {
1573
1574 __le32 param;
1575} __packed;
1576
1577#define WMI_TPC_RATE_MAX 160
1578#define WMI_TPC_TX_N_CHAIN 4
1579
1580enum wmi_tpc_config_event_flag {
1581 WMI_TPC_CONFIG_EVENT_FLAG_TABLE_CDD = 0x1,
1582 WMI_TPC_CONFIG_EVENT_FLAG_TABLE_STBC = 0x2,
1583 WMI_TPC_CONFIG_EVENT_FLAG_TABLE_TXBF = 0x4,
1584};
1585
1586struct wmi_pdev_tpc_config_event {
1587 __le32 reg_domain;
1588 __le32 chan_freq;
1589 __le32 phy_mode;
1590 __le32 twice_antenna_reduction;
1591 __le32 twice_max_rd_power;
1592 s32 twice_antenna_gain;
1593 __le32 power_limit;
1594 __le32 rate_max;
1595 __le32 num_tx_chain;
1596 __le32 ctl;
1597 __le32 flags;
1598 s8 max_reg_allow_pow[WMI_TPC_TX_N_CHAIN];
1599 s8 max_reg_allow_pow_agcdd[WMI_TPC_TX_N_CHAIN][WMI_TPC_TX_N_CHAIN];
1600 s8 max_reg_allow_pow_agstbc[WMI_TPC_TX_N_CHAIN][WMI_TPC_TX_N_CHAIN];
1601 s8 max_reg_allow_pow_agtxbf[WMI_TPC_TX_N_CHAIN][WMI_TPC_TX_N_CHAIN];
1602 u8 rates_array[WMI_TPC_RATE_MAX];
1603} __packed;
1604
1605
1606enum wmi_tp_scale {
1607 WMI_TP_SCALE_MAX = 0,
1608 WMI_TP_SCALE_50 = 1,
1609 WMI_TP_SCALE_25 = 2,
1610 WMI_TP_SCALE_12 = 3,
1611 WMI_TP_SCALE_MIN = 4,
1612 WMI_TP_SCALE_SIZE = 5,
1613};
1614
1615struct wmi_set_channel_cmd {
1616
1617 struct wmi_channel chan;
1618} __packed;
1619
1620struct wmi_pdev_chanlist_update_event {
1621
1622 __le32 num_chan;
1623
1624 struct wmi_channel channel_list[1];
1625} __packed;
1626
1627#define WMI_MAX_DEBUG_MESG (sizeof(u32) * 32)
1628
1629struct wmi_debug_mesg_event {
1630
1631 char bufp[WMI_MAX_DEBUG_MESG];
1632} __packed;
1633
1634enum {
1635
1636 VDEV_SUBTYPE_P2PDEV = 0,
1637
1638 VDEV_SUBTYPE_P2PCLI,
1639
1640 VDEV_SUBTYPE_P2PGO,
1641
1642 VDEV_SUBTYPE_BT,
1643};
1644
1645struct wmi_pdev_set_channel_cmd {
1646
1647 struct wmi_channel chan;
1648} __packed;
1649
1650
1651#define WMI_DSCP_MAP_MAX (64)
1652struct wmi_pdev_set_dscp_tid_map_cmd {
1653
1654 __le32 dscp_to_tid_map[WMI_DSCP_MAP_MAX];
1655} __packed;
1656
1657enum mcast_bcast_rate_id {
1658 WMI_SET_MCAST_RATE,
1659 WMI_SET_BCAST_RATE
1660};
1661
1662struct mcast_bcast_rate {
1663 enum mcast_bcast_rate_id rate_id;
1664 __le32 rate;
1665} __packed;
1666
1667struct wmi_wmm_params {
1668 __le32 cwmin;
1669 __le32 cwmax;
1670 __le32 aifs;
1671 __le32 txop;
1672 __le32 acm;
1673 __le32 no_ack;
1674} __packed;
1675
1676struct wmi_pdev_set_wmm_params {
1677 struct wmi_wmm_params ac_be;
1678 struct wmi_wmm_params ac_bk;
1679 struct wmi_wmm_params ac_vi;
1680 struct wmi_wmm_params ac_vo;
1681} __packed;
1682
1683struct wmi_wmm_params_arg {
1684 u32 cwmin;
1685 u32 cwmax;
1686 u32 aifs;
1687 u32 txop;
1688 u32 acm;
1689 u32 no_ack;
1690};
1691
1692struct wmi_pdev_set_wmm_params_arg {
1693 struct wmi_wmm_params_arg ac_be;
1694 struct wmi_wmm_params_arg ac_bk;
1695 struct wmi_wmm_params_arg ac_vi;
1696 struct wmi_wmm_params_arg ac_vo;
1697};
1698
1699struct wal_dbg_tx_stats {
1700
1701 __le32 comp_queued;
1702
1703
1704 __le32 comp_delivered;
1705
1706
1707 __le32 msdu_enqued;
1708
1709
1710 __le32 mpdu_enqued;
1711
1712
1713 __le32 wmm_drop;
1714
1715
1716 __le32 local_enqued;
1717
1718
1719 __le32 local_freed;
1720
1721
1722 __le32 hw_queued;
1723
1724
1725 __le32 hw_reaped;
1726
1727
1728 __le32 underrun;
1729
1730
1731 __le32 tx_abort;
1732
1733
1734 __le32 mpdus_requed;
1735
1736
1737 __le32 tx_ko;
1738
1739
1740 __le32 data_rc;
1741
1742
1743 __le32 self_triggers;
1744
1745
1746 __le32 sw_retry_failure;
1747
1748
1749 __le32 illgl_rate_phy_err;
1750
1751
1752 __le32 pdev_cont_xretry;
1753
1754
1755 __le32 pdev_tx_timeout;
1756
1757
1758 __le32 pdev_resets;
1759
1760 __le32 phy_underrun;
1761
1762
1763 __le32 txop_ovf;
1764} __packed;
1765
1766struct wal_dbg_rx_stats {
1767
1768 __le32 mid_ppdu_route_change;
1769
1770
1771 __le32 status_rcvd;
1772
1773
1774 __le32 r0_frags;
1775 __le32 r1_frags;
1776 __le32 r2_frags;
1777 __le32 r3_frags;
1778
1779
1780 __le32 htt_msdus;
1781 __le32 htt_mpdus;
1782
1783
1784 __le32 loc_msdus;
1785 __le32 loc_mpdus;
1786
1787
1788 __le32 oversize_amsdu;
1789
1790
1791 __le32 phy_errs;
1792
1793
1794 __le32 phy_err_drop;
1795
1796
1797 __le32 mpdu_errs;
1798} __packed;
1799
1800struct wal_dbg_peer_stats {
1801
1802 __le32 dummy;
1803} __packed;
1804
1805struct wal_dbg_stats {
1806 struct wal_dbg_tx_stats tx;
1807 struct wal_dbg_rx_stats rx;
1808 struct wal_dbg_peer_stats peer;
1809} __packed;
1810
1811enum wmi_stats_id {
1812 WMI_REQUEST_PEER_STAT = 0x01,
1813 WMI_REQUEST_AP_STAT = 0x02
1814};
1815
1816struct wmi_request_stats_cmd {
1817 __le32 stats_id;
1818
1819
1820
1821
1822
1823} __packed;
1824
1825
1826enum {
1827
1828 WMI_PDEV_SUSPEND,
1829
1830
1831 WMI_PDEV_SUSPEND_AND_DISABLE_INTR,
1832};
1833
1834struct wmi_pdev_suspend_cmd {
1835
1836 __le32 suspend_opt;
1837} __packed;
1838
1839struct wmi_stats_event {
1840 __le32 stats_id;
1841
1842
1843
1844
1845 __le32 num_pdev_stats;
1846
1847
1848
1849
1850 __le32 num_vdev_stats;
1851
1852
1853
1854
1855 __le32 num_peer_stats;
1856 __le32 num_bcnflt_stats;
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866 u8 data[0];
1867} __packed;
1868
1869
1870
1871
1872
1873struct wmi_pdev_stats {
1874 __le32 chan_nf;
1875 __le32 tx_frame_count;
1876 __le32 rx_frame_count;
1877 __le32 rx_clear_count;
1878 __le32 cycle_count;
1879 __le32 phy_err_count;
1880 __le32 chan_tx_pwr;
1881 struct wal_dbg_stats wal;
1882} __packed;
1883
1884
1885
1886
1887
1888struct wmi_vdev_stats {
1889 __le32 vdev_id;
1890} __packed;
1891
1892
1893
1894
1895
1896struct wmi_peer_stats {
1897 struct wmi_mac_addr peer_macaddr;
1898 __le32 peer_rssi;
1899 __le32 peer_tx_rate;
1900} __packed;
1901
1902struct wmi_vdev_create_cmd {
1903 __le32 vdev_id;
1904 __le32 vdev_type;
1905 __le32 vdev_subtype;
1906 struct wmi_mac_addr vdev_macaddr;
1907} __packed;
1908
1909enum wmi_vdev_type {
1910 WMI_VDEV_TYPE_AP = 1,
1911 WMI_VDEV_TYPE_STA = 2,
1912 WMI_VDEV_TYPE_IBSS = 3,
1913 WMI_VDEV_TYPE_MONITOR = 4,
1914};
1915
1916enum wmi_vdev_subtype {
1917 WMI_VDEV_SUBTYPE_NONE = 0,
1918 WMI_VDEV_SUBTYPE_P2P_DEVICE = 1,
1919 WMI_VDEV_SUBTYPE_P2P_CLIENT = 2,
1920 WMI_VDEV_SUBTYPE_P2P_GO = 3,
1921};
1922
1923
1924
1925
1926
1927
1928
1929#define WMI_VDEV_START_HIDDEN_SSID (1<<0)
1930
1931
1932
1933
1934
1935
1936#define WMI_VDEV_START_PMF_ENABLED (1<<1)
1937
1938struct wmi_p2p_noa_descriptor {
1939 __le32 type_count;
1940 __le32 duration;
1941 __le32 interval;
1942 __le32 start_time;
1943} __packed;
1944
1945struct wmi_vdev_start_request_cmd {
1946
1947 struct wmi_channel chan;
1948
1949 __le32 vdev_id;
1950
1951 __le32 requestor_id;
1952
1953 __le32 beacon_interval;
1954
1955 __le32 dtim_period;
1956
1957 __le32 flags;
1958
1959 struct wmi_ssid ssid;
1960
1961 __le32 bcn_tx_rate;
1962
1963 __le32 bcn_tx_power;
1964
1965 __le32 num_noa_descriptors;
1966
1967
1968
1969
1970 __le32 disable_hw_ack;
1971
1972 struct wmi_p2p_noa_descriptor noa_descriptors[2];
1973} __packed;
1974
1975struct wmi_vdev_restart_request_cmd {
1976 struct wmi_vdev_start_request_cmd vdev_start_request_cmd;
1977} __packed;
1978
1979struct wmi_vdev_start_request_arg {
1980 u32 vdev_id;
1981 struct wmi_channel_arg channel;
1982 u32 bcn_intval;
1983 u32 dtim_period;
1984 u8 *ssid;
1985 u32 ssid_len;
1986 u32 bcn_tx_rate;
1987 u32 bcn_tx_power;
1988 bool disable_hw_ack;
1989 bool hidden_ssid;
1990 bool pmf_enabled;
1991};
1992
1993struct wmi_vdev_delete_cmd {
1994
1995 __le32 vdev_id;
1996} __packed;
1997
1998struct wmi_vdev_up_cmd {
1999 __le32 vdev_id;
2000 __le32 vdev_assoc_id;
2001 struct wmi_mac_addr vdev_bssid;
2002} __packed;
2003
2004struct wmi_vdev_stop_cmd {
2005 __le32 vdev_id;
2006} __packed;
2007
2008struct wmi_vdev_down_cmd {
2009 __le32 vdev_id;
2010} __packed;
2011
2012struct wmi_vdev_standby_response_cmd {
2013
2014 __le32 vdev_id;
2015} __packed;
2016
2017struct wmi_vdev_resume_response_cmd {
2018
2019 __le32 vdev_id;
2020} __packed;
2021
2022struct wmi_vdev_set_param_cmd {
2023 __le32 vdev_id;
2024 __le32 param_id;
2025 __le32 param_value;
2026} __packed;
2027
2028#define WMI_MAX_KEY_INDEX 3
2029#define WMI_MAX_KEY_LEN 32
2030
2031#define WMI_KEY_PAIRWISE 0x00
2032#define WMI_KEY_GROUP 0x01
2033#define WMI_KEY_TX_USAGE 0x02
2034
2035struct wmi_key_seq_counter {
2036 __le32 key_seq_counter_l;
2037 __le32 key_seq_counter_h;
2038} __packed;
2039
2040#define WMI_CIPHER_NONE 0x0
2041#define WMI_CIPHER_WEP 0x1
2042#define WMI_CIPHER_TKIP 0x2
2043#define WMI_CIPHER_AES_OCB 0x3
2044#define WMI_CIPHER_AES_CCM 0x4
2045#define WMI_CIPHER_WAPI 0x5
2046#define WMI_CIPHER_CKIP 0x6
2047#define WMI_CIPHER_AES_CMAC 0x7
2048
2049struct wmi_vdev_install_key_cmd {
2050 __le32 vdev_id;
2051 struct wmi_mac_addr peer_macaddr;
2052 __le32 key_idx;
2053 __le32 key_flags;
2054 __le32 key_cipher;
2055 struct wmi_key_seq_counter key_rsc_counter;
2056 struct wmi_key_seq_counter key_global_rsc_counter;
2057 struct wmi_key_seq_counter key_tsc_counter;
2058 u8 wpi_key_rsc_counter[16];
2059 u8 wpi_key_tsc_counter[16];
2060 __le32 key_len;
2061 __le32 key_txmic_len;
2062 __le32 key_rxmic_len;
2063
2064
2065 u8 key_data[0];
2066} __packed;
2067
2068struct wmi_vdev_install_key_arg {
2069 u32 vdev_id;
2070 const u8 *macaddr;
2071 u32 key_idx;
2072 u32 key_flags;
2073 u32 key_cipher;
2074 u32 key_len;
2075 u32 key_txmic_len;
2076 u32 key_rxmic_len;
2077 const void *key_data;
2078};
2079
2080
2081enum wmi_rate_preamble {
2082 WMI_RATE_PREAMBLE_OFDM,
2083 WMI_RATE_PREAMBLE_CCK,
2084 WMI_RATE_PREAMBLE_HT,
2085 WMI_RATE_PREAMBLE_VHT,
2086};
2087
2088
2089#define WMI_FIXED_RATE_NONE (0xff)
2090
2091
2092enum wmi_vdev_param {
2093
2094 WMI_VDEV_PARAM_RTS_THRESHOLD = 0x1,
2095
2096 WMI_VDEV_PARAM_FRAGMENTATION_THRESHOLD,
2097
2098 WMI_VDEV_PARAM_BEACON_INTERVAL,
2099
2100 WMI_VDEV_PARAM_LISTEN_INTERVAL,
2101
2102 WMI_VDEV_PARAM_MULTICAST_RATE,
2103
2104 WMI_VDEV_PARAM_MGMT_TX_RATE,
2105
2106 WMI_VDEV_PARAM_SLOT_TIME,
2107
2108 WMI_VDEV_PARAM_PREAMBLE,
2109
2110 WMI_VDEV_PARAM_SWBA_TIME,
2111
2112 WMI_VDEV_STATS_UPDATE_PERIOD,
2113
2114 WMI_VDEV_PWRSAVE_AGEOUT_TIME,
2115
2116
2117
2118
2119 WMI_VDEV_HOST_SWBA_INTERVAL,
2120
2121 WMI_VDEV_PARAM_DTIM_PERIOD,
2122
2123
2124
2125
2126 WMI_VDEV_OC_SCHEDULER_AIR_TIME_LIMIT,
2127
2128 WMI_VDEV_PARAM_WDS,
2129
2130 WMI_VDEV_PARAM_ATIM_WINDOW,
2131
2132 WMI_VDEV_PARAM_BMISS_COUNT_MAX,
2133
2134 WMI_VDEV_PARAM_BMISS_FIRST_BCNT,
2135
2136 WMI_VDEV_PARAM_BMISS_FINAL_BCNT,
2137
2138 WMI_VDEV_PARAM_FEATURE_WMM,
2139
2140 WMI_VDEV_PARAM_CHWIDTH,
2141
2142 WMI_VDEV_PARAM_CHEXTOFFSET,
2143
2144 WMI_VDEV_PARAM_DISABLE_HTPROTECTION,
2145
2146 WMI_VDEV_PARAM_STA_QUICKKICKOUT,
2147
2148 WMI_VDEV_PARAM_MGMT_RATE,
2149
2150 WMI_VDEV_PARAM_PROTECTION_MODE,
2151
2152 WMI_VDEV_PARAM_FIXED_RATE,
2153
2154 WMI_VDEV_PARAM_SGI,
2155
2156 WMI_VDEV_PARAM_LDPC,
2157
2158 WMI_VDEV_PARAM_TX_STBC,
2159
2160 WMI_VDEV_PARAM_RX_STBC,
2161
2162 WMI_VDEV_PARAM_INTRA_BSS_FWD,
2163
2164 WMI_VDEV_PARAM_DEF_KEYID,
2165
2166 WMI_VDEV_PARAM_NSS,
2167
2168 WMI_VDEV_PARAM_BCAST_DATA_RATE,
2169
2170 WMI_VDEV_PARAM_MCAST_DATA_RATE,
2171
2172 WMI_VDEV_PARAM_MCAST_INDICATE,
2173
2174 WMI_VDEV_PARAM_DHCP_INDICATE,
2175
2176 WMI_VDEV_PARAM_UNKNOWN_DEST_INDICATE,
2177
2178
2179 WMI_VDEV_PARAM_AP_KEEPALIVE_MIN_IDLE_INACTIVE_TIME_SECS,
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191 WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_IDLE_INACTIVE_TIME_SECS,
2192
2193
2194
2195
2196
2197
2198 WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_UNRESPONSIVE_TIME_SECS,
2199
2200
2201 WMI_VDEV_PARAM_AP_ENABLE_NAWDS,
2202
2203 WMI_VDEV_PARAM_ENABLE_RTSCTS,
2204
2205 WMI_VDEV_PARAM_TXBF,
2206
2207
2208 WMI_VDEV_PARAM_PACKET_POWERSAVE,
2209
2210
2211
2212
2213
2214 WMI_VDEV_PARAM_DROP_UNENCRY,
2215
2216
2217
2218
2219 WMI_VDEV_PARAM_TX_ENCAP_TYPE,
2220};
2221
2222
2223#define WMI_VDEV_SLOT_TIME_LONG 0x1
2224
2225#define WMI_VDEV_SLOT_TIME_SHORT 0x2
2226
2227#define WMI_VDEV_PREAMBLE_LONG 0x1
2228
2229#define WMI_VDEV_PREAMBLE_SHORT 0x2
2230
2231enum wmi_start_event_param {
2232 WMI_VDEV_RESP_START_EVENT = 0,
2233 WMI_VDEV_RESP_RESTART_EVENT,
2234};
2235
2236struct wmi_vdev_start_response_event {
2237 __le32 vdev_id;
2238 __le32 req_id;
2239 __le32 resp_type;
2240 __le32 status;
2241} __packed;
2242
2243struct wmi_vdev_standby_req_event {
2244
2245 __le32 vdev_id;
2246} __packed;
2247
2248struct wmi_vdev_resume_req_event {
2249
2250 __le32 vdev_id;
2251} __packed;
2252
2253struct wmi_vdev_stopped_event {
2254
2255 __le32 vdev_id;
2256} __packed;
2257
2258
2259
2260
2261
2262struct wmi_vdev_simple_event {
2263
2264 __le32 vdev_id;
2265} __packed;
2266
2267
2268
2269#define WMI_INIFIED_VDEV_START_RESPONSE_STATUS_SUCCESS 0x0
2270
2271
2272#define WMI_INIFIED_VDEV_START_RESPONSE_INVALID_VDEVID 0x1
2273
2274
2275#define WMI_INIFIED_VDEV_START_RESPONSE_NOT_SUPPORTED 0x2
2276
2277
2278struct wmi_bcn_tx_hdr {
2279 __le32 vdev_id;
2280 __le32 tx_rate;
2281 __le32 tx_power;
2282 __le32 bcn_len;
2283} __packed;
2284
2285struct wmi_bcn_tx_cmd {
2286 struct wmi_bcn_tx_hdr hdr;
2287 u8 *bcn[0];
2288} __packed;
2289
2290struct wmi_bcn_tx_arg {
2291 u32 vdev_id;
2292 u32 tx_rate;
2293 u32 tx_power;
2294 u32 bcn_len;
2295 const void *bcn;
2296};
2297
2298
2299#define WMI_BCN_FILTER_ALL 0
2300#define WMI_BCN_FILTER_NONE 1
2301#define WMI_BCN_FILTER_RSSI 2
2302#define WMI_BCN_FILTER_BSSID 3
2303#define WMI_BCN_FILTER_SSID 4
2304
2305struct wmi_bcn_filter_rx_cmd {
2306
2307 __le32 bcn_filter_id;
2308
2309 __le32 bcn_filter;
2310
2311 __le32 bcn_filter_len;
2312
2313 u8 *bcn_filter_buf;
2314} __packed;
2315
2316
2317struct wmi_bcn_prb_info {
2318
2319 __le32 caps;
2320
2321 __le32 erp;
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331} __packed;
2332
2333struct wmi_bcn_tmpl_cmd {
2334
2335 __le32 vdev_id;
2336
2337 __le32 tim_ie_offset;
2338
2339 struct wmi_bcn_prb_info bcn_prb_info;
2340
2341 __le32 buf_len;
2342
2343 u8 data[1];
2344} __packed;
2345
2346struct wmi_prb_tmpl_cmd {
2347
2348 __le32 vdev_id;
2349
2350 struct wmi_bcn_prb_info bcn_prb_info;
2351
2352 __le32 buf_len;
2353
2354 u8 data[1];
2355} __packed;
2356
2357enum wmi_sta_ps_mode {
2358
2359 WMI_STA_PS_MODE_DISABLED = 0,
2360
2361 WMI_STA_PS_MODE_ENABLED = 1,
2362};
2363
2364struct wmi_sta_powersave_mode_cmd {
2365
2366 __le32 vdev_id;
2367
2368
2369
2370
2371
2372 __le32 sta_ps_mode;
2373} __packed;
2374
2375enum wmi_csa_offload_en {
2376 WMI_CSA_OFFLOAD_DISABLE = 0,
2377 WMI_CSA_OFFLOAD_ENABLE = 1,
2378};
2379
2380struct wmi_csa_offload_enable_cmd {
2381 __le32 vdev_id;
2382 __le32 csa_offload_enable;
2383} __packed;
2384
2385struct wmi_csa_offload_chanswitch_cmd {
2386 __le32 vdev_id;
2387 struct wmi_channel chan;
2388} __packed;
2389
2390
2391
2392
2393
2394
2395
2396enum wmi_sta_ps_param_rx_wake_policy {
2397
2398
2399
2400
2401
2402
2403 WMI_STA_PS_RX_WAKE_POLICY_WAKE = 0,
2404
2405
2406
2407
2408
2409
2410
2411
2412 WMI_STA_PS_RX_WAKE_POLICY_POLL_UAPSD = 1,
2413};
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423enum wmi_sta_ps_param_tx_wake_threshold {
2424 WMI_STA_PS_TX_WAKE_THRESHOLD_NEVER = 0,
2425 WMI_STA_PS_TX_WAKE_THRESHOLD_ALWAYS = 1,
2426
2427
2428
2429
2430
2431};
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442enum wmi_sta_ps_param_pspoll_count {
2443 WMI_STA_PS_PSPOLL_COUNT_NO_MAX = 0,
2444
2445
2446
2447
2448};
2449
2450
2451
2452
2453
2454
2455
2456#define WMI_UAPSD_AC_TYPE_DELI 0
2457#define WMI_UAPSD_AC_TYPE_TRIG 1
2458
2459#define WMI_UAPSD_AC_BIT_MASK(ac, type) \
2460 ((type == WMI_UAPSD_AC_TYPE_DELI) ? (1<<(ac<<1)) : (1<<((ac<<1)+1)))
2461
2462enum wmi_sta_ps_param_uapsd {
2463 WMI_STA_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0),
2464 WMI_STA_PS_UAPSD_AC0_TRIGGER_EN = (1 << 1),
2465 WMI_STA_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2),
2466 WMI_STA_PS_UAPSD_AC1_TRIGGER_EN = (1 << 3),
2467 WMI_STA_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4),
2468 WMI_STA_PS_UAPSD_AC2_TRIGGER_EN = (1 << 5),
2469 WMI_STA_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6),
2470 WMI_STA_PS_UAPSD_AC3_TRIGGER_EN = (1 << 7),
2471};
2472
2473enum wmi_sta_powersave_param {
2474
2475
2476
2477
2478
2479 WMI_STA_PS_PARAM_RX_WAKE_POLICY = 0,
2480
2481
2482
2483
2484
2485
2486 WMI_STA_PS_PARAM_TX_WAKE_THRESHOLD = 1,
2487
2488
2489
2490
2491
2492
2493
2494 WMI_STA_PS_PARAM_PSPOLL_COUNT = 2,
2495
2496
2497
2498
2499
2500
2501
2502
2503 WMI_STA_PS_PARAM_INACTIVITY_TIME = 3,
2504
2505
2506
2507
2508
2509
2510 WMI_STA_PS_PARAM_UAPSD = 4,
2511};
2512
2513struct wmi_sta_powersave_param_cmd {
2514 __le32 vdev_id;
2515 __le32 param_id;
2516 __le32 param_value;
2517} __packed;
2518
2519
2520#define WMI_STA_MIMO_PS_MODE_DISABLE
2521
2522#define WMI_STA_MIMO_PS_MODE_STATIC
2523
2524#define WMI_STA_MIMO_PS_MODE_DYNAMIC
2525
2526struct wmi_sta_mimo_ps_mode_cmd {
2527
2528 __le32 vdev_id;
2529
2530 __le32 mimo_pwrsave_mode;
2531} __packed;
2532
2533
2534enum wmi_ap_ps_param_uapsd {
2535 WMI_AP_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0),
2536 WMI_AP_PS_UAPSD_AC0_TRIGGER_EN = (1 << 1),
2537 WMI_AP_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2),
2538 WMI_AP_PS_UAPSD_AC1_TRIGGER_EN = (1 << 3),
2539 WMI_AP_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4),
2540 WMI_AP_PS_UAPSD_AC2_TRIGGER_EN = (1 << 5),
2541 WMI_AP_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6),
2542 WMI_AP_PS_UAPSD_AC3_TRIGGER_EN = (1 << 7),
2543};
2544
2545
2546enum wmi_ap_ps_peer_param_max_sp {
2547 WMI_AP_PS_PEER_PARAM_MAX_SP_UNLIMITED = 0,
2548 WMI_AP_PS_PEER_PARAM_MAX_SP_2 = 1,
2549 WMI_AP_PS_PEER_PARAM_MAX_SP_4 = 2,
2550 WMI_AP_PS_PEER_PARAM_MAX_SP_6 = 3,
2551 MAX_WMI_AP_PS_PEER_PARAM_MAX_SP,
2552};
2553
2554
2555
2556
2557
2558enum wmi_ap_ps_peer_param {
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570 WMI_AP_PS_PEER_PARAM_UAPSD = 0,
2571
2572
2573
2574
2575
2576
2577
2578
2579 WMI_AP_PS_PEER_PARAM_MAX_SP = 1,
2580
2581
2582 WMI_AP_PS_PEER_PARAM_AGEOUT_TIME = 2,
2583};
2584
2585struct wmi_ap_ps_peer_cmd {
2586
2587 __le32 vdev_id;
2588
2589
2590 struct wmi_mac_addr peer_macaddr;
2591
2592
2593 __le32 param_id;
2594
2595
2596 __le32 param_value;
2597} __packed;
2598
2599
2600#define WMI_TIM_BITMAP_ARRAY_SIZE 4
2601
2602struct wmi_tim_info {
2603 __le32 tim_len;
2604 __le32 tim_mcast;
2605 __le32 tim_bitmap[WMI_TIM_BITMAP_ARRAY_SIZE];
2606 __le32 tim_changed;
2607 __le32 tim_num_ps_pending;
2608} __packed;
2609
2610
2611#define WMI_P2P_MAX_NOA_DESCRIPTORS 4
2612#define WMI_P2P_OPPPS_ENABLE_BIT BIT(0)
2613#define WMI_P2P_OPPPS_CTWINDOW_OFFSET 1
2614#define WMI_P2P_NOA_CHANGED_BIT BIT(0)
2615
2616struct wmi_p2p_noa_info {
2617
2618
2619 u8 changed;
2620
2621 u8 index;
2622
2623
2624 u8 ctwindow_oppps;
2625
2626 u8 num_descriptors;
2627
2628 struct wmi_p2p_noa_descriptor descriptors[WMI_P2P_MAX_NOA_DESCRIPTORS];
2629} __packed;
2630
2631struct wmi_bcn_info {
2632 struct wmi_tim_info tim_info;
2633 struct wmi_p2p_noa_info p2p_noa_info;
2634} __packed;
2635
2636struct wmi_host_swba_event {
2637 __le32 vdev_map;
2638 struct wmi_bcn_info bcn_info[1];
2639} __packed;
2640
2641#define WMI_MAX_AP_VDEV 16
2642
2643struct wmi_tbtt_offset_event {
2644 __le32 vdev_map;
2645 __le32 tbttoffset_list[WMI_MAX_AP_VDEV];
2646} __packed;
2647
2648
2649struct wmi_peer_create_cmd {
2650 __le32 vdev_id;
2651 struct wmi_mac_addr peer_macaddr;
2652} __packed;
2653
2654struct wmi_peer_delete_cmd {
2655 __le32 vdev_id;
2656 struct wmi_mac_addr peer_macaddr;
2657} __packed;
2658
2659struct wmi_peer_flush_tids_cmd {
2660 __le32 vdev_id;
2661 struct wmi_mac_addr peer_macaddr;
2662 __le32 peer_tid_bitmap;
2663} __packed;
2664
2665struct wmi_fixed_rate {
2666
2667
2668
2669
2670
2671
2672 __le32 rate_mode;
2673
2674
2675
2676
2677 __le32 rate_series;
2678
2679
2680
2681
2682
2683 __le32 rate_retries;
2684} __packed;
2685
2686struct wmi_peer_fixed_rate_cmd {
2687
2688 __le32 vdev_id;
2689
2690 struct wmi_mac_addr peer_macaddr;
2691
2692 struct wmi_fixed_rate peer_fixed_rate;
2693} __packed;
2694
2695#define WMI_MGMT_TID 17
2696
2697struct wmi_addba_clear_resp_cmd {
2698
2699 __le32 vdev_id;
2700
2701 struct wmi_mac_addr peer_macaddr;
2702} __packed;
2703
2704struct wmi_addba_send_cmd {
2705
2706 __le32 vdev_id;
2707
2708 struct wmi_mac_addr peer_macaddr;
2709
2710 __le32 tid;
2711
2712 __le32 buffersize;
2713} __packed;
2714
2715struct wmi_delba_send_cmd {
2716
2717 __le32 vdev_id;
2718
2719 struct wmi_mac_addr peer_macaddr;
2720
2721 __le32 tid;
2722
2723 __le32 initiator;
2724
2725 __le32 reasoncode;
2726} __packed;
2727
2728struct wmi_addba_setresponse_cmd {
2729
2730 __le32 vdev_id;
2731
2732 struct wmi_mac_addr peer_macaddr;
2733
2734 __le32 tid;
2735
2736 __le32 statuscode;
2737} __packed;
2738
2739struct wmi_send_singleamsdu_cmd {
2740
2741 __le32 vdev_id;
2742
2743 struct wmi_mac_addr peer_macaddr;
2744
2745 __le32 tid;
2746} __packed;
2747
2748enum wmi_peer_smps_state {
2749 WMI_PEER_SMPS_PS_NONE = 0x0,
2750 WMI_PEER_SMPS_STATIC = 0x1,
2751 WMI_PEER_SMPS_DYNAMIC = 0x2
2752};
2753
2754enum wmi_peer_param {
2755 WMI_PEER_SMPS_STATE = 0x1,
2756 WMI_PEER_AMPDU = 0x2,
2757 WMI_PEER_AUTHORIZE = 0x3,
2758 WMI_PEER_CHAN_WIDTH = 0x4,
2759 WMI_PEER_NSS = 0x5,
2760 WMI_PEER_USE_4ADDR = 0x6
2761};
2762
2763struct wmi_peer_set_param_cmd {
2764 __le32 vdev_id;
2765 struct wmi_mac_addr peer_macaddr;
2766 __le32 param_id;
2767 __le32 param_value;
2768} __packed;
2769
2770#define MAX_SUPPORTED_RATES 128
2771
2772struct wmi_rate_set {
2773
2774 __le32 num_rates;
2775
2776
2777
2778
2779
2780 __le32 rates[(MAX_SUPPORTED_RATES/4)+1];
2781} __packed;
2782
2783struct wmi_rate_set_arg {
2784 unsigned int num_rates;
2785 u8 rates[MAX_SUPPORTED_RATES];
2786};
2787
2788
2789
2790
2791
2792
2793struct wmi_vht_rate_set {
2794 __le32 rx_max_rate;
2795 __le32 rx_mcs_set;
2796 __le32 tx_max_rate;
2797 __le32 tx_mcs_set;
2798} __packed;
2799
2800struct wmi_vht_rate_set_arg {
2801 u32 rx_max_rate;
2802 u32 rx_mcs_set;
2803 u32 tx_max_rate;
2804 u32 tx_mcs_set;
2805};
2806
2807struct wmi_peer_set_rates_cmd {
2808
2809 struct wmi_mac_addr peer_macaddr;
2810
2811 struct wmi_rate_set peer_legacy_rates;
2812
2813 struct wmi_rate_set peer_ht_rates;
2814} __packed;
2815
2816struct wmi_peer_set_q_empty_callback_cmd {
2817
2818 __le32 vdev_id;
2819
2820 struct wmi_mac_addr peer_macaddr;
2821 __le32 callback_enable;
2822} __packed;
2823
2824#define WMI_PEER_AUTH 0x00000001
2825#define WMI_PEER_QOS 0x00000002
2826#define WMI_PEER_NEED_PTK_4_WAY 0x00000004
2827#define WMI_PEER_NEED_GTK_2_WAY 0x00000010
2828#define WMI_PEER_APSD 0x00000800
2829#define WMI_PEER_HT 0x00001000
2830#define WMI_PEER_40MHZ 0x00002000
2831#define WMI_PEER_STBC 0x00008000
2832#define WMI_PEER_LDPC 0x00010000
2833#define WMI_PEER_DYN_MIMOPS 0x00020000
2834#define WMI_PEER_STATIC_MIMOPS 0x00040000
2835#define WMI_PEER_SPATIAL_MUX 0x00200000
2836#define WMI_PEER_VHT 0x02000000
2837#define WMI_PEER_80MHZ 0x04000000
2838#define WMI_PEER_PMF 0x08000000
2839
2840
2841
2842
2843
2844
2845
2846
2847#define WMI_RC_DS_FLAG 0x01
2848#define WMI_RC_CW40_FLAG 0x02
2849#define WMI_RC_SGI_FLAG 0x04
2850#define WMI_RC_HT_FLAG 0x08
2851#define WMI_RC_RTSCTS_FLAG 0x10
2852#define WMI_RC_TX_STBC_FLAG 0x20
2853#define WMI_RC_RX_STBC_FLAG 0xC0
2854#define WMI_RC_RX_STBC_FLAG_S 6
2855#define WMI_RC_WEP_TKIP_FLAG 0x100
2856#define WMI_RC_TS_FLAG 0x200
2857#define WMI_RC_UAPSD_FLAG 0x400
2858
2859
2860#define ATH10K_MAX_HW_LISTEN_INTERVAL 5
2861
2862struct wmi_peer_assoc_complete_cmd {
2863 struct wmi_mac_addr peer_macaddr;
2864 __le32 vdev_id;
2865 __le32 peer_new_assoc;
2866 __le32 peer_associd;
2867 __le32 peer_flags;
2868 __le32 peer_caps;
2869 __le32 peer_listen_intval;
2870 __le32 peer_ht_caps;
2871 __le32 peer_max_mpdu;
2872 __le32 peer_mpdu_density;
2873 __le32 peer_rate_caps;
2874 struct wmi_rate_set peer_legacy_rates;
2875 struct wmi_rate_set peer_ht_rates;
2876 __le32 peer_nss;
2877 __le32 peer_vht_caps;
2878 __le32 peer_phymode;
2879 struct wmi_vht_rate_set peer_vht_rates;
2880
2881
2882 __le32 peer_ht_info[2];
2883} __packed;
2884
2885struct wmi_peer_assoc_complete_arg {
2886 u8 addr[ETH_ALEN];
2887 u32 vdev_id;
2888 bool peer_reassoc;
2889 u16 peer_aid;
2890 u32 peer_flags;
2891 u16 peer_caps;
2892 u32 peer_listen_intval;
2893 u32 peer_ht_caps;
2894 u32 peer_max_mpdu;
2895 u32 peer_mpdu_density;
2896 u32 peer_rate_caps;
2897 struct wmi_rate_set_arg peer_legacy_rates;
2898 struct wmi_rate_set_arg peer_ht_rates;
2899 u32 peer_num_spatial_streams;
2900 u32 peer_vht_caps;
2901 enum wmi_phy_mode peer_phymode;
2902 struct wmi_vht_rate_set_arg peer_vht_rates;
2903};
2904
2905struct wmi_peer_add_wds_entry_cmd {
2906
2907 struct wmi_mac_addr peer_macaddr;
2908
2909 struct wmi_mac_addr wds_macaddr;
2910} __packed;
2911
2912struct wmi_peer_remove_wds_entry_cmd {
2913
2914 struct wmi_mac_addr wds_macaddr;
2915} __packed;
2916
2917struct wmi_peer_q_empty_callback_event {
2918
2919 struct wmi_mac_addr peer_macaddr;
2920} __packed;
2921
2922
2923
2924
2925struct wmi_chan_info_event {
2926 __le32 err_code;
2927 __le32 freq;
2928 __le32 cmd_flags;
2929 __le32 noise_floor;
2930 __le32 rx_clear_count;
2931 __le32 cycle_count;
2932} __packed;
2933
2934#define WMI_CHAN_INFO_FLAG_COMPLETE BIT(0)
2935
2936
2937#define WMI_CHAN_INFO_MSEC(x) ((x) / 76595)
2938
2939
2940#define BCN_FLT_MAX_SUPPORTED_IES 256
2941#define BCN_FLT_MAX_ELEMS_IE_LIST (BCN_FLT_MAX_SUPPORTED_IES / 32)
2942
2943struct bss_bcn_stats {
2944 __le32 vdev_id;
2945 __le32 bss_bcnsdropped;
2946 __le32 bss_bcnsdelivered;
2947} __packed;
2948
2949struct bcn_filter_stats {
2950 __le32 bcns_dropped;
2951 __le32 bcns_delivered;
2952 __le32 activefilters;
2953 struct bss_bcn_stats bss_stats;
2954} __packed;
2955
2956struct wmi_add_bcn_filter_cmd {
2957 u32 vdev_id;
2958 u32 ie_map[BCN_FLT_MAX_ELEMS_IE_LIST];
2959} __packed;
2960
2961enum wmi_sta_keepalive_method {
2962 WMI_STA_KEEPALIVE_METHOD_NULL_FRAME = 1,
2963 WMI_STA_KEEPALIVE_METHOD_UNSOLICITATED_ARP_RESPONSE = 2,
2964};
2965
2966
2967struct wmi_sta_keepalive_arp_resp {
2968 __be32 src_ip4_addr;
2969 __be32 dest_ip4_addr;
2970 struct wmi_mac_addr dest_mac_addr;
2971} __packed;
2972
2973struct wmi_sta_keepalive_cmd {
2974 __le32 vdev_id;
2975 __le32 enabled;
2976 __le32 method;
2977 __le32 interval;
2978 struct wmi_sta_keepalive_arp_resp arp_resp;
2979} __packed;
2980
2981enum wmi_force_fw_hang_type {
2982 WMI_FORCE_FW_HANG_ASSERT = 1,
2983 WMI_FORCE_FW_HANG_NO_DETECT,
2984 WMI_FORCE_FW_HANG_CTRL_EP_FULL,
2985 WMI_FORCE_FW_HANG_EMPTY_POINT,
2986 WMI_FORCE_FW_HANG_STACK_OVERFLOW,
2987 WMI_FORCE_FW_HANG_INFINITE_LOOP,
2988};
2989
2990#define WMI_FORCE_FW_HANG_RANDOM_TIME 0xFFFFFFFF
2991
2992struct wmi_force_fw_hang_cmd {
2993 __le32 type;
2994 __le32 delay_ms;
2995} __packed;
2996
2997#define ATH10K_RTS_MAX 2347
2998#define ATH10K_FRAGMT_THRESHOLD_MIN 540
2999#define ATH10K_FRAGMT_THRESHOLD_MAX 2346
3000
3001#define WMI_MAX_EVENT 0x1000
3002
3003#define WMI_MAX_PENDING_TX_COUNT 128
3004#define WMI_SKB_HEADROOM sizeof(struct wmi_cmd_hdr)
3005
3006
3007#define ATH10K_DEFAULT_ATIM 0
3008
3009struct ath10k;
3010struct ath10k_vif;
3011
3012int ath10k_wmi_attach(struct ath10k *ar);
3013void ath10k_wmi_detach(struct ath10k *ar);
3014int ath10k_wmi_wait_for_service_ready(struct ath10k *ar);
3015int ath10k_wmi_wait_for_unified_ready(struct ath10k *ar);
3016void ath10k_wmi_flush_tx(struct ath10k *ar);
3017
3018int ath10k_wmi_connect_htc_service(struct ath10k *ar);
3019int ath10k_wmi_pdev_set_channel(struct ath10k *ar,
3020 const struct wmi_channel_arg *);
3021int ath10k_wmi_pdev_suspend_target(struct ath10k *ar);
3022int ath10k_wmi_pdev_resume_target(struct ath10k *ar);
3023int ath10k_wmi_pdev_set_regdomain(struct ath10k *ar, u16 rd, u16 rd2g,
3024 u16 rd5g, u16 ctl2g, u16 ctl5g);
3025int ath10k_wmi_pdev_set_param(struct ath10k *ar, enum wmi_pdev_param id,
3026 u32 value);
3027int ath10k_wmi_cmd_init(struct ath10k *ar);
3028int ath10k_wmi_start_scan(struct ath10k *ar, const struct wmi_start_scan_arg *);
3029void ath10k_wmi_start_scan_init(struct ath10k *ar, struct wmi_start_scan_arg *);
3030int ath10k_wmi_stop_scan(struct ath10k *ar,
3031 const struct wmi_stop_scan_arg *arg);
3032int ath10k_wmi_vdev_create(struct ath10k *ar, u32 vdev_id,
3033 enum wmi_vdev_type type,
3034 enum wmi_vdev_subtype subtype,
3035 const u8 macaddr[ETH_ALEN]);
3036int ath10k_wmi_vdev_delete(struct ath10k *ar, u32 vdev_id);
3037int ath10k_wmi_vdev_start(struct ath10k *ar,
3038 const struct wmi_vdev_start_request_arg *);
3039int ath10k_wmi_vdev_restart(struct ath10k *ar,
3040 const struct wmi_vdev_start_request_arg *);
3041int ath10k_wmi_vdev_stop(struct ath10k *ar, u32 vdev_id);
3042int ath10k_wmi_vdev_up(struct ath10k *ar, u32 vdev_id, u32 aid,
3043 const u8 *bssid);
3044int ath10k_wmi_vdev_down(struct ath10k *ar, u32 vdev_id);
3045int ath10k_wmi_vdev_set_param(struct ath10k *ar, u32 vdev_id,
3046 enum wmi_vdev_param param_id, u32 param_value);
3047int ath10k_wmi_vdev_install_key(struct ath10k *ar,
3048 const struct wmi_vdev_install_key_arg *arg);
3049int ath10k_wmi_peer_create(struct ath10k *ar, u32 vdev_id,
3050 const u8 peer_addr[ETH_ALEN]);
3051int ath10k_wmi_peer_delete(struct ath10k *ar, u32 vdev_id,
3052 const u8 peer_addr[ETH_ALEN]);
3053int ath10k_wmi_peer_flush(struct ath10k *ar, u32 vdev_id,
3054 const u8 peer_addr[ETH_ALEN], u32 tid_bitmap);
3055int ath10k_wmi_peer_set_param(struct ath10k *ar, u32 vdev_id,
3056 const u8 *peer_addr,
3057 enum wmi_peer_param param_id, u32 param_value);
3058int ath10k_wmi_peer_assoc(struct ath10k *ar,
3059 const struct wmi_peer_assoc_complete_arg *arg);
3060int ath10k_wmi_set_psmode(struct ath10k *ar, u32 vdev_id,
3061 enum wmi_sta_ps_mode psmode);
3062int ath10k_wmi_set_sta_ps_param(struct ath10k *ar, u32 vdev_id,
3063 enum wmi_sta_powersave_param param_id,
3064 u32 value);
3065int ath10k_wmi_set_ap_ps_param(struct ath10k *ar, u32 vdev_id, const u8 *mac,
3066 enum wmi_ap_ps_peer_param param_id, u32 value);
3067int ath10k_wmi_scan_chan_list(struct ath10k *ar,
3068 const struct wmi_scan_chan_list_arg *arg);
3069int ath10k_wmi_beacon_send(struct ath10k *ar, const struct wmi_bcn_tx_arg *arg);
3070int ath10k_wmi_pdev_set_wmm_params(struct ath10k *ar,
3071 const struct wmi_pdev_set_wmm_params_arg *arg);
3072int ath10k_wmi_request_stats(struct ath10k *ar, enum wmi_stats_id stats_id);
3073int ath10k_wmi_force_fw_hang(struct ath10k *ar,
3074 enum wmi_force_fw_hang_type type, u32 delay_ms);
3075
3076#endif
3077