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43#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44
45#include <linux/module.h>
46#include <linux/delay.h>
47#include <linux/dma-mapping.h>
48#include <linux/hardirq.h>
49#include <linux/if.h>
50#include <linux/io.h>
51#include <linux/netdevice.h>
52#include <linux/cache.h>
53#include <linux/ethtool.h>
54#include <linux/uaccess.h>
55#include <linux/slab.h>
56#include <linux/etherdevice.h>
57#include <linux/nl80211.h>
58
59#include <net/cfg80211.h>
60#include <net/ieee80211_radiotap.h>
61
62#include <asm/unaligned.h>
63
64#include <net/mac80211.h>
65#include "base.h"
66#include "reg.h"
67#include "debug.h"
68#include "ani.h"
69#include "ath5k.h"
70#include "../regd.h"
71
72#define CREATE_TRACE_POINTS
73#include "trace.h"
74
75bool ath5k_modparam_nohwcrypt;
76module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO);
77MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
78
79static bool modparam_fastchanswitch;
80module_param_named(fastchanswitch, modparam_fastchanswitch, bool, S_IRUGO);
81MODULE_PARM_DESC(fastchanswitch, "Enable fast channel switching for AR2413/AR5413 radios.");
82
83static bool ath5k_modparam_no_hw_rfkill_switch;
84module_param_named(no_hw_rfkill_switch, ath5k_modparam_no_hw_rfkill_switch,
85 bool, S_IRUGO);
86MODULE_PARM_DESC(no_hw_rfkill_switch, "Ignore the GPIO RFKill switch state");
87
88
89
90MODULE_AUTHOR("Jiri Slaby");
91MODULE_AUTHOR("Nick Kossifidis");
92MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
93MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
94MODULE_LICENSE("Dual BSD/GPL");
95
96static int ath5k_init(struct ieee80211_hw *hw);
97static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
98 bool skip_pcu);
99
100
101static const struct ath5k_srev_name srev_names[] = {
102#ifdef CONFIG_ATHEROS_AR231X
103 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 },
104 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 },
105 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 },
106 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 },
107 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 },
108 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 },
109 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 },
110#else
111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
129#endif
130 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
131 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
132 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
133 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
134 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
135 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
136 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
137 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
138 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
139 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
140 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
141 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
142 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
143 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
144 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
145#ifdef CONFIG_ATHEROS_AR231X
146 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
147 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
148#endif
149 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
150};
151
152static const struct ieee80211_rate ath5k_rates[] = {
153 { .bitrate = 10,
154 .hw_value = ATH5K_RATE_CODE_1M, },
155 { .bitrate = 20,
156 .hw_value = ATH5K_RATE_CODE_2M,
157 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
158 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
159 { .bitrate = 55,
160 .hw_value = ATH5K_RATE_CODE_5_5M,
161 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
162 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
163 { .bitrate = 110,
164 .hw_value = ATH5K_RATE_CODE_11M,
165 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
166 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
167 { .bitrate = 60,
168 .hw_value = ATH5K_RATE_CODE_6M,
169 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
170 IEEE80211_RATE_SUPPORTS_10MHZ },
171 { .bitrate = 90,
172 .hw_value = ATH5K_RATE_CODE_9M,
173 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
174 IEEE80211_RATE_SUPPORTS_10MHZ },
175 { .bitrate = 120,
176 .hw_value = ATH5K_RATE_CODE_12M,
177 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
178 IEEE80211_RATE_SUPPORTS_10MHZ },
179 { .bitrate = 180,
180 .hw_value = ATH5K_RATE_CODE_18M,
181 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
182 IEEE80211_RATE_SUPPORTS_10MHZ },
183 { .bitrate = 240,
184 .hw_value = ATH5K_RATE_CODE_24M,
185 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
186 IEEE80211_RATE_SUPPORTS_10MHZ },
187 { .bitrate = 360,
188 .hw_value = ATH5K_RATE_CODE_36M,
189 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
190 IEEE80211_RATE_SUPPORTS_10MHZ },
191 { .bitrate = 480,
192 .hw_value = ATH5K_RATE_CODE_48M,
193 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
194 IEEE80211_RATE_SUPPORTS_10MHZ },
195 { .bitrate = 540,
196 .hw_value = ATH5K_RATE_CODE_54M,
197 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
198 IEEE80211_RATE_SUPPORTS_10MHZ },
199};
200
201static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
202{
203 u64 tsf = ath5k_hw_get_tsf64(ah);
204
205 if ((tsf & 0x7fff) < rstamp)
206 tsf -= 0x8000;
207
208 return (tsf & ~0x7fff) | rstamp;
209}
210
211const char *
212ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
213{
214 const char *name = "xxxxx";
215 unsigned int i;
216
217 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
218 if (srev_names[i].sr_type != type)
219 continue;
220
221 if ((val & 0xf0) == srev_names[i].sr_val)
222 name = srev_names[i].sr_name;
223
224 if ((val & 0xff) == srev_names[i].sr_val) {
225 name = srev_names[i].sr_name;
226 break;
227 }
228 }
229
230 return name;
231}
232static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
233{
234 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
235 return ath5k_hw_reg_read(ah, reg_offset);
236}
237
238static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
239{
240 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
241 ath5k_hw_reg_write(ah, val, reg_offset);
242}
243
244static const struct ath_ops ath5k_common_ops = {
245 .read = ath5k_ioread32,
246 .write = ath5k_iowrite32,
247};
248
249
250
251
252
253static void ath5k_reg_notifier(struct wiphy *wiphy,
254 struct regulatory_request *request)
255{
256 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
257 struct ath5k_hw *ah = hw->priv;
258 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
259
260 ath_reg_notifier_apply(wiphy, request, regulatory);
261}
262
263
264
265
266
267
268
269
270#ifdef CONFIG_ATH5K_TEST_CHANNELS
271static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band)
272{
273 return true;
274}
275
276#else
277static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band)
278{
279 if (band == IEEE80211_BAND_2GHZ && chan <= 14)
280 return true;
281
282 return
283 (((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
284
285 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
286
287 ((chan & 3) == 1 && chan >= 149 && chan <= 165) ||
288
289 (chan == 8 || chan == 12 || chan == 16) ||
290
291 (chan == 184 || chan == 188 || chan == 192 || chan == 196));
292}
293#endif
294
295static unsigned int
296ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels,
297 unsigned int mode, unsigned int max)
298{
299 unsigned int count, size, freq, ch;
300 enum ieee80211_band band;
301
302 switch (mode) {
303 case AR5K_MODE_11A:
304
305 size = 220;
306 band = IEEE80211_BAND_5GHZ;
307 break;
308 case AR5K_MODE_11B:
309 case AR5K_MODE_11G:
310 size = 26;
311 band = IEEE80211_BAND_2GHZ;
312 break;
313 default:
314 ATH5K_WARN(ah, "bad mode, not copying channels\n");
315 return 0;
316 }
317
318 count = 0;
319 for (ch = 1; ch <= size && count < max; ch++) {
320 freq = ieee80211_channel_to_frequency(ch, band);
321
322 if (freq == 0)
323 continue;
324
325
326 channels[count].center_freq = freq;
327 channels[count].band = band;
328 channels[count].hw_value = mode;
329
330
331 if (!ath5k_channel_ok(ah, &channels[count]))
332 continue;
333
334 if (!ath5k_is_standard_channel(ch, band))
335 continue;
336
337 count++;
338 }
339
340 return count;
341}
342
343static void
344ath5k_setup_rate_idx(struct ath5k_hw *ah, struct ieee80211_supported_band *b)
345{
346 u8 i;
347
348 for (i = 0; i < AR5K_MAX_RATES; i++)
349 ah->rate_idx[b->band][i] = -1;
350
351 for (i = 0; i < b->n_bitrates; i++) {
352 ah->rate_idx[b->band][b->bitrates[i].hw_value] = i;
353 if (b->bitrates[i].hw_value_short)
354 ah->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
355 }
356}
357
358static int
359ath5k_setup_bands(struct ieee80211_hw *hw)
360{
361 struct ath5k_hw *ah = hw->priv;
362 struct ieee80211_supported_band *sband;
363 int max_c, count_c = 0;
364 int i;
365
366 BUILD_BUG_ON(ARRAY_SIZE(ah->sbands) < IEEE80211_NUM_BANDS);
367 max_c = ARRAY_SIZE(ah->channels);
368
369
370 sband = &ah->sbands[IEEE80211_BAND_2GHZ];
371 sband->band = IEEE80211_BAND_2GHZ;
372 sband->bitrates = &ah->rates[IEEE80211_BAND_2GHZ][0];
373
374 if (test_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode)) {
375
376 memcpy(sband->bitrates, &ath5k_rates[0],
377 sizeof(struct ieee80211_rate) * 12);
378 sband->n_bitrates = 12;
379
380 sband->channels = ah->channels;
381 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
382 AR5K_MODE_11G, max_c);
383
384 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
385 count_c = sband->n_channels;
386 max_c -= count_c;
387 } else if (test_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode)) {
388
389 memcpy(sband->bitrates, &ath5k_rates[0],
390 sizeof(struct ieee80211_rate) * 4);
391 sband->n_bitrates = 4;
392
393
394
395
396
397 if (ah->ah_version == AR5K_AR5211) {
398 for (i = 0; i < 4; i++) {
399 sband->bitrates[i].hw_value =
400 sband->bitrates[i].hw_value & 0xF;
401 sband->bitrates[i].hw_value_short =
402 sband->bitrates[i].hw_value_short & 0xF;
403 }
404 }
405
406 sband->channels = ah->channels;
407 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
408 AR5K_MODE_11B, max_c);
409
410 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
411 count_c = sband->n_channels;
412 max_c -= count_c;
413 }
414 ath5k_setup_rate_idx(ah, sband);
415
416
417 if (test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) {
418 sband = &ah->sbands[IEEE80211_BAND_5GHZ];
419 sband->band = IEEE80211_BAND_5GHZ;
420 sband->bitrates = &ah->rates[IEEE80211_BAND_5GHZ][0];
421
422 memcpy(sband->bitrates, &ath5k_rates[4],
423 sizeof(struct ieee80211_rate) * 8);
424 sband->n_bitrates = 8;
425
426 sband->channels = &ah->channels[count_c];
427 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
428 AR5K_MODE_11A, max_c);
429
430 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
431 }
432 ath5k_setup_rate_idx(ah, sband);
433
434 ath5k_debug_dump_bands(ah);
435
436 return 0;
437}
438
439
440
441
442
443
444
445
446int
447ath5k_chan_set(struct ath5k_hw *ah, struct cfg80211_chan_def *chandef)
448{
449 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
450 "channel set, resetting (%u -> %u MHz)\n",
451 ah->curchan->center_freq, chandef->chan->center_freq);
452
453 switch (chandef->width) {
454 case NL80211_CHAN_WIDTH_20:
455 case NL80211_CHAN_WIDTH_20_NOHT:
456 ah->ah_bwmode = AR5K_BWMODE_DEFAULT;
457 break;
458 case NL80211_CHAN_WIDTH_5:
459 ah->ah_bwmode = AR5K_BWMODE_5MHZ;
460 break;
461 case NL80211_CHAN_WIDTH_10:
462 ah->ah_bwmode = AR5K_BWMODE_10MHZ;
463 break;
464 default:
465 WARN_ON(1);
466 return -EINVAL;
467 }
468
469
470
471
472
473
474
475 return ath5k_reset(ah, chandef->chan, true);
476}
477
478void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
479{
480 struct ath5k_vif_iter_data *iter_data = data;
481 int i;
482 struct ath5k_vif *avf = (void *)vif->drv_priv;
483
484 if (iter_data->hw_macaddr)
485 for (i = 0; i < ETH_ALEN; i++)
486 iter_data->mask[i] &=
487 ~(iter_data->hw_macaddr[i] ^ mac[i]);
488
489 if (!iter_data->found_active) {
490 iter_data->found_active = true;
491 memcpy(iter_data->active_mac, mac, ETH_ALEN);
492 }
493
494 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
495 if (ether_addr_equal(iter_data->hw_macaddr, mac))
496 iter_data->need_set_hw_addr = false;
497
498 if (!iter_data->any_assoc) {
499 if (avf->assoc)
500 iter_data->any_assoc = true;
501 }
502
503
504
505
506
507
508 if (avf->opmode == NL80211_IFTYPE_AP)
509 iter_data->opmode = NL80211_IFTYPE_AP;
510 else {
511 if (avf->opmode == NL80211_IFTYPE_STATION)
512 iter_data->n_stas++;
513 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
514 iter_data->opmode = avf->opmode;
515 }
516}
517
518void
519ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah,
520 struct ieee80211_vif *vif)
521{
522 struct ath_common *common = ath5k_hw_common(ah);
523 struct ath5k_vif_iter_data iter_data;
524 u32 rfilt;
525
526
527
528
529
530 iter_data.hw_macaddr = common->macaddr;
531 memset(&iter_data.mask, 0xff, ETH_ALEN);
532 iter_data.found_active = false;
533 iter_data.need_set_hw_addr = true;
534 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
535 iter_data.n_stas = 0;
536
537 if (vif)
538 ath5k_vif_iter(&iter_data, vif->addr, vif);
539
540
541 ieee80211_iterate_active_interfaces_atomic(
542 ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
543 ath5k_vif_iter, &iter_data);
544 memcpy(ah->bssidmask, iter_data.mask, ETH_ALEN);
545
546 ah->opmode = iter_data.opmode;
547 if (ah->opmode == NL80211_IFTYPE_UNSPECIFIED)
548
549 ah->opmode = NL80211_IFTYPE_STATION;
550
551 ath5k_hw_set_opmode(ah, ah->opmode);
552 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
553 ah->opmode, ath_opmode_to_string(ah->opmode));
554
555 if (iter_data.need_set_hw_addr && iter_data.found_active)
556 ath5k_hw_set_lladdr(ah, iter_data.active_mac);
557
558 if (ath5k_hw_hasbssidmask(ah))
559 ath5k_hw_set_bssid_mask(ah, ah->bssidmask);
560
561
562 if (iter_data.n_stas > 1) {
563
564
565
566
567 ah->filter_flags |= AR5K_RX_FILTER_PROM;
568 }
569
570 rfilt = ah->filter_flags;
571 ath5k_hw_set_rx_filter(ah, rfilt);
572 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
573}
574
575static inline int
576ath5k_hw_to_driver_rix(struct ath5k_hw *ah, int hw_rix)
577{
578 int rix;
579
580
581 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
582 "hw_rix out of bounds: %x\n", hw_rix))
583 return 0;
584
585 rix = ah->rate_idx[ah->curchan->band][hw_rix];
586 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
587 rix = 0;
588
589 return rix;
590}
591
592
593
594
595
596static
597struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_hw *ah, dma_addr_t *skb_addr)
598{
599 struct ath_common *common = ath5k_hw_common(ah);
600 struct sk_buff *skb;
601
602
603
604
605
606 skb = ath_rxbuf_alloc(common,
607 common->rx_bufsize,
608 GFP_ATOMIC);
609
610 if (!skb) {
611 ATH5K_ERR(ah, "can't alloc skbuff of size %u\n",
612 common->rx_bufsize);
613 return NULL;
614 }
615
616 *skb_addr = dma_map_single(ah->dev,
617 skb->data, common->rx_bufsize,
618 DMA_FROM_DEVICE);
619
620 if (unlikely(dma_mapping_error(ah->dev, *skb_addr))) {
621 ATH5K_ERR(ah, "%s: DMA mapping failed\n", __func__);
622 dev_kfree_skb(skb);
623 return NULL;
624 }
625 return skb;
626}
627
628static int
629ath5k_rxbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
630{
631 struct sk_buff *skb = bf->skb;
632 struct ath5k_desc *ds;
633 int ret;
634
635 if (!skb) {
636 skb = ath5k_rx_skb_alloc(ah, &bf->skbaddr);
637 if (!skb)
638 return -ENOMEM;
639 bf->skb = skb;
640 }
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657 ds = bf->desc;
658 ds->ds_link = bf->daddr;
659 ds->ds_data = bf->skbaddr;
660 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
661 if (ret) {
662 ATH5K_ERR(ah, "%s: could not setup RX desc\n", __func__);
663 return ret;
664 }
665
666 if (ah->rxlink != NULL)
667 *ah->rxlink = bf->daddr;
668 ah->rxlink = &ds->ds_link;
669 return 0;
670}
671
672static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
673{
674 struct ieee80211_hdr *hdr;
675 enum ath5k_pkt_type htype;
676 __le16 fc;
677
678 hdr = (struct ieee80211_hdr *)skb->data;
679 fc = hdr->frame_control;
680
681 if (ieee80211_is_beacon(fc))
682 htype = AR5K_PKT_TYPE_BEACON;
683 else if (ieee80211_is_probe_resp(fc))
684 htype = AR5K_PKT_TYPE_PROBE_RESP;
685 else if (ieee80211_is_atim(fc))
686 htype = AR5K_PKT_TYPE_ATIM;
687 else if (ieee80211_is_pspoll(fc))
688 htype = AR5K_PKT_TYPE_PSPOLL;
689 else
690 htype = AR5K_PKT_TYPE_NORMAL;
691
692 return htype;
693}
694
695static struct ieee80211_rate *
696ath5k_get_rate(const struct ieee80211_hw *hw,
697 const struct ieee80211_tx_info *info,
698 struct ath5k_buf *bf, int idx)
699{
700
701
702
703
704 if (bf->rates[idx].idx < 0) {
705 return NULL;
706 }
707
708 return &hw->wiphy->bands[info->band]->bitrates[ bf->rates[idx].idx ];
709}
710
711static u16
712ath5k_get_rate_hw_value(const struct ieee80211_hw *hw,
713 const struct ieee80211_tx_info *info,
714 struct ath5k_buf *bf, int idx)
715{
716 struct ieee80211_rate *rate;
717 u16 hw_rate;
718 u8 rc_flags;
719
720 rate = ath5k_get_rate(hw, info, bf, idx);
721 if (!rate)
722 return 0;
723
724 rc_flags = bf->rates[idx].flags;
725 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
726 rate->hw_value_short : rate->hw_value;
727
728 return hw_rate;
729}
730
731static int
732ath5k_txbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf,
733 struct ath5k_txq *txq, int padsize,
734 struct ieee80211_tx_control *control)
735{
736 struct ath5k_desc *ds = bf->desc;
737 struct sk_buff *skb = bf->skb;
738 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
739 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
740 struct ieee80211_rate *rate;
741 unsigned int mrr_rate[3], mrr_tries[3];
742 int i, ret;
743 u16 hw_rate;
744 u16 cts_rate = 0;
745 u16 duration = 0;
746 u8 rc_flags;
747
748 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
749
750
751 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
752 DMA_TO_DEVICE);
753
754 ieee80211_get_tx_rates(info->control.vif, (control) ? control->sta : NULL, skb, bf->rates,
755 ARRAY_SIZE(bf->rates));
756
757 rate = ath5k_get_rate(ah->hw, info, bf, 0);
758
759 if (!rate) {
760 ret = -EINVAL;
761 goto err_unmap;
762 }
763
764 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
765 flags |= AR5K_TXDESC_NOACK;
766
767 rc_flags = info->control.rates[0].flags;
768
769 hw_rate = ath5k_get_rate_hw_value(ah->hw, info, bf, 0);
770
771 pktlen = skb->len;
772
773
774
775
776 if (info->control.hw_key) {
777 keyidx = info->control.hw_key->hw_key_idx;
778 pktlen += info->control.hw_key->icv_len;
779 }
780 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
781 flags |= AR5K_TXDESC_RTSENA;
782 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
783 duration = le16_to_cpu(ieee80211_rts_duration(ah->hw,
784 info->control.vif, pktlen, info));
785 }
786 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
787 flags |= AR5K_TXDESC_CTSENA;
788 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
789 duration = le16_to_cpu(ieee80211_ctstoself_duration(ah->hw,
790 info->control.vif, pktlen, info));
791 }
792
793 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
794 ieee80211_get_hdrlen_from_skb(skb), padsize,
795 get_hw_packet_type(skb),
796 (ah->ah_txpower.txp_requested * 2),
797 hw_rate,
798 bf->rates[0].count, keyidx, ah->ah_tx_ant, flags,
799 cts_rate, duration);
800 if (ret)
801 goto err_unmap;
802
803
804 if (ah->ah_capabilities.cap_has_mrr_support) {
805 memset(mrr_rate, 0, sizeof(mrr_rate));
806 memset(mrr_tries, 0, sizeof(mrr_tries));
807
808 for (i = 0; i < 3; i++) {
809
810 rate = ath5k_get_rate(ah->hw, info, bf, i);
811 if (!rate)
812 break;
813
814 mrr_rate[i] = ath5k_get_rate_hw_value(ah->hw, info, bf, i);
815 mrr_tries[i] = bf->rates[i].count;
816 }
817
818 ath5k_hw_setup_mrr_tx_desc(ah, ds,
819 mrr_rate[0], mrr_tries[0],
820 mrr_rate[1], mrr_tries[1],
821 mrr_rate[2], mrr_tries[2]);
822 }
823
824 ds->ds_link = 0;
825 ds->ds_data = bf->skbaddr;
826
827 spin_lock_bh(&txq->lock);
828 list_add_tail(&bf->list, &txq->q);
829 txq->txq_len++;
830 if (txq->link == NULL)
831 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
832 else
833 *txq->link = bf->daddr;
834
835 txq->link = &ds->ds_link;
836 ath5k_hw_start_tx_dma(ah, txq->qnum);
837 mmiowb();
838 spin_unlock_bh(&txq->lock);
839
840 return 0;
841err_unmap:
842 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
843 return ret;
844}
845
846
847
848
849
850static int
851ath5k_desc_alloc(struct ath5k_hw *ah)
852{
853 struct ath5k_desc *ds;
854 struct ath5k_buf *bf;
855 dma_addr_t da;
856 unsigned int i;
857 int ret;
858
859
860 ah->desc_len = sizeof(struct ath5k_desc) *
861 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
862
863 ah->desc = dma_alloc_coherent(ah->dev, ah->desc_len,
864 &ah->desc_daddr, GFP_KERNEL);
865 if (ah->desc == NULL) {
866 ATH5K_ERR(ah, "can't allocate descriptors\n");
867 ret = -ENOMEM;
868 goto err;
869 }
870 ds = ah->desc;
871 da = ah->desc_daddr;
872 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
873 ds, ah->desc_len, (unsigned long long)ah->desc_daddr);
874
875 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
876 sizeof(struct ath5k_buf), GFP_KERNEL);
877 if (bf == NULL) {
878 ATH5K_ERR(ah, "can't allocate bufptr\n");
879 ret = -ENOMEM;
880 goto err_free;
881 }
882 ah->bufptr = bf;
883
884 INIT_LIST_HEAD(&ah->rxbuf);
885 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
886 bf->desc = ds;
887 bf->daddr = da;
888 list_add_tail(&bf->list, &ah->rxbuf);
889 }
890
891 INIT_LIST_HEAD(&ah->txbuf);
892 ah->txbuf_len = ATH_TXBUF;
893 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
894 bf->desc = ds;
895 bf->daddr = da;
896 list_add_tail(&bf->list, &ah->txbuf);
897 }
898
899
900 INIT_LIST_HEAD(&ah->bcbuf);
901 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
902 bf->desc = ds;
903 bf->daddr = da;
904 list_add_tail(&bf->list, &ah->bcbuf);
905 }
906
907 return 0;
908err_free:
909 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
910err:
911 ah->desc = NULL;
912 return ret;
913}
914
915void
916ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
917{
918 BUG_ON(!bf);
919 if (!bf->skb)
920 return;
921 dma_unmap_single(ah->dev, bf->skbaddr, bf->skb->len,
922 DMA_TO_DEVICE);
923 ieee80211_free_txskb(ah->hw, bf->skb);
924 bf->skb = NULL;
925 bf->skbaddr = 0;
926 bf->desc->ds_data = 0;
927}
928
929void
930ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
931{
932 struct ath_common *common = ath5k_hw_common(ah);
933
934 BUG_ON(!bf);
935 if (!bf->skb)
936 return;
937 dma_unmap_single(ah->dev, bf->skbaddr, common->rx_bufsize,
938 DMA_FROM_DEVICE);
939 dev_kfree_skb_any(bf->skb);
940 bf->skb = NULL;
941 bf->skbaddr = 0;
942 bf->desc->ds_data = 0;
943}
944
945static void
946ath5k_desc_free(struct ath5k_hw *ah)
947{
948 struct ath5k_buf *bf;
949
950 list_for_each_entry(bf, &ah->txbuf, list)
951 ath5k_txbuf_free_skb(ah, bf);
952 list_for_each_entry(bf, &ah->rxbuf, list)
953 ath5k_rxbuf_free_skb(ah, bf);
954 list_for_each_entry(bf, &ah->bcbuf, list)
955 ath5k_txbuf_free_skb(ah, bf);
956
957
958 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
959 ah->desc = NULL;
960 ah->desc_daddr = 0;
961
962 kfree(ah->bufptr);
963 ah->bufptr = NULL;
964}
965
966
967
968
969
970
971static struct ath5k_txq *
972ath5k_txq_setup(struct ath5k_hw *ah,
973 int qtype, int subtype)
974{
975 struct ath5k_txq *txq;
976 struct ath5k_txq_info qi = {
977 .tqi_subtype = subtype,
978
979
980 .tqi_aifs = AR5K_TUNE_AIFS,
981 .tqi_cw_min = AR5K_TUNE_CWMIN,
982 .tqi_cw_max = AR5K_TUNE_CWMAX
983 };
984 int qnum;
985
986
987
988
989
990
991
992
993
994
995
996
997
998 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
999 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1000 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1001 if (qnum < 0) {
1002
1003
1004
1005
1006 return ERR_PTR(qnum);
1007 }
1008 txq = &ah->txqs[qnum];
1009 if (!txq->setup) {
1010 txq->qnum = qnum;
1011 txq->link = NULL;
1012 INIT_LIST_HEAD(&txq->q);
1013 spin_lock_init(&txq->lock);
1014 txq->setup = true;
1015 txq->txq_len = 0;
1016 txq->txq_max = ATH5K_TXQ_LEN_MAX;
1017 txq->txq_poll_mark = false;
1018 txq->txq_stuck = 0;
1019 }
1020 return &ah->txqs[qnum];
1021}
1022
1023static int
1024ath5k_beaconq_setup(struct ath5k_hw *ah)
1025{
1026 struct ath5k_txq_info qi = {
1027
1028
1029 .tqi_aifs = AR5K_TUNE_AIFS,
1030 .tqi_cw_min = AR5K_TUNE_CWMIN,
1031 .tqi_cw_max = AR5K_TUNE_CWMAX,
1032
1033 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1034 };
1035
1036 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1037}
1038
1039static int
1040ath5k_beaconq_config(struct ath5k_hw *ah)
1041{
1042 struct ath5k_txq_info qi;
1043 int ret;
1044
1045 ret = ath5k_hw_get_tx_queueprops(ah, ah->bhalq, &qi);
1046 if (ret)
1047 goto err;
1048
1049 if (ah->opmode == NL80211_IFTYPE_AP ||
1050 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
1051
1052
1053
1054
1055 qi.tqi_aifs = 0;
1056 qi.tqi_cw_min = 0;
1057 qi.tqi_cw_max = 0;
1058 } else if (ah->opmode == NL80211_IFTYPE_ADHOC) {
1059
1060
1061
1062 qi.tqi_aifs = 0;
1063 qi.tqi_cw_min = 0;
1064 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
1065 }
1066
1067 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1068 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1069 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1070
1071 ret = ath5k_hw_set_tx_queueprops(ah, ah->bhalq, &qi);
1072 if (ret) {
1073 ATH5K_ERR(ah, "%s: unable to update parameters for beacon "
1074 "hardware queue!\n", __func__);
1075 goto err;
1076 }
1077 ret = ath5k_hw_reset_tx_queue(ah, ah->bhalq);
1078 if (ret)
1079 goto err;
1080
1081
1082 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1083 if (ret)
1084 goto err;
1085
1086 qi.tqi_ready_time = (ah->bintval * 80) / 100;
1087 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1088 if (ret)
1089 goto err;
1090
1091 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1092err:
1093 return ret;
1094}
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107static void
1108ath5k_drain_tx_buffs(struct ath5k_hw *ah)
1109{
1110 struct ath5k_txq *txq;
1111 struct ath5k_buf *bf, *bf0;
1112 int i;
1113
1114 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
1115 if (ah->txqs[i].setup) {
1116 txq = &ah->txqs[i];
1117 spin_lock_bh(&txq->lock);
1118 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1119 ath5k_debug_printtxbuf(ah, bf);
1120
1121 ath5k_txbuf_free_skb(ah, bf);
1122
1123 spin_lock(&ah->txbuflock);
1124 list_move_tail(&bf->list, &ah->txbuf);
1125 ah->txbuf_len++;
1126 txq->txq_len--;
1127 spin_unlock(&ah->txbuflock);
1128 }
1129 txq->link = NULL;
1130 txq->txq_poll_mark = false;
1131 spin_unlock_bh(&txq->lock);
1132 }
1133 }
1134}
1135
1136static void
1137ath5k_txq_release(struct ath5k_hw *ah)
1138{
1139 struct ath5k_txq *txq = ah->txqs;
1140 unsigned int i;
1141
1142 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++, txq++)
1143 if (txq->setup) {
1144 ath5k_hw_release_tx_queue(ah, txq->qnum);
1145 txq->setup = false;
1146 }
1147}
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157static int
1158ath5k_rx_start(struct ath5k_hw *ah)
1159{
1160 struct ath_common *common = ath5k_hw_common(ah);
1161 struct ath5k_buf *bf;
1162 int ret;
1163
1164 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
1165
1166 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1167 common->cachelsz, common->rx_bufsize);
1168
1169 spin_lock_bh(&ah->rxbuflock);
1170 ah->rxlink = NULL;
1171 list_for_each_entry(bf, &ah->rxbuf, list) {
1172 ret = ath5k_rxbuf_setup(ah, bf);
1173 if (ret != 0) {
1174 spin_unlock_bh(&ah->rxbuflock);
1175 goto err;
1176 }
1177 }
1178 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
1179 ath5k_hw_set_rxdp(ah, bf->daddr);
1180 spin_unlock_bh(&ah->rxbuflock);
1181
1182 ath5k_hw_start_rx_dma(ah);
1183 ath5k_update_bssid_mask_and_opmode(ah, NULL);
1184 ath5k_hw_start_rx_pcu(ah);
1185
1186 return 0;
1187err:
1188 return ret;
1189}
1190
1191
1192
1193
1194
1195
1196
1197
1198static void
1199ath5k_rx_stop(struct ath5k_hw *ah)
1200{
1201
1202 ath5k_hw_set_rx_filter(ah, 0);
1203 ath5k_hw_stop_rx_pcu(ah);
1204
1205 ath5k_debug_printrxbuffs(ah);
1206}
1207
1208static unsigned int
1209ath5k_rx_decrypted(struct ath5k_hw *ah, struct sk_buff *skb,
1210 struct ath5k_rx_status *rs)
1211{
1212 struct ath_common *common = ath5k_hw_common(ah);
1213 struct ieee80211_hdr *hdr = (void *)skb->data;
1214 unsigned int keyix, hlen;
1215
1216 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1217 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1218 return RX_FLAG_DECRYPTED;
1219
1220
1221
1222
1223 hlen = ieee80211_hdrlen(hdr->frame_control);
1224 if (ieee80211_has_protected(hdr->frame_control) &&
1225 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1226 skb->len >= hlen + 4) {
1227 keyix = skb->data[hlen + 3] >> 6;
1228
1229 if (test_bit(keyix, common->keymap))
1230 return RX_FLAG_DECRYPTED;
1231 }
1232
1233 return 0;
1234}
1235
1236
1237static void
1238ath5k_check_ibss_tsf(struct ath5k_hw *ah, struct sk_buff *skb,
1239 struct ieee80211_rx_status *rxs)
1240{
1241 struct ath_common *common = ath5k_hw_common(ah);
1242 u64 tsf, bc_tstamp;
1243 u32 hw_tu;
1244 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1245
1246 if (ieee80211_is_beacon(mgmt->frame_control) &&
1247 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1248 ether_addr_equal(mgmt->bssid, common->curbssid)) {
1249
1250
1251
1252
1253
1254 tsf = ath5k_hw_get_tsf64(ah);
1255 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1256 hw_tu = TSF_TO_TU(tsf);
1257
1258 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1259 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1260 (unsigned long long)bc_tstamp,
1261 (unsigned long long)rxs->mactime,
1262 (unsigned long long)(rxs->mactime - bc_tstamp),
1263 (unsigned long long)tsf);
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276 if (bc_tstamp > rxs->mactime) {
1277 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1278 "fixing mactime from %llx to %llx\n",
1279 (unsigned long long)rxs->mactime,
1280 (unsigned long long)tsf);
1281 rxs->mactime = tsf;
1282 }
1283
1284
1285
1286
1287
1288
1289
1290 if (hw_tu >= ah->nexttbtt)
1291 ath5k_beacon_update_timers(ah, bc_tstamp);
1292
1293
1294
1295
1296 if (!ath5k_hw_check_beacon_timers(ah, ah->bintval)) {
1297 ath5k_beacon_update_timers(ah, bc_tstamp);
1298 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1299 "fixed beacon timers after beacon receive\n");
1300 }
1301 }
1302}
1303
1304static void
1305ath5k_update_beacon_rssi(struct ath5k_hw *ah, struct sk_buff *skb, int rssi)
1306{
1307 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1308 struct ath_common *common = ath5k_hw_common(ah);
1309
1310
1311 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1312 !ether_addr_equal(mgmt->bssid, common->curbssid))
1313 return;
1314
1315 ewma_add(&ah->ah_beacon_rssi_avg, rssi);
1316
1317
1318
1319}
1320
1321
1322
1323
1324static int ath5k_common_padpos(struct sk_buff *skb)
1325{
1326 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1327 __le16 frame_control = hdr->frame_control;
1328 int padpos = 24;
1329
1330 if (ieee80211_has_a4(frame_control))
1331 padpos += ETH_ALEN;
1332
1333 if (ieee80211_is_data_qos(frame_control))
1334 padpos += IEEE80211_QOS_CTL_LEN;
1335
1336 return padpos;
1337}
1338
1339
1340
1341
1342
1343static int ath5k_add_padding(struct sk_buff *skb)
1344{
1345 int padpos = ath5k_common_padpos(skb);
1346 int padsize = padpos & 3;
1347
1348 if (padsize && skb->len > padpos) {
1349
1350 if (skb_headroom(skb) < padsize)
1351 return -1;
1352
1353 skb_push(skb, padsize);
1354 memmove(skb->data, skb->data + padsize, padpos);
1355 return padsize;
1356 }
1357
1358 return 0;
1359}
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374static int ath5k_remove_padding(struct sk_buff *skb)
1375{
1376 int padpos = ath5k_common_padpos(skb);
1377 int padsize = padpos & 3;
1378
1379 if (padsize && skb->len >= padpos + padsize) {
1380 memmove(skb->data + padsize, skb->data, padpos);
1381 skb_pull(skb, padsize);
1382 return padsize;
1383 }
1384
1385 return 0;
1386}
1387
1388static void
1389ath5k_receive_frame(struct ath5k_hw *ah, struct sk_buff *skb,
1390 struct ath5k_rx_status *rs)
1391{
1392 struct ieee80211_rx_status *rxs;
1393
1394 ath5k_remove_padding(skb);
1395
1396 rxs = IEEE80211_SKB_RXCB(skb);
1397
1398 rxs->flag = 0;
1399 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1400 rxs->flag |= RX_FLAG_MMIC_ERROR;
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411 rxs->mactime = ath5k_extend_tsf(ah, rs->rs_tstamp);
1412 rxs->flag |= RX_FLAG_MACTIME_END;
1413
1414 rxs->freq = ah->curchan->center_freq;
1415 rxs->band = ah->curchan->band;
1416
1417 rxs->signal = ah->ah_noise_floor + rs->rs_rssi;
1418
1419 rxs->antenna = rs->rs_antenna;
1420
1421 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1422 ah->stats.antenna_rx[rs->rs_antenna]++;
1423 else
1424 ah->stats.antenna_rx[0]++;
1425
1426 rxs->rate_idx = ath5k_hw_to_driver_rix(ah, rs->rs_rate);
1427 rxs->flag |= ath5k_rx_decrypted(ah, skb, rs);
1428 switch (ah->ah_bwmode) {
1429 case AR5K_BWMODE_5MHZ:
1430 rxs->flag |= RX_FLAG_5MHZ;
1431 break;
1432 case AR5K_BWMODE_10MHZ:
1433 rxs->flag |= RX_FLAG_10MHZ;
1434 break;
1435 default:
1436 break;
1437 }
1438
1439 if (rxs->rate_idx >= 0 && rs->rs_rate ==
1440 ah->sbands[ah->curchan->band].bitrates[rxs->rate_idx].hw_value_short)
1441 rxs->flag |= RX_FLAG_SHORTPRE;
1442
1443 trace_ath5k_rx(ah, skb);
1444
1445 ath5k_update_beacon_rssi(ah, skb, rs->rs_rssi);
1446
1447
1448 if (ah->opmode == NL80211_IFTYPE_ADHOC)
1449 ath5k_check_ibss_tsf(ah, skb, rxs);
1450
1451 ieee80211_rx(ah->hw, skb);
1452}
1453
1454
1455
1456
1457
1458
1459static bool
1460ath5k_receive_frame_ok(struct ath5k_hw *ah, struct ath5k_rx_status *rs)
1461{
1462 ah->stats.rx_all_count++;
1463 ah->stats.rx_bytes_count += rs->rs_datalen;
1464
1465 if (unlikely(rs->rs_status)) {
1466 if (rs->rs_status & AR5K_RXERR_CRC)
1467 ah->stats.rxerr_crc++;
1468 if (rs->rs_status & AR5K_RXERR_FIFO)
1469 ah->stats.rxerr_fifo++;
1470 if (rs->rs_status & AR5K_RXERR_PHY) {
1471 ah->stats.rxerr_phy++;
1472 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1473 ah->stats.rxerr_phy_code[rs->rs_phyerr]++;
1474 return false;
1475 }
1476 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487 ah->stats.rxerr_decrypt++;
1488 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1489 !(rs->rs_status & AR5K_RXERR_CRC))
1490 return true;
1491 }
1492 if (rs->rs_status & AR5K_RXERR_MIC) {
1493 ah->stats.rxerr_mic++;
1494 return true;
1495 }
1496
1497
1498 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
1499 return false;
1500 }
1501
1502 if (unlikely(rs->rs_more)) {
1503 ah->stats.rxerr_jumbo++;
1504 return false;
1505 }
1506 return true;
1507}
1508
1509static void
1510ath5k_set_current_imask(struct ath5k_hw *ah)
1511{
1512 enum ath5k_int imask;
1513 unsigned long flags;
1514
1515 spin_lock_irqsave(&ah->irqlock, flags);
1516 imask = ah->imask;
1517 if (ah->rx_pending)
1518 imask &= ~AR5K_INT_RX_ALL;
1519 if (ah->tx_pending)
1520 imask &= ~AR5K_INT_TX_ALL;
1521 ath5k_hw_set_imr(ah, imask);
1522 spin_unlock_irqrestore(&ah->irqlock, flags);
1523}
1524
1525static void
1526ath5k_tasklet_rx(unsigned long data)
1527{
1528 struct ath5k_rx_status rs = {};
1529 struct sk_buff *skb, *next_skb;
1530 dma_addr_t next_skb_addr;
1531 struct ath5k_hw *ah = (void *)data;
1532 struct ath_common *common = ath5k_hw_common(ah);
1533 struct ath5k_buf *bf;
1534 struct ath5k_desc *ds;
1535 int ret;
1536
1537 spin_lock(&ah->rxbuflock);
1538 if (list_empty(&ah->rxbuf)) {
1539 ATH5K_WARN(ah, "empty rx buf pool\n");
1540 goto unlock;
1541 }
1542 do {
1543 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
1544 BUG_ON(bf->skb == NULL);
1545 skb = bf->skb;
1546 ds = bf->desc;
1547
1548
1549 if (ath5k_hw_get_rxdp(ah) == bf->daddr)
1550 break;
1551
1552 ret = ah->ah_proc_rx_desc(ah, ds, &rs);
1553 if (unlikely(ret == -EINPROGRESS))
1554 break;
1555 else if (unlikely(ret)) {
1556 ATH5K_ERR(ah, "error in processing rx descriptor\n");
1557 ah->stats.rxerr_proc++;
1558 break;
1559 }
1560
1561 if (ath5k_receive_frame_ok(ah, &rs)) {
1562 next_skb = ath5k_rx_skb_alloc(ah, &next_skb_addr);
1563
1564
1565
1566
1567
1568 if (!next_skb)
1569 goto next;
1570
1571 dma_unmap_single(ah->dev, bf->skbaddr,
1572 common->rx_bufsize,
1573 DMA_FROM_DEVICE);
1574
1575 skb_put(skb, rs.rs_datalen);
1576
1577 ath5k_receive_frame(ah, skb, &rs);
1578
1579 bf->skb = next_skb;
1580 bf->skbaddr = next_skb_addr;
1581 }
1582next:
1583 list_move_tail(&bf->list, &ah->rxbuf);
1584 } while (ath5k_rxbuf_setup(ah, bf) == 0);
1585unlock:
1586 spin_unlock(&ah->rxbuflock);
1587 ah->rx_pending = false;
1588 ath5k_set_current_imask(ah);
1589}
1590
1591
1592
1593
1594
1595
1596void
1597ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1598 struct ath5k_txq *txq, struct ieee80211_tx_control *control)
1599{
1600 struct ath5k_hw *ah = hw->priv;
1601 struct ath5k_buf *bf;
1602 unsigned long flags;
1603 int padsize;
1604
1605 trace_ath5k_tx(ah, skb, txq);
1606
1607
1608
1609
1610
1611 padsize = ath5k_add_padding(skb);
1612 if (padsize < 0) {
1613 ATH5K_ERR(ah, "tx hdrlen not %%4: not enough"
1614 " headroom to pad");
1615 goto drop_packet;
1616 }
1617
1618 if (txq->txq_len >= txq->txq_max &&
1619 txq->qnum <= AR5K_TX_QUEUE_ID_DATA_MAX)
1620 ieee80211_stop_queue(hw, txq->qnum);
1621
1622 spin_lock_irqsave(&ah->txbuflock, flags);
1623 if (list_empty(&ah->txbuf)) {
1624 ATH5K_ERR(ah, "no further txbuf available, dropping packet\n");
1625 spin_unlock_irqrestore(&ah->txbuflock, flags);
1626 ieee80211_stop_queues(hw);
1627 goto drop_packet;
1628 }
1629 bf = list_first_entry(&ah->txbuf, struct ath5k_buf, list);
1630 list_del(&bf->list);
1631 ah->txbuf_len--;
1632 if (list_empty(&ah->txbuf))
1633 ieee80211_stop_queues(hw);
1634 spin_unlock_irqrestore(&ah->txbuflock, flags);
1635
1636 bf->skb = skb;
1637
1638 if (ath5k_txbuf_setup(ah, bf, txq, padsize, control)) {
1639 bf->skb = NULL;
1640 spin_lock_irqsave(&ah->txbuflock, flags);
1641 list_add_tail(&bf->list, &ah->txbuf);
1642 ah->txbuf_len++;
1643 spin_unlock_irqrestore(&ah->txbuflock, flags);
1644 goto drop_packet;
1645 }
1646 return;
1647
1648drop_packet:
1649 ieee80211_free_txskb(hw, skb);
1650}
1651
1652static void
1653ath5k_tx_frame_completed(struct ath5k_hw *ah, struct sk_buff *skb,
1654 struct ath5k_txq *txq, struct ath5k_tx_status *ts,
1655 struct ath5k_buf *bf)
1656{
1657 struct ieee80211_tx_info *info;
1658 u8 tries[3];
1659 int i;
1660 int size = 0;
1661
1662 ah->stats.tx_all_count++;
1663 ah->stats.tx_bytes_count += skb->len;
1664 info = IEEE80211_SKB_CB(skb);
1665
1666 tries[0] = info->status.rates[0].count;
1667 tries[1] = info->status.rates[1].count;
1668 tries[2] = info->status.rates[2].count;
1669
1670 ieee80211_tx_info_clear_status(info);
1671
1672 size = min_t(int, sizeof(info->status.rates), sizeof(bf->rates));
1673 memcpy(info->status.rates, bf->rates, size);
1674
1675 for (i = 0; i < ts->ts_final_idx; i++) {
1676 struct ieee80211_tx_rate *r =
1677 &info->status.rates[i];
1678
1679 r->count = tries[i];
1680 }
1681
1682 info->status.rates[ts->ts_final_idx].count = ts->ts_final_retry;
1683 info->status.rates[ts->ts_final_idx + 1].idx = -1;
1684
1685 if (unlikely(ts->ts_status)) {
1686 ah->stats.ack_fail++;
1687 if (ts->ts_status & AR5K_TXERR_FILT) {
1688 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1689 ah->stats.txerr_filt++;
1690 }
1691 if (ts->ts_status & AR5K_TXERR_XRETRY)
1692 ah->stats.txerr_retry++;
1693 if (ts->ts_status & AR5K_TXERR_FIFO)
1694 ah->stats.txerr_fifo++;
1695 } else {
1696 info->flags |= IEEE80211_TX_STAT_ACK;
1697 info->status.ack_signal = ts->ts_rssi;
1698
1699
1700 info->status.rates[ts->ts_final_idx].count++;
1701 }
1702
1703
1704
1705
1706
1707 ath5k_remove_padding(skb);
1708
1709 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1710 ah->stats.antenna_tx[ts->ts_antenna]++;
1711 else
1712 ah->stats.antenna_tx[0]++;
1713
1714 trace_ath5k_tx_complete(ah, skb, txq, ts);
1715 ieee80211_tx_status(ah->hw, skb);
1716}
1717
1718static void
1719ath5k_tx_processq(struct ath5k_hw *ah, struct ath5k_txq *txq)
1720{
1721 struct ath5k_tx_status ts = {};
1722 struct ath5k_buf *bf, *bf0;
1723 struct ath5k_desc *ds;
1724 struct sk_buff *skb;
1725 int ret;
1726
1727 spin_lock(&txq->lock);
1728 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1729
1730 txq->txq_poll_mark = false;
1731
1732
1733 if (bf->skb != NULL) {
1734 ds = bf->desc;
1735
1736 ret = ah->ah_proc_tx_desc(ah, ds, &ts);
1737 if (unlikely(ret == -EINPROGRESS))
1738 break;
1739 else if (unlikely(ret)) {
1740 ATH5K_ERR(ah,
1741 "error %d while processing "
1742 "queue %u\n", ret, txq->qnum);
1743 break;
1744 }
1745
1746 skb = bf->skb;
1747 bf->skb = NULL;
1748
1749 dma_unmap_single(ah->dev, bf->skbaddr, skb->len,
1750 DMA_TO_DEVICE);
1751 ath5k_tx_frame_completed(ah, skb, txq, &ts, bf);
1752 }
1753
1754
1755
1756
1757
1758
1759
1760 if (ath5k_hw_get_txdp(ah, txq->qnum) != bf->daddr) {
1761 spin_lock(&ah->txbuflock);
1762 list_move_tail(&bf->list, &ah->txbuf);
1763 ah->txbuf_len++;
1764 txq->txq_len--;
1765 spin_unlock(&ah->txbuflock);
1766 }
1767 }
1768 spin_unlock(&txq->lock);
1769 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
1770 ieee80211_wake_queue(ah->hw, txq->qnum);
1771}
1772
1773static void
1774ath5k_tasklet_tx(unsigned long data)
1775{
1776 int i;
1777 struct ath5k_hw *ah = (void *)data;
1778
1779 for (i = 0; i < AR5K_NUM_TX_QUEUES; i++)
1780 if (ah->txqs[i].setup && (ah->ah_txq_isr_txok_all & BIT(i)))
1781 ath5k_tx_processq(ah, &ah->txqs[i]);
1782
1783 ah->tx_pending = false;
1784 ath5k_set_current_imask(ah);
1785}
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795static int
1796ath5k_beacon_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
1797{
1798 struct sk_buff *skb = bf->skb;
1799 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1800 struct ath5k_desc *ds;
1801 int ret = 0;
1802 u8 antenna;
1803 u32 flags;
1804 const int padsize = 0;
1805
1806 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
1807 DMA_TO_DEVICE);
1808 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1809 "skbaddr %llx\n", skb, skb->data, skb->len,
1810 (unsigned long long)bf->skbaddr);
1811
1812 if (dma_mapping_error(ah->dev, bf->skbaddr)) {
1813 ATH5K_ERR(ah, "beacon DMA mapping failed\n");
1814 dev_kfree_skb_any(skb);
1815 bf->skb = NULL;
1816 return -EIO;
1817 }
1818
1819 ds = bf->desc;
1820 antenna = ah->ah_tx_ant;
1821
1822 flags = AR5K_TXDESC_NOACK;
1823 if (ah->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
1824 ds->ds_link = bf->daddr;
1825 flags |= AR5K_TXDESC_VEOL;
1826 } else
1827 ds->ds_link = 0;
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1848 antenna = ah->bsent & 4 ? 2 : 1;
1849
1850
1851
1852
1853
1854 ds->ds_data = bf->skbaddr;
1855 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1856 ieee80211_get_hdrlen_from_skb(skb), padsize,
1857 AR5K_PKT_TYPE_BEACON,
1858 (ah->ah_txpower.txp_requested * 2),
1859 ieee80211_get_tx_rate(ah->hw, info)->hw_value,
1860 1, AR5K_TXKEYIX_INVALID,
1861 antenna, flags, 0, 0);
1862 if (ret)
1863 goto err_unmap;
1864
1865 return 0;
1866err_unmap:
1867 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
1868 return ret;
1869}
1870
1871
1872
1873
1874
1875
1876
1877
1878int
1879ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1880{
1881 int ret;
1882 struct ath5k_hw *ah = hw->priv;
1883 struct ath5k_vif *avf;
1884 struct sk_buff *skb;
1885
1886 if (WARN_ON(!vif)) {
1887 ret = -EINVAL;
1888 goto out;
1889 }
1890
1891 skb = ieee80211_beacon_get(hw, vif);
1892
1893 if (!skb) {
1894 ret = -ENOMEM;
1895 goto out;
1896 }
1897
1898 avf = (void *)vif->drv_priv;
1899 ath5k_txbuf_free_skb(ah, avf->bbuf);
1900 avf->bbuf->skb = skb;
1901 ret = ath5k_beacon_setup(ah, avf->bbuf);
1902out:
1903 return ret;
1904}
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914static void
1915ath5k_beacon_send(struct ath5k_hw *ah)
1916{
1917 struct ieee80211_vif *vif;
1918 struct ath5k_vif *avf;
1919 struct ath5k_buf *bf;
1920 struct sk_buff *skb;
1921 int err;
1922
1923 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "in beacon_send\n");
1924
1925
1926
1927
1928
1929
1930
1931
1932 if (unlikely(ath5k_hw_num_tx_pending(ah, ah->bhalq) != 0)) {
1933 ah->bmisscount++;
1934 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1935 "missed %u consecutive beacons\n", ah->bmisscount);
1936 if (ah->bmisscount > 10) {
1937 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1938 "stuck beacon time (%u missed)\n",
1939 ah->bmisscount);
1940 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
1941 "stuck beacon, resetting\n");
1942 ieee80211_queue_work(ah->hw, &ah->reset_work);
1943 }
1944 return;
1945 }
1946 if (unlikely(ah->bmisscount != 0)) {
1947 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1948 "resume beacon xmit after %u misses\n",
1949 ah->bmisscount);
1950 ah->bmisscount = 0;
1951 }
1952
1953 if ((ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs +
1954 ah->num_mesh_vifs > 1) ||
1955 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
1956 u64 tsf = ath5k_hw_get_tsf64(ah);
1957 u32 tsftu = TSF_TO_TU(tsf);
1958 int slot = ((tsftu % ah->bintval) * ATH_BCBUF) / ah->bintval;
1959 vif = ah->bslot[(slot + 1) % ATH_BCBUF];
1960 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1961 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1962 (unsigned long long)tsf, tsftu, ah->bintval, slot, vif);
1963 } else
1964 vif = ah->bslot[0];
1965
1966 if (!vif)
1967 return;
1968
1969 avf = (void *)vif->drv_priv;
1970 bf = avf->bbuf;
1971
1972
1973
1974
1975
1976
1977 if (unlikely(ath5k_hw_stop_beacon_queue(ah, ah->bhalq))) {
1978 ATH5K_WARN(ah, "beacon queue %u didn't start/stop ?\n", ah->bhalq);
1979
1980 }
1981
1982
1983 if (ah->opmode == NL80211_IFTYPE_AP ||
1984 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
1985 err = ath5k_beacon_update(ah->hw, vif);
1986 if (err)
1987 return;
1988 }
1989
1990 if (unlikely(bf->skb == NULL || ah->opmode == NL80211_IFTYPE_STATION ||
1991 ah->opmode == NL80211_IFTYPE_MONITOR)) {
1992 ATH5K_WARN(ah, "bf=%p bf_skb=%p\n", bf, bf->skb);
1993 return;
1994 }
1995
1996 trace_ath5k_tx(ah, bf->skb, &ah->txqs[ah->bhalq]);
1997
1998 ath5k_hw_set_txdp(ah, ah->bhalq, bf->daddr);
1999 ath5k_hw_start_tx_dma(ah, ah->bhalq);
2000 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2001 ah->bhalq, (unsigned long long)bf->daddr, bf->desc);
2002
2003 skb = ieee80211_get_buffered_bc(ah->hw, vif);
2004 while (skb) {
2005 ath5k_tx_queue(ah->hw, skb, ah->cabq, NULL);
2006
2007 if (ah->cabq->txq_len >= ah->cabq->txq_max)
2008 break;
2009
2010 skb = ieee80211_get_buffered_bc(ah->hw, vif);
2011 }
2012
2013 ah->bsent++;
2014}
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032void
2033ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf)
2034{
2035 u32 nexttbtt, intval, hw_tu, bc_tu;
2036 u64 hw_tsf;
2037
2038 intval = ah->bintval & AR5K_BEACON_PERIOD;
2039 if (ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs
2040 + ah->num_mesh_vifs > 1) {
2041 intval /= ATH_BCBUF;
2042 if (intval < 15)
2043 ATH5K_WARN(ah, "intval %u is too low, min 15\n",
2044 intval);
2045 }
2046 if (WARN_ON(!intval))
2047 return;
2048
2049
2050 bc_tu = TSF_TO_TU(bc_tsf);
2051
2052
2053 hw_tsf = ath5k_hw_get_tsf64(ah);
2054 hw_tu = TSF_TO_TU(hw_tsf);
2055
2056#define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3)
2057
2058
2059
2060
2061 if (bc_tsf == -1) {
2062
2063
2064
2065
2066 nexttbtt = roundup(hw_tu + FUDGE, intval);
2067 } else if (bc_tsf == 0) {
2068
2069
2070
2071
2072 nexttbtt = intval;
2073 intval |= AR5K_BEACON_RESET_TSF;
2074 } else if (bc_tsf > hw_tsf) {
2075
2076
2077
2078
2079
2080
2081
2082 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2083 "need to wait for HW TSF sync\n");
2084 return;
2085 } else {
2086
2087
2088
2089
2090
2091
2092
2093 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2094 }
2095#undef FUDGE
2096
2097 ah->nexttbtt = nexttbtt;
2098
2099 intval |= AR5K_BEACON_ENA;
2100 ath5k_hw_init_beacon_timers(ah, nexttbtt, intval);
2101
2102
2103
2104
2105
2106 if (bc_tsf == -1)
2107 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2108 "reconfigured timers based on HW TSF\n");
2109 else if (bc_tsf == 0)
2110 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2111 "reset HW TSF and timers\n");
2112 else
2113 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2114 "updated timers based on beacon TSF\n");
2115
2116 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2117 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2118 (unsigned long long) bc_tsf,
2119 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2120 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2121 intval & AR5K_BEACON_PERIOD,
2122 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2123 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2124}
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134void
2135ath5k_beacon_config(struct ath5k_hw *ah)
2136{
2137 spin_lock_bh(&ah->block);
2138 ah->bmisscount = 0;
2139 ah->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2140
2141 if (ah->enable_beacon) {
2142
2143
2144
2145
2146
2147
2148
2149 ath5k_beaconq_config(ah);
2150
2151 ah->imask |= AR5K_INT_SWBA;
2152
2153 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
2154 if (ath5k_hw_hasveol(ah))
2155 ath5k_beacon_send(ah);
2156 } else
2157 ath5k_beacon_update_timers(ah, -1);
2158 } else {
2159 ath5k_hw_stop_beacon_queue(ah, ah->bhalq);
2160 }
2161
2162 ath5k_hw_set_imr(ah, ah->imask);
2163 mmiowb();
2164 spin_unlock_bh(&ah->block);
2165}
2166
2167static void ath5k_tasklet_beacon(unsigned long data)
2168{
2169 struct ath5k_hw *ah = (struct ath5k_hw *) data;
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
2180
2181 u64 tsf = ath5k_hw_get_tsf64(ah);
2182 ah->nexttbtt += ah->bintval;
2183 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
2184 "SWBA nexttbtt: %x hw_tu: %x "
2185 "TSF: %llx\n",
2186 ah->nexttbtt,
2187 TSF_TO_TU(tsf),
2188 (unsigned long long) tsf);
2189 } else {
2190 spin_lock(&ah->block);
2191 ath5k_beacon_send(ah);
2192 spin_unlock(&ah->block);
2193 }
2194}
2195
2196
2197
2198
2199
2200
2201static void
2202ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2203{
2204 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2205 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) &&
2206 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) {
2207
2208
2209
2210 ah->ah_cal_next_ani = jiffies +
2211 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2212 tasklet_schedule(&ah->ani_tasklet);
2213
2214 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_short) &&
2215 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) &&
2216 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) {
2217
2218
2219
2220
2221
2222
2223
2224
2225 ah->ah_cal_next_short = jiffies +
2226 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT);
2227 ieee80211_queue_work(ah->hw, &ah->calib_work);
2228 }
2229
2230
2231
2232}
2233
2234static void
2235ath5k_schedule_rx(struct ath5k_hw *ah)
2236{
2237 ah->rx_pending = true;
2238 tasklet_schedule(&ah->rxtq);
2239}
2240
2241static void
2242ath5k_schedule_tx(struct ath5k_hw *ah)
2243{
2244 ah->tx_pending = true;
2245 tasklet_schedule(&ah->txtq);
2246}
2247
2248static irqreturn_t
2249ath5k_intr(int irq, void *dev_id)
2250{
2251 struct ath5k_hw *ah = dev_id;
2252 enum ath5k_int status;
2253 unsigned int counter = 1000;
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266 if (unlikely(test_bit(ATH_STAT_INVALID, ah->status) ||
2267 ((ath5k_get_bus_type(ah) != ATH_AHB) &&
2268 !ath5k_hw_is_intr_pending(ah))))
2269 return IRQ_NONE;
2270
2271
2272 do {
2273 ath5k_hw_get_isr(ah, &status);
2274
2275 ATH5K_DBG(ah, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2276 status, ah->imask);
2277
2278
2279
2280
2281
2282
2283
2284
2285 if (unlikely(status & AR5K_INT_FATAL)) {
2286
2287 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2288 "fatal int, resetting\n");
2289 ieee80211_queue_work(ah->hw, &ah->reset_work);
2290
2291
2292
2293
2294
2295
2296
2297
2298 } else if (unlikely(status & AR5K_INT_RXORN)) {
2299
2300
2301
2302
2303
2304
2305
2306 ah->stats.rxorn_intr++;
2307
2308 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2309 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2310 "rx overrun, resetting\n");
2311 ieee80211_queue_work(ah->hw, &ah->reset_work);
2312 } else
2313 ath5k_schedule_rx(ah);
2314
2315 } else {
2316
2317
2318 if (status & AR5K_INT_SWBA)
2319 tasklet_hi_schedule(&ah->beacontq);
2320
2321
2322
2323
2324
2325
2326
2327
2328 if (status & AR5K_INT_RXEOL)
2329 ah->stats.rxeol_intr++;
2330
2331
2332
2333 if (status & AR5K_INT_TXURN)
2334 ath5k_hw_update_tx_triglevel(ah, true);
2335
2336
2337 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2338 ath5k_schedule_rx(ah);
2339
2340
2341 if (status & (AR5K_INT_TXOK
2342 | AR5K_INT_TXDESC
2343 | AR5K_INT_TXERR
2344 | AR5K_INT_TXEOL))
2345 ath5k_schedule_tx(ah);
2346
2347
2348
2349
2350
2351
2352 if (status & AR5K_INT_MIB) {
2353 ah->stats.mib_intr++;
2354 ath5k_hw_update_mib_counters(ah);
2355 ath5k_ani_mib_intr(ah);
2356 }
2357
2358
2359 if (status & AR5K_INT_GPIO)
2360 tasklet_schedule(&ah->rf_kill.toggleq);
2361
2362 }
2363
2364 if (ath5k_get_bus_type(ah) == ATH_AHB)
2365 break;
2366
2367 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2368
2369
2370
2371
2372
2373
2374
2375 if (ah->rx_pending || ah->tx_pending)
2376 ath5k_set_current_imask(ah);
2377
2378 if (unlikely(!counter))
2379 ATH5K_WARN(ah, "too many interrupts, giving up for now\n");
2380
2381
2382 ath5k_intr_calibration_poll(ah);
2383
2384 return IRQ_HANDLED;
2385}
2386
2387
2388
2389
2390
2391static void
2392ath5k_calibrate_work(struct work_struct *work)
2393{
2394 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2395 calib_work);
2396
2397
2398 if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
2399
2400 ah->ah_cal_next_full = jiffies +
2401 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2402 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
2403
2404 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
2405 "running full calibration\n");
2406
2407 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2408
2409
2410
2411
2412 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2413 "got new rfgain, resetting\n");
2414 ieee80211_queue_work(ah->hw, &ah->reset_work);
2415 }
2416 } else
2417 ah->ah_cal_mask |= AR5K_CALIBRATION_SHORT;
2418
2419
2420 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2421 ieee80211_frequency_to_channel(ah->curchan->center_freq),
2422 ah->curchan->hw_value);
2423
2424 if (ath5k_hw_phy_calibrate(ah, ah->curchan))
2425 ATH5K_ERR(ah, "calibration of channel %u failed\n",
2426 ieee80211_frequency_to_channel(
2427 ah->curchan->center_freq));
2428
2429
2430 if (ah->ah_cal_mask & AR5K_CALIBRATION_FULL)
2431 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
2432 else if (ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)
2433 ah->ah_cal_mask &= ~AR5K_CALIBRATION_SHORT;
2434}
2435
2436
2437static void
2438ath5k_tasklet_ani(unsigned long data)
2439{
2440 struct ath5k_hw *ah = (void *)data;
2441
2442 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2443 ath5k_ani_calibration(ah);
2444 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
2445}
2446
2447
2448static void
2449ath5k_tx_complete_poll_work(struct work_struct *work)
2450{
2451 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2452 tx_complete_work.work);
2453 struct ath5k_txq *txq;
2454 int i;
2455 bool needreset = false;
2456
2457 if (!test_bit(ATH_STAT_STARTED, ah->status))
2458 return;
2459
2460 mutex_lock(&ah->lock);
2461
2462 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
2463 if (ah->txqs[i].setup) {
2464 txq = &ah->txqs[i];
2465 spin_lock_bh(&txq->lock);
2466 if (txq->txq_len > 1) {
2467 if (txq->txq_poll_mark) {
2468 ATH5K_DBG(ah, ATH5K_DEBUG_XMIT,
2469 "TX queue stuck %d\n",
2470 txq->qnum);
2471 needreset = true;
2472 txq->txq_stuck++;
2473 spin_unlock_bh(&txq->lock);
2474 break;
2475 } else {
2476 txq->txq_poll_mark = true;
2477 }
2478 }
2479 spin_unlock_bh(&txq->lock);
2480 }
2481 }
2482
2483 if (needreset) {
2484 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2485 "TX queues stuck, resetting\n");
2486 ath5k_reset(ah, NULL, true);
2487 }
2488
2489 mutex_unlock(&ah->lock);
2490
2491 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
2492 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2493}
2494
2495
2496
2497
2498
2499
2500static const struct ieee80211_iface_limit if_limits[] = {
2501 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) },
2502 { .max = 4, .types =
2503#ifdef CONFIG_MAC80211_MESH
2504 BIT(NL80211_IFTYPE_MESH_POINT) |
2505#endif
2506 BIT(NL80211_IFTYPE_AP) },
2507};
2508
2509static const struct ieee80211_iface_combination if_comb = {
2510 .limits = if_limits,
2511 .n_limits = ARRAY_SIZE(if_limits),
2512 .max_interfaces = 2048,
2513 .num_different_channels = 1,
2514};
2515
2516int
2517ath5k_init_ah(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops)
2518{
2519 struct ieee80211_hw *hw = ah->hw;
2520 struct ath_common *common;
2521 int ret;
2522 int csz;
2523
2524
2525 SET_IEEE80211_DEV(hw, ah->dev);
2526 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
2527 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2528 IEEE80211_HW_SIGNAL_DBM |
2529 IEEE80211_HW_MFP_CAPABLE |
2530 IEEE80211_HW_REPORTS_TX_ACK_STATUS |
2531 IEEE80211_HW_SUPPORTS_RC_TABLE;
2532
2533 hw->wiphy->interface_modes =
2534 BIT(NL80211_IFTYPE_AP) |
2535 BIT(NL80211_IFTYPE_STATION) |
2536 BIT(NL80211_IFTYPE_ADHOC) |
2537 BIT(NL80211_IFTYPE_MESH_POINT);
2538
2539 hw->wiphy->iface_combinations = &if_comb;
2540 hw->wiphy->n_iface_combinations = 1;
2541
2542
2543 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
2544
2545 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
2546
2547
2548 hw->wiphy->available_antennas_tx = 0x3;
2549 hw->wiphy->available_antennas_rx = 0x3;
2550
2551 hw->extra_tx_headroom = 2;
2552 hw->channel_change_time = 5000;
2553
2554
2555
2556
2557
2558 __set_bit(ATH_STAT_INVALID, ah->status);
2559
2560 ah->opmode = NL80211_IFTYPE_STATION;
2561 ah->bintval = 1000;
2562 mutex_init(&ah->lock);
2563 spin_lock_init(&ah->rxbuflock);
2564 spin_lock_init(&ah->txbuflock);
2565 spin_lock_init(&ah->block);
2566 spin_lock_init(&ah->irqlock);
2567
2568
2569 ret = request_irq(ah->irq, ath5k_intr, IRQF_SHARED, "ath", ah);
2570 if (ret) {
2571 ATH5K_ERR(ah, "request_irq failed\n");
2572 goto err;
2573 }
2574
2575 common = ath5k_hw_common(ah);
2576 common->ops = &ath5k_common_ops;
2577 common->bus_ops = bus_ops;
2578 common->ah = ah;
2579 common->hw = hw;
2580 common->priv = ah;
2581 common->clockrate = 40;
2582
2583
2584
2585
2586
2587 ath5k_read_cachesize(common, &csz);
2588 common->cachelsz = csz << 2;
2589
2590 spin_lock_init(&common->cc_lock);
2591
2592
2593 ret = ath5k_hw_init(ah);
2594 if (ret)
2595 goto err_irq;
2596
2597
2598 if (ah->ah_capabilities.cap_has_mrr_support) {
2599 hw->max_rates = 4;
2600 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT,
2601 AR5K_INIT_RETRY_LONG);
2602 }
2603
2604 hw->vif_data_size = sizeof(struct ath5k_vif);
2605
2606
2607 ret = ath5k_init(hw);
2608 if (ret)
2609 goto err_ah;
2610
2611 ATH5K_INFO(ah, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2612 ath5k_chip_name(AR5K_VERSION_MAC, ah->ah_mac_srev),
2613 ah->ah_mac_srev,
2614 ah->ah_phy_revision);
2615
2616 if (!ah->ah_single_chip) {
2617
2618 if (ah->ah_radio_5ghz_revision &&
2619 !ah->ah_radio_2ghz_revision) {
2620
2621 if (!test_bit(AR5K_MODE_11A,
2622 ah->ah_capabilities.cap_mode)) {
2623 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
2624 ath5k_chip_name(AR5K_VERSION_RAD,
2625 ah->ah_radio_5ghz_revision),
2626 ah->ah_radio_5ghz_revision);
2627
2628
2629 } else if (!test_bit(AR5K_MODE_11B,
2630 ah->ah_capabilities.cap_mode)) {
2631 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
2632 ath5k_chip_name(AR5K_VERSION_RAD,
2633 ah->ah_radio_5ghz_revision),
2634 ah->ah_radio_5ghz_revision);
2635
2636 } else {
2637 ATH5K_INFO(ah, "RF%s multiband radio found"
2638 " (0x%x)\n",
2639 ath5k_chip_name(AR5K_VERSION_RAD,
2640 ah->ah_radio_5ghz_revision),
2641 ah->ah_radio_5ghz_revision);
2642 }
2643 }
2644
2645
2646 else if (ah->ah_radio_5ghz_revision &&
2647 ah->ah_radio_2ghz_revision) {
2648 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
2649 ath5k_chip_name(AR5K_VERSION_RAD,
2650 ah->ah_radio_5ghz_revision),
2651 ah->ah_radio_5ghz_revision);
2652 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
2653 ath5k_chip_name(AR5K_VERSION_RAD,
2654 ah->ah_radio_2ghz_revision),
2655 ah->ah_radio_2ghz_revision);
2656 }
2657 }
2658
2659 ath5k_debug_init_device(ah);
2660
2661
2662 __clear_bit(ATH_STAT_INVALID, ah->status);
2663
2664 return 0;
2665err_ah:
2666 ath5k_hw_deinit(ah);
2667err_irq:
2668 free_irq(ah->irq, ah);
2669err:
2670 return ret;
2671}
2672
2673static int
2674ath5k_stop_locked(struct ath5k_hw *ah)
2675{
2676
2677 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "invalid %u\n",
2678 test_bit(ATH_STAT_INVALID, ah->status));
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695 ieee80211_stop_queues(ah->hw);
2696
2697 if (!test_bit(ATH_STAT_INVALID, ah->status)) {
2698 ath5k_led_off(ah);
2699 ath5k_hw_set_imr(ah, 0);
2700 synchronize_irq(ah->irq);
2701 ath5k_rx_stop(ah);
2702 ath5k_hw_dma_stop(ah);
2703 ath5k_drain_tx_buffs(ah);
2704 ath5k_hw_phy_disable(ah);
2705 }
2706
2707 return 0;
2708}
2709
2710int ath5k_start(struct ieee80211_hw *hw)
2711{
2712 struct ath5k_hw *ah = hw->priv;
2713 struct ath_common *common = ath5k_hw_common(ah);
2714 int ret, i;
2715
2716 mutex_lock(&ah->lock);
2717
2718 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "mode %d\n", ah->opmode);
2719
2720
2721
2722
2723
2724 ath5k_stop_locked(ah);
2725
2726
2727
2728
2729
2730
2731
2732
2733 ah->curchan = ah->hw->conf.chandef.chan;
2734 ah->imask = AR5K_INT_RXOK
2735 | AR5K_INT_RXERR
2736 | AR5K_INT_RXEOL
2737 | AR5K_INT_RXORN
2738 | AR5K_INT_TXDESC
2739 | AR5K_INT_TXEOL
2740 | AR5K_INT_FATAL
2741 | AR5K_INT_GLOBAL
2742 | AR5K_INT_MIB;
2743
2744 ret = ath5k_reset(ah, NULL, false);
2745 if (ret)
2746 goto done;
2747
2748 if (!ath5k_modparam_no_hw_rfkill_switch)
2749 ath5k_rfkill_hw_start(ah);
2750
2751
2752
2753
2754
2755 for (i = 0; i < common->keymax; i++)
2756 ath_hw_keyreset(common, (u16) i);
2757
2758
2759
2760 ah->ah_ack_bitrate_high = true;
2761
2762 for (i = 0; i < ARRAY_SIZE(ah->bslot); i++)
2763 ah->bslot[i] = NULL;
2764
2765 ret = 0;
2766done:
2767 mmiowb();
2768 mutex_unlock(&ah->lock);
2769
2770 set_bit(ATH_STAT_STARTED, ah->status);
2771 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
2772 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2773
2774 return ret;
2775}
2776
2777static void ath5k_stop_tasklets(struct ath5k_hw *ah)
2778{
2779 ah->rx_pending = false;
2780 ah->tx_pending = false;
2781 tasklet_kill(&ah->rxtq);
2782 tasklet_kill(&ah->txtq);
2783 tasklet_kill(&ah->beacontq);
2784 tasklet_kill(&ah->ani_tasklet);
2785}
2786
2787
2788
2789
2790
2791
2792
2793void ath5k_stop(struct ieee80211_hw *hw)
2794{
2795 struct ath5k_hw *ah = hw->priv;
2796 int ret;
2797
2798 mutex_lock(&ah->lock);
2799 ret = ath5k_stop_locked(ah);
2800 if (ret == 0 && !test_bit(ATH_STAT_INVALID, ah->status)) {
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821 ret = ath5k_hw_on_hold(ah);
2822
2823 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2824 "putting device to sleep\n");
2825 }
2826
2827 mmiowb();
2828 mutex_unlock(&ah->lock);
2829
2830 ath5k_stop_tasklets(ah);
2831
2832 clear_bit(ATH_STAT_STARTED, ah->status);
2833 cancel_delayed_work_sync(&ah->tx_complete_work);
2834
2835 if (!ath5k_modparam_no_hw_rfkill_switch)
2836 ath5k_rfkill_hw_stop(ah);
2837}
2838
2839
2840
2841
2842
2843
2844
2845static int
2846ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
2847 bool skip_pcu)
2848{
2849 struct ath_common *common = ath5k_hw_common(ah);
2850 int ret, ani_mode;
2851 bool fast;
2852
2853 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "resetting\n");
2854
2855 ath5k_hw_set_imr(ah, 0);
2856 synchronize_irq(ah->irq);
2857 ath5k_stop_tasklets(ah);
2858
2859
2860
2861
2862 ani_mode = ah->ani_state.ani_mode;
2863 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
2864
2865
2866
2867
2868 ath5k_drain_tx_buffs(ah);
2869 if (chan)
2870 ah->curchan = chan;
2871
2872 fast = ((chan != NULL) && modparam_fastchanswitch) ? 1 : 0;
2873
2874 ret = ath5k_hw_reset(ah, ah->opmode, ah->curchan, fast, skip_pcu);
2875 if (ret) {
2876 ATH5K_ERR(ah, "can't reset hardware (%d)\n", ret);
2877 goto err;
2878 }
2879
2880 ret = ath5k_rx_start(ah);
2881 if (ret) {
2882 ATH5K_ERR(ah, "can't start recv logic\n");
2883 goto err;
2884 }
2885
2886 ath5k_ani_init(ah, ani_mode);
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899 ah->ah_cal_next_full = jiffies +
2900 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2901 ah->ah_cal_next_ani = jiffies +
2902 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2903 ah->ah_cal_next_short = jiffies +
2904 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT);
2905
2906 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
2907
2908
2909 memset(&ah->survey, 0, sizeof(ah->survey));
2910 spin_lock_bh(&common->cc_lock);
2911 ath_hw_cycle_counters_update(common);
2912 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
2913 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
2914 spin_unlock_bh(&common->cc_lock);
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927 ath5k_beacon_config(ah);
2928
2929
2930 ieee80211_wake_queues(ah->hw);
2931
2932 return 0;
2933err:
2934 return ret;
2935}
2936
2937static void ath5k_reset_work(struct work_struct *work)
2938{
2939 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2940 reset_work);
2941
2942 mutex_lock(&ah->lock);
2943 ath5k_reset(ah, NULL, true);
2944 mutex_unlock(&ah->lock);
2945}
2946
2947static int
2948ath5k_init(struct ieee80211_hw *hw)
2949{
2950
2951 struct ath5k_hw *ah = hw->priv;
2952 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2953 struct ath5k_txq *txq;
2954 u8 mac[ETH_ALEN] = {};
2955 int ret;
2956
2957
2958
2959
2960
2961
2962
2963
2964 ret = ath5k_setup_bands(hw);
2965 if (ret) {
2966 ATH5K_ERR(ah, "can't get channels\n");
2967 goto err;
2968 }
2969
2970
2971
2972
2973 ret = ath5k_desc_alloc(ah);
2974 if (ret) {
2975 ATH5K_ERR(ah, "can't allocate descriptors\n");
2976 goto err;
2977 }
2978
2979
2980
2981
2982
2983
2984
2985 ret = ath5k_beaconq_setup(ah);
2986 if (ret < 0) {
2987 ATH5K_ERR(ah, "can't setup a beacon xmit queue\n");
2988 goto err_desc;
2989 }
2990 ah->bhalq = ret;
2991 ah->cabq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_CAB, 0);
2992 if (IS_ERR(ah->cabq)) {
2993 ATH5K_ERR(ah, "can't setup cab queue\n");
2994 ret = PTR_ERR(ah->cabq);
2995 goto err_bhal;
2996 }
2997
2998
2999
3000 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
3001
3002
3003 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
3004 if (IS_ERR(txq)) {
3005 ATH5K_ERR(ah, "can't setup xmit queue\n");
3006 ret = PTR_ERR(txq);
3007 goto err_queues;
3008 }
3009 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
3010 if (IS_ERR(txq)) {
3011 ATH5K_ERR(ah, "can't setup xmit queue\n");
3012 ret = PTR_ERR(txq);
3013 goto err_queues;
3014 }
3015 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
3016 if (IS_ERR(txq)) {
3017 ATH5K_ERR(ah, "can't setup xmit queue\n");
3018 ret = PTR_ERR(txq);
3019 goto err_queues;
3020 }
3021 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
3022 if (IS_ERR(txq)) {
3023 ATH5K_ERR(ah, "can't setup xmit queue\n");
3024 ret = PTR_ERR(txq);
3025 goto err_queues;
3026 }
3027 hw->queues = 4;
3028 } else {
3029
3030 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
3031 if (IS_ERR(txq)) {
3032 ATH5K_ERR(ah, "can't setup xmit queue\n");
3033 ret = PTR_ERR(txq);
3034 goto err_queues;
3035 }
3036 hw->queues = 1;
3037 }
3038
3039 tasklet_init(&ah->rxtq, ath5k_tasklet_rx, (unsigned long)ah);
3040 tasklet_init(&ah->txtq, ath5k_tasklet_tx, (unsigned long)ah);
3041 tasklet_init(&ah->beacontq, ath5k_tasklet_beacon, (unsigned long)ah);
3042 tasklet_init(&ah->ani_tasklet, ath5k_tasklet_ani, (unsigned long)ah);
3043
3044 INIT_WORK(&ah->reset_work, ath5k_reset_work);
3045 INIT_WORK(&ah->calib_work, ath5k_calibrate_work);
3046 INIT_DELAYED_WORK(&ah->tx_complete_work, ath5k_tx_complete_poll_work);
3047
3048 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac);
3049 if (ret) {
3050 ATH5K_ERR(ah, "unable to read address from EEPROM\n");
3051 goto err_queues;
3052 }
3053
3054 SET_IEEE80211_PERM_ADDR(hw, mac);
3055
3056 ath5k_update_bssid_mask_and_opmode(ah, NULL);
3057
3058 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
3059 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
3060 if (ret) {
3061 ATH5K_ERR(ah, "can't initialize regulatory system\n");
3062 goto err_queues;
3063 }
3064
3065 ret = ieee80211_register_hw(hw);
3066 if (ret) {
3067 ATH5K_ERR(ah, "can't register ieee80211 hw\n");
3068 goto err_queues;
3069 }
3070
3071 if (!ath_is_world_regd(regulatory))
3072 regulatory_hint(hw->wiphy, regulatory->alpha2);
3073
3074 ath5k_init_leds(ah);
3075
3076 ath5k_sysfs_register(ah);
3077
3078 return 0;
3079err_queues:
3080 ath5k_txq_release(ah);
3081err_bhal:
3082 ath5k_hw_release_tx_queue(ah, ah->bhalq);
3083err_desc:
3084 ath5k_desc_free(ah);
3085err:
3086 return ret;
3087}
3088
3089void
3090ath5k_deinit_ah(struct ath5k_hw *ah)
3091{
3092 struct ieee80211_hw *hw = ah->hw;
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107 ieee80211_unregister_hw(hw);
3108 ath5k_desc_free(ah);
3109 ath5k_txq_release(ah);
3110 ath5k_hw_release_tx_queue(ah, ah->bhalq);
3111 ath5k_unregister_leds(ah);
3112
3113 ath5k_sysfs_unregister(ah);
3114
3115
3116
3117
3118
3119 ath5k_hw_deinit(ah);
3120 free_irq(ah->irq, ah);
3121}
3122
3123bool
3124ath5k_any_vif_assoc(struct ath5k_hw *ah)
3125{
3126 struct ath5k_vif_iter_data iter_data;
3127 iter_data.hw_macaddr = NULL;
3128 iter_data.any_assoc = false;
3129 iter_data.need_set_hw_addr = false;
3130 iter_data.found_active = true;
3131
3132 ieee80211_iterate_active_interfaces_atomic(
3133 ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
3134 ath5k_vif_iter, &iter_data);
3135 return iter_data.any_assoc;
3136}
3137
3138void
3139ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3140{
3141 struct ath5k_hw *ah = hw->priv;
3142 u32 rfilt;
3143 rfilt = ath5k_hw_get_rx_filter(ah);
3144 if (enable)
3145 rfilt |= AR5K_RX_FILTER_BEACON;
3146 else
3147 rfilt &= ~AR5K_RX_FILTER_BEACON;
3148 ath5k_hw_set_rx_filter(ah, rfilt);
3149 ah->filter_flags = rfilt;
3150}
3151
3152void _ath5k_printk(const struct ath5k_hw *ah, const char *level,
3153 const char *fmt, ...)
3154{
3155 struct va_format vaf;
3156 va_list args;
3157
3158 va_start(args, fmt);
3159
3160 vaf.fmt = fmt;
3161 vaf.va = &args;
3162
3163 if (ah && ah->hw)
3164 printk("%s" pr_fmt("%s: %pV"),
3165 level, wiphy_name(ah->hw->wiphy), &vaf);
3166 else
3167 printk("%s" pr_fmt("%pV"), level, &vaf);
3168
3169 va_end(args);
3170}
3171