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17#ifndef DEBUG_H
18#define DEBUG_H
19
20#include "hw.h"
21#include "rc.h"
22#include "dfs_debug.h"
23
24struct ath_txq;
25struct ath_buf;
26struct fft_sample_tlv;
27
28#ifdef CONFIG_ATH9K_DEBUGFS
29#define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++
30#define RESET_STAT_INC(sc, type) sc->debug.stats.reset[type]++
31#define ANT_STAT_INC(i, c) sc->debug.stats.ant_stats[i].c++
32#define ANT_LNA_INC(i, c) sc->debug.stats.ant_stats[i].lna_recv_cnt[c]++;
33#else
34#define TX_STAT_INC(q, c) do { } while (0)
35#define RESET_STAT_INC(sc, type) do { } while (0)
36#define ANT_STAT_INC(i, c) do { } while (0)
37#define ANT_LNA_INC(i, c) do { } while (0)
38#endif
39
40enum ath_reset_type {
41 RESET_TYPE_BB_HANG,
42 RESET_TYPE_BB_WATCHDOG,
43 RESET_TYPE_FATAL_INT,
44 RESET_TYPE_TX_ERROR,
45 RESET_TYPE_TX_HANG,
46 RESET_TYPE_PLL_HANG,
47 RESET_TYPE_MAC_HANG,
48 RESET_TYPE_BEACON_STUCK,
49 RESET_TYPE_MCI,
50 __RESET_TYPE_MAX
51};
52
53#ifdef CONFIG_ATH9K_DEBUGFS
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85struct ath_interrupt_stats {
86 u32 total;
87 u32 rxok;
88 u32 rxlp;
89 u32 rxhp;
90 u32 rxeol;
91 u32 rxorn;
92 u32 txok;
93 u32 txeol;
94 u32 txurn;
95 u32 mib;
96 u32 rxphyerr;
97 u32 rx_keycache_miss;
98 u32 swba;
99 u32 bmiss;
100 u32 bnr;
101 u32 cst;
102 u32 gtt;
103 u32 tim;
104 u32 cabend;
105 u32 dtimsync;
106 u32 dtim;
107 u32 bb_watchdog;
108 u32 tsfoor;
109 u32 mci;
110 u32 gen_timer;
111
112
113 u32 sync_cause_all;
114 u32 sync_rtc_irq;
115 u32 sync_mac_irq;
116 u32 eeprom_illegal_access;
117 u32 apb_timeout;
118 u32 pci_mode_conflict;
119 u32 host1_fatal;
120 u32 host1_perr;
121 u32 trcv_fifo_perr;
122 u32 radm_cpl_ep;
123 u32 radm_cpl_dllp_abort;
124 u32 radm_cpl_tlp_abort;
125 u32 radm_cpl_ecrc_err;
126 u32 radm_cpl_timeout;
127 u32 local_timeout;
128 u32 pm_access;
129 u32 mac_awake;
130 u32 mac_asleep;
131 u32 mac_sleep_access;
132};
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164struct ath_tx_stats {
165 u32 tx_pkts_all;
166 u32 tx_bytes_all;
167 u32 queued;
168 u32 completed;
169 u32 xretries;
170 u32 a_aggr;
171 u32 a_queued_hw;
172 u32 a_queued_sw;
173 u32 a_completed;
174 u32 a_retries;
175 u32 a_xretries;
176 u32 txerr_filtered;
177 u32 fifo_underrun;
178 u32 xtxop;
179 u32 timer_exp;
180 u32 desc_cfg_err;
181 u32 data_underrun;
182 u32 delim_underrun;
183 u32 puttxbuf;
184 u32 txstart;
185 u32 txprocdesc;
186 u32 txfailed;
187};
188
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190
191
192#define PR_QNUM(_n) sc->tx.txq_map[_n]->axq_qnum
193#define TXSTATS sc->debug.stats.txstats
194#define PR(str, elem) \
195 do { \
196 len += snprintf(buf + len, size - len, \
197 "%s%13u%11u%10u%10u\n", str, \
198 TXSTATS[PR_QNUM(IEEE80211_AC_BE)].elem, \
199 TXSTATS[PR_QNUM(IEEE80211_AC_BK)].elem, \
200 TXSTATS[PR_QNUM(IEEE80211_AC_VI)].elem, \
201 TXSTATS[PR_QNUM(IEEE80211_AC_VO)].elem); \
202 } while(0)
203
204#define RX_STAT_INC(c) (sc->debug.stats.rxstats.c++)
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230struct ath_rx_stats {
231 u32 rx_pkts_all;
232 u32 rx_bytes_all;
233 u32 crc_err;
234 u32 decrypt_crc_err;
235 u32 phy_err;
236 u32 mic_err;
237 u32 pre_delim_crc_err;
238 u32 post_delim_crc_err;
239 u32 decrypt_busy_err;
240 u32 phy_err_stats[ATH9K_PHYERR_MAX];
241 u32 rx_len_err;
242 u32 rx_oom_err;
243 u32 rx_rate_err;
244 u32 rx_too_many_frags_err;
245 u32 rx_beacons;
246 u32 rx_frags;
247 u32 rx_spectral;
248};
249
250#define ANT_MAIN 0
251#define ANT_ALT 1
252
253struct ath_antenna_stats {
254 u32 recv_cnt;
255 u32 rssi_avg;
256 u32 lna_recv_cnt[4];
257 u32 lna_attempt_cnt[4];
258};
259
260struct ath_stats {
261 struct ath_interrupt_stats istats;
262 struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
263 struct ath_rx_stats rxstats;
264 struct ath_dfs_stats dfs_stats;
265 struct ath_antenna_stats ant_stats[2];
266 u32 reset[__RESET_TYPE_MAX];
267};
268
269struct ath9k_debug {
270 struct dentry *debugfs_phy;
271 u32 regidx;
272 struct ath_stats stats;
273};
274
275int ath9k_init_debug(struct ath_hw *ah);
276void ath9k_deinit_debug(struct ath_softc *sc);
277
278void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
279void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
280 struct ath_tx_status *ts, struct ath_txq *txq,
281 unsigned int flags);
282void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs);
283int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
284 struct ieee80211_vif *vif, int sset);
285void ath9k_get_et_stats(struct ieee80211_hw *hw,
286 struct ieee80211_vif *vif,
287 struct ethtool_stats *stats, u64 *data);
288void ath9k_get_et_strings(struct ieee80211_hw *hw,
289 struct ieee80211_vif *vif,
290 u32 sset, u8 *data);
291void ath9k_sta_add_debugfs(struct ieee80211_hw *hw,
292 struct ieee80211_vif *vif,
293 struct ieee80211_sta *sta,
294 struct dentry *dir);
295void ath_debug_send_fft_sample(struct ath_softc *sc,
296 struct fft_sample_tlv *fft_sample);
297void ath9k_debug_stat_ant(struct ath_softc *sc,
298 struct ath_hw_antcomb_conf *div_ant_conf,
299 int main_rssi_avg, int alt_rssi_avg);
300#else
301
302#define RX_STAT_INC(c)
303
304static inline int ath9k_init_debug(struct ath_hw *ah)
305{
306 return 0;
307}
308
309static inline void ath9k_deinit_debug(struct ath_softc *sc)
310{
311}
312static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
313 enum ath9k_int status)
314{
315}
316static inline void ath_debug_stat_tx(struct ath_softc *sc,
317 struct ath_buf *bf,
318 struct ath_tx_status *ts,
319 struct ath_txq *txq,
320 unsigned int flags)
321{
322}
323static inline void ath_debug_stat_rx(struct ath_softc *sc,
324 struct ath_rx_status *rs)
325{
326}
327static inline void ath9k_debug_stat_ant(struct ath_softc *sc,
328 struct ath_hw_antcomb_conf *div_ant_conf,
329 int main_rssi_avg, int alt_rssi_avg)
330{
331
332}
333
334#endif
335
336#endif
337