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30#include "../wifi.h"
31#include "../pci.h"
32#include "../ps.h"
33#include "reg.h"
34#include "def.h"
35#include "hw.h"
36#include "phy.h"
37#include "rf.h"
38#include "dm.h"
39#include "table.h"
40
41static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
42
43u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw,
44 enum radio_path rfpath, u32 regaddr, u32 bitmask)
45{
46 struct rtl_priv *rtlpriv = rtl_priv(hw);
47 u32 original_value, readback_value, bitshift;
48 struct rtl_phy *rtlphy = &(rtlpriv->phy);
49
50 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
51 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
52 regaddr, rfpath, bitmask);
53
54 spin_lock(&rtlpriv->locks.rf_lock);
55
56 if (rtlphy->rf_mode != RF_OP_BY_FW) {
57 original_value = _rtl92c_phy_rf_serial_read(hw,
58 rfpath, regaddr);
59 } else {
60 original_value = _rtl92c_phy_fw_rf_serial_read(hw,
61 rfpath, regaddr);
62 }
63
64 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
65 readback_value = (original_value & bitmask) >> bitshift;
66
67 spin_unlock(&rtlpriv->locks.rf_lock);
68
69 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
70 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
71 regaddr, rfpath, bitmask, original_value);
72
73 return readback_value;
74}
75
76bool rtl92c_phy_mac_config(struct ieee80211_hw *hw)
77{
78 struct rtl_priv *rtlpriv = rtl_priv(hw);
79 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
80 bool is92c = IS_92C_SERIAL(rtlhal->version);
81 bool rtstatus = _rtl92c_phy_config_mac_with_headerfile(hw);
82
83 if (is92c)
84 rtl_write_byte(rtlpriv, 0x14, 0x71);
85 else
86 rtl_write_byte(rtlpriv, 0x04CA, 0x0A);
87 return rtstatus;
88}
89
90bool rtl92c_phy_bb_config(struct ieee80211_hw *hw)
91{
92 bool rtstatus = true;
93 struct rtl_priv *rtlpriv = rtl_priv(hw);
94 u16 regval;
95 u32 regvaldw;
96 u8 reg_hwparafile = 1;
97
98 _rtl92c_phy_init_bb_rf_register_definition(hw);
99 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
100 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
101 regval | BIT(13) | BIT(0) | BIT(1));
102 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
103 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
104 rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
105 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
106 FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE |
107 FEN_BB_GLB_RSTn | FEN_BBRSTB);
108 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
109 regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
110 rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
111 if (reg_hwparafile == 1)
112 rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw);
113 return rtstatus;
114}
115
116void rtl92ce_phy_set_rf_reg(struct ieee80211_hw *hw,
117 enum radio_path rfpath,
118 u32 regaddr, u32 bitmask, u32 data)
119{
120 struct rtl_priv *rtlpriv = rtl_priv(hw);
121 struct rtl_phy *rtlphy = &(rtlpriv->phy);
122 u32 original_value, bitshift;
123
124 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
125 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
126 regaddr, bitmask, data, rfpath);
127
128 spin_lock(&rtlpriv->locks.rf_lock);
129
130 if (rtlphy->rf_mode != RF_OP_BY_FW) {
131 if (bitmask != RFREG_OFFSET_MASK) {
132 original_value = _rtl92c_phy_rf_serial_read(hw,
133 rfpath,
134 regaddr);
135 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
136 data =
137 ((original_value & (~bitmask)) |
138 (data << bitshift));
139 }
140
141 _rtl92c_phy_rf_serial_write(hw, rfpath, regaddr, data);
142 } else {
143 if (bitmask != RFREG_OFFSET_MASK) {
144 original_value = _rtl92c_phy_fw_rf_serial_read(hw,
145 rfpath,
146 regaddr);
147 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
148 data =
149 ((original_value & (~bitmask)) |
150 (data << bitshift));
151 }
152 _rtl92c_phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
153 }
154
155 spin_unlock(&rtlpriv->locks.rf_lock);
156
157 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
158 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
159 regaddr, bitmask, data, rfpath);
160}
161
162static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
163{
164 struct rtl_priv *rtlpriv = rtl_priv(hw);
165 u32 i;
166 u32 arraylength;
167 u32 *ptrarray;
168
169 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n");
170 arraylength = MAC_2T_ARRAYLENGTH;
171 ptrarray = RTL8192CEMAC_2T_ARRAY;
172 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Img:RTL8192CEMAC_2T_ARRAY\n");
173 for (i = 0; i < arraylength; i = i + 2)
174 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
175 return true;
176}
177
178bool _rtl92ce_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
179 u8 configtype)
180{
181 int i;
182 u32 *phy_regarray_table;
183 u32 *agctab_array_table;
184 u16 phy_reg_arraylen, agctab_arraylen;
185 struct rtl_priv *rtlpriv = rtl_priv(hw);
186 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
187
188 if (IS_92C_SERIAL(rtlhal->version)) {
189 agctab_arraylen = AGCTAB_2TARRAYLENGTH;
190 agctab_array_table = RTL8192CEAGCTAB_2TARRAY;
191 phy_reg_arraylen = PHY_REG_2TARRAY_LENGTH;
192 phy_regarray_table = RTL8192CEPHY_REG_2TARRAY;
193 } else {
194 agctab_arraylen = AGCTAB_1TARRAYLENGTH;
195 agctab_array_table = RTL8192CEAGCTAB_1TARRAY;
196 phy_reg_arraylen = PHY_REG_1TARRAY_LENGTH;
197 phy_regarray_table = RTL8192CEPHY_REG_1TARRAY;
198 }
199 if (configtype == BASEBAND_CONFIG_PHY_REG) {
200 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
201 if (phy_regarray_table[i] == 0xfe)
202 mdelay(50);
203 else if (phy_regarray_table[i] == 0xfd)
204 mdelay(5);
205 else if (phy_regarray_table[i] == 0xfc)
206 mdelay(1);
207 else if (phy_regarray_table[i] == 0xfb)
208 udelay(50);
209 else if (phy_regarray_table[i] == 0xfa)
210 udelay(5);
211 else if (phy_regarray_table[i] == 0xf9)
212 udelay(1);
213 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
214 phy_regarray_table[i + 1]);
215 udelay(1);
216 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
217 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
218 phy_regarray_table[i],
219 phy_regarray_table[i + 1]);
220 }
221 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
222 for (i = 0; i < agctab_arraylen; i = i + 2) {
223 rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
224 agctab_array_table[i + 1]);
225 udelay(1);
226 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
227 "The agctab_array_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
228 agctab_array_table[i],
229 agctab_array_table[i + 1]);
230 }
231 }
232 return true;
233}
234
235bool _rtl92ce_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
236 u8 configtype)
237{
238 struct rtl_priv *rtlpriv = rtl_priv(hw);
239 int i;
240 u32 *phy_regarray_table_pg;
241 u16 phy_regarray_pg_len;
242
243 phy_regarray_pg_len = PHY_REG_ARRAY_PGLENGTH;
244 phy_regarray_table_pg = RTL8192CEPHY_REG_ARRAY_PG;
245
246 if (configtype == BASEBAND_CONFIG_PHY_REG) {
247 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
248 if (phy_regarray_table_pg[i] == 0xfe)
249 mdelay(50);
250 else if (phy_regarray_table_pg[i] == 0xfd)
251 mdelay(5);
252 else if (phy_regarray_table_pg[i] == 0xfc)
253 mdelay(1);
254 else if (phy_regarray_table_pg[i] == 0xfb)
255 udelay(50);
256 else if (phy_regarray_table_pg[i] == 0xfa)
257 udelay(5);
258 else if (phy_regarray_table_pg[i] == 0xf9)
259 udelay(1);
260
261 _rtl92c_store_pwrIndex_diffrate_offset(hw,
262 phy_regarray_table_pg[i],
263 phy_regarray_table_pg[i + 1],
264 phy_regarray_table_pg[i + 2]);
265 }
266 } else {
267
268 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
269 "configtype != BaseBand_Config_PHY_REG\n");
270 }
271 return true;
272}
273
274bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
275 enum radio_path rfpath)
276{
277
278 int i;
279 u32 *radioa_array_table;
280 u32 *radiob_array_table;
281 u16 radioa_arraylen, radiob_arraylen;
282 struct rtl_priv *rtlpriv = rtl_priv(hw);
283 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
284
285 if (IS_92C_SERIAL(rtlhal->version)) {
286 radioa_arraylen = RADIOA_2TARRAYLENGTH;
287 radioa_array_table = RTL8192CERADIOA_2TARRAY;
288 radiob_arraylen = RADIOB_2TARRAYLENGTH;
289 radiob_array_table = RTL8192CE_RADIOB_2TARRAY;
290 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
291 "Radio_A:RTL8192CERADIOA_2TARRAY\n");
292 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
293 "Radio_B:RTL8192CE_RADIOB_2TARRAY\n");
294 } else {
295 radioa_arraylen = RADIOA_1TARRAYLENGTH;
296 radioa_array_table = RTL8192CE_RADIOA_1TARRAY;
297 radiob_arraylen = RADIOB_1TARRAYLENGTH;
298 radiob_array_table = RTL8192CE_RADIOB_1TARRAY;
299 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
300 "Radio_A:RTL8192CE_RADIOA_1TARRAY\n");
301 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
302 "Radio_B:RTL8192CE_RADIOB_1TARRAY\n");
303 }
304 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath);
305 switch (rfpath) {
306 case RF90_PATH_A:
307 for (i = 0; i < radioa_arraylen; i = i + 2) {
308 if (radioa_array_table[i] == 0xfe)
309 mdelay(50);
310 else if (radioa_array_table[i] == 0xfd)
311 mdelay(5);
312 else if (radioa_array_table[i] == 0xfc)
313 mdelay(1);
314 else if (radioa_array_table[i] == 0xfb)
315 udelay(50);
316 else if (radioa_array_table[i] == 0xfa)
317 udelay(5);
318 else if (radioa_array_table[i] == 0xf9)
319 udelay(1);
320 else {
321 rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
322 RFREG_OFFSET_MASK,
323 radioa_array_table[i + 1]);
324 udelay(1);
325 }
326 }
327 break;
328 case RF90_PATH_B:
329 for (i = 0; i < radiob_arraylen; i = i + 2) {
330 if (radiob_array_table[i] == 0xfe) {
331 mdelay(50);
332 } else if (radiob_array_table[i] == 0xfd)
333 mdelay(5);
334 else if (radiob_array_table[i] == 0xfc)
335 mdelay(1);
336 else if (radiob_array_table[i] == 0xfb)
337 udelay(50);
338 else if (radiob_array_table[i] == 0xfa)
339 udelay(5);
340 else if (radiob_array_table[i] == 0xf9)
341 udelay(1);
342 else {
343 rtl_set_rfreg(hw, rfpath, radiob_array_table[i],
344 RFREG_OFFSET_MASK,
345 radiob_array_table[i + 1]);
346 udelay(1);
347 }
348 }
349 break;
350 case RF90_PATH_C:
351 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
352 "switch case not processed\n");
353 break;
354 case RF90_PATH_D:
355 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
356 "switch case not processed\n");
357 break;
358 }
359 return true;
360}
361
362void rtl92ce_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
363{
364 struct rtl_priv *rtlpriv = rtl_priv(hw);
365 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
366 struct rtl_phy *rtlphy = &(rtlpriv->phy);
367 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
368 u8 reg_bw_opmode;
369 u8 reg_prsr_rsc;
370
371 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
372 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
373 "20MHz" : "40MHz");
374
375 if (is_hal_stop(rtlhal)) {
376 rtlphy->set_bwmode_inprogress = false;
377 return;
378 }
379
380 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
381 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
382
383 switch (rtlphy->current_chan_bw) {
384 case HT_CHANNEL_WIDTH_20:
385 reg_bw_opmode |= BW_OPMODE_20MHZ;
386 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
387 break;
388 case HT_CHANNEL_WIDTH_20_40:
389 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
390 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
391 reg_prsr_rsc =
392 (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
393 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
394 break;
395 default:
396 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
397 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
398 break;
399 }
400
401 switch (rtlphy->current_chan_bw) {
402 case HT_CHANNEL_WIDTH_20:
403 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
404 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
405 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
406 break;
407 case HT_CHANNEL_WIDTH_20_40:
408 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
409 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
410
411 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
412 (mac->cur_40_prime_sc >> 1));
413 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
414 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);
415
416 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
417 (mac->cur_40_prime_sc ==
418 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
419 break;
420 default:
421 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
422 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
423 break;
424 }
425 rtl92ce_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
426 rtlphy->set_bwmode_inprogress = false;
427 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
428}
429
430void _rtl92ce_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
431{
432 u8 tmpreg;
433 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
434 struct rtl_priv *rtlpriv = rtl_priv(hw);
435
436 tmpreg = rtl_read_byte(rtlpriv, 0xd03);
437
438 if ((tmpreg & 0x70) != 0)
439 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
440 else
441 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
442
443 if ((tmpreg & 0x70) != 0) {
444 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
445
446 if (is2t)
447 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
448 MASK12BITS);
449
450 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
451 (rf_a_mode & 0x8FFFF) | 0x10000);
452
453 if (is2t)
454 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
455 (rf_b_mode & 0x8FFFF) | 0x10000);
456 }
457 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
458
459 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
460
461 mdelay(100);
462
463 if ((tmpreg & 0x70) != 0) {
464 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
465 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
466
467 if (is2t)
468 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
469 rf_b_mode);
470 } else {
471 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
472 }
473}
474
475static void _rtl92ce_phy_set_rf_sleep(struct ieee80211_hw *hw)
476{
477 u32 u4b_tmp;
478 u8 delay = 5;
479 struct rtl_priv *rtlpriv = rtl_priv(hw);
480
481 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
482 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
483 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
484 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
485 while (u4b_tmp != 0 && delay > 0) {
486 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
487 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
488 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
489 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
490 delay--;
491 }
492 if (delay == 0) {
493 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
494 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
495 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
496 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
497 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
498 "Switch RF timeout !!!\n");
499 return;
500 }
501 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
502 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
503}
504
505static bool _rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
506 enum rf_pwrstate rfpwr_state)
507{
508 struct rtl_priv *rtlpriv = rtl_priv(hw);
509 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
510 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
511 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
512 bool bresult = true;
513 u8 i, queue_id;
514 struct rtl8192_tx_ring *ring = NULL;
515
516 switch (rfpwr_state) {
517 case ERFON:{
518 if ((ppsc->rfpwr_state == ERFOFF) &&
519 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
520 bool rtstatus;
521 u32 InitializeCount = 0;
522 do {
523 InitializeCount++;
524 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
525 "IPS Set eRf nic enable\n");
526 rtstatus = rtl_ps_enable_nic(hw);
527 } while (!rtstatus && (InitializeCount < 10));
528 RT_CLEAR_PS_LEVEL(ppsc,
529 RT_RF_OFF_LEVL_HALT_NIC);
530 } else {
531 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
532 "Set ERFON sleeped:%d ms\n",
533 jiffies_to_msecs(jiffies -
534 ppsc->
535 last_sleep_jiffies));
536 ppsc->last_awake_jiffies = jiffies;
537 rtl92ce_phy_set_rf_on(hw);
538 }
539 if (mac->link_state == MAC80211_LINKED) {
540 rtlpriv->cfg->ops->led_control(hw,
541 LED_CTL_LINK);
542 } else {
543 rtlpriv->cfg->ops->led_control(hw,
544 LED_CTL_NO_LINK);
545 }
546 break;
547 }
548 case ERFOFF:{
549 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
550 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
551 "IPS Set eRf nic disable\n");
552 rtl_ps_disable_nic(hw);
553 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
554 } else {
555 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
556 rtlpriv->cfg->ops->led_control(hw,
557 LED_CTL_NO_LINK);
558 } else {
559 rtlpriv->cfg->ops->led_control(hw,
560 LED_CTL_POWER_OFF);
561 }
562 }
563 break;
564 }
565 case ERFSLEEP:{
566 if (ppsc->rfpwr_state == ERFOFF)
567 return false;
568 for (queue_id = 0, i = 0;
569 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
570 ring = &pcipriv->dev.tx_ring[queue_id];
571 if (skb_queue_len(&ring->queue) == 0) {
572 queue_id++;
573 continue;
574 } else {
575 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
576 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
577 i + 1, queue_id,
578 skb_queue_len(&ring->queue));
579
580 udelay(10);
581 i++;
582 }
583 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
584 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
585 "ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
586 MAX_DOZE_WAITING_TIMES_9x,
587 queue_id,
588 skb_queue_len(&ring->queue));
589 break;
590 }
591 }
592 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
593 "Set ERFSLEEP awaked:%d ms\n",
594 jiffies_to_msecs(jiffies -
595 ppsc->last_awake_jiffies));
596 ppsc->last_sleep_jiffies = jiffies;
597 _rtl92ce_phy_set_rf_sleep(hw);
598 break;
599 }
600 default:
601 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
602 "switch case not processed\n");
603 bresult = false;
604 break;
605 }
606 if (bresult)
607 ppsc->rfpwr_state = rfpwr_state;
608 return bresult;
609}
610
611bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw,
612 enum rf_pwrstate rfpwr_state)
613{
614 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
615
616 bool bresult = false;
617
618 if (rfpwr_state == ppsc->rfpwr_state)
619 return bresult;
620 bresult = _rtl92ce_phy_set_rf_power_state(hw, rfpwr_state);
621 return bresult;
622}
623
