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10#include <linux/kernel.h>
11#include <linux/delay.h>
12#include <linux/init.h>
13#include <linux/pci.h>
14#include <linux/pm.h>
15#include <linux/slab.h>
16#include <linux/module.h>
17#include <linux/spinlock.h>
18#include <linux/string.h>
19#include <linux/log2.h>
20#include <linux/pci-aspm.h>
21#include <linux/pm_wakeup.h>
22#include <linux/interrupt.h>
23#include <linux/device.h>
24#include <linux/pm_runtime.h>
25#include <linux/pci_hotplug.h>
26#include <asm-generic/pci-bridge.h>
27#include <asm/setup.h>
28#include "pci.h"
29
30const char *pci_power_names[] = {
31 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
32};
33EXPORT_SYMBOL_GPL(pci_power_names);
34
35int isa_dma_bridge_buggy;
36EXPORT_SYMBOL(isa_dma_bridge_buggy);
37
38int pci_pci_problems;
39EXPORT_SYMBOL(pci_pci_problems);
40
41unsigned int pci_pm_d3_delay;
42
43static void pci_pme_list_scan(struct work_struct *work);
44
45static LIST_HEAD(pci_pme_list);
46static DEFINE_MUTEX(pci_pme_list_mutex);
47static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
48
49struct pci_pme_device {
50 struct list_head list;
51 struct pci_dev *dev;
52};
53
54#define PME_TIMEOUT 1000
55
56static void pci_dev_d3_sleep(struct pci_dev *dev)
57{
58 unsigned int delay = dev->d3_delay;
59
60 if (delay < pci_pm_d3_delay)
61 delay = pci_pm_d3_delay;
62
63 msleep(delay);
64}
65
66#ifdef CONFIG_PCI_DOMAINS
67int pci_domains_supported = 1;
68#endif
69
70#define DEFAULT_CARDBUS_IO_SIZE (256)
71#define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
72
73unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
74unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
75
76#define DEFAULT_HOTPLUG_IO_SIZE (256)
77#define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
78
79unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
80unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
81
82enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
83
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87
88
89
90u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
91u8 pci_cache_line_size;
92
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94
95
96
97unsigned int pcibios_max_latency = 255;
98
99
100static bool pcie_ari_disabled;
101
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107
108
109unsigned char pci_bus_max_busnr(struct pci_bus* bus)
110{
111 struct list_head *tmp;
112 unsigned char max, n;
113
114 max = bus->busn_res.end;
115 list_for_each(tmp, &bus->children) {
116 n = pci_bus_max_busnr(pci_bus_b(tmp));
117 if(n > max)
118 max = n;
119 }
120 return max;
121}
122EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
123
124#ifdef CONFIG_HAS_IOMEM
125void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
126{
127
128
129
130 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
131 WARN_ON(1);
132 return NULL;
133 }
134 return ioremap_nocache(pci_resource_start(pdev, bar),
135 pci_resource_len(pdev, bar));
136}
137EXPORT_SYMBOL_GPL(pci_ioremap_bar);
138#endif
139
140#define PCI_FIND_CAP_TTL 48
141
142static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
143 u8 pos, int cap, int *ttl)
144{
145 u8 id;
146
147 while ((*ttl)--) {
148 pci_bus_read_config_byte(bus, devfn, pos, &pos);
149 if (pos < 0x40)
150 break;
151 pos &= ~3;
152 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
153 &id);
154 if (id == 0xff)
155 break;
156 if (id == cap)
157 return pos;
158 pos += PCI_CAP_LIST_NEXT;
159 }
160 return 0;
161}
162
163static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
164 u8 pos, int cap)
165{
166 int ttl = PCI_FIND_CAP_TTL;
167
168 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
169}
170
171int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
172{
173 return __pci_find_next_cap(dev->bus, dev->devfn,
174 pos + PCI_CAP_LIST_NEXT, cap);
175}
176EXPORT_SYMBOL_GPL(pci_find_next_capability);
177
178static int __pci_bus_find_cap_start(struct pci_bus *bus,
179 unsigned int devfn, u8 hdr_type)
180{
181 u16 status;
182
183 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
184 if (!(status & PCI_STATUS_CAP_LIST))
185 return 0;
186
187 switch (hdr_type) {
188 case PCI_HEADER_TYPE_NORMAL:
189 case PCI_HEADER_TYPE_BRIDGE:
190 return PCI_CAPABILITY_LIST;
191 case PCI_HEADER_TYPE_CARDBUS:
192 return PCI_CB_CAPABILITY_LIST;
193 default:
194 return 0;
195 }
196
197 return 0;
198}
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218
219int pci_find_capability(struct pci_dev *dev, int cap)
220{
221 int pos;
222
223 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
224 if (pos)
225 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
226
227 return pos;
228}
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242
243int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
244{
245 int pos;
246 u8 hdr_type;
247
248 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
249
250 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
251 if (pos)
252 pos = __pci_find_next_cap(bus, devfn, pos, cap);
253
254 return pos;
255}
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267
268int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
269{
270 u32 header;
271 int ttl;
272 int pos = PCI_CFG_SPACE_SIZE;
273
274
275 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
276
277 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
278 return 0;
279
280 if (start)
281 pos = start;
282
283 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
284 return 0;
285
286
287
288
289
290 if (header == 0)
291 return 0;
292
293 while (ttl-- > 0) {
294 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
295 return pos;
296
297 pos = PCI_EXT_CAP_NEXT(header);
298 if (pos < PCI_CFG_SPACE_SIZE)
299 break;
300
301 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
302 break;
303 }
304
305 return 0;
306}
307EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
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322
323int pci_find_ext_capability(struct pci_dev *dev, int cap)
324{
325 return pci_find_next_ext_capability(dev, 0, cap);
326}
327EXPORT_SYMBOL_GPL(pci_find_ext_capability);
328
329static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
330{
331 int rc, ttl = PCI_FIND_CAP_TTL;
332 u8 cap, mask;
333
334 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
335 mask = HT_3BIT_CAP_MASK;
336 else
337 mask = HT_5BIT_CAP_MASK;
338
339 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
340 PCI_CAP_ID_HT, &ttl);
341 while (pos) {
342 rc = pci_read_config_byte(dev, pos + 3, &cap);
343 if (rc != PCIBIOS_SUCCESSFUL)
344 return 0;
345
346 if ((cap & mask) == ht_cap)
347 return pos;
348
349 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
350 pos + PCI_CAP_LIST_NEXT,
351 PCI_CAP_ID_HT, &ttl);
352 }
353
354 return 0;
355}
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368
369int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
370{
371 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
372}
373EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
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386int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
387{
388 int pos;
389
390 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
391 if (pos)
392 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
393
394 return pos;
395}
396EXPORT_SYMBOL_GPL(pci_find_ht_capability);
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406
407struct resource *
408pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
409{
410 const struct pci_bus *bus = dev->bus;
411 int i;
412 struct resource *best = NULL, *r;
413
414 pci_bus_for_each_resource(bus, r, i) {
415 if (!r)
416 continue;
417 if (res->start && !(res->start >= r->start && res->end <= r->end))
418 continue;
419 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
420 continue;
421 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
422 return r;
423
424 if (r->flags & IORESOURCE_PREFETCH)
425 continue;
426
427 if (!best)
428 best = r;
429 }
430 return best;
431}
432
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439
440static void
441pci_restore_bars(struct pci_dev *dev)
442{
443 int i;
444
445 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
446 pci_update_resource(dev, i);
447}
448
449static struct pci_platform_pm_ops *pci_platform_pm;
450
451int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
452{
453 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
454 || !ops->sleep_wake)
455 return -EINVAL;
456 pci_platform_pm = ops;
457 return 0;
458}
459
460static inline bool platform_pci_power_manageable(struct pci_dev *dev)
461{
462 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
463}
464
465static inline int platform_pci_set_power_state(struct pci_dev *dev,
466 pci_power_t t)
467{
468 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
469}
470
471static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
472{
473 return pci_platform_pm ?
474 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
475}
476
477static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
478{
479 return pci_platform_pm ?
480 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
481}
482
483static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
484{
485 return pci_platform_pm ?
486 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
487}
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501
502static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
503{
504 u16 pmcsr;
505 bool need_restore = false;
506
507
508 if (dev->current_state == state)
509 return 0;
510
511 if (!dev->pm_cap)
512 return -EIO;
513
514 if (state < PCI_D0 || state > PCI_D3hot)
515 return -EINVAL;
516
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519
520
521 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
522 && dev->current_state > state) {
523 dev_err(&dev->dev, "invalid power transition "
524 "(from state %d to %d)\n", dev->current_state, state);
525 return -EINVAL;
526 }
527
528
529 if ((state == PCI_D1 && !dev->d1_support)
530 || (state == PCI_D2 && !dev->d2_support))
531 return -EIO;
532
533 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
534
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539 switch (dev->current_state) {
540 case PCI_D0:
541 case PCI_D1:
542 case PCI_D2:
543 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
544 pmcsr |= state;
545 break;
546 case PCI_D3hot:
547 case PCI_D3cold:
548 case PCI_UNKNOWN:
549 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
550 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
551 need_restore = true;
552
553 default:
554 pmcsr = 0;
555 break;
556 }
557
558
559 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
560
561
562
563 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
564 pci_dev_d3_sleep(dev);
565 else if (state == PCI_D2 || dev->current_state == PCI_D2)
566 udelay(PCI_PM_D2_DELAY);
567
568 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
569 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
570 if (dev->current_state != state && printk_ratelimit())
571 dev_info(&dev->dev, "Refused to change power state, "
572 "currently in D%d\n", dev->current_state);
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586
587 if (need_restore)
588 pci_restore_bars(dev);
589
590 if (dev->bus->self)
591 pcie_aspm_pm_state_change(dev->bus->self);
592
593 return 0;
594}
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601
602void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
603{
604 if (dev->pm_cap) {
605 u16 pmcsr;
606
607
608
609
610
611 if (dev->current_state == PCI_D3cold)
612 return;
613 if (state == PCI_D3cold) {
614 dev->current_state = PCI_D3cold;
615 return;
616 }
617 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
618 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
619 } else {
620 dev->current_state = state;
621 }
622}
623
624
625
626
627
628void pci_power_up(struct pci_dev *dev)
629{
630 if (platform_pci_power_manageable(dev))
631 platform_pci_set_power_state(dev, PCI_D0);
632
633 pci_raw_set_power_state(dev, PCI_D0);
634 pci_update_current_state(dev, PCI_D0);
635}
636
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640
641
642static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
643{
644 int error;
645
646 if (platform_pci_power_manageable(dev)) {
647 error = platform_pci_set_power_state(dev, state);
648 if (!error)
649 pci_update_current_state(dev, state);
650 } else
651 error = -ENODEV;
652
653 if (error && !dev->pm_cap)
654 dev->current_state = PCI_D0;
655
656 return error;
657}
658
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662
663
664static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
665{
666 if (state == PCI_D0) {
667 pci_platform_power_transition(dev, PCI_D0);
668
669
670
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672
673
674
675 if (dev->runtime_d3cold) {
676 msleep(dev->d3cold_delay);
677
678
679
680
681
682
683 pci_wakeup_bus(dev->subordinate);
684 }
685 }
686}
687
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691
692
693static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
694{
695 pci_power_t state = *(pci_power_t *)data;
696
697 dev->current_state = state;
698 return 0;
699}
700
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704
705
706static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
707{
708 if (bus)
709 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
710}
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717
718
719int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
720{
721 int ret;
722
723 if (state <= PCI_D0)
724 return -EINVAL;
725 ret = pci_platform_power_transition(dev, state);
726
727 if (!ret && state == PCI_D3cold)
728 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
729 return ret;
730}
731EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
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746
747
748int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
749{
750 int error;
751
752
753 if (state > PCI_D3cold)
754 state = PCI_D3cold;
755 else if (state < PCI_D0)
756 state = PCI_D0;
757 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
758
759
760
761
762
763 return 0;
764
765
766 if (dev->current_state == state)
767 return 0;
768
769 __pci_start_power_transition(dev, state);
770
771
772
773 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
774 return 0;
775
776
777
778
779
780 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
781 PCI_D3hot : state);
782
783 if (!__pci_complete_power_transition(dev, state))
784 error = 0;
785
786
787
788
789 if (!error && dev->bus->self)
790 pcie_aspm_powersave_config_link(dev->bus->self);
791
792 return error;
793}
794
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804
805pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
806{
807 pci_power_t ret;
808
809 if (!dev->pm_cap)
810 return PCI_D0;
811
812 ret = platform_pci_choose_state(dev);
813 if (ret != PCI_POWER_ERROR)
814 return ret;
815
816 switch (state.event) {
817 case PM_EVENT_ON:
818 return PCI_D0;
819 case PM_EVENT_FREEZE:
820 case PM_EVENT_PRETHAW:
821
822 case PM_EVENT_SUSPEND:
823 case PM_EVENT_HIBERNATE:
824 return PCI_D3hot;
825 default:
826 dev_info(&dev->dev, "unrecognized suspend event %d\n",
827 state.event);
828 BUG();
829 }
830 return PCI_D0;
831}
832
833EXPORT_SYMBOL(pci_choose_state);
834
835#define PCI_EXP_SAVE_REGS 7
836
837
838static struct pci_cap_saved_state *pci_find_saved_cap(
839 struct pci_dev *pci_dev, char cap)
840{
841 struct pci_cap_saved_state *tmp;
842
843 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
844 if (tmp->cap.cap_nr == cap)
845 return tmp;
846 }
847 return NULL;
848}
849
850static int pci_save_pcie_state(struct pci_dev *dev)
851{
852 int i = 0;
853 struct pci_cap_saved_state *save_state;
854 u16 *cap;
855
856 if (!pci_is_pcie(dev))
857 return 0;
858
859 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
860 if (!save_state) {
861 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
862 return -ENOMEM;
863 }
864
865 cap = (u16 *)&save_state->cap.data[0];
866 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
867 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
868 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
869 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
870 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
871 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
872 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
873
874 return 0;
875}
876
877static void pci_restore_pcie_state(struct pci_dev *dev)
878{
879 int i = 0;
880 struct pci_cap_saved_state *save_state;
881 u16 *cap;
882
883 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
884 if (!save_state)
885 return;
886
887 cap = (u16 *)&save_state->cap.data[0];
888 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
889 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
890 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
891 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
892 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
893 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
894 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
895}
896
897
898static int pci_save_pcix_state(struct pci_dev *dev)
899{
900 int pos;
901 struct pci_cap_saved_state *save_state;
902
903 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
904 if (pos <= 0)
905 return 0;
906
907 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
908 if (!save_state) {
909 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
910 return -ENOMEM;
911 }
912
913 pci_read_config_word(dev, pos + PCI_X_CMD,
914 (u16 *)save_state->cap.data);
915
916 return 0;
917}
918
919static void pci_restore_pcix_state(struct pci_dev *dev)
920{
921 int i = 0, pos;
922 struct pci_cap_saved_state *save_state;
923 u16 *cap;
924
925 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
926 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
927 if (!save_state || pos <= 0)
928 return;
929 cap = (u16 *)&save_state->cap.data[0];
930
931 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
932}
933
934
935
936
937
938
939int
940pci_save_state(struct pci_dev *dev)
941{
942 int i;
943
944 for (i = 0; i < 16; i++)
945 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
946 dev->state_saved = true;
947 if ((i = pci_save_pcie_state(dev)) != 0)
948 return i;
949 if ((i = pci_save_pcix_state(dev)) != 0)
950 return i;
951 return 0;
952}
953
954static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
955 u32 saved_val, int retry)
956{
957 u32 val;
958
959 pci_read_config_dword(pdev, offset, &val);
960 if (val == saved_val)
961 return;
962
963 for (;;) {
964 dev_dbg(&pdev->dev, "restoring config space at offset "
965 "%#x (was %#x, writing %#x)\n", offset, val, saved_val);
966 pci_write_config_dword(pdev, offset, saved_val);
967 if (retry-- <= 0)
968 return;
969
970 pci_read_config_dword(pdev, offset, &val);
971 if (val == saved_val)
972 return;
973
974 mdelay(1);
975 }
976}
977
978static void pci_restore_config_space_range(struct pci_dev *pdev,
979 int start, int end, int retry)
980{
981 int index;
982
983 for (index = end; index >= start; index--)
984 pci_restore_config_dword(pdev, 4 * index,
985 pdev->saved_config_space[index],
986 retry);
987}
988
989static void pci_restore_config_space(struct pci_dev *pdev)
990{
991 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
992 pci_restore_config_space_range(pdev, 10, 15, 0);
993
994 pci_restore_config_space_range(pdev, 4, 9, 10);
995 pci_restore_config_space_range(pdev, 0, 3, 0);
996 } else {
997 pci_restore_config_space_range(pdev, 0, 15, 0);
998 }
999}
1000
1001
1002
1003
1004
1005void pci_restore_state(struct pci_dev *dev)
1006{
1007 if (!dev->state_saved)
1008 return;
1009
1010
1011 pci_restore_pcie_state(dev);
1012 pci_restore_ats_state(dev);
1013
1014 pci_restore_config_space(dev);
1015
1016 pci_restore_pcix_state(dev);
1017 pci_restore_msi_state(dev);
1018 pci_restore_iov_state(dev);
1019
1020 dev->state_saved = false;
1021}
1022
1023struct pci_saved_state {
1024 u32 config_space[16];
1025 struct pci_cap_saved_data cap[0];
1026};
1027
1028
1029
1030
1031
1032
1033
1034
1035struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1036{
1037 struct pci_saved_state *state;
1038 struct pci_cap_saved_state *tmp;
1039 struct pci_cap_saved_data *cap;
1040 size_t size;
1041
1042 if (!dev->state_saved)
1043 return NULL;
1044
1045 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1046
1047 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1048 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1049
1050 state = kzalloc(size, GFP_KERNEL);
1051 if (!state)
1052 return NULL;
1053
1054 memcpy(state->config_space, dev->saved_config_space,
1055 sizeof(state->config_space));
1056
1057 cap = state->cap;
1058 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1059 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1060 memcpy(cap, &tmp->cap, len);
1061 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1062 }
1063
1064
1065 return state;
1066}
1067EXPORT_SYMBOL_GPL(pci_store_saved_state);
1068
1069
1070
1071
1072
1073
1074int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state)
1075{
1076 struct pci_cap_saved_data *cap;
1077
1078 dev->state_saved = false;
1079
1080 if (!state)
1081 return 0;
1082
1083 memcpy(dev->saved_config_space, state->config_space,
1084 sizeof(state->config_space));
1085
1086 cap = state->cap;
1087 while (cap->size) {
1088 struct pci_cap_saved_state *tmp;
1089
1090 tmp = pci_find_saved_cap(dev, cap->cap_nr);
1091 if (!tmp || tmp->cap.size != cap->size)
1092 return -EINVAL;
1093
1094 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1095 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1096 sizeof(struct pci_cap_saved_data) + cap->size);
1097 }
1098
1099 dev->state_saved = true;
1100 return 0;
1101}
1102EXPORT_SYMBOL_GPL(pci_load_saved_state);
1103
1104
1105
1106
1107
1108
1109
1110int pci_load_and_free_saved_state(struct pci_dev *dev,
1111 struct pci_saved_state **state)
1112{
1113 int ret = pci_load_saved_state(dev, *state);
1114 kfree(*state);
1115 *state = NULL;
1116 return ret;
1117}
1118EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1119
1120static int do_pci_enable_device(struct pci_dev *dev, int bars)
1121{
1122 int err;
1123
1124 err = pci_set_power_state(dev, PCI_D0);
1125 if (err < 0 && err != -EIO)
1126 return err;
1127 err = pcibios_enable_device(dev, bars);
1128 if (err < 0)
1129 return err;
1130 pci_fixup_device(pci_fixup_enable, dev);
1131
1132 return 0;
1133}
1134
1135
1136
1137
1138
1139
1140
1141
1142int pci_reenable_device(struct pci_dev *dev)
1143{
1144 if (pci_is_enabled(dev))
1145 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1146 return 0;
1147}
1148
1149static void pci_enable_bridge(struct pci_dev *dev)
1150{
1151 int retval;
1152
1153 if (!dev)
1154 return;
1155
1156 pci_enable_bridge(dev->bus->self);
1157
1158 if (pci_is_enabled(dev)) {
1159 if (!dev->is_busmaster) {
1160 dev_warn(&dev->dev, "driver skip pci_set_master, fix it!\n");
1161 pci_set_master(dev);
1162 }
1163 return;
1164 }
1165
1166 retval = pci_enable_device(dev);
1167 if (retval)
1168 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n",
1169 retval);
1170 pci_set_master(dev);
1171}
1172
1173static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1174{
1175 int err;
1176 int i, bars = 0;
1177
1178
1179
1180
1181
1182
1183
1184 if (dev->pm_cap) {
1185 u16 pmcsr;
1186 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1187 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1188 }
1189
1190 if (atomic_inc_return(&dev->enable_cnt) > 1)
1191 return 0;
1192
1193 pci_enable_bridge(dev->bus->self);
1194
1195
1196 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1197 if (dev->resource[i].flags & flags)
1198 bars |= (1 << i);
1199 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1200 if (dev->resource[i].flags & flags)
1201 bars |= (1 << i);
1202
1203 err = do_pci_enable_device(dev, bars);
1204 if (err < 0)
1205 atomic_dec(&dev->enable_cnt);
1206 return err;
1207}
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217int pci_enable_device_io(struct pci_dev *dev)
1218{
1219 return pci_enable_device_flags(dev, IORESOURCE_IO);
1220}
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230int pci_enable_device_mem(struct pci_dev *dev)
1231{
1232 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1233}
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246int pci_enable_device(struct pci_dev *dev)
1247{
1248 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1249}
1250
1251
1252
1253
1254
1255
1256
1257struct pci_devres {
1258 unsigned int enabled:1;
1259 unsigned int pinned:1;
1260 unsigned int orig_intx:1;
1261 unsigned int restore_intx:1;
1262 u32 region_mask;
1263};
1264
1265static void pcim_release(struct device *gendev, void *res)
1266{
1267 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1268 struct pci_devres *this = res;
1269 int i;
1270
1271 if (dev->msi_enabled)
1272 pci_disable_msi(dev);
1273 if (dev->msix_enabled)
1274 pci_disable_msix(dev);
1275
1276 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1277 if (this->region_mask & (1 << i))
1278 pci_release_region(dev, i);
1279
1280 if (this->restore_intx)
1281 pci_intx(dev, this->orig_intx);
1282
1283 if (this->enabled && !this->pinned)
1284 pci_disable_device(dev);
1285}
1286
1287static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1288{
1289 struct pci_devres *dr, *new_dr;
1290
1291 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1292 if (dr)
1293 return dr;
1294
1295 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1296 if (!new_dr)
1297 return NULL;
1298 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1299}
1300
1301static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1302{
1303 if (pci_is_managed(pdev))
1304 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1305 return NULL;
1306}
1307
1308
1309
1310
1311
1312
1313
1314int pcim_enable_device(struct pci_dev *pdev)
1315{
1316 struct pci_devres *dr;
1317 int rc;
1318
1319 dr = get_pci_dr(pdev);
1320 if (unlikely(!dr))
1321 return -ENOMEM;
1322 if (dr->enabled)
1323 return 0;
1324
1325 rc = pci_enable_device(pdev);
1326 if (!rc) {
1327 pdev->is_managed = 1;
1328 dr->enabled = 1;
1329 }
1330 return rc;
1331}
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341void pcim_pin_device(struct pci_dev *pdev)
1342{
1343 struct pci_devres *dr;
1344
1345 dr = find_pci_dr(pdev);
1346 WARN_ON(!dr || !dr->enabled);
1347 if (dr)
1348 dr->pinned = 1;
1349}
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359int __weak pcibios_add_device (struct pci_dev *dev)
1360{
1361 return 0;
1362}
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372void __weak pcibios_release_device(struct pci_dev *dev) {}
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382void __weak pcibios_disable_device (struct pci_dev *dev) {}
1383
1384static void do_pci_disable_device(struct pci_dev *dev)
1385{
1386 u16 pci_command;
1387
1388 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1389 if (pci_command & PCI_COMMAND_MASTER) {
1390 pci_command &= ~PCI_COMMAND_MASTER;
1391 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1392 }
1393
1394 pcibios_disable_device(dev);
1395}
1396
1397
1398
1399
1400
1401
1402
1403
1404void pci_disable_enabled_device(struct pci_dev *dev)
1405{
1406 if (pci_is_enabled(dev))
1407 do_pci_disable_device(dev);
1408}
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420void
1421pci_disable_device(struct pci_dev *dev)
1422{
1423 struct pci_devres *dr;
1424
1425 dr = find_pci_dr(dev);
1426 if (dr)
1427 dr->enabled = 0;
1428
1429 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1430 "disabling already-disabled device");
1431
1432 if (atomic_dec_return(&dev->enable_cnt) != 0)
1433 return;
1434
1435 do_pci_disable_device(dev);
1436
1437 dev->is_busmaster = 0;
1438}
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1450 enum pcie_reset_state state)
1451{
1452 return -EINVAL;
1453}
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1464{
1465 return pcibios_set_pcie_reset_state(dev, state);
1466}
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476bool pci_check_pme_status(struct pci_dev *dev)
1477{
1478 int pmcsr_pos;
1479 u16 pmcsr;
1480 bool ret = false;
1481
1482 if (!dev->pm_cap)
1483 return false;
1484
1485 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1486 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1487 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1488 return false;
1489
1490
1491 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1492 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1493
1494 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1495 ret = true;
1496 }
1497
1498 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1499
1500 return ret;
1501}
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1512{
1513 if (pme_poll_reset && dev->pme_poll)
1514 dev->pme_poll = false;
1515
1516 if (pci_check_pme_status(dev)) {
1517 pci_wakeup_event(dev);
1518 pm_request_resume(&dev->dev);
1519 }
1520 return 0;
1521}
1522
1523
1524
1525
1526
1527void pci_pme_wakeup_bus(struct pci_bus *bus)
1528{
1529 if (bus)
1530 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1531}
1532
1533
1534
1535
1536
1537
1538static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
1539{
1540 pci_wakeup_event(pci_dev);
1541 pm_request_resume(&pci_dev->dev);
1542 return 0;
1543}
1544
1545
1546
1547
1548
1549void pci_wakeup_bus(struct pci_bus *bus)
1550{
1551 if (bus)
1552 pci_walk_bus(bus, pci_wakeup, NULL);
1553}
1554
1555
1556
1557
1558
1559
1560bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1561{
1562 if (!dev->pm_cap)
1563 return false;
1564
1565 return !!(dev->pme_support & (1 << state));
1566}
1567
1568static void pci_pme_list_scan(struct work_struct *work)
1569{
1570 struct pci_pme_device *pme_dev, *n;
1571
1572 mutex_lock(&pci_pme_list_mutex);
1573 if (!list_empty(&pci_pme_list)) {
1574 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1575 if (pme_dev->dev->pme_poll) {
1576 struct pci_dev *bridge;
1577
1578 bridge = pme_dev->dev->bus->self;
1579
1580
1581
1582
1583
1584 if (bridge && bridge->current_state != PCI_D0)
1585 continue;
1586 pci_pme_wakeup(pme_dev->dev, NULL);
1587 } else {
1588 list_del(&pme_dev->list);
1589 kfree(pme_dev);
1590 }
1591 }
1592 if (!list_empty(&pci_pme_list))
1593 schedule_delayed_work(&pci_pme_work,
1594 msecs_to_jiffies(PME_TIMEOUT));
1595 }
1596 mutex_unlock(&pci_pme_list_mutex);
1597}
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607void pci_pme_active(struct pci_dev *dev, bool enable)
1608{
1609 u16 pmcsr;
1610
1611 if (!dev->pme_support)
1612 return;
1613
1614 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1615
1616 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1617 if (!enable)
1618 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1619
1620 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642 if (dev->pme_poll) {
1643 struct pci_pme_device *pme_dev;
1644 if (enable) {
1645 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1646 GFP_KERNEL);
1647 if (!pme_dev)
1648 goto out;
1649 pme_dev->dev = dev;
1650 mutex_lock(&pci_pme_list_mutex);
1651 list_add(&pme_dev->list, &pci_pme_list);
1652 if (list_is_singular(&pci_pme_list))
1653 schedule_delayed_work(&pci_pme_work,
1654 msecs_to_jiffies(PME_TIMEOUT));
1655 mutex_unlock(&pci_pme_list_mutex);
1656 } else {
1657 mutex_lock(&pci_pme_list_mutex);
1658 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1659 if (pme_dev->dev == dev) {
1660 list_del(&pme_dev->list);
1661 kfree(pme_dev);
1662 break;
1663 }
1664 }
1665 mutex_unlock(&pci_pme_list_mutex);
1666 }
1667 }
1668
1669out:
1670 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
1671}
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1694 bool runtime, bool enable)
1695{
1696 int ret = 0;
1697
1698 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1699 return -EINVAL;
1700
1701
1702 if (!!enable == !!dev->wakeup_prepared)
1703 return 0;
1704
1705
1706
1707
1708
1709
1710
1711 if (enable) {
1712 int error;
1713
1714 if (pci_pme_capable(dev, state))
1715 pci_pme_active(dev, true);
1716 else
1717 ret = 1;
1718 error = runtime ? platform_pci_run_wake(dev, true) :
1719 platform_pci_sleep_wake(dev, true);
1720 if (ret)
1721 ret = error;
1722 if (!ret)
1723 dev->wakeup_prepared = true;
1724 } else {
1725 if (runtime)
1726 platform_pci_run_wake(dev, false);
1727 else
1728 platform_pci_sleep_wake(dev, false);
1729 pci_pme_active(dev, false);
1730 dev->wakeup_prepared = false;
1731 }
1732
1733 return ret;
1734}
1735EXPORT_SYMBOL(__pci_enable_wake);
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1752{
1753 return pci_pme_capable(dev, PCI_D3cold) ?
1754 pci_enable_wake(dev, PCI_D3cold, enable) :
1755 pci_enable_wake(dev, PCI_D3hot, enable);
1756}
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766pci_power_t pci_target_state(struct pci_dev *dev)
1767{
1768 pci_power_t target_state = PCI_D3hot;
1769
1770 if (platform_pci_power_manageable(dev)) {
1771
1772
1773
1774
1775 pci_power_t state = platform_pci_choose_state(dev);
1776
1777 switch (state) {
1778 case PCI_POWER_ERROR:
1779 case PCI_UNKNOWN:
1780 break;
1781 case PCI_D1:
1782 case PCI_D2:
1783 if (pci_no_d1d2(dev))
1784 break;
1785 default:
1786 target_state = state;
1787 }
1788 } else if (!dev->pm_cap) {
1789 target_state = PCI_D0;
1790 } else if (device_may_wakeup(&dev->dev)) {
1791
1792
1793
1794
1795
1796 if (dev->pme_support) {
1797 while (target_state
1798 && !(dev->pme_support & (1 << target_state)))
1799 target_state--;
1800 }
1801 }
1802
1803 return target_state;
1804}
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814int pci_prepare_to_sleep(struct pci_dev *dev)
1815{
1816 pci_power_t target_state = pci_target_state(dev);
1817 int error;
1818
1819 if (target_state == PCI_POWER_ERROR)
1820 return -EIO;
1821
1822
1823 if (target_state > PCI_D3hot)
1824 target_state = PCI_D3hot;
1825
1826 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1827
1828 error = pci_set_power_state(dev, target_state);
1829
1830 if (error)
1831 pci_enable_wake(dev, target_state, false);
1832
1833 return error;
1834}
1835
1836
1837
1838
1839
1840
1841
1842int pci_back_from_sleep(struct pci_dev *dev)
1843{
1844 pci_enable_wake(dev, PCI_D0, false);
1845 return pci_set_power_state(dev, PCI_D0);
1846}
1847
1848
1849
1850
1851
1852
1853
1854
1855int pci_finish_runtime_suspend(struct pci_dev *dev)
1856{
1857 pci_power_t target_state = pci_target_state(dev);
1858 int error;
1859
1860 if (target_state == PCI_POWER_ERROR)
1861 return -EIO;
1862
1863 dev->runtime_d3cold = target_state == PCI_D3cold;
1864
1865 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1866
1867 error = pci_set_power_state(dev, target_state);
1868
1869 if (error) {
1870 __pci_enable_wake(dev, target_state, true, false);
1871 dev->runtime_d3cold = false;
1872 }
1873
1874 return error;
1875}
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885bool pci_dev_run_wake(struct pci_dev *dev)
1886{
1887 struct pci_bus *bus = dev->bus;
1888
1889 if (device_run_wake(&dev->dev))
1890 return true;
1891
1892 if (!dev->pme_support)
1893 return false;
1894
1895 while (bus->parent) {
1896 struct pci_dev *bridge = bus->self;
1897
1898 if (device_run_wake(&bridge->dev))
1899 return true;
1900
1901 bus = bus->parent;
1902 }
1903
1904
1905 if (bus->bridge)
1906 return device_run_wake(bus->bridge);
1907
1908 return false;
1909}
1910EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1911
1912void pci_config_pm_runtime_get(struct pci_dev *pdev)
1913{
1914 struct device *dev = &pdev->dev;
1915 struct device *parent = dev->parent;
1916
1917 if (parent)
1918 pm_runtime_get_sync(parent);
1919 pm_runtime_get_noresume(dev);
1920
1921
1922
1923
1924 pm_runtime_barrier(dev);
1925
1926
1927
1928
1929
1930 if (pdev->current_state == PCI_D3cold)
1931 pm_runtime_resume(dev);
1932}
1933
1934void pci_config_pm_runtime_put(struct pci_dev *pdev)
1935{
1936 struct device *dev = &pdev->dev;
1937 struct device *parent = dev->parent;
1938
1939 pm_runtime_put(dev);
1940 if (parent)
1941 pm_runtime_put_sync(parent);
1942}
1943
1944
1945
1946
1947
1948void pci_pm_init(struct pci_dev *dev)
1949{
1950 int pm;
1951 u16 pmc;
1952
1953 pm_runtime_forbid(&dev->dev);
1954 pm_runtime_set_active(&dev->dev);
1955 pm_runtime_enable(&dev->dev);
1956 device_enable_async_suspend(&dev->dev);
1957 dev->wakeup_prepared = false;
1958
1959 dev->pm_cap = 0;
1960 dev->pme_support = 0;
1961
1962
1963 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1964 if (!pm)
1965 return;
1966
1967 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1968
1969 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1970 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1971 pmc & PCI_PM_CAP_VER_MASK);
1972 return;
1973 }
1974
1975 dev->pm_cap = pm;
1976 dev->d3_delay = PCI_PM_D3_WAIT;
1977 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
1978 dev->d3cold_allowed = true;
1979
1980 dev->d1_support = false;
1981 dev->d2_support = false;
1982 if (!pci_no_d1d2(dev)) {
1983 if (pmc & PCI_PM_CAP_D1)
1984 dev->d1_support = true;
1985 if (pmc & PCI_PM_CAP_D2)
1986 dev->d2_support = true;
1987
1988 if (dev->d1_support || dev->d2_support)
1989 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
1990 dev->d1_support ? " D1" : "",
1991 dev->d2_support ? " D2" : "");
1992 }
1993
1994 pmc &= PCI_PM_CAP_PME_MASK;
1995 if (pmc) {
1996 dev_printk(KERN_DEBUG, &dev->dev,
1997 "PME# supported from%s%s%s%s%s\n",
1998 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1999 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
2000 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
2001 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
2002 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
2003 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
2004 dev->pme_poll = true;
2005
2006
2007
2008
2009 device_set_wakeup_capable(&dev->dev, true);
2010
2011 pci_pme_active(dev, false);
2012 }
2013}
2014
2015static void pci_add_saved_cap(struct pci_dev *pci_dev,
2016 struct pci_cap_saved_state *new_cap)
2017{
2018 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2019}
2020
2021
2022
2023
2024
2025
2026
2027static int pci_add_cap_save_buffer(
2028 struct pci_dev *dev, char cap, unsigned int size)
2029{
2030 int pos;
2031 struct pci_cap_saved_state *save_state;
2032
2033 pos = pci_find_capability(dev, cap);
2034 if (pos <= 0)
2035 return 0;
2036
2037 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2038 if (!save_state)
2039 return -ENOMEM;
2040
2041 save_state->cap.cap_nr = cap;
2042 save_state->cap.size = size;
2043 pci_add_saved_cap(dev, save_state);
2044
2045 return 0;
2046}
2047
2048
2049
2050
2051
2052void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2053{
2054 int error;
2055
2056 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2057 PCI_EXP_SAVE_REGS * sizeof(u16));
2058 if (error)
2059 dev_err(&dev->dev,
2060 "unable to preallocate PCI Express save buffer\n");
2061
2062 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2063 if (error)
2064 dev_err(&dev->dev,
2065 "unable to preallocate PCI-X save buffer\n");
2066}
2067
2068void pci_free_cap_save_buffers(struct pci_dev *dev)
2069{
2070 struct pci_cap_saved_state *tmp;
2071 struct hlist_node *n;
2072
2073 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
2074 kfree(tmp);
2075}
2076
2077
2078
2079
2080
2081
2082
2083
2084void pci_configure_ari(struct pci_dev *dev)
2085{
2086 u32 cap;
2087 struct pci_dev *bridge;
2088
2089 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2090 return;
2091
2092 bridge = dev->bus->self;
2093 if (!bridge)
2094 return;
2095
2096 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2097 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2098 return;
2099
2100 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2101 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2102 PCI_EXP_DEVCTL2_ARI);
2103 bridge->ari_enabled = 1;
2104 } else {
2105 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2106 PCI_EXP_DEVCTL2_ARI);
2107 bridge->ari_enabled = 0;
2108 }
2109}
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120void pci_enable_ido(struct pci_dev *dev, unsigned long type)
2121{
2122 u16 ctrl = 0;
2123
2124 if (type & PCI_EXP_IDO_REQUEST)
2125 ctrl |= PCI_EXP_DEVCTL2_IDO_REQ_EN;
2126 if (type & PCI_EXP_IDO_COMPLETION)
2127 ctrl |= PCI_EXP_DEVCTL2_IDO_CMP_EN;
2128 if (ctrl)
2129 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, ctrl);
2130}
2131EXPORT_SYMBOL(pci_enable_ido);
2132
2133
2134
2135
2136
2137
2138void pci_disable_ido(struct pci_dev *dev, unsigned long type)
2139{
2140 u16 ctrl = 0;
2141
2142 if (type & PCI_EXP_IDO_REQUEST)
2143 ctrl |= PCI_EXP_DEVCTL2_IDO_REQ_EN;
2144 if (type & PCI_EXP_IDO_COMPLETION)
2145 ctrl |= PCI_EXP_DEVCTL2_IDO_CMP_EN;
2146 if (ctrl)
2147 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, ctrl);
2148}
2149EXPORT_SYMBOL(pci_disable_ido);
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
2171{
2172 u32 cap;
2173 u16 ctrl;
2174 int ret;
2175
2176 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2177 if (!(cap & PCI_EXP_DEVCAP2_OBFF_MASK))
2178 return -ENOTSUPP;
2179
2180
2181 if (dev->bus->self) {
2182 ret = pci_enable_obff(dev->bus->self, type);
2183 if (ret)
2184 return ret;
2185 }
2186
2187 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &ctrl);
2188 if (cap & PCI_EXP_DEVCAP2_OBFF_WAKE)
2189 ctrl |= PCI_EXP_DEVCTL2_OBFF_WAKE_EN;
2190 else {
2191 switch (type) {
2192 case PCI_EXP_OBFF_SIGNAL_L0:
2193 if (!(ctrl & PCI_EXP_DEVCTL2_OBFF_WAKE_EN))
2194 ctrl |= PCI_EXP_DEVCTL2_OBFF_MSGA_EN;
2195 break;
2196 case PCI_EXP_OBFF_SIGNAL_ALWAYS:
2197 ctrl &= ~PCI_EXP_DEVCTL2_OBFF_WAKE_EN;
2198 ctrl |= PCI_EXP_DEVCTL2_OBFF_MSGB_EN;
2199 break;
2200 default:
2201 WARN(1, "bad OBFF signal type\n");
2202 return -ENOTSUPP;
2203 }
2204 }
2205 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, ctrl);
2206
2207 return 0;
2208}
2209EXPORT_SYMBOL(pci_enable_obff);
2210
2211
2212
2213
2214
2215
2216
2217void pci_disable_obff(struct pci_dev *dev)
2218{
2219 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2,
2220 PCI_EXP_DEVCTL2_OBFF_WAKE_EN);
2221}
2222EXPORT_SYMBOL(pci_disable_obff);
2223
2224
2225
2226
2227
2228
2229
2230
2231static bool pci_ltr_supported(struct pci_dev *dev)
2232{
2233 u32 cap;
2234
2235 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2236
2237 return cap & PCI_EXP_DEVCAP2_LTR;
2238}
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250int pci_enable_ltr(struct pci_dev *dev)
2251{
2252 int ret;
2253
2254
2255 if (PCI_FUNC(dev->devfn) != 0)
2256 return -EINVAL;
2257
2258 if (!pci_ltr_supported(dev))
2259 return -ENOTSUPP;
2260
2261
2262 if (dev->bus->self) {
2263 ret = pci_enable_ltr(dev->bus->self);
2264 if (ret)
2265 return ret;
2266 }
2267
2268 return pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
2269 PCI_EXP_DEVCTL2_LTR_EN);
2270}
2271EXPORT_SYMBOL(pci_enable_ltr);
2272
2273
2274
2275
2276
2277void pci_disable_ltr(struct pci_dev *dev)
2278{
2279
2280 if (PCI_FUNC(dev->devfn) != 0)
2281 return;
2282
2283 if (!pci_ltr_supported(dev))
2284 return;
2285
2286 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2,
2287 PCI_EXP_DEVCTL2_LTR_EN);
2288}
2289EXPORT_SYMBOL(pci_disable_ltr);
2290
2291static int __pci_ltr_scale(int *val)
2292{
2293 int scale = 0;
2294
2295 while (*val > 1023) {
2296 *val = (*val + 31) / 32;
2297 scale++;
2298 }
2299 return scale;
2300}
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns)
2311{
2312 int pos, ret, snoop_scale, nosnoop_scale;
2313 u16 val;
2314
2315 if (!pci_ltr_supported(dev))
2316 return -ENOTSUPP;
2317
2318 snoop_scale = __pci_ltr_scale(&snoop_lat_ns);
2319 nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns);
2320
2321 if (snoop_lat_ns > PCI_LTR_VALUE_MASK ||
2322 nosnoop_lat_ns > PCI_LTR_VALUE_MASK)
2323 return -EINVAL;
2324
2325 if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) ||
2326 (nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)))
2327 return -EINVAL;
2328
2329 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
2330 if (!pos)
2331 return -ENOTSUPP;
2332
2333 val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns;
2334 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val);
2335 if (ret != 4)
2336 return -EIO;
2337
2338 val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns;
2339 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val);
2340 if (ret != 4)
2341 return -EIO;
2342
2343 return 0;
2344}
2345EXPORT_SYMBOL(pci_set_ltr);
2346
2347static int pci_acs_enable;
2348
2349
2350
2351
2352void pci_request_acs(void)
2353{
2354 pci_acs_enable = 1;
2355}
2356
2357
2358
2359
2360
2361void pci_enable_acs(struct pci_dev *dev)
2362{
2363 int pos;
2364 u16 cap;
2365 u16 ctrl;
2366
2367 if (!pci_acs_enable)
2368 return;
2369
2370 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2371 if (!pos)
2372 return;
2373
2374 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2375 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2376
2377
2378 ctrl |= (cap & PCI_ACS_SV);
2379
2380
2381 ctrl |= (cap & PCI_ACS_RR);
2382
2383
2384 ctrl |= (cap & PCI_ACS_CR);
2385
2386
2387 ctrl |= (cap & PCI_ACS_UF);
2388
2389 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2390}
2391
2392static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
2393{
2394 int pos;
2395 u16 cap, ctrl;
2396
2397 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2398 if (!pos)
2399 return false;
2400
2401
2402
2403
2404
2405
2406 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
2407 acs_flags &= (cap | PCI_ACS_EC);
2408
2409 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2410 return (ctrl & acs_flags) == acs_flags;
2411}
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2430{
2431 int ret;
2432
2433 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2434 if (ret >= 0)
2435 return ret > 0;
2436
2437
2438
2439
2440
2441
2442 if (!pci_is_pcie(pdev))
2443 return false;
2444
2445 switch (pci_pcie_type(pdev)) {
2446
2447
2448
2449
2450
2451 case PCI_EXP_TYPE_PCIE_BRIDGE:
2452
2453
2454
2455
2456
2457
2458 case PCI_EXP_TYPE_PCI_BRIDGE:
2459 case PCI_EXP_TYPE_RC_EC:
2460 return false;
2461
2462
2463
2464
2465
2466 case PCI_EXP_TYPE_DOWNSTREAM:
2467 case PCI_EXP_TYPE_ROOT_PORT:
2468 return pci_acs_flags_enabled(pdev, acs_flags);
2469
2470
2471
2472
2473
2474
2475
2476 case PCI_EXP_TYPE_ENDPOINT:
2477 case PCI_EXP_TYPE_UPSTREAM:
2478 case PCI_EXP_TYPE_LEG_END:
2479 case PCI_EXP_TYPE_RC_END:
2480 if (!pdev->multifunction)
2481 break;
2482
2483 return pci_acs_flags_enabled(pdev, acs_flags);
2484 }
2485
2486
2487
2488
2489
2490 return true;
2491}
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502bool pci_acs_path_enabled(struct pci_dev *start,
2503 struct pci_dev *end, u16 acs_flags)
2504{
2505 struct pci_dev *pdev, *parent = start;
2506
2507 do {
2508 pdev = parent;
2509
2510 if (!pci_acs_enabled(pdev, acs_flags))
2511 return false;
2512
2513 if (pci_is_root_bus(pdev->bus))
2514 return (end == NULL);
2515
2516 parent = pdev->bus->self;
2517 } while (pdev != end);
2518
2519 return true;
2520}
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
2534{
2535 int slot;
2536
2537 if (pci_ari_enabled(dev->bus))
2538 slot = 0;
2539 else
2540 slot = PCI_SLOT(dev->devfn);
2541
2542 return (((pin - 1) + slot) % 4) + 1;
2543}
2544
2545int
2546pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2547{
2548 u8 pin;
2549
2550 pin = dev->pin;
2551 if (!pin)
2552 return -1;
2553
2554 while (!pci_is_root_bus(dev->bus)) {
2555 pin = pci_swizzle_interrupt_pin(dev, pin);
2556 dev = dev->bus->self;
2557 }
2558 *bridge = dev;
2559 return pin;
2560}
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2571{
2572 u8 pin = *pinp;
2573
2574 while (!pci_is_root_bus(dev->bus)) {
2575 pin = pci_swizzle_interrupt_pin(dev, pin);
2576 dev = dev->bus->self;
2577 }
2578 *pinp = pin;
2579 return PCI_SLOT(dev->devfn);
2580}
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591void pci_release_region(struct pci_dev *pdev, int bar)
2592{
2593 struct pci_devres *dr;
2594
2595 if (pci_resource_len(pdev, bar) == 0)
2596 return;
2597 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2598 release_region(pci_resource_start(pdev, bar),
2599 pci_resource_len(pdev, bar));
2600 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2601 release_mem_region(pci_resource_start(pdev, bar),
2602 pci_resource_len(pdev, bar));
2603
2604 dr = find_pci_dr(pdev);
2605 if (dr)
2606 dr->region_mask &= ~(1 << bar);
2607}
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
2629 int exclusive)
2630{
2631 struct pci_devres *dr;
2632
2633 if (pci_resource_len(pdev, bar) == 0)
2634 return 0;
2635
2636 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2637 if (!request_region(pci_resource_start(pdev, bar),
2638 pci_resource_len(pdev, bar), res_name))
2639 goto err_out;
2640 }
2641 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
2642 if (!__request_mem_region(pci_resource_start(pdev, bar),
2643 pci_resource_len(pdev, bar), res_name,
2644 exclusive))
2645 goto err_out;
2646 }
2647
2648 dr = find_pci_dr(pdev);
2649 if (dr)
2650 dr->region_mask |= 1 << bar;
2651
2652 return 0;
2653
2654err_out:
2655 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
2656 &pdev->resource[bar]);
2657 return -EBUSY;
2658}
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2675{
2676 return __pci_request_region(pdev, bar, res_name, 0);
2677}
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
2698{
2699 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2700}
2701
2702
2703
2704
2705
2706
2707
2708
2709void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2710{
2711 int i;
2712
2713 for (i = 0; i < 6; i++)
2714 if (bars & (1 << i))
2715 pci_release_region(pdev, i);
2716}
2717
2718static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2719 const char *res_name, int excl)
2720{
2721 int i;
2722
2723 for (i = 0; i < 6; i++)
2724 if (bars & (1 << i))
2725 if (__pci_request_region(pdev, i, res_name, excl))
2726 goto err_out;
2727 return 0;
2728
2729err_out:
2730 while(--i >= 0)
2731 if (bars & (1 << i))
2732 pci_release_region(pdev, i);
2733
2734 return -EBUSY;
2735}
2736
2737
2738
2739
2740
2741
2742
2743
2744int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2745 const char *res_name)
2746{
2747 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2748}
2749
2750int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2751 int bars, const char *res_name)
2752{
2753 return __pci_request_selected_regions(pdev, bars, res_name,
2754 IORESOURCE_EXCLUSIVE);
2755}
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766void pci_release_regions(struct pci_dev *pdev)
2767{
2768 pci_release_selected_regions(pdev, (1 << 6) - 1);
2769}
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784int pci_request_regions(struct pci_dev *pdev, const char *res_name)
2785{
2786 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
2787}
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2806{
2807 return pci_request_selected_regions_exclusive(pdev,
2808 ((1 << 6) - 1), res_name);
2809}
2810
2811static void __pci_set_master(struct pci_dev *dev, bool enable)
2812{
2813 u16 old_cmd, cmd;
2814
2815 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2816 if (enable)
2817 cmd = old_cmd | PCI_COMMAND_MASTER;
2818 else
2819 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2820 if (cmd != old_cmd) {
2821 dev_dbg(&dev->dev, "%s bus mastering\n",
2822 enable ? "enabling" : "disabling");
2823 pci_write_config_word(dev, PCI_COMMAND, cmd);
2824 }
2825 dev->is_busmaster = enable;
2826}
2827
2828
2829
2830
2831
2832
2833
2834
2835char * __weak __init pcibios_setup(char *str)
2836{
2837 return str;
2838}
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848void __weak pcibios_set_master(struct pci_dev *dev)
2849{
2850 u8 lat;
2851
2852
2853 if (pci_is_pcie(dev))
2854 return;
2855
2856 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
2857 if (lat < 16)
2858 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
2859 else if (lat > pcibios_max_latency)
2860 lat = pcibios_max_latency;
2861 else
2862 return;
2863 dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat);
2864 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
2865}
2866
2867
2868
2869
2870
2871
2872
2873
2874void pci_set_master(struct pci_dev *dev)
2875{
2876 __pci_set_master(dev, true);
2877 pcibios_set_master(dev);
2878}
2879
2880
2881
2882
2883
2884void pci_clear_master(struct pci_dev *dev)
2885{
2886 __pci_set_master(dev, false);
2887}
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899int pci_set_cacheline_size(struct pci_dev *dev)
2900{
2901 u8 cacheline_size;
2902
2903 if (!pci_cache_line_size)
2904 return -EINVAL;
2905
2906
2907
2908 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2909 if (cacheline_size >= pci_cache_line_size &&
2910 (cacheline_size % pci_cache_line_size) == 0)
2911 return 0;
2912
2913
2914 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2915
2916 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2917 if (cacheline_size == pci_cache_line_size)
2918 return 0;
2919
2920 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2921 "supported\n", pci_cache_line_size << 2);
2922
2923 return -EINVAL;
2924}
2925EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2926
2927#ifdef PCI_DISABLE_MWI
2928int pci_set_mwi(struct pci_dev *dev)
2929{
2930 return 0;
2931}
2932
2933int pci_try_set_mwi(struct pci_dev *dev)
2934{
2935 return 0;
2936}
2937
2938void pci_clear_mwi(struct pci_dev *dev)
2939{
2940}
2941
2942#else
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952int
2953pci_set_mwi(struct pci_dev *dev)
2954{
2955 int rc;
2956 u16 cmd;
2957
2958 rc = pci_set_cacheline_size(dev);
2959 if (rc)
2960 return rc;
2961
2962 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2963 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
2964 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
2965 cmd |= PCI_COMMAND_INVALIDATE;
2966 pci_write_config_word(dev, PCI_COMMAND, cmd);
2967 }
2968
2969 return 0;
2970}
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981int pci_try_set_mwi(struct pci_dev *dev)
2982{
2983 int rc = pci_set_mwi(dev);
2984 return rc;
2985}
2986
2987
2988
2989
2990
2991
2992
2993void
2994pci_clear_mwi(struct pci_dev *dev)
2995{
2996 u16 cmd;
2997
2998 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2999 if (cmd & PCI_COMMAND_INVALIDATE) {
3000 cmd &= ~PCI_COMMAND_INVALIDATE;
3001 pci_write_config_word(dev, PCI_COMMAND, cmd);
3002 }
3003}
3004#endif
3005
3006
3007
3008
3009
3010
3011
3012
3013void
3014pci_intx(struct pci_dev *pdev, int enable)
3015{
3016 u16 pci_command, new;
3017
3018 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
3019
3020 if (enable) {
3021 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
3022 } else {
3023 new = pci_command | PCI_COMMAND_INTX_DISABLE;
3024 }
3025
3026 if (new != pci_command) {
3027 struct pci_devres *dr;
3028
3029 pci_write_config_word(pdev, PCI_COMMAND, new);
3030
3031 dr = find_pci_dr(pdev);
3032 if (dr && !dr->restore_intx) {
3033 dr->restore_intx = 1;
3034 dr->orig_intx = !enable;
3035 }
3036 }
3037}
3038
3039
3040
3041
3042
3043
3044
3045
3046bool pci_intx_mask_supported(struct pci_dev *dev)
3047{
3048 bool mask_supported = false;
3049 u16 orig, new;
3050
3051 if (dev->broken_intx_masking)
3052 return false;
3053
3054 pci_cfg_access_lock(dev);
3055
3056 pci_read_config_word(dev, PCI_COMMAND, &orig);
3057 pci_write_config_word(dev, PCI_COMMAND,
3058 orig ^ PCI_COMMAND_INTX_DISABLE);
3059 pci_read_config_word(dev, PCI_COMMAND, &new);
3060
3061
3062
3063
3064
3065
3066 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
3067 dev_err(&dev->dev, "Command register changed from "
3068 "0x%x to 0x%x: driver or hardware bug?\n", orig, new);
3069 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
3070 mask_supported = true;
3071 pci_write_config_word(dev, PCI_COMMAND, orig);
3072 }
3073
3074 pci_cfg_access_unlock(dev);
3075 return mask_supported;
3076}
3077EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
3078
3079static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
3080{
3081 struct pci_bus *bus = dev->bus;
3082 bool mask_updated = true;
3083 u32 cmd_status_dword;
3084 u16 origcmd, newcmd;
3085 unsigned long flags;
3086 bool irq_pending;
3087
3088
3089
3090
3091
3092 BUILD_BUG_ON(PCI_COMMAND % 4);
3093 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
3094
3095 raw_spin_lock_irqsave(&pci_lock, flags);
3096
3097 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
3098
3099 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
3100
3101
3102
3103
3104
3105
3106 if (mask != irq_pending) {
3107 mask_updated = false;
3108 goto done;
3109 }
3110
3111 origcmd = cmd_status_dword;
3112 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
3113 if (mask)
3114 newcmd |= PCI_COMMAND_INTX_DISABLE;
3115 if (newcmd != origcmd)
3116 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
3117
3118done:
3119 raw_spin_unlock_irqrestore(&pci_lock, flags);
3120
3121 return mask_updated;
3122}
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132bool pci_check_and_mask_intx(struct pci_dev *dev)
3133{
3134 return pci_check_and_set_intx_mask(dev, true);
3135}
3136EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146bool pci_check_and_unmask_intx(struct pci_dev *dev)
3147{
3148 return pci_check_and_set_intx_mask(dev, false);
3149}
3150EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160void pci_msi_off(struct pci_dev *dev)
3161{
3162 int pos;
3163 u16 control;
3164
3165
3166
3167
3168
3169
3170 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
3171 if (pos) {
3172 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
3173 control &= ~PCI_MSI_FLAGS_ENABLE;
3174 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
3175 }
3176 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
3177 if (pos) {
3178 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
3179 control &= ~PCI_MSIX_FLAGS_ENABLE;
3180 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
3181 }
3182}
3183EXPORT_SYMBOL_GPL(pci_msi_off);
3184
3185int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
3186{
3187 return dma_set_max_seg_size(&dev->dev, size);
3188}
3189EXPORT_SYMBOL(pci_set_dma_max_seg_size);
3190
3191int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
3192{
3193 return dma_set_seg_boundary(&dev->dev, mask);
3194}
3195EXPORT_SYMBOL(pci_set_dma_seg_boundary);
3196
3197
3198
3199
3200
3201
3202
3203int pci_wait_for_pending_transaction(struct pci_dev *dev)
3204{
3205 int i;
3206 u16 status;
3207
3208
3209 for (i = 0; i < 4; i++) {
3210 if (i)
3211 msleep((1 << (i - 1)) * 100);
3212
3213 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
3214 if (!(status & PCI_EXP_DEVSTA_TRPND))
3215 return 1;
3216 }
3217
3218 return 0;
3219}
3220EXPORT_SYMBOL(pci_wait_for_pending_transaction);
3221
3222static int pcie_flr(struct pci_dev *dev, int probe)
3223{
3224 u32 cap;
3225
3226 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
3227 if (!(cap & PCI_EXP_DEVCAP_FLR))
3228 return -ENOTTY;
3229
3230 if (probe)
3231 return 0;
3232
3233 if (!pci_wait_for_pending_transaction(dev))
3234 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3235
3236 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3237
3238 msleep(100);
3239
3240 return 0;
3241}
3242
3243static int pci_af_flr(struct pci_dev *dev, int probe)
3244{
3245 int i;
3246 int pos;
3247 u8 cap;
3248 u8 status;
3249
3250 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3251 if (!pos)
3252 return -ENOTTY;
3253
3254 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
3255 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3256 return -ENOTTY;
3257
3258 if (probe)
3259 return 0;
3260
3261
3262 for (i = 0; i < 4; i++) {
3263 if (i)
3264 msleep((1 << (i - 1)) * 100);
3265
3266 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
3267 if (!(status & PCI_AF_STATUS_TP))
3268 goto clear;
3269 }
3270
3271 dev_err(&dev->dev, "transaction is not cleared; "
3272 "proceeding with reset anyway\n");
3273
3274clear:
3275 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
3276 msleep(100);
3277
3278 return 0;
3279}
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296static int pci_pm_reset(struct pci_dev *dev, int probe)
3297{
3298 u16 csr;
3299
3300 if (!dev->pm_cap)
3301 return -ENOTTY;
3302
3303 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
3304 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
3305 return -ENOTTY;
3306
3307 if (probe)
3308 return 0;
3309
3310 if (dev->current_state != PCI_D0)
3311 return -EINVAL;
3312
3313 csr &= ~PCI_PM_CTRL_STATE_MASK;
3314 csr |= PCI_D3hot;
3315 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3316 pci_dev_d3_sleep(dev);
3317
3318 csr &= ~PCI_PM_CTRL_STATE_MASK;
3319 csr |= PCI_D0;
3320 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3321 pci_dev_d3_sleep(dev);
3322
3323 return 0;
3324}
3325
3326
3327
3328
3329
3330
3331
3332
3333void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
3334{
3335 u16 ctrl;
3336
3337 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
3338 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3339 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3340
3341
3342
3343
3344 msleep(2);
3345
3346 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3347 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3348
3349
3350
3351
3352
3353
3354
3355
3356 ssleep(1);
3357}
3358EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
3359
3360static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3361{
3362 struct pci_dev *pdev;
3363
3364 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
3365 return -ENOTTY;
3366
3367 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3368 if (pdev != dev)
3369 return -ENOTTY;
3370
3371 if (probe)
3372 return 0;
3373
3374 pci_reset_bridge_secondary_bus(dev->bus->self);
3375
3376 return 0;
3377}
3378
3379static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
3380{
3381 int rc = -ENOTTY;
3382
3383 if (!hotplug || !try_module_get(hotplug->ops->owner))
3384 return rc;
3385
3386 if (hotplug->ops->reset_slot)
3387 rc = hotplug->ops->reset_slot(hotplug, probe);
3388
3389 module_put(hotplug->ops->owner);
3390
3391 return rc;
3392}
3393
3394static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
3395{
3396 struct pci_dev *pdev;
3397
3398 if (dev->subordinate || !dev->slot)
3399 return -ENOTTY;
3400
3401 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3402 if (pdev != dev && pdev->slot == dev->slot)
3403 return -ENOTTY;
3404
3405 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
3406}
3407
3408static int __pci_dev_reset(struct pci_dev *dev, int probe)
3409{
3410 int rc;
3411
3412 might_sleep();
3413
3414 rc = pci_dev_specific_reset(dev, probe);
3415 if (rc != -ENOTTY)
3416 goto done;
3417
3418 rc = pcie_flr(dev, probe);
3419 if (rc != -ENOTTY)
3420 goto done;
3421
3422 rc = pci_af_flr(dev, probe);
3423 if (rc != -ENOTTY)
3424 goto done;
3425
3426 rc = pci_pm_reset(dev, probe);
3427 if (rc != -ENOTTY)
3428 goto done;
3429
3430 rc = pci_dev_reset_slot_function(dev, probe);
3431 if (rc != -ENOTTY)
3432 goto done;
3433
3434 rc = pci_parent_bus_reset(dev, probe);
3435done:
3436 return rc;
3437}
3438
3439static void pci_dev_lock(struct pci_dev *dev)
3440{
3441 pci_cfg_access_lock(dev);
3442
3443 device_lock(&dev->dev);
3444}
3445
3446static void pci_dev_unlock(struct pci_dev *dev)
3447{
3448 device_unlock(&dev->dev);
3449 pci_cfg_access_unlock(dev);
3450}
3451
3452static void pci_dev_save_and_disable(struct pci_dev *dev)
3453{
3454
3455
3456
3457
3458
3459 pci_set_power_state(dev, PCI_D0);
3460
3461 pci_save_state(dev);
3462
3463
3464
3465
3466
3467
3468
3469 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3470}
3471
3472static void pci_dev_restore(struct pci_dev *dev)
3473{
3474 pci_restore_state(dev);
3475}
3476
3477static int pci_dev_reset(struct pci_dev *dev, int probe)
3478{
3479 int rc;
3480
3481 if (!probe)
3482 pci_dev_lock(dev);
3483
3484 rc = __pci_dev_reset(dev, probe);
3485
3486 if (!probe)
3487 pci_dev_unlock(dev);
3488
3489 return rc;
3490}
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508int __pci_reset_function(struct pci_dev *dev)
3509{
3510 return pci_dev_reset(dev, 0);
3511}
3512EXPORT_SYMBOL_GPL(__pci_reset_function);
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533int __pci_reset_function_locked(struct pci_dev *dev)
3534{
3535 return __pci_dev_reset(dev, 0);
3536}
3537EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550int pci_probe_reset_function(struct pci_dev *dev)
3551{
3552 return pci_dev_reset(dev, 1);
3553}
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571int pci_reset_function(struct pci_dev *dev)
3572{
3573 int rc;
3574
3575 rc = pci_dev_reset(dev, 1);
3576 if (rc)
3577 return rc;
3578
3579 pci_dev_save_and_disable(dev);
3580
3581 rc = pci_dev_reset(dev, 0);
3582
3583 pci_dev_restore(dev);
3584
3585 return rc;
3586}
3587EXPORT_SYMBOL_GPL(pci_reset_function);
3588
3589
3590static void pci_bus_lock(struct pci_bus *bus)
3591{
3592 struct pci_dev *dev;
3593
3594 list_for_each_entry(dev, &bus->devices, bus_list) {
3595 pci_dev_lock(dev);
3596 if (dev->subordinate)
3597 pci_bus_lock(dev->subordinate);
3598 }
3599}
3600
3601
3602static void pci_bus_unlock(struct pci_bus *bus)
3603{
3604 struct pci_dev *dev;
3605
3606 list_for_each_entry(dev, &bus->devices, bus_list) {
3607 if (dev->subordinate)
3608 pci_bus_unlock(dev->subordinate);
3609 pci_dev_unlock(dev);
3610 }
3611}
3612
3613
3614static void pci_slot_lock(struct pci_slot *slot)
3615{
3616 struct pci_dev *dev;
3617
3618 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3619 if (!dev->slot || dev->slot != slot)
3620 continue;
3621 pci_dev_lock(dev);
3622 if (dev->subordinate)
3623 pci_bus_lock(dev->subordinate);
3624 }
3625}
3626
3627
3628static void pci_slot_unlock(struct pci_slot *slot)
3629{
3630 struct pci_dev *dev;
3631
3632 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3633 if (!dev->slot || dev->slot != slot)
3634 continue;
3635 if (dev->subordinate)
3636 pci_bus_unlock(dev->subordinate);
3637 pci_dev_unlock(dev);
3638 }
3639}
3640
3641
3642static void pci_bus_save_and_disable(struct pci_bus *bus)
3643{
3644 struct pci_dev *dev;
3645
3646 list_for_each_entry(dev, &bus->devices, bus_list) {
3647 pci_dev_save_and_disable(dev);
3648 if (dev->subordinate)
3649 pci_bus_save_and_disable(dev->subordinate);
3650 }
3651}
3652
3653
3654
3655
3656
3657static void pci_bus_restore(struct pci_bus *bus)
3658{
3659 struct pci_dev *dev;
3660
3661 list_for_each_entry(dev, &bus->devices, bus_list) {
3662 pci_dev_restore(dev);
3663 if (dev->subordinate)
3664 pci_bus_restore(dev->subordinate);
3665 }
3666}
3667
3668
3669static void pci_slot_save_and_disable(struct pci_slot *slot)
3670{
3671 struct pci_dev *dev;
3672
3673 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3674 if (!dev->slot || dev->slot != slot)
3675 continue;
3676 pci_dev_save_and_disable(dev);
3677 if (dev->subordinate)
3678 pci_bus_save_and_disable(dev->subordinate);
3679 }
3680}
3681
3682
3683
3684
3685
3686static void pci_slot_restore(struct pci_slot *slot)
3687{
3688 struct pci_dev *dev;
3689
3690 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3691 if (!dev->slot || dev->slot != slot)
3692 continue;
3693 pci_dev_restore(dev);
3694 if (dev->subordinate)
3695 pci_bus_restore(dev->subordinate);
3696 }
3697}
3698
3699static int pci_slot_reset(struct pci_slot *slot, int probe)
3700{
3701 int rc;
3702
3703 if (!slot)
3704 return -ENOTTY;
3705
3706 if (!probe)
3707 pci_slot_lock(slot);
3708
3709 might_sleep();
3710
3711 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
3712
3713 if (!probe)
3714 pci_slot_unlock(slot);
3715
3716 return rc;
3717}
3718
3719
3720
3721
3722
3723
3724
3725int pci_probe_reset_slot(struct pci_slot *slot)
3726{
3727 return pci_slot_reset(slot, 1);
3728}
3729EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746int pci_reset_slot(struct pci_slot *slot)
3747{
3748 int rc;
3749
3750 rc = pci_slot_reset(slot, 1);
3751 if (rc)
3752 return rc;
3753
3754 pci_slot_save_and_disable(slot);
3755
3756 rc = pci_slot_reset(slot, 0);
3757
3758 pci_slot_restore(slot);
3759
3760 return rc;
3761}
3762EXPORT_SYMBOL_GPL(pci_reset_slot);
3763
3764static int pci_bus_reset(struct pci_bus *bus, int probe)
3765{
3766 if (!bus->self)
3767 return -ENOTTY;
3768
3769 if (probe)
3770 return 0;
3771
3772 pci_bus_lock(bus);
3773
3774 might_sleep();
3775
3776 pci_reset_bridge_secondary_bus(bus->self);
3777
3778 pci_bus_unlock(bus);
3779
3780 return 0;
3781}
3782
3783
3784
3785
3786
3787
3788
3789int pci_probe_reset_bus(struct pci_bus *bus)
3790{
3791 return pci_bus_reset(bus, 1);
3792}
3793EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804int pci_reset_bus(struct pci_bus *bus)
3805{
3806 int rc;
3807
3808 rc = pci_bus_reset(bus, 1);
3809 if (rc)
3810 return rc;
3811
3812 pci_bus_save_and_disable(bus);
3813
3814 rc = pci_bus_reset(bus, 0);
3815
3816 pci_bus_restore(bus);
3817
3818 return rc;
3819}
3820EXPORT_SYMBOL_GPL(pci_reset_bus);
3821
3822
3823
3824
3825
3826
3827
3828
3829int pcix_get_max_mmrbc(struct pci_dev *dev)
3830{
3831 int cap;
3832 u32 stat;
3833
3834 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3835 if (!cap)
3836 return -EINVAL;
3837
3838 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3839 return -EINVAL;
3840
3841 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
3842}
3843EXPORT_SYMBOL(pcix_get_max_mmrbc);
3844
3845
3846
3847
3848
3849
3850
3851
3852int pcix_get_mmrbc(struct pci_dev *dev)
3853{
3854 int cap;
3855 u16 cmd;
3856
3857 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3858 if (!cap)
3859 return -EINVAL;
3860
3861 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3862 return -EINVAL;
3863
3864 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
3865}
3866EXPORT_SYMBOL(pcix_get_mmrbc);
3867
3868
3869
3870
3871
3872
3873
3874
3875
3876
3877int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
3878{
3879 int cap;
3880 u32 stat, v, o;
3881 u16 cmd;
3882
3883 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
3884 return -EINVAL;
3885
3886 v = ffs(mmrbc) - 10;
3887
3888 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3889 if (!cap)
3890 return -EINVAL;
3891
3892 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3893 return -EINVAL;
3894
3895 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
3896 return -E2BIG;
3897
3898 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3899 return -EINVAL;
3900
3901 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
3902 if (o != v) {
3903 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
3904 return -EIO;
3905
3906 cmd &= ~PCI_X_CMD_MAX_READ;
3907 cmd |= v << 2;
3908 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
3909 return -EIO;
3910 }
3911 return 0;
3912}
3913EXPORT_SYMBOL(pcix_set_mmrbc);
3914
3915
3916
3917
3918
3919
3920
3921
3922int pcie_get_readrq(struct pci_dev *dev)
3923{
3924 u16 ctl;
3925
3926 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
3927
3928 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
3929}
3930EXPORT_SYMBOL(pcie_get_readrq);
3931
3932
3933
3934
3935
3936
3937
3938
3939
3940int pcie_set_readrq(struct pci_dev *dev, int rq)
3941{
3942 u16 v;
3943
3944 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
3945 return -EINVAL;
3946
3947
3948
3949
3950
3951
3952
3953 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
3954 int mps = pcie_get_mps(dev);
3955
3956 if (mps < rq)
3957 rq = mps;
3958 }
3959
3960 v = (ffs(rq) - 8) << 12;
3961
3962 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
3963 PCI_EXP_DEVCTL_READRQ, v);
3964}
3965EXPORT_SYMBOL(pcie_set_readrq);
3966
3967
3968
3969
3970
3971
3972
3973int pcie_get_mps(struct pci_dev *dev)
3974{
3975 u16 ctl;
3976
3977 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
3978
3979 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
3980}
3981
3982
3983
3984
3985
3986
3987
3988
3989
3990int pcie_set_mps(struct pci_dev *dev, int mps)
3991{
3992 u16 v;
3993
3994 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
3995 return -EINVAL;
3996
3997 v = ffs(mps) - 8;
3998 if (v > dev->pcie_mpss)
3999 return -EINVAL;
4000 v <<= 5;
4001
4002 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4003 PCI_EXP_DEVCTL_PAYLOAD, v);
4004}
4005
4006
4007
4008
4009
4010
4011
4012
4013
4014
4015int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
4016 enum pcie_link_width *width)
4017{
4018 int ret;
4019
4020 *speed = PCI_SPEED_UNKNOWN;
4021 *width = PCIE_LNK_WIDTH_UNKNOWN;
4022
4023 while (dev) {
4024 u16 lnksta;
4025 enum pci_bus_speed next_speed;
4026 enum pcie_link_width next_width;
4027
4028 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
4029 if (ret)
4030 return ret;
4031
4032 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
4033 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
4034 PCI_EXP_LNKSTA_NLW_SHIFT;
4035
4036 if (next_speed < *speed)
4037 *speed = next_speed;
4038
4039 if (next_width < *width)
4040 *width = next_width;
4041
4042 dev = dev->bus->self;
4043 }
4044
4045 return 0;
4046}
4047EXPORT_SYMBOL(pcie_get_minimum_link);
4048
4049
4050
4051
4052
4053
4054
4055
4056int pci_select_bars(struct pci_dev *dev, unsigned long flags)
4057{
4058 int i, bars = 0;
4059 for (i = 0; i < PCI_NUM_RESOURCES; i++)
4060 if (pci_resource_flags(dev, i) & flags)
4061 bars |= (1 << i);
4062 return bars;
4063}
4064
4065
4066
4067
4068
4069
4070
4071
4072
4073int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
4074{
4075 int reg;
4076
4077 if (resno < PCI_ROM_RESOURCE) {
4078 *type = pci_bar_unknown;
4079 return PCI_BASE_ADDRESS_0 + 4 * resno;
4080 } else if (resno == PCI_ROM_RESOURCE) {
4081 *type = pci_bar_mem32;
4082 return dev->rom_base_reg;
4083 } else if (resno < PCI_BRIDGE_RESOURCES) {
4084
4085 reg = pci_iov_resource_bar(dev, resno, type);
4086 if (reg)
4087 return reg;
4088 }
4089
4090 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
4091 return 0;
4092}
4093
4094
4095static arch_set_vga_state_t arch_set_vga_state;
4096
4097void __init pci_register_set_vga_state(arch_set_vga_state_t func)
4098{
4099 arch_set_vga_state = func;
4100}
4101
4102static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
4103 unsigned int command_bits, u32 flags)
4104{
4105 if (arch_set_vga_state)
4106 return arch_set_vga_state(dev, decode, command_bits,
4107 flags);
4108 return 0;
4109}
4110
4111
4112
4113
4114
4115
4116
4117
4118
4119int pci_set_vga_state(struct pci_dev *dev, bool decode,
4120 unsigned int command_bits, u32 flags)
4121{
4122 struct pci_bus *bus;
4123 struct pci_dev *bridge;
4124 u16 cmd;
4125 int rc;
4126
4127 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
4128
4129
4130 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
4131 if (rc)
4132 return rc;
4133
4134 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
4135 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4136 if (decode == true)
4137 cmd |= command_bits;
4138 else
4139 cmd &= ~command_bits;
4140 pci_write_config_word(dev, PCI_COMMAND, cmd);
4141 }
4142
4143 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
4144 return 0;
4145
4146 bus = dev->bus;
4147 while (bus) {
4148 bridge = bus->self;
4149 if (bridge) {
4150 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
4151 &cmd);
4152 if (decode == true)
4153 cmd |= PCI_BRIDGE_CTL_VGA;
4154 else
4155 cmd &= ~PCI_BRIDGE_CTL_VGA;
4156 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
4157 cmd);
4158 }
4159 bus = bus->parent;
4160 }
4161 return 0;
4162}
4163
4164#define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
4165static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
4166static DEFINE_SPINLOCK(resource_alignment_lock);
4167
4168
4169
4170
4171
4172
4173
4174
4175static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
4176{
4177 int seg, bus, slot, func, align_order, count;
4178 resource_size_t align = 0;
4179 char *p;
4180
4181 spin_lock(&resource_alignment_lock);
4182 p = resource_alignment_param;
4183 while (*p) {
4184 count = 0;
4185 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
4186 p[count] == '@') {
4187 p += count + 1;
4188 } else {
4189 align_order = -1;
4190 }
4191 if (sscanf(p, "%x:%x:%x.%x%n",
4192 &seg, &bus, &slot, &func, &count) != 4) {
4193 seg = 0;
4194 if (sscanf(p, "%x:%x.%x%n",
4195 &bus, &slot, &func, &count) != 3) {
4196
4197 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
4198 p);
4199 break;
4200 }
4201 }
4202 p += count;
4203 if (seg == pci_domain_nr(dev->bus) &&
4204 bus == dev->bus->number &&
4205 slot == PCI_SLOT(dev->devfn) &&
4206 func == PCI_FUNC(dev->devfn)) {
4207 if (align_order == -1) {
4208 align = PAGE_SIZE;
4209 } else {
4210 align = 1 << align_order;
4211 }
4212
4213 break;
4214 }
4215 if (*p != ';' && *p != ',') {
4216
4217 break;
4218 }
4219 p++;
4220 }
4221 spin_unlock(&resource_alignment_lock);
4222 return align;
4223}
4224
4225
4226
4227
4228
4229
4230
4231
4232void pci_reassigndev_resource_alignment(struct pci_dev *dev)
4233{
4234 int i;
4235 struct resource *r;
4236 resource_size_t align, size;
4237 u16 command;
4238
4239
4240 align = pci_specified_resource_alignment(dev);
4241 if (!align)
4242 return;
4243
4244 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
4245 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
4246 dev_warn(&dev->dev,
4247 "Can't reassign resources to host bridge.\n");
4248 return;
4249 }
4250
4251 dev_info(&dev->dev,
4252 "Disabling memory decoding and releasing memory resources.\n");
4253 pci_read_config_word(dev, PCI_COMMAND, &command);
4254 command &= ~PCI_COMMAND_MEMORY;
4255 pci_write_config_word(dev, PCI_COMMAND, command);
4256
4257 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
4258 r = &dev->resource[i];
4259 if (!(r->flags & IORESOURCE_MEM))
4260 continue;
4261 size = resource_size(r);
4262 if (size < align) {
4263 size = align;
4264 dev_info(&dev->dev,
4265 "Rounding up size of resource #%d to %#llx.\n",
4266 i, (unsigned long long)size);
4267 }
4268 r->end = size - 1;
4269 r->start = 0;
4270 }
4271
4272
4273
4274
4275 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4276 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
4277 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
4278 r = &dev->resource[i];
4279 if (!(r->flags & IORESOURCE_MEM))
4280 continue;
4281 r->end = resource_size(r) - 1;
4282 r->start = 0;
4283 }
4284 pci_disable_bridge_window(dev);
4285 }
4286}
4287
4288static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
4289{
4290 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
4291 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
4292 spin_lock(&resource_alignment_lock);
4293 strncpy(resource_alignment_param, buf, count);
4294 resource_alignment_param[count] = '\0';
4295 spin_unlock(&resource_alignment_lock);
4296 return count;
4297}
4298
4299static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
4300{
4301 size_t count;
4302 spin_lock(&resource_alignment_lock);
4303 count = snprintf(buf, size, "%s", resource_alignment_param);
4304 spin_unlock(&resource_alignment_lock);
4305 return count;
4306}
4307
4308static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
4309{
4310 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
4311}
4312
4313static ssize_t pci_resource_alignment_store(struct bus_type *bus,
4314 const char *buf, size_t count)
4315{
4316 return pci_set_resource_alignment_param(buf, count);
4317}
4318
4319BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
4320 pci_resource_alignment_store);
4321
4322static int __init pci_resource_alignment_sysfs_init(void)
4323{
4324 return bus_create_file(&pci_bus_type,
4325 &bus_attr_resource_alignment);
4326}
4327
4328late_initcall(pci_resource_alignment_sysfs_init);
4329
4330static void pci_no_domains(void)
4331{
4332#ifdef CONFIG_PCI_DOMAINS
4333 pci_domains_supported = 0;
4334#endif
4335}
4336
4337
4338
4339
4340
4341
4342
4343
4344int __weak pci_ext_cfg_avail(void)
4345{
4346 return 1;
4347}
4348
4349void __weak pci_fixup_cardbus(struct pci_bus *bus)
4350{
4351}
4352EXPORT_SYMBOL(pci_fixup_cardbus);
4353
4354static int __init pci_setup(char *str)
4355{
4356 while (str) {
4357 char *k = strchr(str, ',');
4358 if (k)
4359 *k++ = 0;
4360 if (*str && (str = pcibios_setup(str)) && *str) {
4361 if (!strcmp(str, "nomsi")) {
4362 pci_no_msi();
4363 } else if (!strcmp(str, "noaer")) {
4364 pci_no_aer();
4365 } else if (!strncmp(str, "realloc=", 8)) {
4366 pci_realloc_get_opt(str + 8);
4367 } else if (!strncmp(str, "realloc", 7)) {
4368 pci_realloc_get_opt("on");
4369 } else if (!strcmp(str, "nodomains")) {
4370 pci_no_domains();
4371 } else if (!strncmp(str, "noari", 5)) {
4372 pcie_ari_disabled = true;
4373 } else if (!strncmp(str, "cbiosize=", 9)) {
4374 pci_cardbus_io_size = memparse(str + 9, &str);
4375 } else if (!strncmp(str, "cbmemsize=", 10)) {
4376 pci_cardbus_mem_size = memparse(str + 10, &str);
4377 } else if (!strncmp(str, "resource_alignment=", 19)) {
4378 pci_set_resource_alignment_param(str + 19,
4379 strlen(str + 19));
4380 } else if (!strncmp(str, "ecrc=", 5)) {
4381 pcie_ecrc_get_policy(str + 5);
4382 } else if (!strncmp(str, "hpiosize=", 9)) {
4383 pci_hotplug_io_size = memparse(str + 9, &str);
4384 } else if (!strncmp(str, "hpmemsize=", 10)) {
4385 pci_hotplug_mem_size = memparse(str + 10, &str);
4386 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
4387 pcie_bus_config = PCIE_BUS_TUNE_OFF;
4388 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
4389 pcie_bus_config = PCIE_BUS_SAFE;
4390 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
4391 pcie_bus_config = PCIE_BUS_PERFORMANCE;
4392 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
4393 pcie_bus_config = PCIE_BUS_PEER2PEER;
4394 } else if (!strncmp(str, "pcie_scan_all", 13)) {
4395 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
4396 } else {
4397 printk(KERN_ERR "PCI: Unknown option `%s'\n",
4398 str);
4399 }
4400 }
4401 str = k;
4402 }
4403 return 0;
4404}
4405early_param("pci", pci_setup);
4406
4407EXPORT_SYMBOL(pci_reenable_device);
4408EXPORT_SYMBOL(pci_enable_device_io);
4409EXPORT_SYMBOL(pci_enable_device_mem);
4410EXPORT_SYMBOL(pci_enable_device);
4411EXPORT_SYMBOL(pcim_enable_device);
4412EXPORT_SYMBOL(pcim_pin_device);
4413EXPORT_SYMBOL(pci_disable_device);
4414EXPORT_SYMBOL(pci_find_capability);
4415EXPORT_SYMBOL(pci_bus_find_capability);
4416EXPORT_SYMBOL(pci_release_regions);
4417EXPORT_SYMBOL(pci_request_regions);
4418EXPORT_SYMBOL(pci_request_regions_exclusive);
4419EXPORT_SYMBOL(pci_release_region);
4420EXPORT_SYMBOL(pci_request_region);
4421EXPORT_SYMBOL(pci_request_region_exclusive);
4422EXPORT_SYMBOL(pci_release_selected_regions);
4423EXPORT_SYMBOL(pci_request_selected_regions);
4424EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
4425EXPORT_SYMBOL(pci_set_master);
4426EXPORT_SYMBOL(pci_clear_master);
4427EXPORT_SYMBOL(pci_set_mwi);
4428EXPORT_SYMBOL(pci_try_set_mwi);
4429EXPORT_SYMBOL(pci_clear_mwi);
4430EXPORT_SYMBOL_GPL(pci_intx);
4431EXPORT_SYMBOL(pci_assign_resource);
4432EXPORT_SYMBOL(pci_find_parent_resource);
4433EXPORT_SYMBOL(pci_select_bars);
4434
4435EXPORT_SYMBOL(pci_set_power_state);
4436EXPORT_SYMBOL(pci_save_state);
4437EXPORT_SYMBOL(pci_restore_state);
4438EXPORT_SYMBOL(pci_pme_capable);
4439EXPORT_SYMBOL(pci_pme_active);
4440EXPORT_SYMBOL(pci_wake_from_d3);
4441EXPORT_SYMBOL(pci_target_state);
4442EXPORT_SYMBOL(pci_prepare_to_sleep);
4443EXPORT_SYMBOL(pci_back_from_sleep);
4444EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
4445