LXR linux/drivers/scsi/NCR5380.h

   1/* 
   2 * NCR 5380 defines
   3 *
   4 * Copyright 1993, Drew Eckhardt
   5 *      Visionary Computing
   6 *      (Unix consulting and custom programming)
   7 *      drew@colorado.edu
   8 *      +1 (303) 666-5836
   9 *
  10 * DISTRIBUTION RELEASE 7
  11 *
  12 * For more information, please consult 
  13 *
  14 * NCR 5380 Family
  15 * SCSI Protocol Controller
  16 * Databook
  17 * NCR Microelectronics
  18 * 1635 Aeroplaza Drive
  19 * Colorado Springs, CO 80916
  20 * 1+ (719) 578-3400
  21 * 1+ (800) 334-5454
  22 */
  23
  24/*
  25 * $Log: NCR5380.h,v $
  26 */
  27
  28#ifndef NCR5380_H
  29#define NCR5380_H
  30
  31#include <linux/interrupt.h>
  32
  33#ifdef AUTOSENSE
  34#include <scsi/scsi_eh.h>
  35#endif
  36
  37#define NCR5380_PUBLIC_RELEASE 7
  38#define NCR53C400_PUBLIC_RELEASE 2
  39
  40#define NDEBUG_ARBITRATION      0x1
  41#define NDEBUG_AUTOSENSE        0x2
  42#define NDEBUG_DMA              0x4
  43#define NDEBUG_HANDSHAKE        0x8
  44#define NDEBUG_INFORMATION      0x10
  45#define NDEBUG_INIT             0x20
  46#define NDEBUG_INTR             0x40
  47#define NDEBUG_LINKED           0x80
  48#define NDEBUG_MAIN             0x100
  49#define NDEBUG_NO_DATAOUT       0x200
  50#define NDEBUG_NO_WRITE         0x400
  51#define NDEBUG_PIO              0x800
  52#define NDEBUG_PSEUDO_DMA       0x1000
  53#define NDEBUG_QUEUES           0x2000
  54#define NDEBUG_RESELECTION      0x4000
  55#define NDEBUG_SELECTION        0x8000
  56#define NDEBUG_USLEEP           0x10000
  57#define NDEBUG_LAST_BYTE_SENT   0x20000
  58#define NDEBUG_RESTART_SELECT   0x40000
  59#define NDEBUG_EXTENDED         0x80000
  60#define NDEBUG_C400_PREAD       0x100000
  61#define NDEBUG_C400_PWRITE      0x200000
  62#define NDEBUG_LISTS            0x400000
  63
  64#define NDEBUG_ANY              0xFFFFFFFFUL
  65
  66/* 
  67 * The contents of the OUTPUT DATA register are asserted on the bus when
  68 * either arbitration is occurring or the phase-indicating signals (
  69 * IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA
  70 * bit in the INITIATOR COMMAND register is set.
  71 */
  72
  73#define OUTPUT_DATA_REG         0       /* wo DATA lines on SCSI bus */
  74#define CURRENT_SCSI_DATA_REG   0       /* ro same */
  75
  76#define INITIATOR_COMMAND_REG   1       /* rw */
  77#define ICR_ASSERT_RST          0x80    /* rw Set to assert RST  */
  78#define ICR_ARBITRATION_PROGRESS 0x40   /* ro Indicates arbitration complete */
  79#define ICR_TRI_STATE           0x40    /* wo Set to tri-state drivers */
  80#define ICR_ARBITRATION_LOST    0x20    /* ro Indicates arbitration lost */
  81#define ICR_DIFF_ENABLE         0x20    /* wo Set to enable diff. drivers */
  82#define ICR_ASSERT_ACK          0x10    /* rw ini Set to assert ACK */
  83#define ICR_ASSERT_BSY          0x08    /* rw Set to assert BSY */
  84#define ICR_ASSERT_SEL          0x04    /* rw Set to assert SEL */
  85#define ICR_ASSERT_ATN          0x02    /* rw Set to assert ATN */
  86#define ICR_ASSERT_DATA         0x01    /* rw SCSI_DATA_REG is asserted */
  87
  88#ifdef DIFFERENTIAL
  89#define ICR_BASE                ICR_DIFF_ENABLE
  90#else
  91#define ICR_BASE                0
  92#endif
  93
  94#define MODE_REG                2
  95/*
  96 * Note : BLOCK_DMA code will keep DRQ asserted for the duration of the 
  97 * transfer, causing the chip to hog the bus.  You probably don't want 
  98 * this.
  99 */
 100#define MR_BLOCK_DMA_MODE       0x80    /* rw block mode DMA */
 101#define MR_TARGET               0x40    /* rw target mode */
 102#define MR_ENABLE_PAR_CHECK     0x20    /* rw enable parity checking */
 103#define MR_ENABLE_PAR_INTR      0x10    /* rw enable bad parity interrupt */
 104#define MR_ENABLE_EOP_INTR      0x08    /* rw enable eop interrupt */
 105#define MR_MONITOR_BSY          0x04    /* rw enable int on unexpected bsy fail */
 106#define MR_DMA_MODE             0x02    /* rw DMA / pseudo DMA mode */
 107#define MR_ARBITRATE            0x01    /* rw start arbitration */
 108
 109#ifdef PARITY
 110#define MR_BASE                 MR_ENABLE_PAR_CHECK
 111#else
 112#define MR_BASE                 0
 113#endif
 114
 115#define TARGET_COMMAND_REG      3
 116#define TCR_LAST_BYTE_SENT      0x80    /* ro DMA done */
 117#define TCR_ASSERT_REQ          0x08    /* tgt rw assert REQ */
 118#define TCR_ASSERT_MSG          0x04    /* tgt rw assert MSG */
 119#define TCR_ASSERT_CD           0x02    /* tgt rw assert CD */
 120#define TCR_ASSERT_IO           0x01    /* tgt rw assert IO */
 121
 122#define STATUS_REG              4       /* ro */
 123/*
 124 * Note : a set bit indicates an active signal, driven by us or another 
 125 * device.
 126 */
 127#define SR_RST                  0x80
 128#define SR_BSY                  0x40
 129#define SR_REQ                  0x20
 130#define SR_MSG                  0x10
 131#define SR_CD                   0x08
 132#define SR_IO                   0x04
 133#define SR_SEL                  0x02
 134#define SR_DBP                  0x01
 135
 136/*
 137 * Setting a bit in this register will cause an interrupt to be generated when 
 138 * BSY is false and SEL true and this bit is asserted  on the bus.
 139 */
 140#define SELECT_ENABLE_REG       4       /* wo */
 141
 142#define BUS_AND_STATUS_REG      5       /* ro */
 143#define BASR_END_DMA_TRANSFER   0x80    /* ro set on end of transfer */
 144#define BASR_DRQ                0x40    /* ro mirror of DRQ pin */
 145#define BASR_PARITY_ERROR       0x20    /* ro parity error detected */
 146#define BASR_IRQ                0x10    /* ro mirror of IRQ pin */
 147#define BASR_PHASE_MATCH        0x08    /* ro Set when MSG CD IO match TCR */
 148#define BASR_BUSY_ERROR         0x04    /* ro Unexpected change to inactive state */
 149#define BASR_ATN                0x02    /* ro BUS status */
 150#define BASR_ACK                0x01    /* ro BUS status */
 151
 152/* Write any value to this register to start a DMA send */
 153#define START_DMA_SEND_REG      5       /* wo */
 154
 155/* 
 156 * Used in DMA transfer mode, data is latched from the SCSI bus on
 157 * the falling edge of REQ (ini) or ACK (tgt)
 158 */
 159#define INPUT_DATA_REG                  6       /* ro */
 160
 161/* Write any value to this register to start a DMA receive */
 162#define START_DMA_TARGET_RECEIVE_REG    6       /* wo */
 163
 164/* Read this register to clear interrupt conditions */
 165#define RESET_PARITY_INTERRUPT_REG      7       /* ro */
 166
 167/* Write any value to this register to start an ini mode DMA receive */
 168#define START_DMA_INITIATOR_RECEIVE_REG 7       /* wo */
 169
 170#define C400_CONTROL_STATUS_REG NCR53C400_register_offset-8     /* rw */
 171
 172#define CSR_RESET              0x80     /* wo  Resets 53c400 */
 173#define CSR_53C80_REG          0x80     /* ro  5380 registers busy */
 174#define CSR_TRANS_DIR          0x40     /* rw  Data transfer direction */
 175#define CSR_SCSI_BUFF_INTR     0x20     /* rw  Enable int on transfer ready */
 176#define CSR_53C80_INTR         0x10     /* rw  Enable 53c80 interrupts */
 177#define CSR_SHARED_INTR        0x08     /* rw  Interrupt sharing */
 178#define CSR_HOST_BUF_NOT_RDY   0x04     /* ro  Is Host buffer ready */
 179#define CSR_SCSI_BUF_RDY       0x02     /* ro  SCSI buffer read */
 180#define CSR_GATED_53C80_IRQ    0x01     /* ro  Last block xferred */
 181
 182#if 0
 183#define CSR_BASE CSR_SCSI_BUFF_INTR | CSR_53C80_INTR
 184#else
 185#define CSR_BASE CSR_53C80_INTR
 186#endif
 187
 188/* Number of 128-byte blocks to be transferred */
 189#define C400_BLOCK_COUNTER_REG   NCR53C400_register_offset-7    /* rw */
 190
 191/* Resume transfer after disconnect */
 192#define C400_RESUME_TRANSFER_REG NCR53C400_register_offset-6    /* wo */
 193
 194/* Access to host buffer stack */
 195#define C400_HOST_BUFFER         NCR53C400_register_offset-4    /* rw */
 196
 197
 198/* Note : PHASE_* macros are based on the values of the STATUS register */
 199#define PHASE_MASK      (SR_MSG | SR_CD | SR_IO)
 200
 201#define PHASE_DATAOUT           0
 202#define PHASE_DATAIN            SR_IO
 203#define PHASE_CMDOUT            SR_CD
 204#define PHASE_STATIN            (SR_CD | SR_IO)
 205#define PHASE_MSGOUT            (SR_MSG | SR_CD)
 206#define PHASE_MSGIN             (SR_MSG | SR_CD | SR_IO)
 207#define PHASE_UNKNOWN           0xff
 208
 209/* 
 210 * Convert status register phase to something we can use to set phase in 
 211 * the target register so we can get phase mismatch interrupts on DMA 
 212 * transfers.
 213 */
 214
 215#define PHASE_SR_TO_TCR(phase) ((phase) >> 2)
 216
 217/*
 218 * The internal should_disconnect() function returns these based on the 
 219 * expected length of a disconnect if a device supports disconnect/
 220 * reconnect.
 221 */
 222
 223#define DISCONNECT_NONE         0
 224#define DISCONNECT_TIME_TO_DATA 1
 225#define DISCONNECT_LONG         2
 226
 227/* 
 228 * These are "special" values for the tag parameter passed to NCR5380_select.
 229 */
 230
 231#define TAG_NEXT        -1      /* Use next free tag */
 232#define TAG_NONE        -2      /* 
 233                                 * Establish I_T_L nexus instead of I_T_L_Q
 234                                 * even on SCSI-II devices.
 235                                 */
 236
 237/*
 238 * These are "special" values for the irq and dma_channel fields of the 
 239 * Scsi_Host structure
 240 */
 241
 242#define SCSI_IRQ_NONE   255
 243#define DMA_NONE        255
 244#define IRQ_AUTO        254
 245#define DMA_AUTO        254
 246#define PORT_AUTO       0xffff  /* autoprobe io port for 53c400a */
 247
 248#define FLAG_HAS_LAST_BYTE_SENT         1       /* NCR53c81 or better */
 249#define FLAG_CHECK_LAST_BYTE_SENT       2       /* Only test once */
 250#define FLAG_NCR53C400                  4       /* NCR53c400 */
 251#define FLAG_NO_PSEUDO_DMA              8       /* Inhibit DMA */
 252#define FLAG_DTC3181E                   16      /* DTC3181E */
 253
 254#ifndef ASM
 255struct NCR5380_hostdata {
 256        NCR5380_implementation_fields;          /* implementation specific */
 257        struct Scsi_Host *host;                 /* Host backpointer */
 258        unsigned char id_mask, id_higher_mask;  /* 1 << id, all bits greater */
 259        unsigned char targets_present;          /* targets we have connected
 260                                                   to, so we can call a select
 261                                                   failure a retryable condition */
 262        volatile unsigned char busy[8];         /* index = target, bit = lun */
 263#if defined(REAL_DMA) || defined(REAL_DMA_POLL)
 264        volatile int dma_len;                   /* requested length of DMA */
 265#endif
 266        volatile unsigned char last_message;    /* last message OUT */
 267        volatile Scsi_Cmnd *connected;          /* currently connected command */
 268        volatile Scsi_Cmnd *issue_queue;        /* waiting to be issued */
 269        volatile Scsi_Cmnd *disconnected_queue; /* waiting for reconnect */
 270        volatile int restart_select;            /* we have disconnected,
 271                                                   used to restart 
 272                                                   NCR5380_select() */
 273        volatile unsigned aborted:1;            /* flag, says aborted */
 274        int flags;
 275        unsigned long time_expires;             /* in jiffies, set prior to sleeping */
 276        int select_time;                        /* timer in select for target response */
 277        volatile Scsi_Cmnd *selecting;
 278        struct delayed_work coroutine;          /* our co-routine */
 279#ifdef NCR5380_STATS
 280        unsigned timebase;                      /* Base for time calcs */
 281        long time_read[8];                      /* time to do reads */
 282        long time_write[8];                     /* time to do writes */
 283        unsigned long bytes_read[8];            /* bytes read */
 284        unsigned long bytes_write[8];           /* bytes written */
 285        unsigned pendingr;
 286        unsigned pendingw;
 287#endif
 288#ifdef AUTOSENSE
 289        struct scsi_eh_save ses;
 290#endif
 291};
 292
 293#ifdef __KERNEL__
 294
 295#define dprintk(a,b)                    do {} while(0)
 296#define NCR5380_dprint(a,b)             do {} while(0)
 297#define NCR5380_dprint_phase(a,b)       do {} while(0)
 298
 299#if defined(AUTOPROBE_IRQ)
 300static int NCR5380_probe_irq(struct Scsi_Host *instance, int possible);
 301#endif
 302static int NCR5380_init(struct Scsi_Host *instance, int flags);
 303static void NCR5380_exit(struct Scsi_Host *instance);
 304static void NCR5380_information_transfer(struct Scsi_Host *instance);
 305#ifndef DONT_USE_INTR
 306static irqreturn_t NCR5380_intr(int irq, void *dev_id);
 307#endif
 308static void NCR5380_main(struct work_struct *work);
 309static void __maybe_unused NCR5380_print_options(struct Scsi_Host *instance);
 310#ifdef NDEBUG
 311static void NCR5380_print_phase(struct Scsi_Host *instance);
 312static void NCR5380_print(struct Scsi_Host *instance);
 313#endif
 314static int NCR5380_abort(Scsi_Cmnd * cmd);
 315static int NCR5380_bus_reset(Scsi_Cmnd * cmd);
 316static int NCR5380_queue_command(struct Scsi_Host *, struct scsi_cmnd *);
 317static int __maybe_unused NCR5380_show_info(struct seq_file *,
 318        struct Scsi_Host *);
 319static int __maybe_unused NCR5380_write_info(struct Scsi_Host *instance,
 320        char *buffer, int length);
 321
 322static void NCR5380_reselect(struct Scsi_Host *instance);
 323static int NCR5380_select(struct Scsi_Host *instance, Scsi_Cmnd * cmd, int tag);
 324#if defined(PSEUDO_DMA) || defined(REAL_DMA) || defined(REAL_DMA_POLL)
 325static int NCR5380_transfer_dma(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);
 326#endif
 327static int NCR5380_transfer_pio(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);
 328
 329#if (defined(REAL_DMA) || defined(REAL_DMA_POLL))
 330
 331#if defined(i386) || defined(__alpha__)
 332
 333/**
 334 *      NCR5380_pc_dma_setup            -       setup ISA DMA
 335 *      @instance: adapter to set up
 336 *      @ptr: block to transfer (virtual address)
 337 *      @count: number of bytes to transfer
 338 *      @mode: DMA controller mode to use
 339 *
 340 *      Program the DMA controller ready to perform an ISA DMA transfer
 341 *      on this chip.
 342 *
 343 *      Locks: takes and releases the ISA DMA lock.
 344 */
 345 
 346static __inline__ int NCR5380_pc_dma_setup(struct Scsi_Host *instance, unsigned char *ptr, unsigned int count, unsigned char mode)
 347{
 348        unsigned limit;
 349        unsigned long bus_addr = virt_to_bus(ptr);
 350        unsigned long flags;
 351
 352        if (instance->dma_channel <= 3) {
 353                if (count > 65536)
 354                        count = 65536;
 355                limit = 65536 - (bus_addr & 0xFFFF);
 356        } else {
 357                if (count > 65536 * 2)
 358                        count = 65536 * 2;
 359                limit = 65536 * 2 - (bus_addr & 0x1FFFF);
 360        }
 361
 362        if (count > limit)
 363                count = limit;
 364
 365        if ((count & 1) || (bus_addr & 1))
 366                panic("scsi%d : attempted unaligned DMA transfer\n", instance->host_no);
 367        
 368        flags=claim_dma_lock();
 369        disable_dma(instance->dma_channel);
 370        clear_dma_ff(instance->dma_channel);
 371        set_dma_addr(instance->dma_channel, bus_addr);
 372        set_dma_count(instance->dma_channel, count);
 373        set_dma_mode(instance->dma_channel, mode);
 374        enable_dma(instance->dma_channel);
 375        release_dma_lock(flags);
 376        
 377        return count;
 378}
 379
 380/**
 381 *      NCR5380_pc_dma_write_setup              -       setup ISA DMA write
 382 *      @instance: adapter to set up
 383 *      @ptr: block to transfer (virtual address)
 384 *      @count: number of bytes to transfer
 385 *
 386 *      Program the DMA controller ready to perform an ISA DMA write to the
 387 *      SCSI controller.
 388 *
 389 *      Locks: called routines take and release the ISA DMA lock.
 390 */
 391
 392static __inline__ int NCR5380_pc_dma_write_setup(struct Scsi_Host *instance, unsigned char *src, unsigned int count)
 393{
 394        return NCR5380_pc_dma_setup(instance, src, count, DMA_MODE_WRITE);
 395}
 396
 397/**
 398 *      NCR5380_pc_dma_read_setup               -       setup ISA DMA read
 399 *      @instance: adapter to set up
 400 *      @ptr: block to transfer (virtual address)
 401 *      @count: number of bytes to transfer
 402 *
 403 *      Program the DMA controller ready to perform an ISA DMA read from the
 404 *      SCSI controller.
 405 *
 406 *      Locks: called routines take and release the ISA DMA lock.
 407 */
 408
 409static __inline__ int NCR5380_pc_dma_read_setup(struct Scsi_Host *instance, unsigned char *src, unsigned int count)
 410{
 411        return NCR5380_pc_dma_setup(instance, src, count, DMA_MODE_READ);
 412}
 413
 414/**
 415 *      NCR5380_pc_dma_residual         -       return bytes left 
 416 *      @instance: adapter
 417 *
 418 *      Reports the number of bytes left over after the DMA was terminated.
 419 *
 420 *      Locks: takes and releases the ISA DMA lock.
 421 */
 422
 423static __inline__ int NCR5380_pc_dma_residual(struct Scsi_Host *instance)
 424{
 425        unsigned long flags;
 426        int tmp;
 427
 428        flags = claim_dma_lock();
 429        clear_dma_ff(instance->dma_channel);
 430        tmp = get_dma_residue(instance->dma_channel);
 431        release_dma_lock(flags);
 432        
 433        return tmp;
 434}
 435#endif                          /* defined(i386) || defined(__alpha__) */
 436#endif                          /* defined(REAL_DMA)  */
 437#endif                          /* __KERNEL__ */
 438#endif                          /* ndef ASM */
 439#endif                          /* NCR5380_H */
 440