LXR linux/drivers/scsi/arm/fas216.h

   1/*
   2 *  linux/drivers/acorn/scsi/fas216.h
   3 *
   4 *  Copyright (C) 1997-2000 Russell King
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation.
   9 *
  10 *  FAS216 generic driver
  11 */
  12#ifndef FAS216_H
  13#define FAS216_H
  14
  15#include <scsi/scsi_eh.h>
  16
  17#include "queue.h"
  18#include "msgqueue.h"
  19
  20/* FAS register definitions */
  21
  22/* transfer count low */
  23#define REG_CTCL                (0)
  24#define REG_STCL                (0)
  25
  26/* transfer count medium */
  27#define REG_CTCM                (1)
  28#define REG_STCM                (1)
  29
  30/* fifo data */
  31#define REG_FF                  (2)
  32
  33/* command */
  34#define REG_CMD                 (3)
  35#define CMD_NOP                 0x00
  36#define CMD_FLUSHFIFO           0x01
  37#define CMD_RESETCHIP           0x02
  38#define CMD_RESETSCSI           0x03
  39
  40#define CMD_TRANSFERINFO        0x10
  41#define CMD_INITCMDCOMPLETE     0x11
  42#define CMD_MSGACCEPTED         0x12
  43#define CMD_PADBYTES            0x18
  44#define CMD_SETATN              0x1a
  45#define CMD_RSETATN             0x1b
  46
  47#define CMD_SELECTWOATN         0x41
  48#define CMD_SELECTATN           0x42
  49#define CMD_SELECTATNSTOP       0x43
  50#define CMD_ENABLESEL           0x44
  51#define CMD_DISABLESEL          0x45
  52#define CMD_SELECTATN3          0x46
  53#define CMD_RESEL3              0x47
  54
  55#define CMD_WITHDMA             0x80
  56
  57/* status register (read) */
  58#define REG_STAT                (4)
  59#define STAT_IO                 (1 << 0)                        /* IO phase             */
  60#define STAT_CD                 (1 << 1)                        /* CD phase             */
  61#define STAT_MSG                (1 << 2)                        /* MSG phase            */
  62#define STAT_TRANSFERDONE       (1 << 3)                        /* Transfer completed   */
  63#define STAT_TRANSFERCNTZ       (1 << 4)                        /* Transfer counter is zero */
  64#define STAT_PARITYERROR        (1 << 5)                        /* Parity error         */
  65#define STAT_REALBAD            (1 << 6)                        /* Something bad        */
  66#define STAT_INT                (1 << 7)                        /* Interrupt            */
  67
  68#define STAT_BUSMASK            (STAT_MSG|STAT_CD|STAT_IO)
  69#define STAT_DATAOUT            (0)                             /* Data out             */
  70#define STAT_DATAIN             (STAT_IO)                       /* Data in              */
  71#define STAT_COMMAND            (STAT_CD)                       /* Command out          */
  72#define STAT_STATUS             (STAT_CD|STAT_IO)               /* Status In            */
  73#define STAT_MESGOUT            (STAT_MSG|STAT_CD)              /* Message out          */
  74#define STAT_MESGIN             (STAT_MSG|STAT_CD|STAT_IO)      /* Message In           */
  75
  76/* bus ID for select / reselect */
  77#define REG_SDID                (4)
  78#define BUSID(target)           ((target) & 7)
  79
  80/* Interrupt status register (read) */
  81#define REG_INST                (5)
  82#define INST_SELWOATN           (1 << 0)                        /* Select w/o ATN       */
  83#define INST_SELATN             (1 << 1)                        /* Select w/ATN         */
  84#define INST_RESELECTED         (1 << 2)                        /* Reselected           */
  85#define INST_FUNCDONE           (1 << 3)                        /* Function done        */
  86#define INST_BUSSERVICE         (1 << 4)                        /* Bus service          */
  87#define INST_DISCONNECT         (1 << 5)                        /* Disconnect           */
  88#define INST_ILLEGALCMD         (1 << 6)                        /* Illegal command      */
  89#define INST_BUSRESET           (1 << 7)                        /* SCSI Bus reset       */
  90
  91/* Timeout register (write) */
  92#define REG_STIM                (5)
  93
  94/* Sequence step register (read) */
  95#define REG_IS                  (6)
  96#define IS_BITS                 0x07
  97#define IS_SELARB               0x00                            /* Select & Arb ok      */
  98#define IS_MSGBYTESENT          0x01                            /* One byte message sent*/
  99#define IS_NOTCOMMAND           0x02                            /* Not in command state */
 100#define IS_EARLYPHASE           0x03                            /* Early phase change   */
 101#define IS_COMPLETE             0x04                            /* Command ok           */
 102#define IS_SOF                  0x08                            /* Sync off flag        */
 103
 104/* Transfer period step (write) */
 105#define REG_STP                 (6)
 106
 107/* Synchronous Offset (write) */
 108#define REG_SOF                 (7)
 109
 110/* Fifo state register (read) */
 111#define REG_CFIS                (7)
 112#define CFIS_CF                 0x1f                            /* Num bytes in FIFO    */
 113#define CFIS_IS                 0xe0                            /* Step                 */
 114
 115/* config register 1 */
 116#define REG_CNTL1               (8)
 117#define CNTL1_CID               (7 << 0)                        /* Chip ID                      */
 118#define CNTL1_STE               (1 << 3)                        /* Self test enable             */
 119#define CNTL1_PERE              (1 << 4)                        /* Parity enable reporting en.  */
 120#define CNTL1_PTE               (1 << 5)                        /* Parity test enable           */
 121#define CNTL1_DISR              (1 << 6)                        /* Disable Irq on SCSI reset    */
 122#define CNTL1_ETM               (1 << 7)                        /* Extended Timing Mode         */
 123
 124/* Clock conversion factor (read) */
 125#define REG_CLKF                (9)
 126#define CLKF_F37MHZ             0x00                            /* 35.01 - 40 MHz               */
 127#define CLKF_F10MHZ             0x02                            /* 10 MHz                       */
 128#define CLKF_F12MHZ             0x03                            /* 10.01 - 15 MHz               */
 129#define CLKF_F17MHZ             0x04                            /* 15.01 - 20 MHz               */
 130#define CLKF_F22MHZ             0x05                            /* 20.01 - 25 MHz               */
 131#define CLKF_F27MHZ             0x06                            /* 25.01 - 30 MHz               */
 132#define CLKF_F32MHZ             0x07                            /* 30.01 - 35 MHz               */
 133
 134/* Chip test register (write) */
 135#define REG_FTM                 (10)
 136#define TEST_FTM                0x01                            /* Force target mode            */
 137#define TEST_FIM                0x02                            /* Force initiator mode         */
 138#define TEST_FHI                0x04                            /* Force high impedance mode    */
 139
 140/* Configuration register 2 (read/write) */
 141#define REG_CNTL2               (11)
 142#define CNTL2_PGDP              (1 << 0)                        /* Pass Th/Generate Data Parity */
 143#define CNTL2_PGRP              (1 << 1)                        /* Pass Th/Generate Reg Parity  */
 144#define CNTL2_ACDPE             (1 << 2)                        /* Abort on Cmd/Data Parity Err */
 145#define CNTL2_S2FE              (1 << 3)                        /* SCSI2 Features Enable        */
 146#define CNTL2_TSDR              (1 << 4)                        /* Tristate DREQ                */
 147#define CNTL2_SBO               (1 << 5)                        /* Select Byte Order            */
 148#define CNTL2_ENF               (1 << 6)                        /* Enable features              */
 149#define CNTL2_DAE               (1 << 7)                        /* Data Alignment Enable        */
 150
 151/* Configuration register 3 (read/write) */
 152#define REG_CNTL3               (12)
 153#define CNTL3_BS8               (1 << 0)                        /* Burst size 8                 */
 154#define CNTL3_MDM               (1 << 1)                        /* Modify DMA mode              */
 155#define CNTL3_LBTM              (1 << 2)                        /* Last Byte Transfer mode      */
 156#define CNTL3_FASTCLK           (1 << 3)                        /* Fast SCSI clocking           */
 157#define CNTL3_FASTSCSI          (1 << 4)                        /* Fast SCSI                    */
 158#define CNTL3_G2CB              (1 << 5)                        /* Group2 SCSI support          */
 159#define CNTL3_QTAG              (1 << 6)                        /* Enable 3 byte msgs           */
 160#define CNTL3_ADIDCHK           (1 << 7)                        /* Additional ID check          */
 161
 162/* High transfer count (read/write) */
 163#define REG_CTCH                (14)
 164#define REG_STCH                (14)
 165
 166/* ID register (read only) */
 167#define REG_ID                  (14)
 168
 169/* Data alignment */
 170#define REG_DAL                 (15)
 171
 172typedef enum {
 173        PHASE_IDLE,                                     /* we're not planning on doing anything */
 174        PHASE_SELECTION,                                /* selecting a device                   */
 175        PHASE_SELSTEPS,                                 /* selection with command steps         */
 176        PHASE_COMMAND,                                  /* command sent                         */
 177        PHASE_MESSAGESENT,                              /* selected, and we're sending cmd      */
 178        PHASE_DATAOUT,                                  /* data out to device                   */
 179        PHASE_DATAIN,                                   /* data in from device                  */
 180        PHASE_MSGIN,                                    /* message in from device               */
 181        PHASE_MSGIN_DISCONNECT,                         /* disconnecting from bus               */
 182        PHASE_MSGOUT,                                   /* after message out phase              */
 183        PHASE_MSGOUT_EXPECT,                            /* expecting message out                */
 184        PHASE_STATUS,                                   /* status from device                   */
 185        PHASE_DONE                                      /* Command complete                     */
 186} phase_t;
 187
 188typedef enum {
 189        DMA_OUT,                                        /* DMA from memory to chip              */
 190        DMA_IN                                          /* DMA from chip to memory              */
 191} fasdmadir_t;
 192
 193typedef enum {
 194        fasdma_none,                                    /* No dma                               */
 195        fasdma_pio,                                     /* PIO mode                             */
 196        fasdma_pseudo,                                  /* Pseudo DMA                           */
 197        fasdma_real_block,                              /* Real DMA, on block by block basis    */
 198        fasdma_real_all                                 /* Real DMA, on request by request      */
 199} fasdmatype_t;
 200
 201typedef enum {
 202        neg_wait,                                       /* Negotiate with device                */
 203        neg_inprogress,                                 /* Negotiation sent                     */
 204        neg_complete,                                   /* Negotiation complete                 */
 205        neg_targcomplete,                               /* Target completed negotiation         */
 206        neg_invalid                                     /* Negotiation not supported            */
 207} neg_t;
 208
 209#define MAGIC   0x441296bdUL
 210#define NR_MSGS 8
 211
 212#define FASCAP_DMA              (1 << 0)
 213#define FASCAP_PSEUDODMA        (1 << 1)
 214
 215typedef struct {
 216        unsigned long           magic_start;
 217        spinlock_t              host_lock;
 218        struct Scsi_Host        *host;                  /* host                                 */
 219        struct scsi_cmnd        *SCpnt;                 /* currently processing command         */
 220        struct scsi_cmnd        *origSCpnt;             /* original connecting command          */
 221        struct scsi_cmnd        *reqSCpnt;              /* request sense command                */
 222        struct scsi_cmnd        *rstSCpnt;              /* reset command                        */
 223        struct scsi_cmnd        *pending_SCpnt[8];      /* per-device pending commands          */
 224        int                     next_pending;           /* next pending device                  */
 225
 226        /*
 227         * Error recovery
 228         */
 229        wait_queue_head_t       eh_wait;
 230        struct timer_list       eh_timer;
 231        unsigned int            rst_dev_status;
 232        unsigned int            rst_bus_status;
 233
 234        /* driver information */
 235        struct {
 236                phase_t         phase;                  /* current phase                        */
 237                void __iomem    *io_base;               /* iomem base of FAS216                 */
 238                unsigned int    io_shift;               /* shift to adjust reg offsets by       */
 239                unsigned char   cfg[4];                 /* configuration registers              */
 240                const char      *type;                  /* chip type                            */
 241                unsigned int    irq;                    /* interrupt                            */
 242                int             dma;                    /* dma channel                          */
 243
 244                struct scsi_pointer     SCp;                    /* current commands data pointer        */
 245
 246                MsgQueue_t      msgs;                   /* message queue for connected device   */
 247
 248                unsigned int    async_stp;              /* Async transfer STP value             */
 249                unsigned char   msgin_fifo;             /* bytes in fifo at time of message in  */
 250                unsigned char   message[256];           /* last message received from device    */
 251
 252                unsigned char   disconnectable:1;       /* this command can be disconnected     */
 253                unsigned char   aborting:1;             /* aborting command                     */
 254        } scsi;
 255
 256        /* statistics information */
 257        struct {
 258                unsigned int    queues;
 259                unsigned int    removes;
 260                unsigned int    fins;
 261                unsigned int    reads;
 262                unsigned int    writes;
 263                unsigned int    miscs;
 264                unsigned int    disconnects;
 265                unsigned int    aborts;
 266                unsigned int    bus_resets;
 267                unsigned int    host_resets;
 268        } stats;
 269
 270        /* configuration information */
 271        struct {
 272                unsigned char   clockrate;              /* clock rate of FAS device (MHz)       */
 273                unsigned char   select_timeout;         /* timeout (R5)                         */
 274                unsigned char   sync_max_depth;         /* Synchronous xfer max fifo depth      */
 275                unsigned char   wide_max_size;          /* Maximum wide transfer size           */
 276                unsigned char   cntl3;                  /* Control Reg 3                        */
 277                unsigned int    asyncperiod;            /* Async transfer period (ns)           */
 278                unsigned int    capabilities;           /* driver capabilities                  */
 279                unsigned int    disconnect_ok:1;        /* Disconnects allowed?                 */
 280        } ifcfg;
 281
 282        /* queue handling */
 283        struct {
 284                Queue_t         issue;                  /* issue queue                          */
 285                Queue_t         disconnected;           /* disconnected command queue           */
 286        } queues;
 287
 288        /* per-device info */
 289        struct fas216_device {
 290                unsigned char   disconnect_ok:1;        /* device can disconnect                */
 291                unsigned char   parity_enabled:1;       /* parity checking enabled              */
 292                unsigned char   parity_check:1;         /* need to check parity checking        */
 293                unsigned char   period;                 /* sync xfer period in (*4ns)           */
 294                unsigned char   stp;                    /* synchronous transfer period          */
 295                unsigned char   sof;                    /* synchronous offset register          */
 296                unsigned char   wide_xfer;              /* currently negociated wide transfer   */
 297                neg_t           sync_state;             /* synchronous transfer mode            */
 298                neg_t           wide_state;             /* wide transfer mode                   */
 299        } device[8];
 300        unsigned long   busyluns[64/sizeof(unsigned long)];/* array of bits indicating LUNs busy        */
 301
 302        /* dma */
 303        struct {
 304                fasdmatype_t    transfer_type;          /* current type of DMA transfer         */
 305                fasdmatype_t    (*setup) (struct Scsi_Host *host, struct scsi_pointer *SCp, fasdmadir_t direction, fasdmatype_t min_dma);
 306                void            (*pseudo)(struct Scsi_Host *host, struct scsi_pointer *SCp, fasdmadir_t direction, int transfer);
 307                void            (*stop)  (struct Scsi_Host *host, struct scsi_pointer *SCp);
 308        } dma;
 309
 310        /* miscellaneous */
 311        int                     internal_done;          /* flag to indicate request done */
 312        struct scsi_eh_save     ses;            /* holds request sense restore info */
 313        unsigned long           magic_end;
 314} FAS216_Info;
 315
 316/* Function: int fas216_init (struct Scsi_Host *instance)
 317 * Purpose : initialise FAS/NCR/AMD SCSI structures.
 318 * Params  : instance - a driver-specific filled-out structure
 319 * Returns : 0 on success
 320 */
 321extern int fas216_init (struct Scsi_Host *instance);
 322
 323/* Function: int fas216_add (struct Scsi_Host *instance, struct device *dev)
 324 * Purpose : initialise FAS/NCR/AMD SCSI ic.
 325 * Params  : instance - a driver-specific filled-out structure
 326 * Returns : 0 on success
 327 */
 328extern int fas216_add (struct Scsi_Host *instance, struct device *dev);
 329
 330/* Function: int fas216_queue_command(struct Scsi_Host *h, struct scsi_cmnd *SCpnt)
 331 * Purpose : queue a command for adapter to process.
 332 * Params  : h - host adapter
 333 *         : SCpnt - Command to queue
 334 * Returns : 0 - success, else error
 335 */
 336extern int fas216_queue_command(struct Scsi_Host *h, struct scsi_cmnd *SCpnt);
 337
 338/* Function: int fas216_noqueue_command(struct Scsi_Host *h, struct scsi_cmnd *SCpnt)
 339 * Purpose : queue a command for adapter to process, and process it to completion.
 340 * Params  : h - host adapter
 341 *         : SCpnt - Command to queue
 342 * Returns : 0 - success, else error
 343 */
 344extern int fas216_noqueue_command(struct Scsi_Host *, struct scsi_cmnd *);
 345
 346/* Function: irqreturn_t fas216_intr (FAS216_Info *info)
 347 * Purpose : handle interrupts from the interface to progress a command
 348 * Params  : info - interface to service
 349 */
 350extern irqreturn_t fas216_intr (FAS216_Info *info);
 351
 352extern void fas216_remove (struct Scsi_Host *instance);
 353
 354/* Function: void fas216_release (struct Scsi_Host *instance)
 355 * Purpose : release all resources and put everything to bed for FAS/NCR/AMD SCSI ic.
 356 * Params  : instance - a driver-specific filled-out structure
 357 * Returns : 0 on success
 358 */
 359extern void fas216_release (struct Scsi_Host *instance);
 360
 361extern void fas216_print_host(FAS216_Info *info, struct seq_file *m);
 362extern void fas216_print_stats(FAS216_Info *info, struct seq_file *m);
 363extern void fas216_print_devices(FAS216_Info *info, struct seq_file *m);
 364
 365/* Function: int fas216_eh_abort(struct scsi_cmnd *SCpnt)
 366 * Purpose : abort this command
 367 * Params  : SCpnt - command to abort
 368 * Returns : FAILED if unable to abort
 369 */
 370extern int fas216_eh_abort(struct scsi_cmnd *SCpnt);
 371
 372/* Function: int fas216_eh_device_reset(struct scsi_cmnd *SCpnt)
 373 * Purpose : Reset the device associated with this command
 374 * Params  : SCpnt - command specifing device to reset
 375 * Returns : FAILED if unable to reset
 376 */
 377extern int fas216_eh_device_reset(struct scsi_cmnd *SCpnt);
 378
 379/* Function: int fas216_eh_bus_reset(struct scsi_cmnd *SCpnt)
 380 * Purpose : Reset the complete bus associated with this command
 381 * Params  : SCpnt - command specifing bus to reset
 382 * Returns : FAILED if unable to reset
 383 */
 384extern int fas216_eh_bus_reset(struct scsi_cmnd *SCpnt);
 385
 386/* Function: int fas216_eh_host_reset(struct scsi_cmnd *SCpnt)
 387 * Purpose : Reset the host associated with this command
 388 * Params  : SCpnt - command specifing host to reset
 389 * Returns : FAILED if unable to reset
 390 */
 391extern int fas216_eh_host_reset(struct scsi_cmnd *SCpnt);
 392
 393#endif /* FAS216_H */
 394