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27#include "mv_sas.h"
28
29static int lldd_max_execute_num = 1;
30module_param_named(collector, lldd_max_execute_num, int, S_IRUGO);
31MODULE_PARM_DESC(collector, "\n"
32 "\tIf greater than one, tells the SAS Layer to run in Task Collector\n"
33 "\tMode. If 1 or 0, tells the SAS Layer to run in Direct Mode.\n"
34 "\tThe mvsas SAS LLDD supports both modes.\n"
35 "\tDefault: 1 (Direct Mode).\n");
36
37int interrupt_coalescing = 0x80;
38
39static struct scsi_transport_template *mvs_stt;
40struct kmem_cache *mvs_task_list_cache;
41static const struct mvs_chip_info mvs_chips[] = {
42 [chip_6320] = { 1, 2, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },
43 [chip_6440] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },
44 [chip_6485] = { 1, 8, 0x800, 33, 32, 6, 10, &mvs_64xx_dispatch, },
45 [chip_9180] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },
46 [chip_9480] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },
47 [chip_9445] = { 1, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },
48 [chip_9485] = { 2, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },
49 [chip_1300] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },
50 [chip_1320] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },
51};
52
53struct device_attribute *mvst_host_attrs[];
54
55#define SOC_SAS_NUM 2
56
57static struct scsi_host_template mvs_sht = {
58 .module = THIS_MODULE,
59 .name = DRV_NAME,
60 .queuecommand = sas_queuecommand,
61 .target_alloc = sas_target_alloc,
62 .slave_configure = sas_slave_configure,
63 .scan_finished = mvs_scan_finished,
64 .scan_start = mvs_scan_start,
65 .change_queue_depth = sas_change_queue_depth,
66 .change_queue_type = sas_change_queue_type,
67 .bios_param = sas_bios_param,
68 .can_queue = 1,
69 .cmd_per_lun = 1,
70 .this_id = -1,
71 .sg_tablesize = SG_ALL,
72 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
73 .use_clustering = ENABLE_CLUSTERING,
74 .eh_device_reset_handler = sas_eh_device_reset_handler,
75 .eh_bus_reset_handler = sas_eh_bus_reset_handler,
76 .target_destroy = sas_target_destroy,
77 .ioctl = sas_ioctl,
78 .shost_attrs = mvst_host_attrs,
79};
80
81static struct sas_domain_function_template mvs_transport_ops = {
82 .lldd_dev_found = mvs_dev_found,
83 .lldd_dev_gone = mvs_dev_gone,
84 .lldd_execute_task = mvs_queue_command,
85 .lldd_control_phy = mvs_phy_control,
86
87 .lldd_abort_task = mvs_abort_task,
88 .lldd_abort_task_set = mvs_abort_task_set,
89 .lldd_clear_aca = mvs_clear_aca,
90 .lldd_clear_task_set = mvs_clear_task_set,
91 .lldd_I_T_nexus_reset = mvs_I_T_nexus_reset,
92 .lldd_lu_reset = mvs_lu_reset,
93 .lldd_query_task = mvs_query_task,
94 .lldd_port_formed = mvs_port_formed,
95 .lldd_port_deformed = mvs_port_deformed,
96
97};
98
99static void mvs_phy_init(struct mvs_info *mvi, int phy_id)
100{
101 struct mvs_phy *phy = &mvi->phy[phy_id];
102 struct asd_sas_phy *sas_phy = &phy->sas_phy;
103
104 phy->mvi = mvi;
105 phy->port = NULL;
106 init_timer(&phy->timer);
107 sas_phy->enabled = (phy_id < mvi->chip->n_phy) ? 1 : 0;
108 sas_phy->class = SAS;
109 sas_phy->iproto = SAS_PROTOCOL_ALL;
110 sas_phy->tproto = 0;
111 sas_phy->type = PHY_TYPE_PHYSICAL;
112 sas_phy->role = PHY_ROLE_INITIATOR;
113 sas_phy->oob_mode = OOB_NOT_CONNECTED;
114 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
115
116 sas_phy->id = phy_id;
117 sas_phy->sas_addr = &mvi->sas_addr[0];
118 sas_phy->frame_rcvd = &phy->frame_rcvd[0];
119 sas_phy->ha = (struct sas_ha_struct *)mvi->shost->hostdata;
120 sas_phy->lldd_phy = phy;
121}
122
123static void mvs_free(struct mvs_info *mvi)
124{
125 struct mvs_wq *mwq;
126 int slot_nr;
127
128 if (!mvi)
129 return;
130
131 if (mvi->flags & MVF_FLAG_SOC)
132 slot_nr = MVS_SOC_SLOTS;
133 else
134 slot_nr = MVS_CHIP_SLOT_SZ;
135
136 if (mvi->dma_pool)
137 pci_pool_destroy(mvi->dma_pool);
138
139 if (mvi->tx)
140 dma_free_coherent(mvi->dev,
141 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
142 mvi->tx, mvi->tx_dma);
143 if (mvi->rx_fis)
144 dma_free_coherent(mvi->dev, MVS_RX_FISL_SZ,
145 mvi->rx_fis, mvi->rx_fis_dma);
146 if (mvi->rx)
147 dma_free_coherent(mvi->dev,
148 sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
149 mvi->rx, mvi->rx_dma);
150 if (mvi->slot)
151 dma_free_coherent(mvi->dev,
152 sizeof(*mvi->slot) * slot_nr,
153 mvi->slot, mvi->slot_dma);
154
155 if (mvi->bulk_buffer)
156 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
157 mvi->bulk_buffer, mvi->bulk_buffer_dma);
158 if (mvi->bulk_buffer1)
159 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
160 mvi->bulk_buffer1, mvi->bulk_buffer_dma1);
161
162 MVS_CHIP_DISP->chip_iounmap(mvi);
163 if (mvi->shost)
164 scsi_host_put(mvi->shost);
165 list_for_each_entry(mwq, &mvi->wq_list, entry)
166 cancel_delayed_work(&mwq->work_q);
167 kfree(mvi->tags);
168 kfree(mvi);
169}
170
171#ifdef CONFIG_SCSI_MVSAS_TASKLET
172static void mvs_tasklet(unsigned long opaque)
173{
174 u32 stat;
175 u16 core_nr, i = 0;
176
177 struct mvs_info *mvi;
178 struct sas_ha_struct *sha = (struct sas_ha_struct *)opaque;
179
180 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
181 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
182
183 if (unlikely(!mvi))
184 BUG_ON(1);
185
186 stat = MVS_CHIP_DISP->isr_status(mvi, mvi->pdev->irq);
187 if (!stat)
188 goto out;
189
190 for (i = 0; i < core_nr; i++) {
191 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
192 MVS_CHIP_DISP->isr(mvi, mvi->pdev->irq, stat);
193 }
194out:
195 MVS_CHIP_DISP->interrupt_enable(mvi);
196
197}
198#endif
199
200static irqreturn_t mvs_interrupt(int irq, void *opaque)
201{
202 u32 core_nr;
203 u32 stat;
204 struct mvs_info *mvi;
205 struct sas_ha_struct *sha = opaque;
206#ifndef CONFIG_SCSI_MVSAS_TASKLET
207 u32 i;
208#endif
209
210 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
211 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
212
213 if (unlikely(!mvi))
214 return IRQ_NONE;
215#ifdef CONFIG_SCSI_MVSAS_TASKLET
216 MVS_CHIP_DISP->interrupt_disable(mvi);
217#endif
218
219 stat = MVS_CHIP_DISP->isr_status(mvi, irq);
220 if (!stat) {
221 #ifdef CONFIG_SCSI_MVSAS_TASKLET
222 MVS_CHIP_DISP->interrupt_enable(mvi);
223 #endif
224 return IRQ_NONE;
225 }
226
227#ifdef CONFIG_SCSI_MVSAS_TASKLET
228 tasklet_schedule(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet);
229#else
230 for (i = 0; i < core_nr; i++) {
231 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
232 MVS_CHIP_DISP->isr(mvi, irq, stat);
233 }
234#endif
235 return IRQ_HANDLED;
236}
237
238static int mvs_alloc(struct mvs_info *mvi, struct Scsi_Host *shost)
239{
240 int i = 0, slot_nr;
241 char pool_name[32];
242
243 if (mvi->flags & MVF_FLAG_SOC)
244 slot_nr = MVS_SOC_SLOTS;
245 else
246 slot_nr = MVS_CHIP_SLOT_SZ;
247
248 spin_lock_init(&mvi->lock);
249 for (i = 0; i < mvi->chip->n_phy; i++) {
250 mvs_phy_init(mvi, i);
251 mvi->port[i].wide_port_phymap = 0;
252 mvi->port[i].port_attached = 0;
253 INIT_LIST_HEAD(&mvi->port[i].list);
254 }
255 for (i = 0; i < MVS_MAX_DEVICES; i++) {
256 mvi->devices[i].taskfileset = MVS_ID_NOT_MAPPED;
257 mvi->devices[i].dev_type = SAS_PHY_UNUSED;
258 mvi->devices[i].device_id = i;
259 mvi->devices[i].dev_status = MVS_DEV_NORMAL;
260 init_timer(&mvi->devices[i].timer);
261 }
262
263
264
265
266 mvi->tx = dma_alloc_coherent(mvi->dev,
267 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
268 &mvi->tx_dma, GFP_KERNEL);
269 if (!mvi->tx)
270 goto err_out;
271 memset(mvi->tx, 0, sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ);
272 mvi->rx_fis = dma_alloc_coherent(mvi->dev, MVS_RX_FISL_SZ,
273 &mvi->rx_fis_dma, GFP_KERNEL);
274 if (!mvi->rx_fis)
275 goto err_out;
276 memset(mvi->rx_fis, 0, MVS_RX_FISL_SZ);
277
278 mvi->rx = dma_alloc_coherent(mvi->dev,
279 sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
280 &mvi->rx_dma, GFP_KERNEL);
281 if (!mvi->rx)
282 goto err_out;
283 memset(mvi->rx, 0, sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1));
284 mvi->rx[0] = cpu_to_le32(0xfff);
285 mvi->rx_cons = 0xfff;
286
287 mvi->slot = dma_alloc_coherent(mvi->dev,
288 sizeof(*mvi->slot) * slot_nr,
289 &mvi->slot_dma, GFP_KERNEL);
290 if (!mvi->slot)
291 goto err_out;
292 memset(mvi->slot, 0, sizeof(*mvi->slot) * slot_nr);
293
294 mvi->bulk_buffer = dma_alloc_coherent(mvi->dev,
295 TRASH_BUCKET_SIZE,
296 &mvi->bulk_buffer_dma, GFP_KERNEL);
297 if (!mvi->bulk_buffer)
298 goto err_out;
299
300 mvi->bulk_buffer1 = dma_alloc_coherent(mvi->dev,
301 TRASH_BUCKET_SIZE,
302 &mvi->bulk_buffer_dma1, GFP_KERNEL);
303 if (!mvi->bulk_buffer1)
304 goto err_out;
305
306 sprintf(pool_name, "%s%d", "mvs_dma_pool", mvi->id);
307 mvi->dma_pool = pci_pool_create(pool_name, mvi->pdev, MVS_SLOT_BUF_SZ, 16, 0);
308 if (!mvi->dma_pool) {
309 printk(KERN_DEBUG "failed to create dma pool %s.\n", pool_name);
310 goto err_out;
311 }
312 mvi->tags_num = slot_nr;
313
314
315 mvs_tag_init(mvi);
316 return 0;
317err_out:
318 return 1;
319}
320
321
322int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex)
323{
324 unsigned long res_start, res_len, res_flag, res_flag_ex = 0;
325 struct pci_dev *pdev = mvi->pdev;
326 if (bar_ex != -1) {
327
328
329
330 res_start = pci_resource_start(pdev, bar_ex);
331 res_len = pci_resource_len(pdev, bar_ex);
332 if (!res_start || !res_len)
333 goto err_out;
334
335 res_flag_ex = pci_resource_flags(pdev, bar_ex);
336 if (res_flag_ex & IORESOURCE_MEM) {
337 if (res_flag_ex & IORESOURCE_CACHEABLE)
338 mvi->regs_ex = ioremap(res_start, res_len);
339 else
340 mvi->regs_ex = ioremap_nocache(res_start,
341 res_len);
342 } else
343 mvi->regs_ex = (void *)res_start;
344 if (!mvi->regs_ex)
345 goto err_out;
346 }
347
348 res_start = pci_resource_start(pdev, bar);
349 res_len = pci_resource_len(pdev, bar);
350 if (!res_start || !res_len)
351 goto err_out;
352
353 res_flag = pci_resource_flags(pdev, bar);
354 if (res_flag & IORESOURCE_CACHEABLE)
355 mvi->regs = ioremap(res_start, res_len);
356 else
357 mvi->regs = ioremap_nocache(res_start, res_len);
358
359 if (!mvi->regs) {
360 if (mvi->regs_ex && (res_flag_ex & IORESOURCE_MEM))
361 iounmap(mvi->regs_ex);
362 mvi->regs_ex = NULL;
363 goto err_out;
364 }
365
366 return 0;
367err_out:
368 return -1;
369}
370
371void mvs_iounmap(void __iomem *regs)
372{
373 iounmap(regs);
374}
375
376static struct mvs_info *mvs_pci_alloc(struct pci_dev *pdev,
377 const struct pci_device_id *ent,
378 struct Scsi_Host *shost, unsigned int id)
379{
380 struct mvs_info *mvi = NULL;
381 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
382
383 mvi = kzalloc(sizeof(*mvi) +
384 (1L << mvs_chips[ent->driver_data].slot_width) *
385 sizeof(struct mvs_slot_info), GFP_KERNEL);
386 if (!mvi)
387 return NULL;
388
389 mvi->pdev = pdev;
390 mvi->dev = &pdev->dev;
391 mvi->chip_id = ent->driver_data;
392 mvi->chip = &mvs_chips[mvi->chip_id];
393 INIT_LIST_HEAD(&mvi->wq_list);
394
395 ((struct mvs_prv_info *)sha->lldd_ha)->mvi[id] = mvi;
396 ((struct mvs_prv_info *)sha->lldd_ha)->n_phy = mvi->chip->n_phy;
397
398 mvi->id = id;
399 mvi->sas = sha;
400 mvi->shost = shost;
401
402 mvi->tags = kzalloc(MVS_CHIP_SLOT_SZ>>3, GFP_KERNEL);
403 if (!mvi->tags)
404 goto err_out;
405
406 if (MVS_CHIP_DISP->chip_ioremap(mvi))
407 goto err_out;
408 if (!mvs_alloc(mvi, shost))
409 return mvi;
410err_out:
411 mvs_free(mvi);
412 return NULL;
413}
414
415static int pci_go_64(struct pci_dev *pdev)
416{
417 int rc;
418
419 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
420 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
421 if (rc) {
422 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
423 if (rc) {
424 dev_printk(KERN_ERR, &pdev->dev,
425 "64-bit DMA enable failed\n");
426 return rc;
427 }
428 }
429 } else {
430 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
431 if (rc) {
432 dev_printk(KERN_ERR, &pdev->dev,
433 "32-bit DMA enable failed\n");
434 return rc;
435 }
436 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
437 if (rc) {
438 dev_printk(KERN_ERR, &pdev->dev,
439 "32-bit consistent DMA enable failed\n");
440 return rc;
441 }
442 }
443
444 return rc;
445}
446
447static int mvs_prep_sas_ha_init(struct Scsi_Host *shost,
448 const struct mvs_chip_info *chip_info)
449{
450 int phy_nr, port_nr; unsigned short core_nr;
451 struct asd_sas_phy **arr_phy;
452 struct asd_sas_port **arr_port;
453 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
454
455 core_nr = chip_info->n_host;
456 phy_nr = core_nr * chip_info->n_phy;
457 port_nr = phy_nr;
458
459 memset(sha, 0x00, sizeof(struct sas_ha_struct));
460 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
461 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
462 if (!arr_phy || !arr_port)
463 goto exit_free;
464
465 sha->sas_phy = arr_phy;
466 sha->sas_port = arr_port;
467 sha->core.shost = shost;
468
469 sha->lldd_ha = kzalloc(sizeof(struct mvs_prv_info), GFP_KERNEL);
470 if (!sha->lldd_ha)
471 goto exit_free;
472
473 ((struct mvs_prv_info *)sha->lldd_ha)->n_host = core_nr;
474
475 shost->transportt = mvs_stt;
476 shost->max_id = MVS_MAX_DEVICES;
477 shost->max_lun = ~0;
478 shost->max_channel = 1;
479 shost->max_cmd_len = 16;
480
481 return 0;
482exit_free:
483 kfree(arr_phy);
484 kfree(arr_port);
485 return -1;
486
487}
488
489static void mvs_post_sas_ha_init(struct Scsi_Host *shost,
490 const struct mvs_chip_info *chip_info)
491{
492 int can_queue, i = 0, j = 0;
493 struct mvs_info *mvi = NULL;
494 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
495 unsigned short nr_core = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
496
497 for (j = 0; j < nr_core; j++) {
498 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
499 for (i = 0; i < chip_info->n_phy; i++) {
500 sha->sas_phy[j * chip_info->n_phy + i] =
501 &mvi->phy[i].sas_phy;
502 sha->sas_port[j * chip_info->n_phy + i] =
503 &mvi->port[i].sas_port;
504 }
505 }
506
507 sha->sas_ha_name = DRV_NAME;
508 sha->dev = mvi->dev;
509 sha->lldd_module = THIS_MODULE;
510 sha->sas_addr = &mvi->sas_addr[0];
511
512 sha->num_phys = nr_core * chip_info->n_phy;
513
514 sha->lldd_max_execute_num = lldd_max_execute_num;
515
516 if (mvi->flags & MVF_FLAG_SOC)
517 can_queue = MVS_SOC_CAN_QUEUE;
518 else
519 can_queue = MVS_CHIP_SLOT_SZ;
520
521 sha->lldd_queue_size = can_queue;
522 shost->sg_tablesize = min_t(u16, SG_ALL, MVS_MAX_SG);
523 shost->can_queue = can_queue;
524 mvi->shost->cmd_per_lun = MVS_QUEUE_SIZE;
525 sha->core.shost = mvi->shost;
526}
527
528static void mvs_init_sas_add(struct mvs_info *mvi)
529{
530 u8 i;
531 for (i = 0; i < mvi->chip->n_phy; i++) {
532 mvi->phy[i].dev_sas_addr = 0x5005043011ab0000ULL;
533 mvi->phy[i].dev_sas_addr =
534 cpu_to_be64((u64)(*(u64 *)&mvi->phy[i].dev_sas_addr));
535 }
536
537 memcpy(mvi->sas_addr, &mvi->phy[0].dev_sas_addr, SAS_ADDR_SIZE);
538}
539
540static int mvs_pci_init(struct pci_dev *pdev, const struct pci_device_id *ent)
541{
542 unsigned int rc, nhost = 0;
543 struct mvs_info *mvi;
544 struct mvs_prv_info *mpi;
545 irq_handler_t irq_handler = mvs_interrupt;
546 struct Scsi_Host *shost = NULL;
547 const struct mvs_chip_info *chip;
548
549 dev_printk(KERN_INFO, &pdev->dev,
550 "mvsas: driver version %s\n", DRV_VERSION);
551 rc = pci_enable_device(pdev);
552 if (rc)
553 goto err_out_enable;
554
555 pci_set_master(pdev);
556
557 rc = pci_request_regions(pdev, DRV_NAME);
558 if (rc)
559 goto err_out_disable;
560
561 rc = pci_go_64(pdev);
562 if (rc)
563 goto err_out_regions;
564
565 shost = scsi_host_alloc(&mvs_sht, sizeof(void *));
566 if (!shost) {
567 rc = -ENOMEM;
568 goto err_out_regions;
569 }
570
571 chip = &mvs_chips[ent->driver_data];
572 SHOST_TO_SAS_HA(shost) =
573 kcalloc(1, sizeof(struct sas_ha_struct), GFP_KERNEL);
574 if (!SHOST_TO_SAS_HA(shost)) {
575 kfree(shost);
576 rc = -ENOMEM;
577 goto err_out_regions;
578 }
579
580 rc = mvs_prep_sas_ha_init(shost, chip);
581 if (rc) {
582 kfree(shost);
583 rc = -ENOMEM;
584 goto err_out_regions;
585 }
586
587 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
588
589 do {
590 mvi = mvs_pci_alloc(pdev, ent, shost, nhost);
591 if (!mvi) {
592 rc = -ENOMEM;
593 goto err_out_regions;
594 }
595
596 memset(&mvi->hba_info_param, 0xFF,
597 sizeof(struct hba_info_page));
598
599 mvs_init_sas_add(mvi);
600
601 mvi->instance = nhost;
602 rc = MVS_CHIP_DISP->chip_init(mvi);
603 if (rc) {
604 mvs_free(mvi);
605 goto err_out_regions;
606 }
607 nhost++;
608 } while (nhost < chip->n_host);
609 mpi = (struct mvs_prv_info *)(SHOST_TO_SAS_HA(shost)->lldd_ha);
610#ifdef CONFIG_SCSI_MVSAS_TASKLET
611 tasklet_init(&(mpi->mv_tasklet), mvs_tasklet,
612 (unsigned long)SHOST_TO_SAS_HA(shost));
613#endif
614
615 mvs_post_sas_ha_init(shost, chip);
616
617 rc = scsi_add_host(shost, &pdev->dev);
618 if (rc)
619 goto err_out_shost;
620
621 rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
622 if (rc)
623 goto err_out_shost;
624 rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED,
625 DRV_NAME, SHOST_TO_SAS_HA(shost));
626 if (rc)
627 goto err_not_sas;
628
629 MVS_CHIP_DISP->interrupt_enable(mvi);
630
631 scsi_scan_host(mvi->shost);
632
633 return 0;
634
635err_not_sas:
636 sas_unregister_ha(SHOST_TO_SAS_HA(shost));
637err_out_shost:
638 scsi_remove_host(mvi->shost);
639err_out_regions:
640 pci_release_regions(pdev);
641err_out_disable:
642 pci_disable_device(pdev);
643err_out_enable:
644 return rc;
645}
646
647static void mvs_pci_remove(struct pci_dev *pdev)
648{
649 unsigned short core_nr, i = 0;
650 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
651 struct mvs_info *mvi = NULL;
652
653 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
654 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
655
656#ifdef CONFIG_SCSI_MVSAS_TASKLET
657 tasklet_kill(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet);
658#endif
659
660 pci_set_drvdata(pdev, NULL);
661 sas_unregister_ha(sha);
662 sas_remove_host(mvi->shost);
663 scsi_remove_host(mvi->shost);
664
665 MVS_CHIP_DISP->interrupt_disable(mvi);
666 free_irq(mvi->pdev->irq, sha);
667 for (i = 0; i < core_nr; i++) {
668 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
669 mvs_free(mvi);
670 }
671 kfree(sha->sas_phy);
672 kfree(sha->sas_port);
673 kfree(sha);
674 pci_release_regions(pdev);
675 pci_disable_device(pdev);
676 return;
677}
678
679static struct pci_device_id mvs_pci_table[] = {
680 { PCI_VDEVICE(MARVELL, 0x6320), chip_6320 },
681 { PCI_VDEVICE(MARVELL, 0x6340), chip_6440 },
682 {
683 .vendor = PCI_VENDOR_ID_MARVELL,
684 .device = 0x6440,
685 .subvendor = PCI_ANY_ID,
686 .subdevice = 0x6480,
687 .class = 0,
688 .class_mask = 0,
689 .driver_data = chip_6485,
690 },
691 { PCI_VDEVICE(MARVELL, 0x6440), chip_6440 },
692 { PCI_VDEVICE(MARVELL, 0x6485), chip_6485 },
693 { PCI_VDEVICE(MARVELL, 0x9480), chip_9480 },
694 { PCI_VDEVICE(MARVELL, 0x9180), chip_9180 },
695 { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1300), chip_1300 },
696 { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1320), chip_1320 },
697 { PCI_VDEVICE(ADAPTEC2, 0x0450), chip_6440 },
698 { PCI_VDEVICE(TTI, 0x2710), chip_9480 },
699 { PCI_VDEVICE(TTI, 0x2720), chip_9480 },
700 { PCI_VDEVICE(TTI, 0x2721), chip_9480 },
701 { PCI_VDEVICE(TTI, 0x2722), chip_9480 },
702 { PCI_VDEVICE(TTI, 0x2740), chip_9480 },
703 { PCI_VDEVICE(TTI, 0x2744), chip_9480 },
704 { PCI_VDEVICE(TTI, 0x2760), chip_9480 },
705 {
706 .vendor = PCI_VENDOR_ID_MARVELL_EXT,
707 .device = 0x9480,
708 .subvendor = PCI_ANY_ID,
709 .subdevice = 0x9480,
710 .class = 0,
711 .class_mask = 0,
712 .driver_data = chip_9480,
713 },
714 {
715 .vendor = PCI_VENDOR_ID_MARVELL_EXT,
716 .device = 0x9445,
717 .subvendor = PCI_ANY_ID,
718 .subdevice = 0x9480,
719 .class = 0,
720 .class_mask = 0,
721 .driver_data = chip_9445,
722 },
723 {
724 .vendor = PCI_VENDOR_ID_MARVELL_EXT,
725 .device = 0x9485,
726 .subvendor = PCI_ANY_ID,
727 .subdevice = 0x9480,
728 .class = 0,
729 .class_mask = 0,
730 .driver_data = chip_9485,
731 },
732 { PCI_VDEVICE(OCZ, 0x1021), chip_9485},
733 { PCI_VDEVICE(OCZ, 0x1022), chip_9485},
734 { PCI_VDEVICE(OCZ, 0x1040), chip_9485},
735 { PCI_VDEVICE(OCZ, 0x1041), chip_9485},
736 { PCI_VDEVICE(OCZ, 0x1042), chip_9485},
737 { PCI_VDEVICE(OCZ, 0x1043), chip_9485},
738 { PCI_VDEVICE(OCZ, 0x1044), chip_9485},
739 { PCI_VDEVICE(OCZ, 0x1080), chip_9485},
740 { PCI_VDEVICE(OCZ, 0x1083), chip_9485},
741 { PCI_VDEVICE(OCZ, 0x1084), chip_9485},
742
743 { }
744};
745
746static struct pci_driver mvs_pci_driver = {
747 .name = DRV_NAME,
748 .id_table = mvs_pci_table,
749 .probe = mvs_pci_init,
750 .remove = mvs_pci_remove,
751};
752
753static ssize_t
754mvs_show_driver_version(struct device *cdev,
755 struct device_attribute *attr, char *buffer)
756{
757 return snprintf(buffer, PAGE_SIZE, "%s\n", DRV_VERSION);
758}
759
760static DEVICE_ATTR(driver_version,
761 S_IRUGO,
762 mvs_show_driver_version,
763 NULL);
764
765static ssize_t
766mvs_store_interrupt_coalescing(struct device *cdev,
767 struct device_attribute *attr,
768 const char *buffer, size_t size)
769{
770 int val = 0;
771 struct mvs_info *mvi = NULL;
772 struct Scsi_Host *shost = class_to_shost(cdev);
773 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
774 u8 i, core_nr;
775 if (buffer == NULL)
776 return size;
777
778 if (sscanf(buffer, "%d", &val) != 1)
779 return -EINVAL;
780
781 if (val >= 0x10000) {
782 mv_dprintk("interrupt coalescing timer %d us is"
783 "too long\n", val);
784 return strlen(buffer);
785 }
786
787 interrupt_coalescing = val;
788
789 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
790 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
791
792 if (unlikely(!mvi))
793 return -EINVAL;
794
795 for (i = 0; i < core_nr; i++) {
796 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
797 if (MVS_CHIP_DISP->tune_interrupt)
798 MVS_CHIP_DISP->tune_interrupt(mvi,
799 interrupt_coalescing);
800 }
801 mv_dprintk("set interrupt coalescing time to %d us\n",
802 interrupt_coalescing);
803 return strlen(buffer);
804}
805
806static ssize_t mvs_show_interrupt_coalescing(struct device *cdev,
807 struct device_attribute *attr, char *buffer)
808{
809 return snprintf(buffer, PAGE_SIZE, "%d\n", interrupt_coalescing);
810}
811
812static DEVICE_ATTR(interrupt_coalescing,
813 S_IRUGO|S_IWUSR,
814 mvs_show_interrupt_coalescing,
815 mvs_store_interrupt_coalescing);
816
817
818struct task_struct *mvs_th;
819static int __init mvs_init(void)
820{
821 int rc;
822 mvs_stt = sas_domain_attach_transport(&mvs_transport_ops);
823 if (!mvs_stt)
824 return -ENOMEM;
825
826 mvs_task_list_cache = kmem_cache_create("mvs_task_list", sizeof(struct mvs_task_list),
827 0, SLAB_HWCACHE_ALIGN, NULL);
828 if (!mvs_task_list_cache) {
829 rc = -ENOMEM;
830 mv_printk("%s: mvs_task_list_cache alloc failed! \n", __func__);
831 goto err_out;
832 }
833
834 rc = pci_register_driver(&mvs_pci_driver);
835
836 if (rc)
837 goto err_out;
838
839 return 0;
840
841err_out:
842 sas_release_transport(mvs_stt);
843 return rc;
844}
845
846static void __exit mvs_exit(void)
847{
848 pci_unregister_driver(&mvs_pci_driver);
849 sas_release_transport(mvs_stt);
850 kmem_cache_destroy(mvs_task_list_cache);
851}
852
853struct device_attribute *mvst_host_attrs[] = {
854 &dev_attr_driver_version,
855 &dev_attr_interrupt_coalescing,
856 NULL,
857};
858
859module_init(mvs_init);
860module_exit(mvs_exit);
861
862MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
863MODULE_DESCRIPTION("Marvell 88SE6440 SAS/SATA controller driver");
864MODULE_VERSION(DRV_VERSION);
865MODULE_LICENSE("GPL");
866#ifdef CONFIG_PCI
867MODULE_DEVICE_TABLE(pci, mvs_pci_table);
868#endif
869
