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6
7#ifndef __QLA_DEF_H
8#define __QLA_DEF_H
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/types.h>
13#include <linux/module.h>
14#include <linux/list.h>
15#include <linux/pci.h>
16#include <linux/dma-mapping.h>
17#include <linux/sched.h>
18#include <linux/slab.h>
19#include <linux/dmapool.h>
20#include <linux/mempool.h>
21#include <linux/spinlock.h>
22#include <linux/completion.h>
23#include <linux/interrupt.h>
24#include <linux/workqueue.h>
25#include <linux/firmware.h>
26#include <linux/aer.h>
27#include <linux/mutex.h>
28
29#include <scsi/scsi.h>
30#include <scsi/scsi_host.h>
31#include <scsi/scsi_device.h>
32#include <scsi/scsi_cmnd.h>
33#include <scsi/scsi_transport_fc.h>
34#include <scsi/scsi_bsg_fc.h>
35
36#include "qla_bsg.h"
37#include "qla_nx.h"
38#include "qla_nx2.h"
39#define QLA2XXX_DRIVER_NAME "qla2xxx"
40#define QLA2XXX_APIDEV "ql2xapidev"
41#define QLA2XXX_MANUFACTURER "QLogic Corporation"
42
43
44
45
46
47
48#define MAILBOX_REGISTER_COUNT_2100 8
49#define MAILBOX_REGISTER_COUNT_2200 24
50#define MAILBOX_REGISTER_COUNT 32
51
52#define QLA2200A_RISC_ROM_VER 4
53#define FPM_2300 6
54#define FPM_2310 7
55
56#include "qla_settings.h"
57
58
59
60
61#define BIT_0 0x1
62#define BIT_1 0x2
63#define BIT_2 0x4
64#define BIT_3 0x8
65#define BIT_4 0x10
66#define BIT_5 0x20
67#define BIT_6 0x40
68#define BIT_7 0x80
69#define BIT_8 0x100
70#define BIT_9 0x200
71#define BIT_10 0x400
72#define BIT_11 0x800
73#define BIT_12 0x1000
74#define BIT_13 0x2000
75#define BIT_14 0x4000
76#define BIT_15 0x8000
77#define BIT_16 0x10000
78#define BIT_17 0x20000
79#define BIT_18 0x40000
80#define BIT_19 0x80000
81#define BIT_20 0x100000
82#define BIT_21 0x200000
83#define BIT_22 0x400000
84#define BIT_23 0x800000
85#define BIT_24 0x1000000
86#define BIT_25 0x2000000
87#define BIT_26 0x4000000
88#define BIT_27 0x8000000
89#define BIT_28 0x10000000
90#define BIT_29 0x20000000
91#define BIT_30 0x40000000
92#define BIT_31 0x80000000
93
94#define LSB(x) ((uint8_t)(x))
95#define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
96
97#define LSW(x) ((uint16_t)(x))
98#define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
99
100#define LSD(x) ((uint32_t)((uint64_t)(x)))
101#define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
102
103#define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y)))
104
105
106
107
108
109#define RD_REG_BYTE(addr) readb(addr)
110#define RD_REG_WORD(addr) readw(addr)
111#define RD_REG_DWORD(addr) readl(addr)
112#define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
113#define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
114#define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
115#define WRT_REG_BYTE(addr, data) writeb(data,addr)
116#define WRT_REG_WORD(addr, data) writew(data,addr)
117#define WRT_REG_DWORD(addr, data) writel(data,addr)
118
119
120
121
122#define QLA83XX_LED_PORT0 0x00201320
123#define QLA83XX_LED_PORT1 0x00201328
124#define QLA83XX_IDC_DEV_STATE 0x22102384
125#define QLA83XX_IDC_MAJOR_VERSION 0x22102380
126#define QLA83XX_IDC_MINOR_VERSION 0x22102398
127#define QLA83XX_IDC_DRV_PRESENCE 0x22102388
128#define QLA83XX_IDC_DRIVER_ACK 0x2210238c
129#define QLA83XX_IDC_CONTROL 0x22102390
130#define QLA83XX_IDC_AUDIT 0x22102394
131#define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c
132#define QLA83XX_DRIVER_LOCKID 0x22102104
133#define QLA83XX_DRIVER_LOCK 0x8111c028
134#define QLA83XX_DRIVER_UNLOCK 0x8111c02c
135#define QLA83XX_FLASH_LOCKID 0x22102100
136#define QLA83XX_FLASH_LOCK 0x8111c010
137#define QLA83XX_FLASH_UNLOCK 0x8111c014
138#define QLA83XX_DEV_PARTINFO1 0x221023e0
139#define QLA83XX_DEV_PARTINFO2 0x221023e4
140#define QLA83XX_FW_HEARTBEAT 0x221020b0
141#define QLA83XX_PEG_HALT_STATUS1 0x221020a8
142#define QLA83XX_PEG_HALT_STATUS2 0x221020ac
143
144
145#define IDC_DEVICE_STATE_CHANGE BIT_0
146#define IDC_PEG_HALT_STATUS_CHANGE BIT_1
147#define IDC_NIC_FW_REPORTED_FAILURE BIT_2
148#define IDC_HEARTBEAT_FAILURE BIT_3
149
150
151#define ERR_LEVEL_NON_FATAL 0x1
152#define ERR_LEVEL_RECOVERABLE_FATAL 0x2
153#define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4
154
155
156#define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01
157#define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0
158
159
160#define QLA83XX_NIC_CORE_RESET 0x1
161#define QLA83XX_IDC_STATE_HANDLER 0x2
162#define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3
163
164
165#define QLA83XX_IDC_RESET_DISABLED BIT_0
166#define QLA83XX_IDC_GRACEFUL_RESET BIT_1
167
168
169#define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30
170#define QLA83XX_IDC_RESET_ACK_TIMEOUT 10
171#define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ)
172
173
174#define QLA83XX_CLASS_TYPE_NONE 0x0
175#define QLA83XX_CLASS_TYPE_NIC 0x1
176#define QLA83XX_CLASS_TYPE_FCOE 0x2
177#define QLA83XX_CLASS_TYPE_ISCSI 0x3
178
179
180#define IDC_LOCK_RECOVERY_STAGE1 0x1
181
182
183#define IDC_LOCK_RECOVERY_STAGE2 0x2
184
185
186#define IDC_AUDIT_TIMESTAMP 0x0
187
188
189
190#define IDC_AUDIT_COMPLETION 0x1
191
192
193
194
195
196
197
198
199#define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
200#define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
201
202
203
204
205#define WWN_SIZE 8
206#define MAX_FIBRE_DEVICES_2100 512
207#define MAX_FIBRE_DEVICES_2400 2048
208#define MAX_FIBRE_DEVICES_LOOP 128
209#define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400
210#define LOOPID_MAP_SIZE (ha->max_fibre_devices)
211#define MAX_FIBRE_LUNS 0xFFFF
212#define MAX_HOST_COUNT 16
213
214
215
216
217#define MAX_BUSES 1
218#define MIN_LUNS 8
219#define MAX_LUNS MAX_FIBRE_LUNS
220#define MAX_CMDS_PER_LUN 255
221
222
223
224
225#define SNS_LAST_LOOP_ID_2100 0xfe
226#define SNS_LAST_LOOP_ID_2300 0x7ff
227
228#define LAST_LOCAL_LOOP_ID 0x7d
229#define SNS_FL_PORT 0x7e
230#define FABRIC_CONTROLLER 0x7f
231#define SIMPLE_NAME_SERVER 0x80
232#define SNS_FIRST_LOOP_ID 0x81
233#define MANAGEMENT_SERVER 0xfe
234#define BROADCAST 0xff
235
236
237
238
239
240#define NPH_LAST_HANDLE 0x7ef
241#define NPH_MGMT_SERVER 0x7fa
242#define NPH_SNS 0x7fc
243#define NPH_FABRIC_CONTROLLER 0x7fd
244#define NPH_F_PORT 0x7fe
245#define NPH_IP_BROADCAST 0x7ff
246
247#define MAX_CMDSZ 16
248#include "qla_fw.h"
249
250
251
252#define PORT_RETRY_TIME 1
253#define LOOP_DOWN_TIMEOUT 60
254#define LOOP_DOWN_TIME 255
255#define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
256
257#define DEFAULT_OUTSTANDING_COMMANDS 1024
258#define MIN_OUTSTANDING_COMMANDS 128
259
260
261#define REQUEST_ENTRY_CNT_2100 128
262#define REQUEST_ENTRY_CNT_2200 2048
263#define REQUEST_ENTRY_CNT_24XX 2048
264#define RESPONSE_ENTRY_CNT_2100 64
265#define RESPONSE_ENTRY_CNT_2300 512
266#define RESPONSE_ENTRY_CNT_MQ 128
267#define ATIO_ENTRY_CNT_24XX 4096
268#define RESPONSE_ENTRY_CNT_FX00 256
269
270struct req_que;
271
272
273
274
275
276struct sd_dif_tuple {
277 __be16 guard_tag;
278 __be16 app_tag;
279 __be32 ref_tag;
280};
281
282
283
284
285struct srb_cmd {
286 struct scsi_cmnd *cmd;
287 uint32_t request_sense_length;
288 uint32_t fw_sense_length;
289 uint8_t *request_sense_ptr;
290 void *ctx;
291};
292
293
294
295
296#define SRB_DMA_VALID BIT_0
297#define SRB_FCP_CMND_DMA_VALID BIT_12
298#define SRB_CRC_CTX_DMA_VALID BIT_2
299#define SRB_CRC_PROT_DMA_VALID BIT_4
300#define SRB_CRC_CTX_DSD_VALID BIT_5
301
302
303#define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
304
305
306
307
308struct srb_iocb {
309 union {
310 struct {
311 uint16_t flags;
312#define SRB_LOGIN_RETRIED BIT_0
313#define SRB_LOGIN_COND_PLOGI BIT_1
314#define SRB_LOGIN_SKIP_PRLI BIT_2
315 uint16_t data[2];
316 } logio;
317 struct {
318
319
320
321
322
323 uint32_t flags;
324 uint32_t lun;
325 uint32_t data;
326 struct completion comp;
327 __le16 comp_status;
328 } tmf;
329 struct {
330#define SRB_FXDISC_REQ_DMA_VALID BIT_0
331#define SRB_FXDISC_RESP_DMA_VALID BIT_1
332#define SRB_FXDISC_REQ_DWRD_VALID BIT_2
333#define SRB_FXDISC_RSP_DWRD_VALID BIT_3
334#define FXDISC_TIMEOUT 20
335 uint8_t flags;
336 uint32_t req_len;
337 uint32_t rsp_len;
338 void *req_addr;
339 void *rsp_addr;
340 dma_addr_t req_dma_handle;
341 dma_addr_t rsp_dma_handle;
342 __le32 adapter_id;
343 __le32 adapter_id_hi;
344 __le16 req_func_type;
345 __le32 req_data;
346 __le32 req_data_extra;
347 __le32 result;
348 __le32 seq_number;
349 __le16 fw_flags;
350 struct completion fxiocb_comp;
351 __le32 reserved_0;
352 uint8_t reserved_1;
353 } fxiocb;
354 struct {
355 uint32_t cmd_hndl;
356 __le16 comp_status;
357 struct completion comp;
358 } abt;
359 } u;
360
361 struct timer_list timer;
362 void (*timeout)(void *);
363};
364
365
366#define SRB_LOGIN_CMD 1
367#define SRB_LOGOUT_CMD 2
368#define SRB_ELS_CMD_RPT 3
369#define SRB_ELS_CMD_HST 4
370#define SRB_CT_CMD 5
371#define SRB_ADISC_CMD 6
372#define SRB_TM_CMD 7
373#define SRB_SCSI_CMD 8
374#define SRB_BIDI_CMD 9
375#define SRB_FXIOCB_DCMD 10
376#define SRB_FXIOCB_BCMD 11
377#define SRB_ABT_CMD 12
378
379
380typedef struct srb {
381 atomic_t ref_count;
382 struct fc_port *fcport;
383 uint32_t handle;
384 uint16_t flags;
385 uint16_t type;
386 char *name;
387 int iocbs;
388 union {
389 struct srb_iocb iocb_cmd;
390 struct fc_bsg_job *bsg_job;
391 struct srb_cmd scmd;
392 } u;
393 void (*done)(void *, void *, int);
394 void (*free)(void *, void *);
395} srb_t;
396
397#define GET_CMD_SP(sp) (sp->u.scmd.cmd)
398#define SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd)
399#define GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx)
400
401#define GET_CMD_SENSE_LEN(sp) \
402 (sp->u.scmd.request_sense_length)
403#define SET_CMD_SENSE_LEN(sp, len) \
404 (sp->u.scmd.request_sense_length = len)
405#define GET_CMD_SENSE_PTR(sp) \
406 (sp->u.scmd.request_sense_ptr)
407#define SET_CMD_SENSE_PTR(sp, ptr) \
408 (sp->u.scmd.request_sense_ptr = ptr)
409#define GET_FW_SENSE_LEN(sp) \
410 (sp->u.scmd.fw_sense_length)
411#define SET_FW_SENSE_LEN(sp, len) \
412 (sp->u.scmd.fw_sense_length = len)
413
414struct msg_echo_lb {
415 dma_addr_t send_dma;
416 dma_addr_t rcv_dma;
417 uint16_t req_sg_cnt;
418 uint16_t rsp_sg_cnt;
419 uint16_t options;
420 uint32_t transfer_size;
421 uint32_t iteration_count;
422};
423
424
425
426
427struct device_reg_2xxx {
428 uint16_t flash_address;
429 uint16_t flash_data;
430 uint16_t unused_1[1];
431 uint16_t ctrl_status;
432#define CSR_FLASH_64K_BANK BIT_3
433#define CSR_FLASH_ENABLE BIT_1
434#define CSR_ISP_SOFT_RESET BIT_0
435
436 uint16_t ictrl;
437#define ICR_EN_INT BIT_15
438#define ICR_EN_RISC BIT_3
439
440 uint16_t istatus;
441#define ISR_RISC_INT BIT_3
442
443 uint16_t semaphore;
444 uint16_t nvram;
445#define NVR_DESELECT 0
446#define NVR_BUSY BIT_15
447#define NVR_WRT_ENABLE BIT_14
448#define NVR_PR_ENABLE BIT_13
449#define NVR_DATA_IN BIT_3
450#define NVR_DATA_OUT BIT_2
451#define NVR_SELECT BIT_1
452#define NVR_CLOCK BIT_0
453
454#define NVR_WAIT_CNT 20000
455
456 union {
457 struct {
458 uint16_t mailbox0;
459 uint16_t mailbox1;
460 uint16_t mailbox2;
461 uint16_t mailbox3;
462 uint16_t mailbox4;
463 uint16_t mailbox5;
464 uint16_t mailbox6;
465 uint16_t mailbox7;
466 uint16_t unused_2[59];
467 } __attribute__((packed)) isp2100;
468 struct {
469
470 uint16_t req_q_in;
471 uint16_t req_q_out;
472
473 uint16_t rsp_q_in;
474 uint16_t rsp_q_out;
475
476
477 uint32_t host_status;
478#define HSR_RISC_INT BIT_15
479#define HSR_RISC_PAUSED BIT_8
480
481
482 uint16_t host_semaphore;
483 uint16_t unused_3[17];
484 uint16_t mailbox0;
485 uint16_t mailbox1;
486 uint16_t mailbox2;
487 uint16_t mailbox3;
488 uint16_t mailbox4;
489 uint16_t mailbox5;
490 uint16_t mailbox6;
491 uint16_t mailbox7;
492 uint16_t mailbox8;
493 uint16_t mailbox9;
494 uint16_t mailbox10;
495 uint16_t mailbox11;
496 uint16_t mailbox12;
497 uint16_t mailbox13;
498 uint16_t mailbox14;
499 uint16_t mailbox15;
500 uint16_t mailbox16;
501 uint16_t mailbox17;
502 uint16_t mailbox18;
503 uint16_t mailbox19;
504 uint16_t mailbox20;
505 uint16_t mailbox21;
506 uint16_t mailbox22;
507 uint16_t mailbox23;
508 uint16_t mailbox24;
509 uint16_t mailbox25;
510 uint16_t mailbox26;
511 uint16_t mailbox27;
512 uint16_t mailbox28;
513 uint16_t mailbox29;
514 uint16_t mailbox30;
515 uint16_t mailbox31;
516 uint16_t fb_cmd;
517 uint16_t unused_4[10];
518 } __attribute__((packed)) isp2300;
519 } u;
520
521 uint16_t fpm_diag_config;
522 uint16_t unused_5[0x4];
523 uint16_t risc_hw;
524 uint16_t unused_5_1;
525 uint16_t pcr;
526 uint16_t unused_6[0x5];
527 uint16_t mctr;
528 uint16_t unused_7[0x3];
529 uint16_t fb_cmd_2100;
530 uint16_t unused_8[0x3];
531 uint16_t hccr;
532#define HCCR_HOST_INT BIT_7
533#define HCCR_RISC_PAUSE BIT_5
534
535#define HCCR_RESET_RISC 0x1000
536#define HCCR_PAUSE_RISC 0x2000
537#define HCCR_RELEASE_RISC 0x3000
538#define HCCR_SET_HOST_INT 0x5000
539#define HCCR_CLR_HOST_INT 0x6000
540#define HCCR_CLR_RISC_INT 0x7000
541#define HCCR_DISABLE_PARITY_PAUSE 0x4001
542#define HCCR_ENABLE_PARITY 0xA000
543
544 uint16_t unused_9[5];
545 uint16_t gpiod;
546 uint16_t gpioe;
547#define GPIO_LED_MASK 0x00C0
548#define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
549#define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
550#define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
551#define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
552#define GPIO_LED_ALL_OFF 0x0000
553#define GPIO_LED_RED_ON_OTHER_OFF 0x0001
554#define GPIO_LED_RGA_ON 0x00C1
555
556 union {
557 struct {
558 uint16_t unused_10[8];
559 uint16_t mailbox8;
560 uint16_t mailbox9;
561 uint16_t mailbox10;
562 uint16_t mailbox11;
563 uint16_t mailbox12;
564 uint16_t mailbox13;
565 uint16_t mailbox14;
566 uint16_t mailbox15;
567 uint16_t mailbox16;
568 uint16_t mailbox17;
569 uint16_t mailbox18;
570 uint16_t mailbox19;
571 uint16_t mailbox20;
572 uint16_t mailbox21;
573 uint16_t mailbox22;
574 uint16_t mailbox23;
575 } __attribute__((packed)) isp2200;
576 } u_end;
577};
578
579struct device_reg_25xxmq {
580 uint32_t req_q_in;
581 uint32_t req_q_out;
582 uint32_t rsp_q_in;
583 uint32_t rsp_q_out;
584 uint32_t atio_q_in;
585 uint32_t atio_q_out;
586};
587
588
589struct device_reg_fx00 {
590 uint32_t mailbox0;
591 uint32_t mailbox1;
592 uint32_t mailbox2;
593 uint32_t mailbox3;
594 uint32_t mailbox4;
595 uint32_t mailbox5;
596 uint32_t mailbox6;
597 uint32_t mailbox7;
598 uint32_t mailbox8;
599 uint32_t mailbox9;
600 uint32_t mailbox10;
601 uint32_t mailbox11;
602 uint32_t mailbox12;
603 uint32_t mailbox13;
604 uint32_t mailbox14;
605 uint32_t mailbox15;
606 uint32_t mailbox16;
607 uint32_t mailbox17;
608 uint32_t mailbox18;
609 uint32_t mailbox19;
610 uint32_t mailbox20;
611 uint32_t mailbox21;
612 uint32_t mailbox22;
613 uint32_t mailbox23;
614 uint32_t mailbox24;
615 uint32_t mailbox25;
616 uint32_t mailbox26;
617 uint32_t mailbox27;
618 uint32_t mailbox28;
619 uint32_t mailbox29;
620 uint32_t mailbox30;
621 uint32_t mailbox31;
622 uint32_t aenmailbox0;
623 uint32_t aenmailbox1;
624 uint32_t aenmailbox2;
625 uint32_t aenmailbox3;
626 uint32_t aenmailbox4;
627 uint32_t aenmailbox5;
628 uint32_t aenmailbox6;
629 uint32_t aenmailbox7;
630
631 uint32_t req_q_in;
632 uint32_t req_q_out;
633
634 uint32_t rsp_q_in;
635 uint32_t rsp_q_out;
636
637 uint32_t initval0;
638 uint32_t initval1;
639 uint32_t initval2;
640 uint32_t initval3;
641 uint32_t initval4;
642 uint32_t initval5;
643 uint32_t initval6;
644 uint32_t initval7;
645 uint32_t fwheartbeat;
646 uint32_t pseudoaen;
647};
648
649
650
651typedef union {
652 struct device_reg_2xxx isp;
653 struct device_reg_24xx isp24;
654 struct device_reg_25xxmq isp25mq;
655 struct device_reg_82xx isp82;
656 struct device_reg_fx00 ispfx00;
657} device_reg_t;
658
659#define ISP_REQ_Q_IN(ha, reg) \
660 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
661 &(reg)->u.isp2100.mailbox4 : \
662 &(reg)->u.isp2300.req_q_in)
663#define ISP_REQ_Q_OUT(ha, reg) \
664 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
665 &(reg)->u.isp2100.mailbox4 : \
666 &(reg)->u.isp2300.req_q_out)
667#define ISP_RSP_Q_IN(ha, reg) \
668 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
669 &(reg)->u.isp2100.mailbox5 : \
670 &(reg)->u.isp2300.rsp_q_in)
671#define ISP_RSP_Q_OUT(ha, reg) \
672 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
673 &(reg)->u.isp2100.mailbox5 : \
674 &(reg)->u.isp2300.rsp_q_out)
675
676#define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in)
677#define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out)
678
679#define MAILBOX_REG(ha, reg, num) \
680 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
681 (num < 8 ? \
682 &(reg)->u.isp2100.mailbox0 + (num) : \
683 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
684 &(reg)->u.isp2300.mailbox0 + (num))
685#define RD_MAILBOX_REG(ha, reg, num) \
686 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
687#define WRT_MAILBOX_REG(ha, reg, num, data) \
688 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
689
690#define FB_CMD_REG(ha, reg) \
691 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
692 &(reg)->fb_cmd_2100 : \
693 &(reg)->u.isp2300.fb_cmd)
694#define RD_FB_CMD_REG(ha, reg) \
695 RD_REG_WORD(FB_CMD_REG(ha, reg))
696#define WRT_FB_CMD_REG(ha, reg, data) \
697 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
698
699typedef struct {
700 uint32_t out_mb;
701 uint32_t in_mb;
702 uint16_t mb[MAILBOX_REGISTER_COUNT];
703 long buf_size;
704 void *bufp;
705 uint32_t tov;
706 uint8_t flags;
707#define MBX_DMA_IN BIT_0
708#define MBX_DMA_OUT BIT_1
709#define IOCTL_CMD BIT_2
710} mbx_cmd_t;
711
712struct mbx_cmd_32 {
713 uint32_t out_mb;
714 uint32_t in_mb;
715 uint32_t mb[MAILBOX_REGISTER_COUNT];
716 long buf_size;
717 void *bufp;
718 uint32_t tov;
719 uint8_t flags;
720#define MBX_DMA_IN BIT_0
721#define MBX_DMA_OUT BIT_1
722#define IOCTL_CMD BIT_2
723};
724
725
726#define MBX_TOV_SECONDS 30
727
728
729
730
731#define PROD_ID_1 0x4953
732#define PROD_ID_2 0x0000
733#define PROD_ID_2a 0x5020
734#define PROD_ID_3 0x2020
735
736
737
738
739#define MBS_FRM_ALIVE 0
740#define MBS_CHKSUM_ERR 1
741#define MBS_BUSY 4
742
743
744
745
746#define MBS_COMMAND_COMPLETE 0x4000
747#define MBS_INVALID_COMMAND 0x4001
748#define MBS_HOST_INTERFACE_ERROR 0x4002
749#define MBS_TEST_FAILED 0x4003
750#define MBS_COMMAND_ERROR 0x4005
751#define MBS_COMMAND_PARAMETER_ERROR 0x4006
752#define MBS_PORT_ID_USED 0x4007
753#define MBS_LOOP_ID_USED 0x4008
754#define MBS_ALL_IDS_IN_USE 0x4009
755#define MBS_NOT_LOGGED_IN 0x400A
756#define MBS_LINK_DOWN_ERROR 0x400B
757#define MBS_DIAG_ECHO_TEST_ERROR 0x400C
758
759
760
761
762#define MBA_ASYNC_EVENT 0x8000
763#define MBA_RESET 0x8001
764#define MBA_SYSTEM_ERR 0x8002
765#define MBA_REQ_TRANSFER_ERR 0x8003
766#define MBA_RSP_TRANSFER_ERR 0x8004
767#define MBA_WAKEUP_THRES 0x8005
768#define MBA_LIP_OCCURRED 0x8010
769
770#define MBA_LOOP_UP 0x8011
771#define MBA_LOOP_DOWN 0x8012
772#define MBA_LIP_RESET 0x8013
773#define MBA_PORT_UPDATE 0x8014
774#define MBA_RSCN_UPDATE 0x8015
775#define MBA_LIP_F8 0x8016
776#define MBA_LOOP_INIT_ERR 0x8017
777#define MBA_FABRIC_AUTH_REQ 0x801b
778#define MBA_SCSI_COMPLETION 0x8020
779#define MBA_CTIO_COMPLETION 0x8021
780#define MBA_IP_COMPLETION 0x8022
781#define MBA_IP_RECEIVE 0x8023
782#define MBA_IP_BROADCAST 0x8024
783#define MBA_IP_LOW_WATER_MARK 0x8025
784#define MBA_IP_RCV_BUFFER_EMPTY 0x8026
785#define MBA_IP_HDR_DATA_SPLIT 0x8027
786
787#define MBA_TRACE_NOTIFICATION 0x8028
788#define MBA_POINT_TO_POINT 0x8030
789#define MBA_CMPLT_1_16BIT 0x8031
790#define MBA_CMPLT_2_16BIT 0x8032
791#define MBA_CMPLT_3_16BIT 0x8033
792#define MBA_CMPLT_4_16BIT 0x8034
793#define MBA_CMPLT_5_16BIT 0x8035
794#define MBA_CHG_IN_CONNECTION 0x8036
795#define MBA_RIO_RESPONSE 0x8040
796#define MBA_ZIO_RESPONSE 0x8040
797#define MBA_CMPLT_2_32BIT 0x8042
798#define MBA_BYPASS_NOTIFICATION 0x8043
799#define MBA_DISCARD_RND_FRAME 0x8048
800#define MBA_REJECTED_FCP_CMD 0x8049
801#define MBA_FW_NOT_STARTED 0x8050
802#define MBA_FW_STARTING 0x8051
803#define MBA_FW_RESTART_CMPLT 0x8060
804#define MBA_INIT_REQUIRED 0x8061
805#define MBA_SHUTDOWN_REQUESTED 0x8062
806#define MBA_FW_INIT_FAILURE 0x8401
807#define MBA_MIRROR_LUN_CHANGE 0x8402
808
809#define MBA_FW_POLL_STATE 0x8600
810#define MBA_FW_RESET_FCT 0x8502
811
812
813#define MBA_IDC_AEN 0x8200
814
815
816#define INTR_ROM_MB_SUCCESS 0x1
817#define INTR_ROM_MB_FAILED 0x2
818#define INTR_MB_SUCCESS 0x10
819#define INTR_MB_FAILED 0x11
820#define INTR_ASYNC_EVENT 0x12
821#define INTR_RSP_QUE_UPDATE 0x13
822#define INTR_RSP_QUE_UPDATE_83XX 0x14
823#define INTR_ATIO_QUE_UPDATE 0x1C
824#define INTR_ATIO_RSP_QUE_UPDATE 0x1D
825
826
827#define MBS_LB_RESET 0x17
828
829
830
831#define FO1_AE_ON_LIPF8 BIT_0
832#define FO1_AE_ALL_LIP_RESET BIT_1
833#define FO1_CTIO_RETRY BIT_3
834#define FO1_DISABLE_LIP_F7_SW BIT_4
835#define FO1_DISABLE_100MS_LOS_WAIT BIT_5
836#define FO1_DISABLE_GPIO6_7 BIT_6
837#define FO1_AE_ON_LOOP_INIT_ERR BIT_7
838#define FO1_SET_EMPHASIS_SWING BIT_8
839#define FO1_AE_AUTO_BYPASS BIT_9
840#define FO1_ENABLE_PURE_IOCB BIT_10
841#define FO1_AE_PLOGI_RJT BIT_11
842#define FO1_ENABLE_ABORT_SEQUENCE BIT_12
843#define FO1_AE_QUEUE_FULL BIT_13
844
845#define FO2_ENABLE_ATIO_TYPE_3 BIT_0
846#define FO2_REV_LOOPBACK BIT_1
847
848#define FO3_ENABLE_EMERG_IOCB BIT_0
849#define FO3_AE_RND_ERROR BIT_1
850
851
852#define ADD_FO_COUNT 3
853#define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6
854#define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
855
856#define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
857
858#define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
859
860
861
862
863#define MBC_LOAD_RAM 1
864#define MBC_EXECUTE_FIRMWARE 2
865#define MBC_WRITE_RAM_WORD 4
866#define MBC_READ_RAM_WORD 5
867#define MBC_MAILBOX_REGISTER_TEST 6
868#define MBC_VERIFY_CHECKSUM 7
869#define MBC_GET_FIRMWARE_VERSION 8
870#define MBC_LOAD_RISC_RAM 9
871#define MBC_DUMP_RISC_RAM 0xa
872#define MBC_LOAD_RISC_RAM_EXTENDED 0xb
873#define MBC_DUMP_RISC_RAM_EXTENDED 0xc
874#define MBC_WRITE_RAM_WORD_EXTENDED 0xd
875#define MBC_READ_RAM_EXTENDED 0xf
876#define MBC_IOCB_COMMAND 0x12
877#define MBC_STOP_FIRMWARE 0x14
878#define MBC_ABORT_COMMAND 0x15
879#define MBC_ABORT_DEVICE 0x16
880#define MBC_ABORT_TARGET 0x17
881#define MBC_RESET 0x18
882#define MBC_GET_ADAPTER_LOOP_ID 0x20
883#define MBC_GET_RETRY_COUNT 0x22
884#define MBC_DISABLE_VI 0x24
885#define MBC_ENABLE_VI 0x25
886#define MBC_GET_FIRMWARE_OPTION 0x28
887#define MBC_SET_FIRMWARE_OPTION 0x38
888#define MBC_LOOP_PORT_BYPASS 0x40
889#define MBC_LOOP_PORT_ENABLE 0x41
890#define MBC_GET_RESOURCE_COUNTS 0x42
891#define MBC_NON_PARTICIPATE 0x43
892#define MBC_DIAGNOSTIC_ECHO 0x44
893#define MBC_DIAGNOSTIC_LOOP_BACK 0x45
894#define MBC_ONLINE_SELF_TEST 0x46
895#define MBC_ENHANCED_GET_PORT_DATABASE 0x47
896#define MBC_CONFIGURE_VF 0x4b
897#define MBC_RESET_LINK_STATUS 0x52
898#define MBC_IOCB_COMMAND_A64 0x54
899#define MBC_PORT_LOGOUT 0x56
900#define MBC_SEND_RNID_ELS 0x57
901#define MBC_SET_RNID_PARAMS 0x59
902#define MBC_GET_RNID_PARAMS 0x5a
903#define MBC_DATA_RATE 0x5d
904#define MBC_INITIALIZE_FIRMWARE 0x60
905#define MBC_INITIATE_LIP 0x62
906
907#define MBC_GET_FC_AL_POSITION_MAP 0x63
908#define MBC_GET_PORT_DATABASE 0x64
909#define MBC_CLEAR_ACA 0x65
910#define MBC_TARGET_RESET 0x66
911#define MBC_CLEAR_TASK_SET 0x67
912#define MBC_ABORT_TASK_SET 0x68
913#define MBC_GET_FIRMWARE_STATE 0x69
914#define MBC_GET_PORT_NAME 0x6a
915#define MBC_GET_LINK_STATUS 0x6b
916#define MBC_LIP_RESET 0x6c
917#define MBC_SEND_SNS_COMMAND 0x6e
918
919#define MBC_LOGIN_FABRIC_PORT 0x6f
920#define MBC_SEND_CHANGE_REQUEST 0x70
921#define MBC_LOGOUT_FABRIC_PORT 0x71
922#define MBC_LIP_FULL_LOGIN 0x72
923#define MBC_LOGIN_LOOP_PORT 0x74
924#define MBC_PORT_NODE_NAME_LIST 0x75
925#define MBC_INITIALIZE_RECEIVE_QUEUE 0x77
926#define MBC_UNLOAD_IP 0x79
927#define MBC_GET_ID_LIST 0x7C
928#define MBC_SEND_LFA_COMMAND 0x7D
929#define MBC_LUN_RESET 0x7E
930
931
932
933
934
935#define MBC_MR_DRV_SHUTDOWN 0x6A
936
937
938
939
940#define MBC_SERDES_PARAMS 0x10
941#define MBC_GET_IOCB_STATUS 0x12
942#define MBC_PORT_PARAMS 0x1A
943#define MBC_GET_TIMEOUT_PARAMS 0x22
944#define MBC_TRACE_CONTROL 0x27
945#define MBC_GEN_SYSTEM_ERROR 0x2a
946#define MBC_WRITE_SFP 0x30
947#define MBC_READ_SFP 0x31
948#define MBC_SET_TIMEOUT_PARAMS 0x32
949#define MBC_MID_INITIALIZE_FIRMWARE 0x48
950#define MBC_MID_GET_VP_DATABASE 0x49
951#define MBC_MID_GET_VP_ENTRY 0x4a
952#define MBC_HOST_MEMORY_COPY 0x53
953#define MBC_SEND_RNFT_ELS 0x5e
954#define MBC_GET_LINK_PRIV_STATS 0x6d
955#define MBC_LINK_INITIALIZATION 0x72
956#define MBC_SET_VENDOR_ID 0x76
957#define MBC_PORT_RESET 0x120
958#define MBC_SET_PORT_CONFIG 0x122
959#define MBC_GET_PORT_CONFIG 0x123
960
961
962
963
964#define MBC_WRITE_MPI_REGISTER 0x01
965
966
967#define FCAL_MAP_SIZE 128
968
969
970#define MBX_31 BIT_31
971#define MBX_30 BIT_30
972#define MBX_29 BIT_29
973#define MBX_28 BIT_28
974#define MBX_27 BIT_27
975#define MBX_26 BIT_26
976#define MBX_25 BIT_25
977#define MBX_24 BIT_24
978#define MBX_23 BIT_23
979#define MBX_22 BIT_22
980#define MBX_21 BIT_21
981#define MBX_20 BIT_20
982#define MBX_19 BIT_19
983#define MBX_18 BIT_18
984#define MBX_17 BIT_17
985#define MBX_16 BIT_16
986#define MBX_15 BIT_15
987#define MBX_14 BIT_14
988#define MBX_13 BIT_13
989#define MBX_12 BIT_12
990#define MBX_11 BIT_11
991#define MBX_10 BIT_10
992#define MBX_9 BIT_9
993#define MBX_8 BIT_8
994#define MBX_7 BIT_7
995#define MBX_6 BIT_6
996#define MBX_5 BIT_5
997#define MBX_4 BIT_4
998#define MBX_3 BIT_3
999#define MBX_2 BIT_2
1000#define MBX_1 BIT_1
1001#define MBX_0 BIT_0
1002
1003#define RNID_TYPE_SET_VERSION 0x9
1004#define RNID_TYPE_ASIC_TEMP 0xC
1005
1006
1007
1008
1009#define FSTATE_CONFIG_WAIT 0
1010#define FSTATE_WAIT_AL_PA 1
1011#define FSTATE_WAIT_LOGIN 2
1012#define FSTATE_READY 3
1013#define FSTATE_LOSS_OF_SYNC 4
1014#define FSTATE_ERROR 5
1015#define FSTATE_REINIT 6
1016#define FSTATE_NON_PART 7
1017
1018#define FSTATE_CONFIG_CORRECT 0
1019#define FSTATE_P2P_RCV_LIP 1
1020#define FSTATE_P2P_CHOOSE_LOOP 2
1021#define FSTATE_P2P_RCV_UNIDEN_LIP 3
1022#define FSTATE_FATAL_ERROR 4
1023#define FSTATE_LOOP_BACK_CONN 5
1024
1025
1026
1027
1028
1029#define PORT_DATABASE_SIZE 128
1030typedef struct {
1031 uint8_t options;
1032 uint8_t control;
1033 uint8_t master_state;
1034 uint8_t slave_state;
1035 uint8_t reserved[2];
1036 uint8_t hard_address;
1037 uint8_t reserved_1;
1038 uint8_t port_id[4];
1039 uint8_t node_name[WWN_SIZE];
1040 uint8_t port_name[WWN_SIZE];
1041 uint16_t execution_throttle;
1042 uint16_t execution_count;
1043 uint8_t reset_count;
1044 uint8_t reserved_2;
1045 uint16_t resource_allocation;
1046 uint16_t current_allocation;
1047 uint16_t queue_head;
1048 uint16_t queue_tail;
1049 uint16_t transmit_execution_list_next;
1050 uint16_t transmit_execution_list_previous;
1051 uint16_t common_features;
1052 uint16_t total_concurrent_sequences;
1053 uint16_t RO_by_information_category;
1054 uint8_t recipient;
1055 uint8_t initiator;
1056 uint16_t receive_data_size;
1057 uint16_t concurrent_sequences;
1058 uint16_t open_sequences_per_exchange;
1059 uint16_t lun_abort_flags;
1060 uint16_t lun_stop_flags;
1061 uint16_t stop_queue_head;
1062 uint16_t stop_queue_tail;
1063 uint16_t port_retry_timer;
1064 uint16_t next_sequence_id;
1065 uint16_t frame_count;
1066 uint16_t PRLI_payload_length;
1067 uint8_t prli_svc_param_word_0[2];
1068
1069 uint8_t prli_svc_param_word_3[2];
1070
1071 uint16_t loop_id;
1072 uint16_t extended_lun_info_list_pointer;
1073 uint16_t extended_lun_stop_list_pointer;
1074} port_database_t;
1075
1076
1077
1078
1079#define PD_STATE_DISCOVERY 0
1080#define PD_STATE_WAIT_DISCOVERY_ACK 1
1081#define PD_STATE_PORT_LOGIN 2
1082#define PD_STATE_WAIT_PORT_LOGIN_ACK 3
1083#define PD_STATE_PROCESS_LOGIN 4
1084#define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
1085#define PD_STATE_PORT_LOGGED_IN 6
1086#define PD_STATE_PORT_UNAVAILABLE 7
1087#define PD_STATE_PROCESS_LOGOUT 8
1088#define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
1089#define PD_STATE_PORT_LOGOUT 10
1090#define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
1091
1092
1093#define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
1094#define QLA_ZIO_DISABLED 0
1095#define QLA_ZIO_DEFAULT_TIMER 2
1096
1097
1098
1099
1100
1101#define ICB_VERSION 1
1102typedef struct {
1103 uint8_t version;
1104 uint8_t reserved_1;
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125 uint8_t firmware_options[2];
1126
1127 uint16_t frame_payload_size;
1128 uint16_t max_iocb_allocation;
1129 uint16_t execution_throttle;
1130 uint8_t retry_count;
1131 uint8_t retry_delay;
1132 uint8_t port_name[WWN_SIZE];
1133 uint16_t hard_address;
1134 uint8_t inquiry_data;
1135 uint8_t login_timeout;
1136 uint8_t node_name[WWN_SIZE];
1137
1138 uint16_t request_q_outpointer;
1139 uint16_t response_q_inpointer;
1140 uint16_t request_q_length;
1141 uint16_t response_q_length;
1142 uint32_t request_q_address[2];
1143 uint32_t response_q_address[2];
1144
1145 uint16_t lun_enables;
1146 uint8_t command_resource_count;
1147 uint8_t immediate_notify_resource_count;
1148 uint16_t timeout;
1149 uint8_t reserved_2[2];
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170 uint8_t add_firmware_options[2];
1171
1172 uint8_t response_accumulation_timer;
1173 uint8_t interrupt_delay_timer;
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194 uint8_t special_options[2];
1195
1196 uint8_t reserved_3[26];
1197} init_cb_t;
1198
1199
1200struct init_cb_fx {
1201 uint16_t version;
1202 uint16_t reserved_1[13];
1203 __le16 request_q_outpointer;
1204 __le16 response_q_inpointer;
1205 uint16_t reserved_2[2];
1206 __le16 response_q_length;
1207 __le16 request_q_length;
1208 uint16_t reserved_3[2];
1209 __le32 request_q_address[2];
1210 __le32 response_q_address[2];
1211 uint16_t reserved_4[4];
1212 uint8_t response_q_msivec;
1213 uint8_t reserved_5[19];
1214 uint16_t interrupt_delay_timer;
1215 uint16_t reserved_6;
1216 uint32_t fwoptions1;
1217 uint32_t fwoptions2;
1218 uint32_t fwoptions3;
1219 uint8_t reserved_7[24];
1220};
1221
1222
1223
1224
1225
1226#define GLSO_SEND_RPS BIT_0
1227#define GLSO_USE_DID BIT_3
1228
1229struct link_statistics {
1230 uint32_t link_fail_cnt;
1231 uint32_t loss_sync_cnt;
1232 uint32_t loss_sig_cnt;
1233 uint32_t prim_seq_err_cnt;
1234 uint32_t inval_xmit_word_cnt;
1235 uint32_t inval_crc_cnt;
1236 uint32_t lip_cnt;
1237 uint32_t unused1[0x1a];
1238 uint32_t tx_frames;
1239 uint32_t rx_frames;
1240 uint32_t discarded_frames;
1241 uint32_t dropped_frames;
1242 uint32_t unused2[1];
1243 uint32_t nos_rcvd;
1244};
1245
1246
1247
1248
1249#define NV_START_BIT BIT_2
1250#define NV_WRITE_OP (BIT_26+BIT_24)
1251#define NV_READ_OP (BIT_26+BIT_25)
1252#define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
1253#define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
1254#define NV_DELAY_COUNT 10
1255
1256
1257
1258
1259typedef struct {
1260
1261
1262
1263 uint8_t id[4];
1264 uint8_t nvram_version;
1265 uint8_t reserved_0;
1266
1267
1268
1269
1270 uint8_t parameter_block_version;
1271 uint8_t reserved_1;
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292 uint8_t firmware_options[2];
1293
1294 uint16_t frame_payload_size;
1295 uint16_t max_iocb_allocation;
1296 uint16_t execution_throttle;
1297 uint8_t retry_count;
1298 uint8_t retry_delay;
1299 uint8_t port_name[WWN_SIZE];
1300 uint16_t hard_address;
1301 uint8_t inquiry_data;
1302 uint8_t login_timeout;
1303 uint8_t node_name[WWN_SIZE];
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324 uint8_t add_firmware_options[2];
1325
1326 uint8_t response_accumulation_timer;
1327 uint8_t interrupt_delay_timer;
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348 uint8_t special_options[2];
1349
1350
1351 uint8_t reserved_2[22];
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390 uint8_t seriallink_options[4];
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413 uint8_t host_p[2];
1414
1415 uint8_t boot_node_name[WWN_SIZE];
1416 uint8_t boot_lun_number;
1417 uint8_t reset_delay;
1418 uint8_t port_down_retry_count;
1419 uint8_t boot_id_number;
1420 uint16_t max_luns_per_target;
1421 uint8_t fcode_boot_port_name[WWN_SIZE];
1422 uint8_t alternate_port_name[WWN_SIZE];
1423 uint8_t alternate_node_name[WWN_SIZE];
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435 uint8_t efi_parameters;
1436
1437 uint8_t link_down_timeout;
1438
1439 uint8_t adapter_id[16];
1440
1441 uint8_t alt1_boot_node_name[WWN_SIZE];
1442 uint16_t alt1_boot_lun_number;
1443 uint8_t alt2_boot_node_name[WWN_SIZE];
1444 uint16_t alt2_boot_lun_number;
1445 uint8_t alt3_boot_node_name[WWN_SIZE];
1446 uint16_t alt3_boot_lun_number;
1447 uint8_t alt4_boot_node_name[WWN_SIZE];
1448 uint16_t alt4_boot_lun_number;
1449 uint8_t alt5_boot_node_name[WWN_SIZE];
1450 uint16_t alt5_boot_lun_number;
1451 uint8_t alt6_boot_node_name[WWN_SIZE];
1452 uint16_t alt6_boot_lun_number;
1453 uint8_t alt7_boot_node_name[WWN_SIZE];
1454 uint16_t alt7_boot_lun_number;
1455
1456 uint8_t reserved_3[2];
1457
1458
1459 uint8_t model_number[16];
1460
1461
1462 uint8_t oem_specific[16];
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485 uint8_t adapter_features[2];
1486
1487 uint8_t reserved_4[16];
1488
1489
1490 uint16_t subsystem_vendor_id_2200;
1491
1492
1493 uint16_t subsystem_device_id_2200;
1494
1495 uint8_t reserved_5;
1496 uint8_t checksum;
1497} nvram_t;
1498
1499
1500
1501
1502typedef struct {
1503 uint8_t entry_type;
1504 uint8_t entry_count;
1505 uint8_t sys_define;
1506 uint8_t entry_status;
1507 uint32_t handle;
1508 uint8_t data[52];
1509 uint32_t signature;
1510#define RESPONSE_PROCESSED 0xDEADDEAD
1511} response_t;
1512
1513
1514
1515
1516struct atio {
1517 uint8_t entry_type;
1518 uint8_t entry_count;
1519 uint8_t data[58];
1520 uint32_t signature;
1521#define ATIO_PROCESSED 0xDEADDEAD
1522};
1523
1524typedef union {
1525 uint16_t extended;
1526 struct {
1527 uint8_t reserved;
1528 uint8_t standard;
1529 } id;
1530} target_id_t;
1531
1532#define SET_TARGET_ID(ha, to, from) \
1533do { \
1534 if (HAS_EXTENDED_IDS(ha)) \
1535 to.extended = cpu_to_le16(from); \
1536 else \
1537 to.id.standard = (uint8_t)from; \
1538} while (0)
1539
1540
1541
1542
1543#define COMMAND_TYPE 0x11
1544typedef struct {
1545 uint8_t entry_type;
1546 uint8_t entry_count;
1547 uint8_t sys_define;
1548 uint8_t entry_status;
1549 uint32_t handle;
1550 target_id_t target;
1551 uint16_t lun;
1552 uint16_t control_flags;
1553#define CF_WRITE BIT_6
1554#define CF_READ BIT_5
1555#define CF_SIMPLE_TAG BIT_3
1556#define CF_ORDERED_TAG BIT_2
1557#define CF_HEAD_TAG BIT_1
1558 uint16_t reserved_1;
1559 uint16_t timeout;
1560 uint16_t dseg_count;
1561 uint8_t scsi_cdb[MAX_CMDSZ];
1562 uint32_t byte_count;
1563 uint32_t dseg_0_address;
1564 uint32_t dseg_0_length;
1565 uint32_t dseg_1_address;
1566 uint32_t dseg_1_length;
1567 uint32_t dseg_2_address;
1568 uint32_t dseg_2_length;
1569} cmd_entry_t;
1570
1571
1572
1573
1574#define COMMAND_A64_TYPE 0x19
1575typedef struct {
1576 uint8_t entry_type;
1577 uint8_t entry_count;
1578 uint8_t sys_define;
1579 uint8_t entry_status;
1580 uint32_t handle;
1581 target_id_t target;
1582 uint16_t lun;
1583 uint16_t control_flags;
1584 uint16_t reserved_1;
1585 uint16_t timeout;
1586 uint16_t dseg_count;
1587 uint8_t scsi_cdb[MAX_CMDSZ];
1588 uint32_t byte_count;
1589 uint32_t dseg_0_address[2];
1590 uint32_t dseg_0_length;
1591 uint32_t dseg_1_address[2];
1592 uint32_t dseg_1_length;
1593} cmd_a64_entry_t, request_t;
1594
1595
1596
1597
1598#define CONTINUE_TYPE 0x02
1599typedef struct {
1600 uint8_t entry_type;
1601 uint8_t entry_count;
1602 uint8_t sys_define;
1603 uint8_t entry_status;
1604 uint32_t reserved;
1605 uint32_t dseg_0_address;
1606 uint32_t dseg_0_length;
1607 uint32_t dseg_1_address;
1608 uint32_t dseg_1_length;
1609 uint32_t dseg_2_address;
1610 uint32_t dseg_2_length;
1611 uint32_t dseg_3_address;
1612 uint32_t dseg_3_length;
1613 uint32_t dseg_4_address;
1614 uint32_t dseg_4_length;
1615 uint32_t dseg_5_address;
1616 uint32_t dseg_5_length;
1617 uint32_t dseg_6_address;
1618 uint32_t dseg_6_length;
1619} cont_entry_t;
1620
1621
1622
1623
1624#define CONTINUE_A64_TYPE 0x0A
1625typedef struct {
1626 uint8_t entry_type;
1627 uint8_t entry_count;
1628 uint8_t sys_define;
1629 uint8_t entry_status;
1630 uint32_t dseg_0_address[2];
1631 uint32_t dseg_0_length;
1632 uint32_t dseg_1_address[2];
1633 uint32_t dseg_1_length;
1634 uint32_t dseg_2_address [2];
1635 uint32_t dseg_2_length;
1636 uint32_t dseg_3_address[2];
1637 uint32_t dseg_3_length;
1638 uint32_t dseg_4_address[2];
1639 uint32_t dseg_4_length;
1640} cont_a64_entry_t;
1641
1642#define PO_MODE_DIF_INSERT 0
1643#define PO_MODE_DIF_REMOVE 1
1644#define PO_MODE_DIF_PASS 2
1645#define PO_MODE_DIF_REPLACE 3
1646#define PO_MODE_DIF_TCP_CKSUM 6
1647#define PO_ENABLE_DIF_BUNDLING BIT_8
1648#define PO_ENABLE_INCR_GUARD_SEED BIT_3
1649#define PO_DISABLE_INCR_REF_TAG BIT_5
1650#define PO_DISABLE_GUARD_CHECK BIT_4
1651
1652
1653
1654struct crc_context {
1655 uint32_t handle;
1656 uint32_t ref_tag;
1657 uint16_t app_tag;
1658 uint8_t ref_tag_mask[4];
1659 uint8_t app_tag_mask[2];
1660 uint16_t guard_seed;
1661 uint16_t prot_opts;
1662 uint16_t blk_size;
1663 uint16_t runt_blk_guard;
1664
1665 uint32_t byte_count;
1666
1667 union {
1668 struct {
1669 uint32_t reserved_1;
1670 uint16_t reserved_2;
1671 uint16_t reserved_3;
1672 uint32_t reserved_4;
1673 uint32_t data_address[2];
1674 uint32_t data_length;
1675 uint32_t reserved_5[2];
1676 uint32_t reserved_6;
1677 } nobundling;
1678 struct {
1679 uint32_t dif_byte_count;
1680
1681 uint16_t reserved_1;
1682 uint16_t dseg_count;
1683 uint32_t reserved_2;
1684 uint32_t data_address[2];
1685 uint32_t data_length;
1686 uint32_t dif_address[2];
1687 uint32_t dif_length;
1688
1689 } bundling;
1690 } u;
1691
1692 struct fcp_cmnd fcp_cmnd;
1693 dma_addr_t crc_ctx_dma;
1694
1695 struct list_head dsd_list;
1696
1697
1698};
1699
1700#define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
1701#define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
1702
1703
1704
1705
1706#define STATUS_TYPE 0x03
1707typedef struct {
1708 uint8_t entry_type;
1709 uint8_t entry_count;
1710 uint8_t sys_define;
1711 uint8_t entry_status;
1712 uint32_t handle;
1713 uint16_t scsi_status;
1714 uint16_t comp_status;
1715 uint16_t state_flags;
1716 uint16_t status_flags;
1717 uint16_t rsp_info_len;
1718 uint16_t req_sense_length;
1719 uint32_t residual_length;
1720 uint8_t rsp_info[8];
1721 uint8_t req_sense_data[32];
1722} sts_entry_t;
1723
1724
1725
1726
1727#define RF_RQ_DMA_ERROR BIT_6
1728#define RF_INV_E_ORDER BIT_5
1729#define RF_INV_E_COUNT BIT_4
1730#define RF_INV_E_PARAM BIT_3
1731#define RF_INV_E_TYPE BIT_2
1732#define RF_BUSY BIT_1
1733#define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1734 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1735#define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1736 RF_INV_E_TYPE)
1737
1738
1739
1740
1741#define SS_MASK 0xfff
1742#define SS_RESIDUAL_UNDER BIT_11
1743#define SS_RESIDUAL_OVER BIT_10
1744#define SS_SENSE_LEN_VALID BIT_9
1745#define SS_RESPONSE_INFO_LEN_VALID BIT_8
1746
1747#define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1748#define SS_BUSY_CONDITION BIT_3
1749#define SS_CONDITION_MET BIT_2
1750#define SS_CHECK_CONDITION BIT_1
1751
1752
1753
1754
1755#define CS_COMPLETE 0x0
1756#define CS_INCOMPLETE 0x1
1757#define CS_DMA 0x2
1758#define CS_TRANSPORT 0x3
1759#define CS_RESET 0x4
1760#define CS_ABORTED 0x5
1761#define CS_TIMEOUT 0x6
1762#define CS_DATA_OVERRUN 0x7
1763#define CS_DIF_ERROR 0xC
1764
1765#define CS_DATA_UNDERRUN 0x15
1766#define CS_QUEUE_FULL 0x1C
1767#define CS_PORT_UNAVAILABLE 0x28
1768
1769#define CS_PORT_LOGGED_OUT 0x29
1770#define CS_PORT_CONFIG_CHG 0x2A
1771#define CS_PORT_BUSY 0x2B
1772#define CS_COMPLETE_CHKCOND 0x30
1773#define CS_BAD_PAYLOAD 0x80
1774#define CS_UNKNOWN 0x81
1775#define CS_RETRY 0x82
1776#define CS_LOOP_DOWN_ABORT 0x83
1777
1778#define CS_BIDIR_RD_OVERRUN 0x700
1779#define CS_BIDIR_RD_WR_OVERRUN 0x707
1780#define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715
1781#define CS_BIDIR_RD_UNDERRUN 0x1500
1782#define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507
1783#define CS_BIDIR_RD_WR_UNDERRUN 0x1515
1784#define CS_BIDIR_DMA 0x200
1785
1786
1787
1788#define SF_ABTS_TERMINATED BIT_10
1789#define SF_LOGOUT_SENT BIT_13
1790
1791
1792
1793
1794#define STATUS_CONT_TYPE 0x10
1795typedef struct {
1796 uint8_t entry_type;
1797 uint8_t entry_count;
1798 uint8_t sys_define;
1799 uint8_t entry_status;
1800 uint8_t data[60];
1801} sts_cont_entry_t;
1802
1803
1804
1805
1806
1807#define STATUS_TYPE_21 0x21
1808typedef struct {
1809 uint8_t entry_type;
1810 uint8_t entry_count;
1811 uint8_t handle_count;
1812 uint8_t entry_status;
1813 uint32_t handle[15];
1814} sts21_entry_t;
1815
1816
1817
1818
1819
1820#define STATUS_TYPE_22 0x22
1821typedef struct {
1822 uint8_t entry_type;
1823 uint8_t entry_count;
1824 uint8_t handle_count;
1825 uint8_t entry_status;
1826 uint16_t handle[30];
1827} sts22_entry_t;
1828
1829
1830
1831
1832#define MARKER_TYPE 0x04
1833typedef struct {
1834 uint8_t entry_type;
1835 uint8_t entry_count;
1836 uint8_t handle_count;
1837 uint8_t entry_status;
1838 uint32_t sys_define_2;
1839 target_id_t target;
1840 uint8_t modifier;
1841#define MK_SYNC_ID_LUN 0
1842#define MK_SYNC_ID 1
1843#define MK_SYNC_ALL 2
1844#define MK_SYNC_LIP 3
1845
1846
1847 uint8_t reserved_1;
1848 uint16_t sequence_number;
1849 uint16_t lun;
1850 uint8_t reserved_2[48];
1851} mrk_entry_t;
1852
1853
1854
1855
1856#define MS_IOCB_TYPE 0x29
1857typedef struct {
1858 uint8_t entry_type;
1859 uint8_t entry_count;
1860 uint8_t handle_count;
1861 uint8_t entry_status;
1862 uint32_t handle1;
1863 target_id_t loop_id;
1864 uint16_t status;
1865 uint16_t control_flags;
1866 uint16_t reserved2;
1867 uint16_t timeout;
1868 uint16_t cmd_dsd_count;
1869 uint16_t total_dsd_count;
1870 uint8_t type;
1871 uint8_t r_ctl;
1872 uint16_t rx_id;
1873 uint16_t reserved3;
1874 uint32_t handle2;
1875 uint32_t rsp_bytecount;
1876 uint32_t req_bytecount;
1877 uint32_t dseg_req_address[2];
1878 uint32_t dseg_req_length;
1879 uint32_t dseg_rsp_address[2];
1880 uint32_t dseg_rsp_length;
1881} ms_iocb_entry_t;
1882
1883
1884
1885
1886
1887#define MBX_IOCB_TYPE 0x39
1888struct mbx_entry {
1889 uint8_t entry_type;
1890 uint8_t entry_count;
1891 uint8_t sys_define1;
1892
1893#define SOURCE_SCSI 0x00
1894#define SOURCE_IP 0x01
1895#define SOURCE_VI 0x02
1896#define SOURCE_SCTP 0x03
1897#define SOURCE_MP 0x04
1898#define SOURCE_MPIOCTL 0x05
1899#define SOURCE_ASYNC_IOCB 0x07
1900
1901 uint8_t entry_status;
1902
1903 uint32_t handle;
1904 target_id_t loop_id;
1905
1906 uint16_t status;
1907 uint16_t state_flags;
1908 uint16_t status_flags;
1909
1910 uint32_t sys_define2[2];
1911
1912 uint16_t mb0;
1913 uint16_t mb1;
1914 uint16_t mb2;
1915 uint16_t mb3;
1916 uint16_t mb6;
1917 uint16_t mb7;
1918 uint16_t mb9;
1919 uint16_t mb10;
1920 uint32_t reserved_2[2];
1921 uint8_t node_name[WWN_SIZE];
1922 uint8_t port_name[WWN_SIZE];
1923};
1924
1925
1926
1927
1928#define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1929#define REQUEST_ENTRY_SIZE (sizeof(request_t))
1930
1931
1932
1933
1934
1935typedef union {
1936 uint32_t b24 : 24;
1937
1938 struct {
1939#ifdef __BIG_ENDIAN
1940 uint8_t domain;
1941 uint8_t area;
1942 uint8_t al_pa;
1943#elif defined(__LITTLE_ENDIAN)
1944 uint8_t al_pa;
1945 uint8_t area;
1946 uint8_t domain;
1947#else
1948#error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
1949#endif
1950 uint8_t rsvd_1;
1951 } b;
1952} port_id_t;
1953#define INVALID_PORT_ID 0xFFFFFF
1954
1955
1956
1957
1958typedef struct {
1959 port_id_t d_id;
1960 uint8_t node_name[WWN_SIZE];
1961 uint8_t port_name[WWN_SIZE];
1962 uint8_t fabric_port_name[WWN_SIZE];
1963 uint16_t fp_speed;
1964 uint8_t fc4_type;
1965} sw_info_t;
1966
1967
1968#define FC4_TYPE_FCP_SCSI 0x08
1969#define FC4_TYPE_OTHER 0x0
1970#define FC4_TYPE_UNKNOWN 0xff
1971
1972
1973
1974
1975 typedef enum {
1976 FCT_UNKNOWN,
1977 FCT_RSCN,
1978 FCT_SWITCH,
1979 FCT_BROADCAST,
1980 FCT_INITIATOR,
1981 FCT_TARGET
1982} fc_port_type_t;
1983
1984
1985
1986
1987typedef struct fc_port {
1988 struct list_head list;
1989 struct scsi_qla_host *vha;
1990
1991 uint8_t node_name[WWN_SIZE];
1992 uint8_t port_name[WWN_SIZE];
1993 port_id_t d_id;
1994 uint16_t loop_id;
1995 uint16_t old_loop_id;
1996
1997 uint16_t tgt_id;
1998 uint16_t old_tgt_id;
1999
2000 uint8_t fcp_prio;
2001
2002 uint8_t fabric_port_name[WWN_SIZE];
2003 uint16_t fp_speed;
2004
2005 fc_port_type_t port_type;
2006
2007 atomic_t state;
2008 uint32_t flags;
2009
2010 int login_retry;
2011
2012 struct fc_rport *rport, *drport;
2013 u32 supported_classes;
2014
2015 uint8_t fc4_type;
2016 uint8_t scan_state;
2017
2018 unsigned long last_queue_full;
2019 unsigned long last_ramp_up;
2020
2021 uint16_t port_id;
2022} fc_port_t;
2023
2024#include "qla_mr.h"
2025
2026
2027
2028
2029#define FCS_UNCONFIGURED 1
2030#define FCS_DEVICE_DEAD 2
2031#define FCS_DEVICE_LOST 3
2032#define FCS_ONLINE 4
2033
2034static const char * const port_state_str[] = {
2035 "Unknown",
2036 "UNCONFIGURED",
2037 "DEAD",
2038 "LOST",
2039 "ONLINE"
2040};
2041
2042
2043
2044
2045#define FCF_FABRIC_DEVICE BIT_0
2046#define FCF_LOGIN_NEEDED BIT_1
2047#define FCF_FCP2_DEVICE BIT_2
2048#define FCF_ASYNC_SENT BIT_3
2049#define FCF_CONF_COMP_SUPPORTED BIT_4
2050
2051
2052#define FC_NO_LOOP_ID 0x1000
2053
2054
2055
2056
2057
2058
2059
2060#define CT_REJECT_RESPONSE 0x8001
2061#define CT_ACCEPT_RESPONSE 0x8002
2062#define CT_REASON_INVALID_COMMAND_CODE 0x01
2063#define CT_REASON_CANNOT_PERFORM 0x09
2064#define CT_REASON_COMMAND_UNSUPPORTED 0x0b
2065#define CT_EXPL_ALREADY_REGISTERED 0x10
2066
2067#define NS_N_PORT_TYPE 0x01
2068#define NS_NL_PORT_TYPE 0x02
2069#define NS_NX_PORT_TYPE 0x7F
2070
2071#define GA_NXT_CMD 0x100
2072#define GA_NXT_REQ_SIZE (16 + 4)
2073#define GA_NXT_RSP_SIZE (16 + 620)
2074
2075#define GID_PT_CMD 0x1A1
2076#define GID_PT_REQ_SIZE (16 + 4)
2077
2078#define GPN_ID_CMD 0x112
2079#define GPN_ID_REQ_SIZE (16 + 4)
2080#define GPN_ID_RSP_SIZE (16 + 8)
2081
2082#define GNN_ID_CMD 0x113
2083#define GNN_ID_REQ_SIZE (16 + 4)
2084#define GNN_ID_RSP_SIZE (16 + 8)
2085
2086#define GFT_ID_CMD 0x117
2087#define GFT_ID_REQ_SIZE (16 + 4)
2088#define GFT_ID_RSP_SIZE (16 + 32)
2089
2090#define RFT_ID_CMD 0x217
2091#define RFT_ID_REQ_SIZE (16 + 4 + 32)
2092#define RFT_ID_RSP_SIZE 16
2093
2094#define RFF_ID_CMD 0x21F
2095#define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
2096#define RFF_ID_RSP_SIZE 16
2097
2098#define RNN_ID_CMD 0x213
2099#define RNN_ID_REQ_SIZE (16 + 4 + 8)
2100#define RNN_ID_RSP_SIZE 16
2101
2102#define RSNN_NN_CMD 0x239
2103#define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
2104#define RSNN_NN_RSP_SIZE 16
2105
2106#define GFPN_ID_CMD 0x11C
2107#define GFPN_ID_REQ_SIZE (16 + 4)
2108#define GFPN_ID_RSP_SIZE (16 + 8)
2109
2110#define GPSC_CMD 0x127
2111#define GPSC_REQ_SIZE (16 + 8)
2112#define GPSC_RSP_SIZE (16 + 2 + 2)
2113
2114#define GFF_ID_CMD 0x011F
2115#define GFF_ID_REQ_SIZE (16 + 4)
2116#define GFF_ID_RSP_SIZE (16 + 128)
2117
2118
2119
2120
2121#define FDMI_HBA_ATTR_COUNT 9
2122#define FDMI_HBA_NODE_NAME 1
2123#define FDMI_HBA_MANUFACTURER 2
2124#define FDMI_HBA_SERIAL_NUMBER 3
2125#define FDMI_HBA_MODEL 4
2126#define FDMI_HBA_MODEL_DESCRIPTION 5
2127#define FDMI_HBA_HARDWARE_VERSION 6
2128#define FDMI_HBA_DRIVER_VERSION 7
2129#define FDMI_HBA_OPTION_ROM_VERSION 8
2130#define FDMI_HBA_FIRMWARE_VERSION 9
2131#define FDMI_HBA_OS_NAME_AND_VERSION 0xa
2132#define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
2133
2134struct ct_fdmi_hba_attr {
2135 uint16_t type;
2136 uint16_t len;
2137 union {
2138 uint8_t node_name[WWN_SIZE];
2139 uint8_t manufacturer[32];
2140 uint8_t serial_num[8];
2141 uint8_t model[16];
2142 uint8_t model_desc[80];
2143 uint8_t hw_version[16];
2144 uint8_t driver_version[32];
2145 uint8_t orom_version[16];
2146 uint8_t fw_version[16];
2147 uint8_t os_version[128];
2148 uint8_t max_ct_len[4];
2149 } a;
2150};
2151
2152struct ct_fdmi_hba_attributes {
2153 uint32_t count;
2154 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
2155};
2156
2157
2158
2159
2160#define FDMI_PORT_ATTR_COUNT 6
2161#define FDMI_PORT_FC4_TYPES 1
2162#define FDMI_PORT_SUPPORT_SPEED 2
2163#define FDMI_PORT_CURRENT_SPEED 3
2164#define FDMI_PORT_MAX_FRAME_SIZE 4
2165#define FDMI_PORT_OS_DEVICE_NAME 5
2166#define FDMI_PORT_HOST_NAME 6
2167
2168#define FDMI_PORT_SPEED_1GB 0x1
2169#define FDMI_PORT_SPEED_2GB 0x2
2170#define FDMI_PORT_SPEED_10GB 0x4
2171#define FDMI_PORT_SPEED_4GB 0x8
2172#define FDMI_PORT_SPEED_8GB 0x10
2173#define FDMI_PORT_SPEED_16GB 0x20
2174#define FDMI_PORT_SPEED_UNKNOWN 0x8000
2175
2176struct ct_fdmi_port_attr {
2177 uint16_t type;
2178 uint16_t len;
2179 union {
2180 uint8_t fc4_types[32];
2181 uint32_t sup_speed;
2182 uint32_t cur_speed;
2183 uint32_t max_frame_size;
2184 uint8_t os_dev_name[32];
2185 uint8_t host_name[32];
2186 } a;
2187};
2188
2189
2190
2191
2192struct ct_fdmi_port_attributes {
2193 uint32_t count;
2194 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
2195};
2196
2197
2198#define GRHL_CMD 0x100
2199#define GHAT_CMD 0x101
2200#define GRPL_CMD 0x102
2201#define GPAT_CMD 0x110
2202
2203#define RHBA_CMD 0x200
2204#define RHBA_RSP_SIZE 16
2205
2206#define RHAT_CMD 0x201
2207#define RPRT_CMD 0x210
2208
2209#define RPA_CMD 0x211
2210#define RPA_RSP_SIZE 16
2211
2212#define DHBA_CMD 0x300
2213#define DHBA_REQ_SIZE (16 + 8)
2214#define DHBA_RSP_SIZE 16
2215
2216#define DHAT_CMD 0x301
2217#define DPRT_CMD 0x310
2218#define DPA_CMD 0x311
2219
2220
2221struct ct_cmd_hdr {
2222 uint8_t revision;
2223 uint8_t in_id[3];
2224 uint8_t gs_type;
2225 uint8_t gs_subtype;
2226 uint8_t options;
2227 uint8_t reserved;
2228};
2229
2230
2231struct ct_sns_req {
2232 struct ct_cmd_hdr header;
2233 uint16_t command;
2234 uint16_t max_rsp_size;
2235 uint8_t fragment_id;
2236 uint8_t reserved[3];
2237
2238 union {
2239
2240 struct {
2241 uint8_t reserved;
2242 uint8_t port_id[3];
2243 } port_id;
2244
2245 struct {
2246 uint8_t port_type;
2247 uint8_t domain;
2248 uint8_t area;
2249 uint8_t reserved;
2250 } gid_pt;
2251
2252 struct {
2253 uint8_t reserved;
2254 uint8_t port_id[3];
2255 uint8_t fc4_types[32];
2256 } rft_id;
2257
2258 struct {
2259 uint8_t reserved;
2260 uint8_t port_id[3];
2261 uint16_t reserved2;
2262 uint8_t fc4_feature;
2263 uint8_t fc4_type;
2264 } rff_id;
2265
2266 struct {
2267 uint8_t reserved;
2268 uint8_t port_id[3];
2269 uint8_t node_name[8];
2270 } rnn_id;
2271
2272 struct {
2273 uint8_t node_name[8];
2274 uint8_t name_len;
2275 uint8_t sym_node_name[255];
2276 } rsnn_nn;
2277
2278 struct {
2279 uint8_t hba_indentifier[8];
2280 } ghat;
2281
2282 struct {
2283 uint8_t hba_identifier[8];
2284 uint32_t entry_count;
2285 uint8_t port_name[8];
2286 struct ct_fdmi_hba_attributes attrs;
2287 } rhba;
2288
2289 struct {
2290 uint8_t hba_identifier[8];
2291 struct ct_fdmi_hba_attributes attrs;
2292 } rhat;
2293
2294 struct {
2295 uint8_t port_name[8];
2296 struct ct_fdmi_port_attributes attrs;
2297 } rpa;
2298
2299 struct {
2300 uint8_t port_name[8];
2301 } dhba;
2302
2303 struct {
2304 uint8_t port_name[8];
2305 } dhat;
2306
2307 struct {
2308 uint8_t port_name[8];
2309 } dprt;
2310
2311 struct {
2312 uint8_t port_name[8];
2313 } dpa;
2314
2315 struct {
2316 uint8_t port_name[8];
2317 } gpsc;
2318
2319 struct {
2320 uint8_t reserved;
2321 uint8_t port_name[3];
2322 } gff_id;
2323 } req;
2324};
2325
2326
2327struct ct_rsp_hdr {
2328 struct ct_cmd_hdr header;
2329 uint16_t response;
2330 uint16_t residual;
2331 uint8_t fragment_id;
2332 uint8_t reason_code;
2333 uint8_t explanation_code;
2334 uint8_t vendor_unique;
2335};
2336
2337struct ct_sns_gid_pt_data {
2338 uint8_t control_byte;
2339 uint8_t port_id[3];
2340};
2341
2342struct ct_sns_rsp {
2343 struct ct_rsp_hdr header;
2344
2345 union {
2346 struct {
2347 uint8_t port_type;
2348 uint8_t port_id[3];
2349 uint8_t port_name[8];
2350 uint8_t sym_port_name_len;
2351 uint8_t sym_port_name[255];
2352 uint8_t node_name[8];
2353 uint8_t sym_node_name_len;
2354 uint8_t sym_node_name[255];
2355 uint8_t init_proc_assoc[8];
2356 uint8_t node_ip_addr[16];
2357 uint8_t class_of_service[4];
2358 uint8_t fc4_types[32];
2359 uint8_t ip_address[16];
2360 uint8_t fabric_port_name[8];
2361 uint8_t reserved;
2362 uint8_t hard_address[3];
2363 } ga_nxt;
2364
2365 struct {
2366
2367 struct ct_sns_gid_pt_data
2368 entries[MAX_FIBRE_DEVICES_MAX];
2369 } gid_pt;
2370
2371 struct {
2372 uint8_t port_name[8];
2373 } gpn_id;
2374
2375 struct {
2376 uint8_t node_name[8];
2377 } gnn_id;
2378
2379 struct {
2380 uint8_t fc4_types[32];
2381 } gft_id;
2382
2383 struct {
2384 uint32_t entry_count;
2385 uint8_t port_name[8];
2386 struct ct_fdmi_hba_attributes attrs;
2387 } ghat;
2388
2389 struct {
2390 uint8_t port_name[8];
2391 } gfpn_id;
2392
2393 struct {
2394 uint16_t speeds;
2395 uint16_t speed;
2396 } gpsc;
2397
2398#define GFF_FCP_SCSI_OFFSET 7
2399 struct {
2400 uint8_t fc4_features[128];
2401 } gff_id;
2402 } rsp;
2403};
2404
2405struct ct_sns_pkt {
2406 union {
2407 struct ct_sns_req req;
2408 struct ct_sns_rsp rsp;
2409 } p;
2410};
2411
2412
2413
2414
2415#define RFT_ID_SNS_SCMD_LEN 22
2416#define RFT_ID_SNS_CMD_SIZE 60
2417#define RFT_ID_SNS_DATA_SIZE 16
2418
2419#define RNN_ID_SNS_SCMD_LEN 10
2420#define RNN_ID_SNS_CMD_SIZE 36
2421#define RNN_ID_SNS_DATA_SIZE 16
2422
2423#define GA_NXT_SNS_SCMD_LEN 6
2424#define GA_NXT_SNS_CMD_SIZE 28
2425#define GA_NXT_SNS_DATA_SIZE (620 + 16)
2426
2427#define GID_PT_SNS_SCMD_LEN 6
2428#define GID_PT_SNS_CMD_SIZE 28
2429
2430
2431
2432
2433#define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16)
2434
2435#define GPN_ID_SNS_SCMD_LEN 6
2436#define GPN_ID_SNS_CMD_SIZE 28
2437#define GPN_ID_SNS_DATA_SIZE (8 + 16)
2438
2439#define GNN_ID_SNS_SCMD_LEN 6
2440#define GNN_ID_SNS_CMD_SIZE 28
2441#define GNN_ID_SNS_DATA_SIZE (8 + 16)
2442
2443struct sns_cmd_pkt {
2444 union {
2445 struct {
2446 uint16_t buffer_length;
2447 uint16_t reserved_1;
2448 uint32_t buffer_address[2];
2449 uint16_t subcommand_length;
2450 uint16_t reserved_2;
2451 uint16_t subcommand;
2452 uint16_t size;
2453 uint32_t reserved_3;
2454 uint8_t param[36];
2455 } cmd;
2456
2457 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
2458 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
2459 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
2460 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
2461 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
2462 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
2463 } p;
2464};
2465
2466struct fw_blob {
2467 char *name;
2468 uint32_t segs[4];
2469 const struct firmware *fw;
2470};
2471
2472
2473struct gid_list_info {
2474 uint8_t al_pa;
2475 uint8_t area;
2476 uint8_t domain;
2477 uint8_t loop_id_2100;
2478 uint16_t loop_id;
2479 uint16_t reserved_1;
2480};
2481
2482
2483typedef struct vport_info {
2484 uint8_t port_name[WWN_SIZE];
2485 uint8_t node_name[WWN_SIZE];
2486 int vp_id;
2487 uint16_t loop_id;
2488 unsigned long host_no;
2489 uint8_t port_id[3];
2490 int loop_state;
2491} vport_info_t;
2492
2493typedef struct vport_params {
2494 uint8_t port_name[WWN_SIZE];
2495 uint8_t node_name[WWN_SIZE];
2496 uint32_t options;
2497#define VP_OPTS_RETRY_ENABLE BIT_0
2498#define VP_OPTS_VP_DISABLE BIT_1
2499} vport_params_t;
2500
2501
2502#define VP_RET_CODE_OK 0
2503#define VP_RET_CODE_FATAL 1
2504#define VP_RET_CODE_WRONG_ID 2
2505#define VP_RET_CODE_WWPN 3
2506#define VP_RET_CODE_RESOURCES 4
2507#define VP_RET_CODE_NO_MEM 5
2508#define VP_RET_CODE_NOT_FOUND 6
2509
2510struct qla_hw_data;
2511struct rsp_que;
2512
2513
2514
2515struct isp_operations {
2516
2517 int (*pci_config) (struct scsi_qla_host *);
2518 void (*reset_chip) (struct scsi_qla_host *);
2519 int (*chip_diag) (struct scsi_qla_host *);
2520 void (*config_rings) (struct scsi_qla_host *);
2521 void (*reset_adapter) (struct scsi_qla_host *);
2522 int (*nvram_config) (struct scsi_qla_host *);
2523 void (*update_fw_options) (struct scsi_qla_host *);
2524 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2525
2526 char * (*pci_info_str) (struct scsi_qla_host *, char *);
2527 char * (*fw_version_str) (struct scsi_qla_host *, char *);
2528
2529 irq_handler_t intr_handler;
2530 void (*enable_intrs) (struct qla_hw_data *);
2531 void (*disable_intrs) (struct qla_hw_data *);
2532
2533 int (*abort_command) (srb_t *);
2534 int (*target_reset) (struct fc_port *, unsigned int, int);
2535 int (*lun_reset) (struct fc_port *, unsigned int, int);
2536 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2537 uint8_t, uint8_t, uint16_t *, uint8_t);
2538 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2539 uint8_t, uint8_t);
2540
2541 uint16_t (*calc_req_entries) (uint16_t);
2542 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
2543 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
2544 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2545 uint32_t);
2546
2547 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
2548 uint32_t, uint32_t);
2549 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2550 uint32_t);
2551
2552 void (*fw_dump) (struct scsi_qla_host *, int);
2553
2554 int (*beacon_on) (struct scsi_qla_host *);
2555 int (*beacon_off) (struct scsi_qla_host *);
2556 void (*beacon_blink) (struct scsi_qla_host *);
2557
2558 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
2559 uint32_t, uint32_t);
2560 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
2561 uint32_t);
2562
2563 int (*get_flash_version) (struct scsi_qla_host *, void *);
2564 int (*start_scsi) (srb_t *);
2565 int (*abort_isp) (struct scsi_qla_host *);
2566 int (*iospace_config)(struct qla_hw_data*);
2567 int (*initialize_adapter)(struct scsi_qla_host *);
2568};
2569
2570
2571
2572#define QLA_MSIX_CHIP_REV_24XX 3
2573#define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
2574#define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
2575
2576#define QLA_MSIX_DEFAULT 0x00
2577#define QLA_MSIX_RSP_Q 0x01
2578
2579#define QLA_MIDX_DEFAULT 0
2580#define QLA_MIDX_RSP_Q 1
2581#define QLA_PCI_MSIX_CONTROL 0xa2
2582#define QLA_83XX_PCI_MSIX_CONTROL 0x92
2583
2584struct scsi_qla_host;
2585
2586struct qla_msix_entry {
2587 int have_irq;
2588 uint32_t vector;
2589 uint16_t entry;
2590 struct rsp_que *rsp;
2591};
2592
2593#define WATCH_INTERVAL 1
2594
2595
2596enum qla_work_type {
2597 QLA_EVT_AEN,
2598 QLA_EVT_IDC_ACK,
2599 QLA_EVT_ASYNC_LOGIN,
2600 QLA_EVT_ASYNC_LOGIN_DONE,
2601 QLA_EVT_ASYNC_LOGOUT,
2602 QLA_EVT_ASYNC_LOGOUT_DONE,
2603 QLA_EVT_ASYNC_ADISC,
2604 QLA_EVT_ASYNC_ADISC_DONE,
2605 QLA_EVT_UEVENT,
2606 QLA_EVT_AENFX,
2607};
2608
2609
2610struct qla_work_evt {
2611 struct list_head list;
2612 enum qla_work_type type;
2613 u32 flags;
2614#define QLA_EVT_FLAG_FREE 0x1
2615
2616 union {
2617 struct {
2618 enum fc_host_event_code code;
2619 u32 data;
2620 } aen;
2621 struct {
2622#define QLA_IDC_ACK_REGS 7
2623 uint16_t mb[QLA_IDC_ACK_REGS];
2624 } idc_ack;
2625 struct {
2626 struct fc_port *fcport;
2627#define QLA_LOGIO_LOGIN_RETRIED BIT_0
2628 u16 data[2];
2629 } logio;
2630 struct {
2631 u32 code;
2632#define QLA_UEVENT_CODE_FW_DUMP 0
2633 } uevent;
2634 struct {
2635 uint32_t evtcode;
2636 uint32_t mbx[8];
2637 uint32_t count;
2638 } aenfx;
2639 struct {
2640 srb_t *sp;
2641 } iosb;
2642 } u;
2643};
2644
2645struct qla_chip_state_84xx {
2646 struct list_head list;
2647 struct kref kref;
2648
2649 void *bus;
2650 spinlock_t access_lock;
2651 struct mutex fw_update_mutex;
2652 uint32_t fw_update;
2653 uint32_t op_fw_version;
2654 uint32_t op_fw_size;
2655 uint32_t op_fw_seq_size;
2656 uint32_t diag_fw_version;
2657 uint32_t gold_fw_version;
2658};
2659
2660struct qla_statistics {
2661 uint32_t total_isp_aborts;
2662 uint64_t input_bytes;
2663 uint64_t output_bytes;
2664 uint64_t input_requests;
2665 uint64_t output_requests;
2666 uint32_t control_requests;
2667
2668 uint64_t jiffies_at_last_reset;
2669};
2670
2671struct bidi_statistics {
2672 unsigned long long io_count;
2673 unsigned long long transfer_bytes;
2674};
2675
2676
2677#define MBC_INITIALIZE_MULTIQ 0x1f
2678#define QLA_QUE_PAGE 0X1000
2679#define QLA_MQ_SIZE 32
2680#define QLA_MAX_QUEUES 256
2681#define ISP_QUE_REG(ha, id) \
2682 ((ha->mqenable || IS_QLA83XX(ha)) ? \
2683 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\
2684 ((void __iomem *)ha->iobase))
2685#define QLA_REQ_QUE_ID(tag) \
2686 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
2687#define QLA_DEFAULT_QUE_QOS 5
2688#define QLA_PRECONFIG_VPORTS 32
2689#define QLA_MAX_VPORTS_QLA24XX 128
2690#define QLA_MAX_VPORTS_QLA25XX 256
2691
2692struct rsp_que {
2693 dma_addr_t dma;
2694 response_t *ring;
2695 response_t *ring_ptr;
2696 uint32_t __iomem *rsp_q_in;
2697 uint32_t __iomem *rsp_q_out;
2698 uint16_t ring_index;
2699 uint16_t out_ptr;
2700 uint16_t length;
2701 uint16_t options;
2702 uint16_t rid;
2703 uint16_t id;
2704 uint16_t vp_idx;
2705 struct qla_hw_data *hw;
2706 struct qla_msix_entry *msix;
2707 struct req_que *req;
2708 srb_t *status_srb;
2709 struct work_struct q_work;
2710
2711 dma_addr_t dma_fx00;
2712 response_t *ring_fx00;
2713 uint16_t length_fx00;
2714 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE];
2715};
2716
2717
2718struct req_que {
2719 dma_addr_t dma;
2720 request_t *ring;
2721 request_t *ring_ptr;
2722 uint32_t __iomem *req_q_in;
2723 uint32_t __iomem *req_q_out;
2724 uint16_t ring_index;
2725 uint16_t in_ptr;
2726 uint16_t cnt;
2727 uint16_t length;
2728 uint16_t options;
2729 uint16_t rid;
2730 uint16_t id;
2731 uint16_t qos;
2732 uint16_t vp_idx;
2733 struct rsp_que *rsp;
2734 srb_t **outstanding_cmds;
2735 uint32_t current_outstanding_cmd;
2736 uint16_t num_outstanding_cmds;
2737#define MAX_Q_DEPTH 32
2738 int max_q_depth;
2739
2740 dma_addr_t dma_fx00;
2741 request_t *ring_fx00;
2742 uint16_t length_fx00;
2743 uint8_t req_pkt[REQUEST_ENTRY_SIZE];
2744};
2745
2746
2747struct qlfc_fw {
2748 void *fw_buf;
2749 dma_addr_t fw_dma;
2750 uint32_t len;
2751};
2752
2753struct qlt_hw_data {
2754
2755 uint32_t enable_class_2:1;
2756 uint32_t enable_explicit_conf:1;
2757 uint32_t ini_mode_force_reverse:1;
2758 uint32_t node_name_set:1;
2759
2760 dma_addr_t atio_dma;
2761 struct atio *atio_ring;
2762 struct atio *atio_ring_ptr;
2763 uint16_t atio_ring_index;
2764 uint16_t atio_q_length;
2765 uint32_t __iomem *atio_q_in;
2766 uint32_t __iomem *atio_q_out;
2767
2768 void *target_lport_ptr;
2769 struct qla_tgt_func_tmpl *tgt_ops;
2770 struct qla_tgt *qla_tgt;
2771 struct qla_tgt_cmd *cmds[DEFAULT_OUTSTANDING_COMMANDS];
2772 uint16_t current_handle;
2773
2774 struct qla_tgt_vp_map *tgt_vp_map;
2775 struct mutex tgt_mutex;
2776 struct mutex tgt_host_action_mutex;
2777
2778 int saved_set;
2779 uint16_t saved_exchange_count;
2780 uint32_t saved_firmware_options_1;
2781 uint32_t saved_firmware_options_2;
2782 uint32_t saved_firmware_options_3;
2783 uint8_t saved_firmware_options[2];
2784 uint8_t saved_add_firmware_options[2];
2785
2786 uint8_t tgt_node_name[WWN_SIZE];
2787};
2788
2789
2790
2791
2792struct qla_hw_data {
2793 struct pci_dev *pdev;
2794
2795#define SRB_MIN_REQ 128
2796 mempool_t *srb_mempool;
2797
2798 volatile struct {
2799 uint32_t mbox_int :1;
2800 uint32_t mbox_busy :1;
2801 uint32_t disable_risc_code_load :1;
2802 uint32_t enable_64bit_addressing :1;
2803 uint32_t enable_lip_reset :1;
2804 uint32_t enable_target_reset :1;
2805 uint32_t enable_lip_full_login :1;
2806 uint32_t enable_led_scheme :1;
2807
2808 uint32_t msi_enabled :1;
2809 uint32_t msix_enabled :1;
2810 uint32_t disable_serdes :1;
2811 uint32_t gpsc_supported :1;
2812 uint32_t npiv_supported :1;
2813 uint32_t pci_channel_io_perm_failure :1;
2814 uint32_t fce_enabled :1;
2815 uint32_t fac_supported :1;
2816
2817 uint32_t chip_reset_done :1;
2818 uint32_t port0 :1;
2819 uint32_t running_gold_fw :1;
2820 uint32_t eeh_busy :1;
2821 uint32_t cpu_affinity_enabled :1;
2822 uint32_t disable_msix_handshake :1;
2823 uint32_t fcp_prio_enabled :1;
2824 uint32_t isp82xx_fw_hung:1;
2825 uint32_t nic_core_hung:1;
2826
2827 uint32_t quiesce_owner:1;
2828 uint32_t nic_core_reset_hdlr_active:1;
2829 uint32_t nic_core_reset_owner:1;
2830 uint32_t isp82xx_no_md_cap:1;
2831 uint32_t host_shutting_down:1;
2832 uint32_t idc_compl_status:1;
2833
2834 uint32_t mr_reset_hdlr_active:1;
2835 uint32_t mr_intr_valid:1;
2836
2837 } flags;
2838
2839
2840
2841
2842
2843
2844
2845
2846 spinlock_t hardware_lock ____cacheline_aligned;
2847 int bars;
2848 int mem_only;
2849 device_reg_t __iomem *iobase;
2850 resource_size_t pio_address;
2851
2852#define MIN_IOBASE_LEN 0x100
2853 dma_addr_t bar0_hdl;
2854
2855 void __iomem *cregbase;
2856 dma_addr_t bar2_hdl;
2857#define BAR0_LEN_FX00 (1024 * 1024)
2858#define BAR2_LEN_FX00 (128 * 1024)
2859
2860 uint32_t rqstq_intr_code;
2861 uint32_t mbx_intr_code;
2862 uint32_t req_que_len;
2863 uint32_t rsp_que_len;
2864 uint32_t req_que_off;
2865 uint32_t rsp_que_off;
2866
2867
2868 device_reg_t __iomem *mqiobase;
2869 device_reg_t __iomem *msixbase;
2870 uint16_t msix_count;
2871 uint8_t mqenable;
2872 struct req_que **req_q_map;
2873 struct rsp_que **rsp_q_map;
2874 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2875 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2876 uint8_t max_req_queues;
2877 uint8_t max_rsp_queues;
2878 struct qla_npiv_entry *npiv_info;
2879 uint16_t nvram_npiv_size;
2880
2881 uint16_t switch_cap;
2882#define FLOGI_SEQ_DEL BIT_8
2883#define FLOGI_MID_SUPPORT BIT_10
2884#define FLOGI_VSAN_SUPPORT BIT_12
2885#define FLOGI_SP_SUPPORT BIT_13
2886
2887 uint8_t port_no;
2888
2889
2890 uint8_t loop_down_abort_time;
2891 atomic_t loop_down_timer;
2892 uint8_t link_down_timeout;
2893 uint16_t max_loop_id;
2894 uint16_t max_fibre_devices;
2895
2896 uint16_t fb_rev;
2897 uint16_t min_external_loopid;
2898
2899#define PORT_SPEED_UNKNOWN 0xFFFF
2900#define PORT_SPEED_1GB 0x00
2901#define PORT_SPEED_2GB 0x01
2902#define PORT_SPEED_4GB 0x03
2903#define PORT_SPEED_8GB 0x04
2904#define PORT_SPEED_16GB 0x05
2905#define PORT_SPEED_10GB 0x13
2906 uint16_t link_data_rate;
2907
2908 uint8_t current_topology;
2909 uint8_t prev_topology;
2910#define ISP_CFG_NL 1
2911#define ISP_CFG_N 2
2912#define ISP_CFG_FL 4
2913#define ISP_CFG_F 8
2914
2915 uint8_t operating_mode;
2916#define LOOP 0
2917#define P2P 1
2918#define LOOP_P2P 2
2919#define P2P_LOOP 3
2920 uint8_t interrupts_on;
2921 uint32_t isp_abort_cnt;
2922
2923#define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
2924#define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
2925#define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
2926#define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031
2927#define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031
2928 uint32_t device_type;
2929#define DT_ISP2100 BIT_0
2930#define DT_ISP2200 BIT_1
2931#define DT_ISP2300 BIT_2
2932#define DT_ISP2312 BIT_3
2933#define DT_ISP2322 BIT_4
2934#define DT_ISP6312 BIT_5
2935#define DT_ISP6322 BIT_6
2936#define DT_ISP2422 BIT_7
2937#define DT_ISP2432 BIT_8
2938#define DT_ISP5422 BIT_9
2939#define DT_ISP5432 BIT_10
2940#define DT_ISP2532 BIT_11
2941#define DT_ISP8432 BIT_12
2942#define DT_ISP8001 BIT_13
2943#define DT_ISP8021 BIT_14
2944#define DT_ISP2031 BIT_15
2945#define DT_ISP8031 BIT_16
2946#define DT_ISPFX00 BIT_17
2947#define DT_ISP8044 BIT_18
2948#define DT_ISP_LAST (DT_ISP8044 << 1)
2949
2950#define DT_T10_PI BIT_25
2951#define DT_IIDMA BIT_26
2952#define DT_FWI2 BIT_27
2953#define DT_ZIO_SUPPORTED BIT_28
2954#define DT_OEM_001 BIT_29
2955#define DT_ISP2200A BIT_30
2956#define DT_EXTENDED_IDS BIT_31
2957#define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1))
2958#define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
2959#define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
2960#define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
2961#define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
2962#define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
2963#define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
2964#define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
2965#define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
2966#define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
2967#define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
2968#define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
2969#define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
2970#define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
2971#define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
2972#define IS_QLA81XX(ha) (IS_QLA8001(ha))
2973#define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
2974#define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044)
2975#define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031)
2976#define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031)
2977#define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00)
2978
2979#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
2980 IS_QLA6312(ha) || IS_QLA6322(ha))
2981#define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
2982#define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
2983#define IS_QLA25XX(ha) (IS_QLA2532(ha))
2984#define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha))
2985#define IS_QLA84XX(ha) (IS_QLA8432(ha))
2986#define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
2987 IS_QLA84XX(ha))
2988#define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \
2989 IS_QLA8031(ha) || IS_QLA8044(ha))
2990#define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha))
2991#define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
2992 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
2993 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \
2994 IS_QLA8044(ha))
2995#define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha))
2996#define IS_NOPOLLING_TYPE(ha) ((IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
2997 IS_QLA83XX(ha)) && (ha)->flags.msix_enabled)
2998#define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha))
2999#define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha))
3000#define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
3001
3002#define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
3003#define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
3004#define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
3005#define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
3006#define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
3007#define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
3008#define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED)
3009#define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha))
3010#define IS_BIDI_CAPABLE(ha) ((IS_QLA25XX(ha) || IS_QLA2031(ha)))
3011
3012#define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \
3013 ((ha)->fw_attributes_ext[0] & BIT_0))
3014#define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha))
3015#define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha))
3016#define IS_PI_DIFB_DIX0_CAPABLE(ha) (0)
3017#define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha))
3018#define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \
3019 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22))
3020#define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha))
3021#define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length)
3022
3023
3024 uint8_t serial0;
3025 uint8_t serial1;
3026 uint8_t serial2;
3027
3028
3029#define MAX_NVRAM_SIZE 4096
3030#define VPD_OFFSET MAX_NVRAM_SIZE / 2
3031 uint16_t nvram_size;
3032 uint16_t nvram_base;
3033 void *nvram;
3034 uint16_t vpd_size;
3035 uint16_t vpd_base;
3036 void *vpd;
3037
3038 uint16_t loop_reset_delay;
3039 uint8_t retry_count;
3040 uint8_t login_timeout;
3041 uint16_t r_a_tov;
3042 int port_down_retry_count;
3043 uint8_t mbx_count;
3044 uint8_t aen_mbx_count;
3045
3046 uint32_t login_retry_count;
3047
3048 ms_iocb_entry_t *ms_iocb;
3049 dma_addr_t ms_iocb_dma;
3050 struct ct_sns_pkt *ct_sns;
3051 dma_addr_t ct_sns_dma;
3052
3053 struct sns_cmd_pkt *sns_cmd;
3054 dma_addr_t sns_cmd_dma;
3055
3056#define SFP_DEV_SIZE 256
3057#define SFP_BLOCK_SIZE 64
3058 void *sfp_data;
3059 dma_addr_t sfp_data_dma;
3060
3061#define XGMAC_DATA_SIZE 4096
3062 void *xgmac_data;
3063 dma_addr_t xgmac_data_dma;
3064
3065#define DCBX_TLV_DATA_SIZE 4096
3066 void *dcbx_tlv;
3067 dma_addr_t dcbx_tlv_dma;
3068
3069 struct task_struct *dpc_thread;
3070 uint8_t dpc_active;
3071
3072 dma_addr_t gid_list_dma;
3073 struct gid_list_info *gid_list;
3074 int gid_list_info_size;
3075
3076
3077#define DMA_POOL_SIZE 256
3078 struct dma_pool *s_dma_pool;
3079
3080 dma_addr_t init_cb_dma;
3081 init_cb_t *init_cb;
3082 int init_cb_size;
3083 dma_addr_t ex_init_cb_dma;
3084 struct ex_init_cb_81xx *ex_init_cb;
3085
3086 void *async_pd;
3087 dma_addr_t async_pd_dma;
3088
3089 void *swl;
3090
3091
3092 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
3093 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT];
3094 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00];
3095
3096 mbx_cmd_t *mcp;
3097 struct mbx_cmd_32 *mcp32;
3098
3099 unsigned long mbx_cmd_flags;
3100#define MBX_INTERRUPT 1
3101#define MBX_INTR_WAIT 2
3102#define MBX_UPDATE_FLASH_ACTIVE 3
3103
3104 struct mutex vport_lock;
3105 spinlock_t vport_slock;
3106 struct completion mbx_cmd_comp;
3107 struct completion mbx_intr_comp;
3108 struct completion dcbx_comp;
3109 struct completion lb_portup_comp;
3110
3111#define DCBX_COMP_TIMEOUT 20
3112#define LB_PORTUP_COMP_TIMEOUT 10
3113
3114 int notify_dcbx_comp;
3115 int notify_lb_portup_comp;
3116 struct mutex selflogin_lock;
3117
3118
3119 uint16_t fw_major_version;
3120 uint16_t fw_minor_version;
3121 uint16_t fw_subminor_version;
3122 uint16_t fw_attributes;
3123 uint16_t fw_attributes_h;
3124 uint16_t fw_attributes_ext[2];
3125 uint32_t fw_memory_size;
3126 uint32_t fw_transfer_size;
3127 uint32_t fw_srisc_address;
3128#define RISC_START_ADDRESS_2100 0x1000
3129#define RISC_START_ADDRESS_2300 0x800
3130#define RISC_START_ADDRESS_2400 0x100000
3131 uint16_t fw_xcb_count;
3132 uint16_t fw_iocb_count;
3133
3134 uint16_t fw_options[16];
3135 uint8_t fw_seriallink_options[4];
3136 uint16_t fw_seriallink_options24[4];
3137
3138 uint8_t mpi_version[3];
3139 uint32_t mpi_capabilities;
3140 uint8_t phy_version[3];
3141
3142
3143 struct qla2xxx_fw_dump *fw_dump;
3144 uint32_t fw_dump_len;
3145 int fw_dumped;
3146 int fw_dump_reading;
3147 dma_addr_t eft_dma;
3148 void *eft;
3149
3150#define MCTP_DUMP_SIZE 0x086064
3151 dma_addr_t mctp_dump_dma;
3152 void *mctp_dump;
3153 int mctp_dumped;
3154 int mctp_dump_reading;
3155 uint32_t chain_offset;
3156 struct dentry *dfs_dir;
3157 struct dentry *dfs_fce;
3158 dma_addr_t fce_dma;
3159 void *fce;
3160 uint32_t fce_bufs;
3161 uint16_t fce_mb[8];
3162 uint64_t fce_wr, fce_rd;
3163 struct mutex fce_mutex;
3164
3165 uint32_t pci_attr;
3166 uint16_t chip_revision;
3167
3168 uint16_t product_id[4];
3169
3170 uint8_t model_number[16+1];
3171#define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
3172 char model_desc[80];
3173 uint8_t adapter_id[16+1];
3174
3175
3176 char *optrom_buffer;
3177 uint32_t optrom_size;
3178 int optrom_state;
3179#define QLA_SWAITING 0
3180#define QLA_SREADING 1
3181#define QLA_SWRITING 2
3182 uint32_t optrom_region_start;
3183 uint32_t optrom_region_size;
3184
3185
3186#define ROM_CODE_TYPE_BIOS 0
3187#define ROM_CODE_TYPE_FCODE 1
3188#define ROM_CODE_TYPE_EFI 3
3189 uint8_t bios_revision[2];
3190 uint8_t efi_revision[2];
3191 uint8_t fcode_revision[16];
3192 uint32_t fw_revision[4];
3193
3194 uint32_t gold_fw_version[4];
3195
3196
3197 uint32_t flash_conf_off;
3198 uint32_t flash_data_off;
3199 uint32_t nvram_conf_off;
3200 uint32_t nvram_data_off;
3201
3202 uint32_t fdt_wrt_disable;
3203 uint32_t fdt_wrt_enable;
3204 uint32_t fdt_erase_cmd;
3205 uint32_t fdt_block_size;
3206 uint32_t fdt_unprotect_sec_cmd;
3207 uint32_t fdt_protect_sec_cmd;
3208 uint32_t fdt_wrt_sts_reg_cmd;
3209
3210 uint32_t flt_region_flt;
3211 uint32_t flt_region_fdt;
3212 uint32_t flt_region_boot;
3213 uint32_t flt_region_fw;
3214 uint32_t flt_region_vpd_nvram;
3215 uint32_t flt_region_vpd;
3216 uint32_t flt_region_nvram;
3217 uint32_t flt_region_npiv_conf;
3218 uint32_t flt_region_gold_fw;
3219 uint32_t flt_region_fcp_prio;
3220 uint32_t flt_region_bootload;
3221
3222
3223 uint16_t beacon_blink_led;
3224 uint8_t beacon_color_state;
3225#define QLA_LED_GRN_ON 0x01
3226#define QLA_LED_YLW_ON 0x02
3227#define QLA_LED_ABR_ON 0x04
3228#define QLA_LED_ALL_ON 0x07
3229
3230 uint16_t zio_mode;
3231 uint16_t zio_timer;
3232
3233 struct qla_msix_entry *msix_entries;
3234
3235 struct list_head vp_list;
3236 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
3237 sizeof(unsigned long)];
3238 uint16_t num_vhosts;
3239 uint16_t num_vsans;
3240 uint16_t max_npiv_vports;
3241 int cur_vport_count;
3242
3243 struct qla_chip_state_84xx *cs84xx;
3244 struct qla_statistics qla_stats;
3245 struct isp_operations *isp_ops;
3246 struct workqueue_struct *wq;
3247 struct qlfc_fw fw_buf;
3248
3249
3250 struct qla_fcp_prio_cfg *fcp_prio_cfg;
3251
3252 struct dma_pool *dl_dma_pool;
3253#define DSD_LIST_DMA_POOL_SIZE 512
3254
3255 struct dma_pool *fcp_cmnd_dma_pool;
3256 mempool_t *ctx_mempool;
3257#define FCP_CMND_DMA_POOL_SIZE 512
3258
3259 unsigned long nx_pcibase;
3260 uint8_t *nxdb_rd_ptr;
3261 unsigned long nxdb_wr_ptr;
3262
3263 uint32_t crb_win;
3264 uint32_t curr_window;
3265 uint32_t ddr_mn_window;
3266 unsigned long mn_win_crb;
3267 unsigned long ms_win_crb;
3268 int qdr_sn_window;
3269 uint32_t fcoe_dev_init_timeout;
3270 uint32_t fcoe_reset_timeout;
3271 rwlock_t hw_lock;
3272 uint16_t portnum;
3273 int link_width;
3274 struct fw_blob *hablob;
3275 struct qla82xx_legacy_intr_set nx_legacy_intr;
3276
3277 uint16_t gbl_dsd_inuse;
3278 uint16_t gbl_dsd_avail;
3279 struct list_head gbl_dsd_list;
3280#define NUM_DSD_CHAIN 4096
3281
3282 uint8_t fw_type;
3283 __le32 file_prd_off;
3284
3285 uint32_t md_template_size;
3286 void *md_tmplt_hdr;
3287 dma_addr_t md_tmplt_hdr_dma;
3288 void *md_dump;
3289 uint32_t md_dump_size;
3290
3291 void *loop_id_map;
3292
3293
3294 uint32_t idc_audit_ts;
3295 uint32_t idc_extend_tmo;
3296
3297
3298 struct workqueue_struct *dpc_lp_wq;
3299 struct work_struct idc_aen;
3300
3301 struct workqueue_struct *dpc_hp_wq;
3302 struct work_struct nic_core_reset;
3303 struct work_struct idc_state_handler;
3304 struct work_struct nic_core_unrecoverable;
3305
3306#define HOST_QUEUE_RAMPDOWN_INTERVAL (60 * HZ)
3307#define HOST_QUEUE_RAMPUP_INTERVAL (30 * HZ)
3308 unsigned long host_last_rampdown_time;
3309 unsigned long host_last_rampup_time;
3310 int cfg_lun_q_depth;
3311
3312 struct mr_data_fx00 mr;
3313
3314 struct qlt_hw_data tgt;
3315};
3316
3317
3318
3319
3320typedef struct scsi_qla_host {
3321 struct list_head list;
3322 struct list_head vp_fcports;
3323 struct list_head work_list;
3324 spinlock_t work_lock;
3325
3326
3327 struct Scsi_Host *host;
3328 unsigned long host_no;
3329 uint8_t host_str[16];
3330
3331 volatile struct {
3332 uint32_t init_done :1;
3333 uint32_t online :1;
3334 uint32_t reset_active :1;
3335
3336 uint32_t management_server_logged_in :1;
3337 uint32_t process_response_queue :1;
3338 uint32_t difdix_supported:1;
3339 uint32_t delete_progress:1;
3340
3341 uint32_t fw_tgt_reported:1;
3342 } flags;
3343
3344 atomic_t loop_state;
3345#define LOOP_TIMEOUT 1
3346#define LOOP_DOWN 2
3347#define LOOP_UP 3
3348#define LOOP_UPDATE 4
3349#define LOOP_READY 5
3350#define LOOP_DEAD 6
3351
3352 unsigned long dpc_flags;
3353#define RESET_MARKER_NEEDED 0
3354#define RESET_ACTIVE 1
3355#define ISP_ABORT_NEEDED 2
3356#define ABORT_ISP_ACTIVE 3
3357#define LOOP_RESYNC_NEEDED 4
3358#define LOOP_RESYNC_ACTIVE 5
3359#define LOCAL_LOOP_UPDATE 6
3360#define RSCN_UPDATE 7
3361#define RELOGIN_NEEDED 8
3362#define REGISTER_FC4_NEEDED 9
3363#define ISP_ABORT_RETRY 10
3364#define BEACON_BLINK_NEEDED 11
3365#define REGISTER_FDMI_NEEDED 12
3366#define FCPORT_UPDATE_NEEDED 13
3367#define VP_DPC_NEEDED 14
3368#define UNLOADING 15
3369#define NPIV_CONFIG_NEEDED 16
3370#define ISP_UNRECOVERABLE 17
3371#define FCOE_CTX_RESET_NEEDED 18
3372#define MPI_RESET_NEEDED 19
3373#define ISP_QUIESCE_NEEDED 20
3374#define SCR_PENDING 21
3375#define HOST_RAMP_DOWN_QUEUE_DEPTH 22
3376#define HOST_RAMP_UP_QUEUE_DEPTH 23
3377#define PORT_UPDATE_NEEDED 24
3378#define FX00_RESET_RECOVERY 25
3379#define FX00_TARGET_SCAN 26
3380#define FX00_CRITEMP_RECOVERY 27
3381
3382 uint32_t device_flags;
3383#define SWITCH_FOUND BIT_0
3384#define DFLG_NO_CABLE BIT_1
3385#define DFLG_DEV_FAILED BIT_5
3386
3387
3388 uint16_t loop_id;
3389 uint16_t self_login_loop_id;
3390
3391
3392 fc_port_t bidir_fcport;
3393
3394
3395
3396
3397 port_id_t d_id;
3398 uint8_t marker_needed;
3399 uint16_t mgmt_svr_loop_id;
3400
3401
3402
3403
3404 uint8_t loop_down_abort_time;
3405 atomic_t loop_down_timer;
3406 uint8_t link_down_timeout;
3407
3408 uint32_t timer_active;
3409 struct timer_list timer;
3410
3411 uint8_t node_name[WWN_SIZE];
3412 uint8_t port_name[WWN_SIZE];
3413 uint8_t fabric_node_name[WWN_SIZE];
3414
3415 uint16_t fcoe_vlan_id;
3416 uint16_t fcoe_fcf_idx;
3417 uint8_t fcoe_vn_port_mac[6];
3418
3419 uint32_t vp_abort_cnt;
3420
3421 struct fc_vport *fc_vport;
3422 uint16_t vp_idx;
3423
3424 unsigned long vp_flags;
3425#define VP_IDX_ACQUIRED 0
3426#define VP_CREATE_NEEDED 1
3427#define VP_BIND_NEEDED 2
3428#define VP_DELETE_NEEDED 3
3429#define VP_SCR_NEEDED 4
3430 atomic_t vp_state;
3431#define VP_OFFLINE 0
3432#define VP_ACTIVE 1
3433#define VP_FAILED 2
3434
3435 uint16_t vp_err_state;
3436 uint16_t vp_prev_err_state;
3437#define VP_ERR_UNKWN 0
3438#define VP_ERR_PORTDWN 1
3439#define VP_ERR_FAB_UNSUPPORTED 2
3440#define VP_ERR_FAB_NORESOURCES 3
3441#define VP_ERR_FAB_LOGOUT 4
3442#define VP_ERR_ADAP_NORESOURCES 5
3443 struct qla_hw_data *hw;
3444 struct req_que *req;
3445 int fw_heartbeat_counter;
3446 int seconds_since_last_heartbeat;
3447 struct fc_host_statistics fc_host_stat;
3448 struct qla_statistics qla_stats;
3449 struct bidi_statistics bidi_stats;
3450
3451 atomic_t vref_count;
3452 struct qla8044_reset_template reset_tmplt;
3453} scsi_qla_host_t;
3454
3455#define SET_VP_IDX 1
3456#define SET_AL_PA 2
3457#define RESET_VP_IDX 3
3458#define RESET_AL_PA 4
3459struct qla_tgt_vp_map {
3460 uint8_t idx;
3461 scsi_qla_host_t *vha;
3462};
3463
3464
3465
3466
3467#define LOOP_TRANSITION(ha) \
3468 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
3469 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
3470 atomic_read(&ha->loop_state) == LOOP_DOWN)
3471
3472#define STATE_TRANSITION(ha) \
3473 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
3474 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
3475
3476#define QLA_VHA_MARK_BUSY(__vha, __bail) do { \
3477 atomic_inc(&__vha->vref_count); \
3478 mb(); \
3479 if (__vha->flags.delete_progress) { \
3480 atomic_dec(&__vha->vref_count); \
3481 __bail = 1; \
3482 } else { \
3483 __bail = 0; \
3484 } \
3485} while (0)
3486
3487#define QLA_VHA_MARK_NOT_BUSY(__vha) do { \
3488 atomic_dec(&__vha->vref_count); \
3489} while (0)
3490
3491
3492
3493
3494#define MBS_MASK 0x3fff
3495
3496#define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
3497#define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
3498#define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
3499#define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
3500#define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
3501#define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
3502#define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
3503#define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
3504#define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
3505#define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
3506
3507#define QLA_FUNCTION_TIMEOUT 0x100
3508#define QLA_FUNCTION_PARAMETER_ERROR 0x101
3509#define QLA_FUNCTION_FAILED 0x102
3510#define QLA_MEMORY_ALLOC_FAILED 0x103
3511#define QLA_LOCK_TIMEOUT 0x104
3512#define QLA_ABORTED 0x105
3513#define QLA_SUSPENDED 0x106
3514#define QLA_BUSY 0x107
3515#define QLA_ALREADY_REGISTERED 0x109
3516
3517#define NVRAM_DELAY() udelay(10)
3518
3519
3520
3521
3522#define OPTROM_SIZE_2300 0x20000
3523#define OPTROM_SIZE_2322 0x100000
3524#define OPTROM_SIZE_24XX 0x100000
3525#define OPTROM_SIZE_25XX 0x200000
3526#define OPTROM_SIZE_81XX 0x400000
3527#define OPTROM_SIZE_82XX 0x800000
3528#define OPTROM_SIZE_83XX 0x1000000
3529
3530#define OPTROM_BURST_SIZE 0x1000
3531#define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
3532
3533#define QLA_DSDS_PER_IOCB 37
3534
3535#define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
3536
3537#define QLA_SG_ALL 1024
3538
3539enum nexus_wait_type {
3540 WAIT_HOST = 0,
3541 WAIT_TARGET,
3542 WAIT_LUN,
3543};
3544
3545#include "qla_gbl.h"
3546#include "qla_dbg.h"
3547#include "qla_inline.h"
3548#endif
3549