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8#ifndef __QL4_DEF_H
9#define __QL4_DEF_H
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/types.h>
14#include <linux/module.h>
15#include <linux/list.h>
16#include <linux/pci.h>
17#include <linux/dma-mapping.h>
18#include <linux/sched.h>
19#include <linux/slab.h>
20#include <linux/dmapool.h>
21#include <linux/mempool.h>
22#include <linux/spinlock.h>
23#include <linux/workqueue.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26#include <linux/mutex.h>
27#include <linux/aer.h>
28#include <linux/bsg-lib.h>
29
30#include <net/tcp.h>
31#include <scsi/scsi.h>
32#include <scsi/scsi_host.h>
33#include <scsi/scsi_device.h>
34#include <scsi/scsi_cmnd.h>
35#include <scsi/scsi_transport.h>
36#include <scsi/scsi_transport_iscsi.h>
37#include <scsi/scsi_bsg_iscsi.h>
38#include <scsi/scsi_netlink.h>
39#include <scsi/libiscsi.h>
40
41#include "ql4_dbg.h"
42#include "ql4_nx.h"
43#include "ql4_fw.h"
44#include "ql4_nvram.h"
45#include "ql4_83xx.h"
46
47#ifndef PCI_DEVICE_ID_QLOGIC_ISP4010
48#define PCI_DEVICE_ID_QLOGIC_ISP4010 0x4010
49#endif
50
51#ifndef PCI_DEVICE_ID_QLOGIC_ISP4022
52#define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022
53#endif
54
55#ifndef PCI_DEVICE_ID_QLOGIC_ISP4032
56#define PCI_DEVICE_ID_QLOGIC_ISP4032 0x4032
57#endif
58
59#ifndef PCI_DEVICE_ID_QLOGIC_ISP8022
60#define PCI_DEVICE_ID_QLOGIC_ISP8022 0x8022
61#endif
62
63#ifndef PCI_DEVICE_ID_QLOGIC_ISP8324
64#define PCI_DEVICE_ID_QLOGIC_ISP8324 0x8032
65#endif
66
67#ifndef PCI_DEVICE_ID_QLOGIC_ISP8042
68#define PCI_DEVICE_ID_QLOGIC_ISP8042 0x8042
69#endif
70
71#define ISP4XXX_PCI_FN_1 0x1
72#define ISP4XXX_PCI_FN_2 0x3
73
74#define QLA_SUCCESS 0
75#define QLA_ERROR 1
76
77
78
79
80#define BIT_0 0x1
81#define BIT_1 0x2
82#define BIT_2 0x4
83#define BIT_3 0x8
84#define BIT_4 0x10
85#define BIT_5 0x20
86#define BIT_6 0x40
87#define BIT_7 0x80
88#define BIT_8 0x100
89#define BIT_9 0x200
90#define BIT_10 0x400
91#define BIT_11 0x800
92#define BIT_12 0x1000
93#define BIT_13 0x2000
94#define BIT_14 0x4000
95#define BIT_15 0x8000
96#define BIT_16 0x10000
97#define BIT_17 0x20000
98#define BIT_18 0x40000
99#define BIT_19 0x80000
100#define BIT_20 0x100000
101#define BIT_21 0x200000
102#define BIT_22 0x400000
103#define BIT_23 0x800000
104#define BIT_24 0x1000000
105#define BIT_25 0x2000000
106#define BIT_26 0x4000000
107#define BIT_27 0x8000000
108#define BIT_28 0x10000000
109#define BIT_29 0x20000000
110#define BIT_30 0x40000000
111#define BIT_31 0x80000000
112
113
114
115
116#define ql4_printk(level, ha, format, arg...) \
117 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
118
119
120
121
122
123#define MAX_HBAS 16
124#define MAX_BUSES 1
125#define MAX_TARGETS MAX_DEV_DB_ENTRIES
126#define MAX_LUNS 0xffff
127#define MAX_AEN_ENTRIES MAX_DEV_DB_ENTRIES
128#define MAX_DDB_ENTRIES MAX_DEV_DB_ENTRIES
129#define MAX_PDU_ENTRIES 32
130#define INVALID_ENTRY 0xFFFF
131#define MAX_CMDS_TO_RISC 1024
132#define MAX_SRBS MAX_CMDS_TO_RISC
133#define MBOX_AEN_REG_COUNT 8
134#define MAX_INIT_RETRIES 5
135
136
137
138
139#define REQUEST_QUEUE_DEPTH MAX_CMDS_TO_RISC
140#define RESPONSE_QUEUE_DEPTH 64
141#define QUEUE_SIZE 64
142#define DMA_BUFFER_SIZE 512
143#define IOCB_HIWAT_CUSHION 4
144
145
146
147
148#define MAC_ADDR_LEN 6
149#define IP_ADDR_LEN 4
150#define IPv6_ADDR_LEN 16
151#define DRIVER_NAME "qla4xxx"
152
153#define MAX_LINKED_CMDS_PER_LUN 3
154#define MAX_REQS_SERVICED_PER_INTR 1
155
156#define ISCSI_IPADDR_SIZE 4
157#define ISCSI_ALIAS_SIZE 32
158#define ISCSI_NAME_SIZE 0xE0
159
160#define QL4_SESS_RECOVERY_TMO 120
161
162
163#define LSDW(x) ((u32)((u64)(x)))
164#define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16))
165
166#define DEV_DB_NON_PERSISTENT 0
167#define DEV_DB_PERSISTENT 1
168
169#define COPY_ISID(dst_isid, src_isid) { \
170 int i, j; \
171 for (i = 0, j = ISID_SIZE - 1; i < ISID_SIZE;) \
172 dst_isid[i++] = src_isid[j--]; \
173}
174
175#define SET_BITVAL(o, n, v) { \
176 if (o) \
177 n |= v; \
178 else \
179 n &= ~v; \
180}
181
182
183
184
185#define MBOX_TOV 60
186#define SOFT_RESET_TOV 30
187#define RESET_INTR_TOV 3
188#define SEMAPHORE_TOV 10
189#define ADAPTER_INIT_TOV 30
190#define ADAPTER_RESET_TOV 180
191#define EXTEND_CMD_TOV 60
192#define WAIT_CMD_TOV 30
193#define EH_WAIT_CMD_TOV 120
194#define FIRMWARE_UP_TOV 60
195#define RESET_FIRMWARE_TOV 30
196#define LOGOUT_TOV 10
197#define IOCB_TOV_MARGIN 10
198#define RELOGIN_TOV 18
199#define ISNS_DEREG_TOV 5
200#define HBA_ONLINE_TOV 30
201#define DISABLE_ACB_TOV 30
202#define IP_CONFIG_TOV 30
203#define LOGIN_TOV 12
204#define BOOT_LOGIN_RESP_TOV 60
205
206#define MAX_RESET_HA_RETRIES 2
207#define FW_ALIVE_WAIT_TOV 3
208#define IDC_EXTEND_TOV 8
209
210#define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
211
212
213
214
215
216struct srb {
217 struct list_head list;
218 struct scsi_qla_host *ha;
219 struct ddb_entry *ddb;
220 uint16_t flags;
221
222#define SRB_DMA_VALID BIT_3
223#define SRB_GOT_SENSE BIT_4
224 uint8_t state;
225
226#define SRB_NO_QUEUE_STATE 0
227#define SRB_FREE_STATE 1
228#define SRB_ACTIVE_STATE 3
229#define SRB_ACTIVE_TIMEOUT_STATE 4
230#define SRB_SUSPENDED_STATE 7
231
232 struct scsi_cmnd *cmd;
233 dma_addr_t dma_handle;
234 struct kref srb_ref;
235 uint8_t err_id;
236#define SRB_ERR_PORT 1
237#define SRB_ERR_LOOP 2
238#define SRB_ERR_DEVICE 3
239#define SRB_ERR_OTHER 4
240
241 uint16_t reserved;
242 uint16_t iocb_tov;
243 uint16_t iocb_cnt;
244 uint16_t cc_stat;
245
246
247 uint8_t *req_sense_ptr;
248 uint16_t req_sense_len;
249 uint16_t reserved2;
250};
251
252
253struct mrb {
254 struct scsi_qla_host *ha;
255 struct mbox_cmd_iocb *mbox;
256 uint32_t mbox_cmd;
257 uint16_t iocb_cnt;
258 uint32_t pid;
259};
260
261
262
263
264struct aen {
265 uint32_t mbox_sts[MBOX_AEN_REG_COUNT];
266};
267
268struct ql4_aen_log {
269 int count;
270 struct aen entry[MAX_AEN_ENTRIES];
271};
272
273
274
275
276struct ddb_entry {
277 struct scsi_qla_host *ha;
278 struct iscsi_cls_session *sess;
279 struct iscsi_cls_conn *conn;
280
281 uint16_t fw_ddb_index;
282 uint32_t fw_ddb_device_state;
283 uint16_t ddb_type;
284#define FLASH_DDB 0x01
285
286 struct dev_db_entry fw_ddb_entry;
287 int (*unblock_sess)(struct iscsi_cls_session *cls_session);
288 int (*ddb_change)(struct scsi_qla_host *ha, uint32_t fw_ddb_index,
289 struct ddb_entry *ddb_entry, uint32_t state);
290
291
292 unsigned long flags;
293 uint16_t default_relogin_timeout;
294
295 atomic_t retry_relogin_timer;
296
297 atomic_t relogin_timer;
298
299 atomic_t relogin_retry_count;
300
301 uint32_t default_time2wait;
302
303 uint16_t chap_tbl_idx;
304};
305
306struct qla_ddb_index {
307 struct list_head list;
308 uint16_t fw_ddb_idx;
309 struct dev_db_entry fw_ddb;
310 uint8_t flash_isid[6];
311};
312
313#define DDB_IPADDR_LEN 64
314
315struct ql4_tuple_ddb {
316 int port;
317 int tpgt;
318 char ip_addr[DDB_IPADDR_LEN];
319 char iscsi_name[ISCSI_NAME_SIZE];
320 uint16_t options;
321#define DDB_OPT_IPV6 0x0e0e
322#define DDB_OPT_IPV4 0x0f0f
323 uint8_t isid[6];
324};
325
326
327
328
329#define DDB_STATE_DEAD 0
330
331#define DDB_STATE_ONLINE 1
332
333#define DDB_STATE_MISSING 2
334
335
336
337
338
339#define DF_RELOGIN 0
340#define DF_BOOT_TGT 1
341#define DF_ISNS_DISCOVERED 2
342#define DF_FO_MASKED 3
343#define DF_DISABLE_RELOGIN 4
344
345enum qla4_work_type {
346 QLA4_EVENT_AEN,
347 QLA4_EVENT_PING_STATUS,
348};
349
350struct qla4_work_evt {
351 struct list_head list;
352 enum qla4_work_type type;
353 union {
354 struct {
355 enum iscsi_host_event_code code;
356 uint32_t data_size;
357 uint8_t data[0];
358 } aen;
359 struct {
360 uint32_t status;
361 uint32_t pid;
362 uint32_t data_size;
363 uint8_t data[0];
364 } ping;
365 } u;
366};
367
368struct ql82xx_hw_data {
369
370 uint32_t flash_conf_off;
371 uint32_t flash_data_off;
372
373 uint32_t fdt_wrt_disable;
374 uint32_t fdt_erase_cmd;
375 uint32_t fdt_block_size;
376 uint32_t fdt_unprotect_sec_cmd;
377 uint32_t fdt_protect_sec_cmd;
378
379 uint32_t flt_region_flt;
380 uint32_t flt_region_fdt;
381 uint32_t flt_region_boot;
382 uint32_t flt_region_bootload;
383 uint32_t flt_region_fw;
384
385 uint32_t flt_iscsi_param;
386 uint32_t flt_region_chap;
387 uint32_t flt_chap_size;
388 uint32_t flt_region_ddb;
389 uint32_t flt_ddb_size;
390};
391
392struct qla4_8xxx_legacy_intr_set {
393 uint32_t int_vec_bit;
394 uint32_t tgt_status_reg;
395 uint32_t tgt_mask_reg;
396 uint32_t pci_int_reg;
397};
398
399
400
401#define QLA_MSIX_DEFAULT 0x00
402#define QLA_MSIX_RSP_Q 0x01
403
404#define QLA_MSIX_ENTRIES 2
405#define QLA_MIDX_DEFAULT 0
406#define QLA_MIDX_RSP_Q 1
407
408struct ql4_msix_entry {
409 int have_irq;
410 uint16_t msix_vector;
411 uint16_t msix_entry;
412};
413
414
415
416
417struct isp_operations {
418 int (*iospace_config) (struct scsi_qla_host *ha);
419 void (*pci_config) (struct scsi_qla_host *);
420 void (*disable_intrs) (struct scsi_qla_host *);
421 void (*enable_intrs) (struct scsi_qla_host *);
422 int (*start_firmware) (struct scsi_qla_host *);
423 int (*restart_firmware) (struct scsi_qla_host *);
424 irqreturn_t (*intr_handler) (int , void *);
425 void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t);
426 int (*need_reset) (struct scsi_qla_host *);
427 int (*reset_chip) (struct scsi_qla_host *);
428 int (*reset_firmware) (struct scsi_qla_host *);
429 void (*queue_iocb) (struct scsi_qla_host *);
430 void (*complete_iocb) (struct scsi_qla_host *);
431 uint16_t (*rd_shdw_req_q_out) (struct scsi_qla_host *);
432 uint16_t (*rd_shdw_rsp_q_in) (struct scsi_qla_host *);
433 int (*get_sys_info) (struct scsi_qla_host *);
434 uint32_t (*rd_reg_direct) (struct scsi_qla_host *, ulong);
435 void (*wr_reg_direct) (struct scsi_qla_host *, ulong, uint32_t);
436 int (*rd_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t *);
437 int (*wr_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t);
438 int (*idc_lock) (struct scsi_qla_host *);
439 void (*idc_unlock) (struct scsi_qla_host *);
440 void (*rom_lock_recovery) (struct scsi_qla_host *);
441 void (*queue_mailbox_command) (struct scsi_qla_host *, uint32_t *, int);
442 void (*process_mailbox_interrupt) (struct scsi_qla_host *, int);
443};
444
445struct ql4_mdump_size_table {
446 uint32_t size;
447 uint32_t size_cmask_02;
448 uint32_t size_cmask_04;
449 uint32_t size_cmask_08;
450 uint32_t size_cmask_10;
451 uint32_t size_cmask_FF;
452 uint32_t version;
453};
454
455
456struct ipaddress_config {
457 uint16_t ipv4_options;
458 uint16_t tcp_options;
459 uint16_t ipv4_vlan_tag;
460 uint8_t ipv4_addr_state;
461 uint8_t ip_address[IP_ADDR_LEN];
462 uint8_t subnet_mask[IP_ADDR_LEN];
463 uint8_t gateway[IP_ADDR_LEN];
464 uint32_t ipv6_options;
465 uint32_t ipv6_addl_options;
466 uint8_t ipv6_link_local_state;
467 uint8_t ipv6_addr0_state;
468 uint8_t ipv6_addr1_state;
469 uint8_t ipv6_default_router_state;
470 uint16_t ipv6_vlan_tag;
471 struct in6_addr ipv6_link_local_addr;
472 struct in6_addr ipv6_addr0;
473 struct in6_addr ipv6_addr1;
474 struct in6_addr ipv6_default_router_addr;
475 uint16_t eth_mtu_size;
476 uint16_t ipv4_port;
477 uint16_t ipv6_port;
478};
479
480#define QL4_CHAP_MAX_NAME_LEN 256
481#define QL4_CHAP_MAX_SECRET_LEN 100
482#define LOCAL_CHAP 0
483#define BIDI_CHAP 1
484
485struct ql4_chap_format {
486 u8 intr_chap_name[QL4_CHAP_MAX_NAME_LEN];
487 u8 intr_secret[QL4_CHAP_MAX_SECRET_LEN];
488 u8 target_chap_name[QL4_CHAP_MAX_NAME_LEN];
489 u8 target_secret[QL4_CHAP_MAX_SECRET_LEN];
490 u16 intr_chap_name_length;
491 u16 intr_secret_length;
492 u16 target_chap_name_length;
493 u16 target_secret_length;
494};
495
496struct ip_address_format {
497 u8 ip_type;
498 u8 ip_address[16];
499};
500
501struct ql4_conn_info {
502 u16 dest_port;
503 struct ip_address_format dest_ipaddr;
504 struct ql4_chap_format chap;
505};
506
507struct ql4_boot_session_info {
508 u8 target_name[224];
509 struct ql4_conn_info conn_list[1];
510};
511
512struct ql4_boot_tgt_info {
513 struct ql4_boot_session_info boot_pri_sess;
514 struct ql4_boot_session_info boot_sec_sess;
515};
516
517
518
519
520struct scsi_qla_host {
521
522 unsigned long flags;
523
524#define AF_ONLINE 0
525#define AF_INIT_DONE 1
526#define AF_MBOX_COMMAND 2
527#define AF_MBOX_COMMAND_DONE 3
528#define AF_ST_DISCOVERY_IN_PROGRESS 4
529#define AF_INTERRUPTS_ON 6
530#define AF_GET_CRASH_RECORD 7
531#define AF_LINK_UP 8
532#define AF_LOOPBACK 9
533#define AF_IRQ_ATTACHED 10
534#define AF_DISABLE_ACB_COMPLETE 11
535#define AF_HA_REMOVAL 12
536#define AF_INTx_ENABLED 15
537#define AF_MSI_ENABLED 16
538#define AF_MSIX_ENABLED 17
539#define AF_MBOX_COMMAND_NOPOLL 18
540#define AF_FW_RECOVERY 19
541#define AF_EEH_BUSY 20
542#define AF_PCI_CHANNEL_IO_PERM_FAILURE 21
543#define AF_BUILD_DDB_LIST 22
544#define AF_82XX_FW_DUMPED 24
545#define AF_8XXX_RST_OWNER 25
546#define AF_82XX_DUMP_READING 26
547#define AF_83XX_NO_FW_DUMP 27
548#define AF_83XX_IOCB_INTR_ON 28
549#define AF_83XX_MBOX_INTR_ON 29
550
551 unsigned long dpc_flags;
552
553#define DPC_RESET_HA 1
554#define DPC_RETRY_RESET_HA 2
555#define DPC_RELOGIN_DEVICE 3
556#define DPC_RESET_HA_FW_CONTEXT 4
557#define DPC_RESET_HA_INTR 5
558#define DPC_ISNS_RESTART 7
559#define DPC_AEN 9
560#define DPC_GET_DHCP_IP_ADDR 15
561#define DPC_LINK_CHANGED 18
562#define DPC_RESET_ACTIVE 20
563#define DPC_HA_UNRECOVERABLE 21
564#define DPC_HA_NEED_QUIESCENT 22
565#define DPC_POST_IDC_ACK 23
566#define DPC_RESTORE_ACB 24
567
568 struct Scsi_Host *host;
569 uint32_t tot_ddbs;
570
571 uint16_t iocb_cnt;
572 uint16_t iocb_hiwat;
573
574
575#define SRB_MIN_REQ 128
576 mempool_t *srb_mempool;
577
578
579 struct pci_dev *pdev;
580
581 struct isp_reg __iomem *reg;
582 unsigned long pio_address;
583 unsigned long pio_length;
584#define MIN_IOBASE_LEN 0x100
585
586 uint16_t req_q_count;
587
588 unsigned long host_no;
589
590
591 struct eeprom_data *nvram;
592 spinlock_t hardware_lock ____cacheline_aligned;
593 uint32_t eeprom_cmd_data;
594
595
596 uint64_t isr_count;
597 uint64_t adapter_error_count;
598 uint64_t device_error_count;
599 uint64_t total_io_count;
600 uint64_t total_mbytes_xferred;
601 uint64_t link_failure_count;
602 uint64_t invalid_crc_count;
603 uint32_t bytes_xfered;
604 uint32_t spurious_int_count;
605 uint32_t aborted_io_count;
606 uint32_t io_timeout_count;
607 uint32_t mailbox_timeout_count;
608 uint32_t seconds_since_last_intr;
609 uint32_t seconds_since_last_heartbeat;
610 uint32_t mac_index;
611
612
613
614 uint32_t firmware_version[2];
615 uint32_t patch_number;
616 uint32_t build_number;
617 uint32_t board_id;
618
619
620
621 uint16_t firmware_options;
622 uint8_t alias[32];
623 uint8_t name_string[256];
624 uint8_t heartbeat_interval;
625
626
627 uint8_t my_mac[MAC_ADDR_LEN];
628 uint8_t serial_number[16];
629 uint16_t port_num;
630
631 uint32_t firmware_state;
632 uint32_t addl_fw_state;
633
634
635 struct workqueue_struct *dpc_thread;
636 struct work_struct dpc_work;
637
638
639 struct timer_list timer;
640 uint32_t timer_active;
641
642
643 atomic_t check_relogin_timeouts;
644 uint32_t retry_reset_ha_cnt;
645 uint32_t isp_reset_timer;
646 uint32_t nic_reset_timer;
647 int eh_start;
648 struct list_head free_srb_q;
649 uint16_t free_srb_q_count;
650 uint16_t num_srbs_allocated;
651
652
653 void *queues;
654 dma_addr_t queues_dma;
655 unsigned long queues_len;
656
657#define MEM_ALIGN_VALUE \
658 ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \
659 sizeof(struct queue_entry))
660
661 dma_addr_t request_dma;
662 struct queue_entry *request_ring;
663 struct queue_entry *request_ptr;
664 dma_addr_t response_dma;
665 struct queue_entry *response_ring;
666 struct queue_entry *response_ptr;
667 dma_addr_t shadow_regs_dma;
668 struct shadow_regs *shadow_regs;
669 uint16_t request_in;
670 uint16_t request_out;
671 uint16_t response_in;
672 uint16_t response_out;
673
674
675 uint16_t aen_q_count;
676 uint16_t aen_in;
677 uint16_t aen_out;
678 struct aen aen_q[MAX_AEN_ENTRIES];
679
680 struct ql4_aen_log aen_log;
681
682
683
684
685 struct mutex mbox_sem;
686
687
688 volatile uint8_t mbox_status_count;
689 volatile uint32_t mbox_status[MBOX_REG_COUNT];
690
691
692 struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES];
693
694
695 struct srb *status_srb;
696
697 uint8_t acb_version;
698
699
700 struct device_reg_82xx __iomem *qla4_82xx_reg;
701 unsigned long nx_pcibase;
702 uint8_t *nx_db_rd_ptr;
703 unsigned long nx_db_wr_ptr;
704 unsigned long first_page_group_start;
705 unsigned long first_page_group_end;
706
707 uint32_t crb_win;
708 uint32_t curr_window;
709 uint32_t ddr_mn_window;
710 unsigned long mn_win_crb;
711 unsigned long ms_win_crb;
712 int qdr_sn_window;
713 rwlock_t hw_lock;
714 uint16_t func_num;
715 int link_width;
716
717 struct qla4_8xxx_legacy_intr_set nx_legacy_intr;
718 u32 nx_crb_mask;
719
720 uint8_t revision_id;
721 uint32_t fw_heartbeat_counter;
722
723 struct isp_operations *isp_ops;
724 struct ql82xx_hw_data hw;
725
726 struct ql4_msix_entry msix_entries[QLA_MSIX_ENTRIES];
727
728 uint32_t nx_dev_init_timeout;
729 uint32_t nx_reset_timeout;
730 void *fw_dump;
731 uint32_t fw_dump_size;
732 uint32_t fw_dump_capture_mask;
733 void *fw_dump_tmplt_hdr;
734 uint32_t fw_dump_tmplt_size;
735
736 struct completion mbx_intr_comp;
737
738 struct ipaddress_config ip_config;
739 struct iscsi_iface *iface_ipv4;
740 struct iscsi_iface *iface_ipv6_0;
741 struct iscsi_iface *iface_ipv6_1;
742
743
744 struct about_fw_info fw_info;
745 uint32_t fw_uptime_secs;
746 uint32_t fw_uptime_msecs;
747 uint16_t def_timeout;
748
749 uint32_t flash_state;
750#define QLFLASH_WAITING 0
751#define QLFLASH_READING 1
752#define QLFLASH_WRITING 2
753 struct dma_pool *chap_dma_pool;
754 uint8_t *chap_list;
755 struct mutex chap_sem;
756
757#define CHAP_DMA_BLOCK_SIZE 512
758 struct workqueue_struct *task_wq;
759 unsigned long ddb_idx_map[MAX_DDB_ENTRIES / BITS_PER_LONG];
760#define SYSFS_FLAG_FW_SEL_BOOT 2
761 struct iscsi_boot_kset *boot_kset;
762 struct ql4_boot_tgt_info boot_tgt;
763 uint16_t phy_port_num;
764 uint16_t phy_port_cnt;
765 uint16_t iscsi_pci_func_cnt;
766 uint8_t model_name[16];
767 struct completion disable_acb_comp;
768 struct dma_pool *fw_ddb_dma_pool;
769#define DDB_DMA_BLOCK_SIZE 512
770 uint16_t pri_ddb_idx;
771 uint16_t sec_ddb_idx;
772 int is_reset;
773 uint16_t temperature;
774
775
776 struct list_head work_list;
777 spinlock_t work_lock;
778
779
780#define MAX_MRB 128
781 struct mrb *active_mrb_array[MAX_MRB];
782 uint32_t mrb_index;
783
784 uint32_t *reg_tbl;
785 struct qla4_83xx_reset_template reset_tmplt;
786 struct device_reg_83xx __iomem *qla4_83xx_reg;
787
788
789 uint32_t pf_bit;
790 struct qla4_83xx_idc_information idc_info;
791 struct addr_ctrl_blk *saved_acb;
792};
793
794struct ql4_task_data {
795 struct scsi_qla_host *ha;
796 uint8_t iocb_req_cnt;
797 dma_addr_t data_dma;
798 void *req_buffer;
799 dma_addr_t req_dma;
800 uint32_t req_len;
801 void *resp_buffer;
802 dma_addr_t resp_dma;
803 uint32_t resp_len;
804 struct iscsi_task *task;
805 struct passthru_status sts;
806 struct work_struct task_work;
807};
808
809struct qla_endpoint {
810 struct Scsi_Host *host;
811 struct sockaddr_storage dst_addr;
812};
813
814struct qla_conn {
815 struct qla_endpoint *qla_ep;
816};
817
818static inline int is_ipv4_enabled(struct scsi_qla_host *ha)
819{
820 return ((ha->ip_config.ipv4_options & IPOPT_IPV4_PROTOCOL_ENABLE) != 0);
821}
822
823static inline int is_ipv6_enabled(struct scsi_qla_host *ha)
824{
825 return ((ha->ip_config.ipv6_options &
826 IPV6_OPT_IPV6_PROTOCOL_ENABLE) != 0);
827}
828
829static inline int is_qla4010(struct scsi_qla_host *ha)
830{
831 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010;
832}
833
834static inline int is_qla4022(struct scsi_qla_host *ha)
835{
836 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022;
837}
838
839static inline int is_qla4032(struct scsi_qla_host *ha)
840{
841 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032;
842}
843
844static inline int is_qla40XX(struct scsi_qla_host *ha)
845{
846 return is_qla4032(ha) || is_qla4022(ha) || is_qla4010(ha);
847}
848
849static inline int is_qla8022(struct scsi_qla_host *ha)
850{
851 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022;
852}
853
854static inline int is_qla8032(struct scsi_qla_host *ha)
855{
856 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8324;
857}
858
859static inline int is_qla8042(struct scsi_qla_host *ha)
860{
861 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8042;
862}
863
864static inline int is_qla80XX(struct scsi_qla_host *ha)
865{
866 return is_qla8022(ha) || is_qla8032(ha) || is_qla8042(ha);
867}
868
869static inline int is_aer_supported(struct scsi_qla_host *ha)
870{
871 return ((ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022) ||
872 (ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8324));
873}
874
875static inline int adapter_up(struct scsi_qla_host *ha)
876{
877 return (test_bit(AF_ONLINE, &ha->flags) != 0) &&
878 (test_bit(AF_LINK_UP, &ha->flags) != 0) &&
879 (!test_bit(AF_LOOPBACK, &ha->flags));
880}
881
882static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost)
883{
884 return (struct scsi_qla_host *)iscsi_host_priv(shost);
885}
886
887static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha)
888{
889 return (is_qla4010(ha) ?
890 &ha->reg->u1.isp4010.nvram :
891 &ha->reg->u1.isp4022.semaphore);
892}
893
894static inline void __iomem* isp_nvram(struct scsi_qla_host *ha)
895{
896 return (is_qla4010(ha) ?
897 &ha->reg->u1.isp4010.nvram :
898 &ha->reg->u1.isp4022.nvram);
899}
900
901static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha)
902{
903 return (is_qla4010(ha) ?
904 &ha->reg->u2.isp4010.ext_hw_conf :
905 &ha->reg->u2.isp4022.p0.ext_hw_conf);
906}
907
908static inline void __iomem* isp_port_status(struct scsi_qla_host *ha)
909{
910 return (is_qla4010(ha) ?
911 &ha->reg->u2.isp4010.port_status :
912 &ha->reg->u2.isp4022.p0.port_status);
913}
914
915static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha)
916{
917 return (is_qla4010(ha) ?
918 &ha->reg->u2.isp4010.port_ctrl :
919 &ha->reg->u2.isp4022.p0.port_ctrl);
920}
921
922static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha)
923{
924 return (is_qla4010(ha) ?
925 &ha->reg->u2.isp4010.port_err_status :
926 &ha->reg->u2.isp4022.p0.port_err_status);
927}
928
929static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha)
930{
931 return (is_qla4010(ha) ?
932 &ha->reg->u2.isp4010.gp_out :
933 &ha->reg->u2.isp4022.p0.gp_out);
934}
935
936static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha)
937{
938 return (is_qla4010(ha) ?
939 offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2 :
940 offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2);
941}
942
943int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
944void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask);
945int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
946
947static inline int ql4xxx_lock_flash(struct scsi_qla_host *a)
948{
949 if (is_qla4010(a))
950 return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK,
951 QL4010_FLASH_SEM_BITS);
952 else
953 return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK,
954 (QL4022_RESOURCE_BITS_BASE_CODE |
955 (a->mac_index)) << 13);
956}
957
958static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a)
959{
960 if (is_qla4010(a))
961 ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK);
962 else
963 ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK);
964}
965
966static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a)
967{
968 if (is_qla4010(a))
969 return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK,
970 QL4010_NVRAM_SEM_BITS);
971 else
972 return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK,
973 (QL4022_RESOURCE_BITS_BASE_CODE |
974 (a->mac_index)) << 10);
975}
976
977static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a)
978{
979 if (is_qla4010(a))
980 ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK);
981 else
982 ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK);
983}
984
985static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a)
986{
987 if (is_qla4010(a))
988 return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK,
989 QL4010_DRVR_SEM_BITS);
990 else
991 return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK,
992 (QL4022_RESOURCE_BITS_BASE_CODE |
993 (a->mac_index)) << 1);
994}
995
996static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a)
997{
998 if (is_qla4010(a))
999 ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK);
1000 else
1001 ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK);
1002}
1003
1004static inline int ql4xxx_reset_active(struct scsi_qla_host *ha)
1005{
1006 return test_bit(DPC_RESET_ACTIVE, &ha->dpc_flags) ||
1007 test_bit(DPC_RESET_HA, &ha->dpc_flags) ||
1008 test_bit(DPC_RETRY_RESET_HA, &ha->dpc_flags) ||
1009 test_bit(DPC_RESET_HA_INTR, &ha->dpc_flags) ||
1010 test_bit(DPC_RESET_HA_FW_CONTEXT, &ha->dpc_flags) ||
1011 test_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags);
1012
1013}
1014
1015static inline int qla4_8xxx_rd_direct(struct scsi_qla_host *ha,
1016 const uint32_t crb_reg)
1017{
1018 return ha->isp_ops->rd_reg_direct(ha, ha->reg_tbl[crb_reg]);
1019}
1020
1021static inline void qla4_8xxx_wr_direct(struct scsi_qla_host *ha,
1022 const uint32_t crb_reg,
1023 const uint32_t value)
1024{
1025 ha->isp_ops->wr_reg_direct(ha, ha->reg_tbl[crb_reg], value);
1026}
1027
1028
1029
1030
1031
1032#define INIT_ADAPTER 0
1033#define RESET_ADAPTER 1
1034
1035#define PRESERVE_DDB_LIST 0
1036#define REBUILD_DDB_LIST 1
1037
1038
1039#define PROCESS_ALL_AENS 0
1040#define FLUSH_DDB_CHANGED_AENS 1
1041
1042
1043#define QL4_UEVENT_CODE_FW_DUMP 0
1044
1045#endif
1046
