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8#include <linux/kernel.h>
9#include <linux/io.h>
10#include <linux/spi/spi.h>
11#include <linux/spi/spi_bitbang.h>
12#include <linux/gpio.h>
13#include <linux/interrupt.h>
14#include <linux/platform_device.h>
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/module.h>
18#include <linux/of_gpio.h>
19#include <linux/platform_data/efm32-spi.h>
20
21#define DRIVER_NAME "efm32-spi"
22
23#define MASK_VAL(mask, val) ((val << __ffs(mask)) & mask)
24
25#define REG_CTRL 0x00
26#define REG_CTRL_SYNC 0x0001
27#define REG_CTRL_CLKPOL 0x0100
28#define REG_CTRL_CLKPHA 0x0200
29#define REG_CTRL_MSBF 0x0400
30#define REG_CTRL_TXBIL 0x1000
31
32#define REG_FRAME 0x04
33#define REG_FRAME_DATABITS__MASK 0x000f
34#define REG_FRAME_DATABITS(n) ((n) - 3)
35
36#define REG_CMD 0x0c
37#define REG_CMD_RXEN 0x0001
38#define REG_CMD_RXDIS 0x0002
39#define REG_CMD_TXEN 0x0004
40#define REG_CMD_TXDIS 0x0008
41#define REG_CMD_MASTEREN 0x0010
42
43#define REG_STATUS 0x10
44#define REG_STATUS_TXENS 0x0002
45#define REG_STATUS_TXC 0x0020
46#define REG_STATUS_TXBL 0x0040
47#define REG_STATUS_RXDATAV 0x0080
48
49#define REG_CLKDIV 0x14
50
51#define REG_RXDATAX 0x18
52#define REG_RXDATAX_RXDATA__MASK 0x01ff
53#define REG_RXDATAX_PERR 0x4000
54#define REG_RXDATAX_FERR 0x8000
55
56#define REG_TXDATA 0x34
57
58#define REG_IF 0x40
59#define REG_IF_TXBL 0x0002
60#define REG_IF_RXDATAV 0x0004
61
62#define REG_IFS 0x44
63#define REG_IFC 0x48
64#define REG_IEN 0x4c
65
66#define REG_ROUTE 0x54
67#define REG_ROUTE_RXPEN 0x0001
68#define REG_ROUTE_TXPEN 0x0002
69#define REG_ROUTE_CLKPEN 0x0008
70#define REG_ROUTE_LOCATION__MASK 0x0700
71#define REG_ROUTE_LOCATION(n) MASK_VAL(REG_ROUTE_LOCATION__MASK, (n))
72
73struct efm32_spi_ddata {
74 struct spi_bitbang bitbang;
75
76 spinlock_t lock;
77
78 struct clk *clk;
79 void __iomem *base;
80 unsigned int rxirq, txirq;
81 struct efm32_spi_pdata pdata;
82
83
84 struct completion done;
85 const u8 *tx_buf;
86 u8 *rx_buf;
87 unsigned tx_len, rx_len;
88
89
90 unsigned csgpio[];
91};
92
93#define ddata_to_dev(ddata) (&(ddata->bitbang.master->dev))
94#define efm32_spi_vdbg(ddata, format, arg...) \
95 dev_vdbg(ddata_to_dev(ddata), format, ##arg)
96
97static void efm32_spi_write32(struct efm32_spi_ddata *ddata,
98 u32 value, unsigned offset)
99{
100 writel_relaxed(value, ddata->base + offset);
101}
102
103static u32 efm32_spi_read32(struct efm32_spi_ddata *ddata, unsigned offset)
104{
105 return readl_relaxed(ddata->base + offset);
106}
107
108static void efm32_spi_chipselect(struct spi_device *spi, int is_on)
109{
110 struct efm32_spi_ddata *ddata = spi_master_get_devdata(spi->master);
111 int value = !(spi->mode & SPI_CS_HIGH) == !(is_on == BITBANG_CS_ACTIVE);
112
113 gpio_set_value(ddata->csgpio[spi->chip_select], value);
114}
115
116static int efm32_spi_setup_transfer(struct spi_device *spi,
117 struct spi_transfer *t)
118{
119 struct efm32_spi_ddata *ddata = spi_master_get_devdata(spi->master);
120
121 unsigned bpw = t->bits_per_word ?: spi->bits_per_word;
122 unsigned speed = t->speed_hz ?: spi->max_speed_hz;
123 unsigned long clkfreq = clk_get_rate(ddata->clk);
124 u32 clkdiv;
125
126 efm32_spi_write32(ddata, REG_CTRL_SYNC | REG_CTRL_MSBF |
127 (spi->mode & SPI_CPHA ? REG_CTRL_CLKPHA : 0) |
128 (spi->mode & SPI_CPOL ? REG_CTRL_CLKPOL : 0), REG_CTRL);
129
130 efm32_spi_write32(ddata,
131 REG_FRAME_DATABITS(bpw), REG_FRAME);
132
133 if (2 * speed >= clkfreq)
134 clkdiv = 0;
135 else
136 clkdiv = 64 * (DIV_ROUND_UP(2 * clkfreq, speed) - 4);
137
138 if (clkdiv > (1U << 21))
139 return -EINVAL;
140
141 efm32_spi_write32(ddata, clkdiv, REG_CLKDIV);
142 efm32_spi_write32(ddata, REG_CMD_MASTEREN, REG_CMD);
143 efm32_spi_write32(ddata, REG_CMD_RXEN | REG_CMD_TXEN, REG_CMD);
144
145 return 0;
146}
147
148static void efm32_spi_tx_u8(struct efm32_spi_ddata *ddata)
149{
150 u8 val = 0;
151
152 if (ddata->tx_buf) {
153 val = *ddata->tx_buf;
154 ddata->tx_buf++;
155 }
156
157 ddata->tx_len--;
158 efm32_spi_write32(ddata, val, REG_TXDATA);
159 efm32_spi_vdbg(ddata, "%s: tx 0x%x\n", __func__, val);
160}
161
162static void efm32_spi_rx_u8(struct efm32_spi_ddata *ddata)
163{
164 u32 rxdata = efm32_spi_read32(ddata, REG_RXDATAX);
165 efm32_spi_vdbg(ddata, "%s: rx 0x%x\n", __func__, rxdata);
166
167 if (ddata->rx_buf) {
168 *ddata->rx_buf = rxdata;
169 ddata->rx_buf++;
170 }
171
172 ddata->rx_len--;
173}
174
175static void efm32_spi_filltx(struct efm32_spi_ddata *ddata)
176{
177 while (ddata->tx_len &&
178 ddata->tx_len + 2 > ddata->rx_len &&
179 efm32_spi_read32(ddata, REG_STATUS) & REG_STATUS_TXBL) {
180 efm32_spi_tx_u8(ddata);
181 }
182}
183
184static int efm32_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
185{
186 struct efm32_spi_ddata *ddata = spi_master_get_devdata(spi->master);
187 int ret = -EBUSY;
188
189 spin_lock_irq(&ddata->lock);
190
191 if (ddata->tx_buf || ddata->rx_buf)
192 goto out_unlock;
193
194 ddata->tx_buf = t->tx_buf;
195 ddata->rx_buf = t->rx_buf;
196 ddata->tx_len = ddata->rx_len =
197 t->len * DIV_ROUND_UP(t->bits_per_word, 8);
198
199 efm32_spi_filltx(ddata);
200
201 init_completion(&ddata->done);
202
203 efm32_spi_write32(ddata, REG_IF_TXBL | REG_IF_RXDATAV, REG_IEN);
204
205 spin_unlock_irq(&ddata->lock);
206
207 wait_for_completion(&ddata->done);
208
209 spin_lock_irq(&ddata->lock);
210
211 ret = t->len - max(ddata->tx_len, ddata->rx_len);
212
213 efm32_spi_write32(ddata, 0, REG_IEN);
214 ddata->tx_buf = ddata->rx_buf = NULL;
215
216out_unlock:
217 spin_unlock_irq(&ddata->lock);
218
219 return ret;
220}
221
222static irqreturn_t efm32_spi_rxirq(int irq, void *data)
223{
224 struct efm32_spi_ddata *ddata = data;
225 irqreturn_t ret = IRQ_NONE;
226
227 spin_lock(&ddata->lock);
228
229 while (ddata->rx_len > 0 &&
230 efm32_spi_read32(ddata, REG_STATUS) &
231 REG_STATUS_RXDATAV) {
232 efm32_spi_rx_u8(ddata);
233
234 ret = IRQ_HANDLED;
235 }
236
237 if (!ddata->rx_len) {
238 u32 ien = efm32_spi_read32(ddata, REG_IEN);
239
240 ien &= ~REG_IF_RXDATAV;
241
242 efm32_spi_write32(ddata, ien, REG_IEN);
243
244 complete(&ddata->done);
245 }
246
247 spin_unlock(&ddata->lock);
248
249 return ret;
250}
251
252static irqreturn_t efm32_spi_txirq(int irq, void *data)
253{
254 struct efm32_spi_ddata *ddata = data;
255
256 efm32_spi_vdbg(ddata,
257 "%s: txlen = %u, rxlen = %u, if=0x%08x, stat=0x%08x\n",
258 __func__, ddata->tx_len, ddata->rx_len,
259 efm32_spi_read32(ddata, REG_IF),
260 efm32_spi_read32(ddata, REG_STATUS));
261
262 spin_lock(&ddata->lock);
263
264 efm32_spi_filltx(ddata);
265
266 efm32_spi_vdbg(ddata, "%s: txlen = %u, rxlen = %u\n",
267 __func__, ddata->tx_len, ddata->rx_len);
268
269 if (!ddata->tx_len) {
270 u32 ien = efm32_spi_read32(ddata, REG_IEN);
271
272 ien &= ~REG_IF_TXBL;
273
274 efm32_spi_write32(ddata, ien, REG_IEN);
275 efm32_spi_vdbg(ddata, "disable TXBL\n");
276 }
277
278 spin_unlock(&ddata->lock);
279
280 return IRQ_HANDLED;
281}
282
283static const struct efm32_spi_pdata efm32_spi_pdata_default = {
284 .location = 1,
285};
286
287static u32 efm32_spi_get_configured_location(struct efm32_spi_ddata *ddata)
288{
289 u32 reg = efm32_spi_read32(ddata, REG_ROUTE);
290
291 return (reg & REG_ROUTE_LOCATION__MASK) >> __ffs(REG_ROUTE_LOCATION__MASK);
292}
293
294static int efm32_spi_probe_dt(struct platform_device *pdev,
295 struct spi_master *master, struct efm32_spi_ddata *ddata)
296{
297 struct device_node *np = pdev->dev.of_node;
298 u32 location;
299 int ret;
300
301 if (!np)
302 return 1;
303
304 ret = of_property_read_u32(np, "location", &location);
305 if (!ret) {
306 dev_dbg(&pdev->dev, "using location %u\n", location);
307 } else {
308
309 location = efm32_spi_get_configured_location(ddata);
310
311 dev_info(&pdev->dev, "fall back to location %u\n", location);
312 }
313
314 ddata->pdata.location = location;
315
316
317 master->bus_num = -1;
318
319 return 0;
320}
321
322static int efm32_spi_probe(struct platform_device *pdev)
323{
324 struct efm32_spi_ddata *ddata;
325 struct resource *res;
326 int ret;
327 struct spi_master *master;
328 struct device_node *np = pdev->dev.of_node;
329 unsigned int num_cs, i;
330
331 num_cs = of_gpio_named_count(np, "cs-gpios");
332
333 master = spi_alloc_master(&pdev->dev,
334 sizeof(*ddata) + num_cs * sizeof(unsigned));
335 if (!master) {
336 dev_dbg(&pdev->dev,
337 "failed to allocate spi master controller\n");
338 return -ENOMEM;
339 }
340 platform_set_drvdata(pdev, master);
341
342 master->dev.of_node = pdev->dev.of_node;
343
344 master->num_chipselect = num_cs;
345 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
346 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
347
348 ddata = spi_master_get_devdata(master);
349
350 ddata->bitbang.master = spi_master_get(master);
351 ddata->bitbang.chipselect = efm32_spi_chipselect;
352 ddata->bitbang.setup_transfer = efm32_spi_setup_transfer;
353 ddata->bitbang.txrx_bufs = efm32_spi_txrx_bufs;
354
355 spin_lock_init(&ddata->lock);
356
357 ddata->clk = devm_clk_get(&pdev->dev, NULL);
358 if (IS_ERR(ddata->clk)) {
359 ret = PTR_ERR(ddata->clk);
360 dev_err(&pdev->dev, "failed to get clock: %d\n", ret);
361 goto err;
362 }
363
364 for (i = 0; i < num_cs; ++i) {
365 ret = of_get_named_gpio(np, "cs-gpios", i);
366 if (ret < 0) {
367 dev_err(&pdev->dev, "failed to get csgpio#%u (%d)\n",
368 i, ret);
369 goto err;
370 }
371 ddata->csgpio[i] = ret;
372 dev_dbg(&pdev->dev, "csgpio#%u = %u\n", i, ddata->csgpio[i]);
373 ret = devm_gpio_request_one(&pdev->dev, ddata->csgpio[i],
374 GPIOF_OUT_INIT_LOW, DRIVER_NAME);
375 if (ret < 0) {
376 dev_err(&pdev->dev,
377 "failed to configure csgpio#%u (%d)\n",
378 i, ret);
379 goto err;
380 }
381 }
382
383 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
384 if (!res) {
385 ret = -ENODEV;
386 dev_err(&pdev->dev, "failed to determine base address\n");
387 goto err;
388 }
389
390 if (resource_size(res) < 60) {
391 ret = -EINVAL;
392 dev_err(&pdev->dev, "memory resource too small\n");
393 goto err;
394 }
395
396 ddata->base = devm_ioremap_resource(&pdev->dev, res);
397 if (IS_ERR(ddata->base)) {
398 ret = PTR_ERR(ddata->base);
399 goto err;
400 }
401
402 ret = platform_get_irq(pdev, 0);
403 if (ret <= 0) {
404 dev_err(&pdev->dev, "failed to get rx irq (%d)\n", ret);
405 goto err;
406 }
407
408 ddata->rxirq = ret;
409
410 ret = platform_get_irq(pdev, 1);
411 if (ret <= 0)
412 ret = ddata->rxirq + 1;
413
414 ddata->txirq = ret;
415
416 ret = clk_prepare_enable(ddata->clk);
417 if (ret < 0) {
418 dev_err(&pdev->dev, "failed to enable clock (%d)\n", ret);
419 goto err;
420 }
421
422 ret = efm32_spi_probe_dt(pdev, master, ddata);
423 if (ret > 0) {
424
425 const struct efm32_spi_pdata *pdata =
426 dev_get_platdata(&pdev->dev);
427
428 if (pdata)
429 ddata->pdata = *pdata;
430 else
431 ddata->pdata.location =
432 efm32_spi_get_configured_location(ddata);
433
434 master->bus_num = pdev->id;
435
436 } else if (ret < 0) {
437 goto err_disable_clk;
438 }
439
440 efm32_spi_write32(ddata, 0, REG_IEN);
441 efm32_spi_write32(ddata, REG_ROUTE_TXPEN | REG_ROUTE_RXPEN |
442 REG_ROUTE_CLKPEN |
443 REG_ROUTE_LOCATION(ddata->pdata.location), REG_ROUTE);
444
445 ret = request_irq(ddata->rxirq, efm32_spi_rxirq,
446 0, DRIVER_NAME " rx", ddata);
447 if (ret) {
448 dev_err(&pdev->dev, "failed to register rxirq (%d)\n", ret);
449 goto err_disable_clk;
450 }
451
452 ret = request_irq(ddata->txirq, efm32_spi_txirq,
453 0, DRIVER_NAME " tx", ddata);
454 if (ret) {
455 dev_err(&pdev->dev, "failed to register txirq (%d)\n", ret);
456 goto err_free_rx_irq;
457 }
458
459 ret = spi_bitbang_start(&ddata->bitbang);
460 if (ret) {
461 dev_err(&pdev->dev, "spi_bitbang_start failed (%d)\n", ret);
462
463 free_irq(ddata->txirq, ddata);
464err_free_rx_irq:
465 free_irq(ddata->rxirq, ddata);
466err_disable_clk:
467 clk_disable_unprepare(ddata->clk);
468err:
469 spi_master_put(master);
470 kfree(master);
471 }
472
473 return ret;
474}
475
476static int efm32_spi_remove(struct platform_device *pdev)
477{
478 struct spi_master *master = platform_get_drvdata(pdev);
479 struct efm32_spi_ddata *ddata = spi_master_get_devdata(master);
480
481 efm32_spi_write32(ddata, 0, REG_IEN);
482
483 free_irq(ddata->txirq, ddata);
484 free_irq(ddata->rxirq, ddata);
485 clk_disable_unprepare(ddata->clk);
486 spi_master_put(master);
487 kfree(master);
488
489 return 0;
490}
491
492static const struct of_device_id efm32_spi_dt_ids[] = {
493 {
494 .compatible = "efm32,spi",
495 }, {
496
497 }
498};
499MODULE_DEVICE_TABLE(of, efm32_spi_dt_ids);
500
501static struct platform_driver efm32_spi_driver = {
502 .probe = efm32_spi_probe,
503 .remove = efm32_spi_remove,
504
505 .driver = {
506 .name = DRIVER_NAME,
507 .owner = THIS_MODULE,
508 .of_match_table = efm32_spi_dt_ids,
509 },
510};
511module_platform_driver(efm32_spi_driver);
512
513MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
514MODULE_DESCRIPTION("EFM32 SPI driver");
515MODULE_LICENSE("GPL v2");
516MODULE_ALIAS("platform:" DRIVER_NAME);
517
