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19#ifndef _MITE_H_
20#define _MITE_H_
21
22#include <linux/pci.h>
23#include <linux/log2.h>
24#include <linux/slab.h>
25#include "../comedidev.h"
26
27
28#define PCIMIO_COMPAT
29
30#ifdef DEBUG_MITE
31#define MDPRINTK(format, args...) pr_debug(format , ## args)
32#else
33#define MDPRINTK(format, args...) do { } while (0)
34#endif
35
36#define MAX_MITE_DMA_CHANNELS 8
37
38struct mite_dma_descriptor {
39 u32 count;
40 u32 addr;
41 u32 next;
42 u32 dar;
43};
44
45struct mite_dma_descriptor_ring {
46 struct device *hw_dev;
47 unsigned int n_links;
48 struct mite_dma_descriptor *descriptors;
49 dma_addr_t descriptors_dma_addr;
50};
51
52struct mite_channel {
53 struct mite_struct *mite;
54 unsigned channel;
55 int dir;
56 int done;
57 struct mite_dma_descriptor_ring *ring;
58};
59
60struct mite_struct {
61 struct pci_dev *pcidev;
62 resource_size_t mite_phys_addr;
63 void __iomem *mite_io_addr;
64 resource_size_t daq_phys_addr;
65 void __iomem *daq_io_addr;
66 struct mite_channel channels[MAX_MITE_DMA_CHANNELS];
67 short channel_allocated[MAX_MITE_DMA_CHANNELS];
68 int num_channels;
69 unsigned fifo_size;
70 spinlock_t lock;
71};
72
73struct mite_struct *mite_alloc(struct pci_dev *pcidev);
74
75static inline void mite_free(struct mite_struct *mite)
76{
77 kfree(mite);
78}
79
80static inline unsigned int mite_irq(struct mite_struct *mite)
81{
82 return mite->pcidev->irq;
83};
84
85static inline unsigned int mite_device_id(struct mite_struct *mite)
86{
87 return mite->pcidev->device;
88};
89
90int mite_setup(struct mite_struct *mite);
91int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1);
92void mite_unsetup(struct mite_struct *mite);
93struct mite_dma_descriptor_ring *mite_alloc_ring(struct mite_struct *mite);
94void mite_free_ring(struct mite_dma_descriptor_ring *ring);
95struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite,
96 struct
97 mite_dma_descriptor_ring
98 *ring, unsigned min_channel,
99 unsigned max_channel);
100static inline struct mite_channel *mite_request_channel(struct mite_struct
101 *mite,
102 struct
103 mite_dma_descriptor_ring
104 *ring)
105{
106 return mite_request_channel_in_range(mite, ring, 0,
107 mite->num_channels - 1);
108}
109
110void mite_release_channel(struct mite_channel *mite_chan);
111
112unsigned mite_dma_tcr(struct mite_channel *mite_chan);
113void mite_dma_arm(struct mite_channel *mite_chan);
114void mite_dma_disarm(struct mite_channel *mite_chan);
115int mite_sync_input_dma(struct mite_channel *mite_chan,
116 struct comedi_async *async);
117int mite_sync_output_dma(struct mite_channel *mite_chan,
118 struct comedi_async *async);
119u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan);
120u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan);
121u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan);
122u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan);
123u32 mite_bytes_in_transit(struct mite_channel *mite_chan);
124unsigned mite_get_status(struct mite_channel *mite_chan);
125int mite_done(struct mite_channel *mite_chan);
126
127void mite_prep_dma(struct mite_channel *mite_chan,
128 unsigned int num_device_bits, unsigned int num_memory_bits);
129int mite_buf_change(struct mite_dma_descriptor_ring *ring,
130 struct comedi_async *async);
131
132#ifdef DEBUG_MITE
133void mite_print_chsr(unsigned int chsr);
134void mite_dump_regs(struct mite_channel *mite_chan);
135#endif
136
137static inline int CHAN_OFFSET(int channel)
138{
139 return 0x500 + 0x100 * channel;
140};
141
142enum mite_registers {
143
144
145
146 MITE_UNKNOWN_DMA_BURST_REG = 0x28,
147 MITE_IODWBSR = 0xc0,
148 MITE_IODWBSR_1 = 0xc4,
149 MITE_IODWCR_1 = 0xf4,
150 MITE_PCI_CONFIG_OFFSET = 0x300,
151 MITE_CSIGR = 0x460
152};
153static inline int MITE_CHOR(int channel)
154{
155 return CHAN_OFFSET(channel) + 0x0;
156};
157
158static inline int MITE_CHCR(int channel)
159{
160 return CHAN_OFFSET(channel) + 0x4;
161};
162
163static inline int MITE_TCR(int channel)
164{
165 return CHAN_OFFSET(channel) + 0x8;
166};
167
168static inline int MITE_MCR(int channel)
169{
170 return CHAN_OFFSET(channel) + 0xc;
171};
172
173static inline int MITE_MAR(int channel)
174{
175 return CHAN_OFFSET(channel) + 0x10;
176};
177
178static inline int MITE_DCR(int channel)
179{
180 return CHAN_OFFSET(channel) + 0x14;
181};
182
183static inline int MITE_DAR(int channel)
184{
185 return CHAN_OFFSET(channel) + 0x18;
186};
187
188static inline int MITE_LKCR(int channel)
189{
190 return CHAN_OFFSET(channel) + 0x1c;
191};
192
193static inline int MITE_LKAR(int channel)
194{
195 return CHAN_OFFSET(channel) + 0x20;
196};
197
198static inline int MITE_LLKAR(int channel)
199{
200 return CHAN_OFFSET(channel) + 0x24;
201};
202
203static inline int MITE_BAR(int channel)
204{
205 return CHAN_OFFSET(channel) + 0x28;
206};
207
208static inline int MITE_BCR(int channel)
209{
210 return CHAN_OFFSET(channel) + 0x2c;
211};
212
213static inline int MITE_SAR(int channel)
214{
215 return CHAN_OFFSET(channel) + 0x30;
216};
217
218static inline int MITE_WSCR(int channel)
219{
220 return CHAN_OFFSET(channel) + 0x34;
221};
222
223static inline int MITE_WSER(int channel)
224{
225 return CHAN_OFFSET(channel) + 0x38;
226};
227
228static inline int MITE_CHSR(int channel)
229{
230 return CHAN_OFFSET(channel) + 0x3c;
231};
232
233static inline int MITE_FCR(int channel)
234{
235 return CHAN_OFFSET(channel) + 0x40;
236};
237
238enum MITE_IODWBSR_bits {
239 WENAB = 0x80,
240};
241
242static inline unsigned MITE_IODWBSR_1_WSIZE_bits(unsigned size)
243{
244 unsigned order = 0;
245
246 BUG_ON(size == 0);
247 order = ilog2(size);
248 BUG_ON(order < 1);
249 return (order - 1) & 0x1f;
250}
251
252enum MITE_UNKNOWN_DMA_BURST_bits {
253 UNKNOWN_DMA_BURST_ENABLE_BITS = 0x600
254};
255
256static inline int mite_csigr_version(u32 csigr_bits)
257{
258 return csigr_bits & 0xf;
259};
260
261static inline int mite_csigr_type(u32 csigr_bits)
262{
263 return (csigr_bits >> 4) & 0xf;
264};
265
266static inline int mite_csigr_mmode(u32 csigr_bits)
267{
268 return (csigr_bits >> 8) & 0x3;
269};
270
271static inline int mite_csigr_imode(u32 csigr_bits)
272{
273 return (csigr_bits >> 12) & 0x3;
274};
275
276static inline int mite_csigr_dmac(u32 csigr_bits)
277{
278 return (csigr_bits >> 16) & 0xf;
279};
280
281static inline int mite_csigr_wpdep(u32 csigr_bits)
282{
283 unsigned int wpdep_bits = (csigr_bits >> 20) & 0x7;
284 if (wpdep_bits == 0)
285 return 0;
286 else
287 return 1 << (wpdep_bits - 1);
288};
289
290static inline int mite_csigr_wins(u32 csigr_bits)
291{
292 return (csigr_bits >> 24) & 0x1f;
293};
294
295static inline int mite_csigr_iowins(u32 csigr_bits)
296{
297 return (csigr_bits >> 29) & 0x7;
298};
299
300enum MITE_MCR_bits {
301 MCRPON = 0,
302};
303
304enum MITE_DCR_bits {
305 DCR_NORMAL = (1 << 29),
306 DCRPON = 0,
307};
308
309enum MITE_CHOR_bits {
310 CHOR_DMARESET = (1 << 31),
311 CHOR_SET_SEND_TC = (1 << 11),
312 CHOR_CLR_SEND_TC = (1 << 10),
313 CHOR_SET_LPAUSE = (1 << 9),
314 CHOR_CLR_LPAUSE = (1 << 8),
315 CHOR_CLRDONE = (1 << 7),
316 CHOR_CLRRB = (1 << 6),
317 CHOR_CLRLC = (1 << 5),
318 CHOR_FRESET = (1 << 4),
319 CHOR_ABORT = (1 << 3),
320 CHOR_STOP = (1 << 2),
321 CHOR_CONT = (1 << 1),
322 CHOR_START = (1 << 0),
323 CHOR_PON = (CHOR_CLR_SEND_TC | CHOR_CLR_LPAUSE),
324};
325
326enum MITE_CHCR_bits {
327 CHCR_SET_DMA_IE = (1 << 31),
328 CHCR_CLR_DMA_IE = (1 << 30),
329 CHCR_SET_LINKP_IE = (1 << 29),
330 CHCR_CLR_LINKP_IE = (1 << 28),
331 CHCR_SET_SAR_IE = (1 << 27),
332 CHCR_CLR_SAR_IE = (1 << 26),
333 CHCR_SET_DONE_IE = (1 << 25),
334 CHCR_CLR_DONE_IE = (1 << 24),
335 CHCR_SET_MRDY_IE = (1 << 23),
336 CHCR_CLR_MRDY_IE = (1 << 22),
337 CHCR_SET_DRDY_IE = (1 << 21),
338 CHCR_CLR_DRDY_IE = (1 << 20),
339 CHCR_SET_LC_IE = (1 << 19),
340 CHCR_CLR_LC_IE = (1 << 18),
341 CHCR_SET_CONT_RB_IE = (1 << 17),
342 CHCR_CLR_CONT_RB_IE = (1 << 16),
343 CHCR_FIFODIS = (1 << 15),
344 CHCR_FIFO_ON = 0,
345 CHCR_BURSTEN = (1 << 14),
346 CHCR_NO_BURSTEN = 0,
347 CHCR_BYTE_SWAP_DEVICE = (1 << 6),
348 CHCR_BYTE_SWAP_MEMORY = (1 << 4),
349 CHCR_DIR = (1 << 3),
350 CHCR_DEV_TO_MEM = CHCR_DIR,
351 CHCR_MEM_TO_DEV = 0,
352 CHCR_NORMAL = (0 << 0),
353 CHCR_CONTINUE = (1 << 0),
354 CHCR_RINGBUFF = (2 << 0),
355 CHCR_LINKSHORT = (4 << 0),
356 CHCR_LINKLONG = (5 << 0),
357 CHCRPON =
358 (CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
359 CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
360 CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE),
361};
362
363enum ConfigRegister_bits {
364 CR_REQS_MASK = 0x7 << 16,
365 CR_ASEQDONT = 0x0 << 10,
366 CR_ASEQUP = 0x1 << 10,
367 CR_ASEQDOWN = 0x2 << 10,
368 CR_ASEQ_MASK = 0x3 << 10,
369 CR_PSIZE8 = (1 << 8),
370 CR_PSIZE16 = (2 << 8),
371 CR_PSIZE32 = (3 << 8),
372 CR_PORTCPU = (0 << 6),
373 CR_PORTIO = (1 << 6),
374 CR_PORTVXI = (2 << 6),
375 CR_PORTMXI = (3 << 6),
376 CR_AMDEVICE = (1 << 0),
377};
378static inline int CR_REQS(int source)
379{
380 return (source & 0x7) << 16;
381};
382
383static inline int CR_REQSDRQ(unsigned drq_line)
384{
385
386
387 return CR_REQS((drq_line & 0x3) | 0x4);
388}
389
390static inline int CR_RL(unsigned int retry_limit)
391{
392 int value = 0;
393
394 if (retry_limit)
395 value = 1 + ilog2(retry_limit);
396 if (value > 0x7)
397 value = 0x7;
398 return (value & 0x7) << 21;
399}
400
401enum CHSR_bits {
402 CHSR_INT = (1 << 31),
403 CHSR_LPAUSES = (1 << 29),
404 CHSR_SARS = (1 << 27),
405 CHSR_DONE = (1 << 25),
406 CHSR_MRDY = (1 << 23),
407 CHSR_DRDY = (1 << 21),
408 CHSR_LINKC = (1 << 19),
409 CHSR_CONTS_RB = (1 << 17),
410 CHSR_ERROR = (1 << 15),
411 CHSR_SABORT = (1 << 14),
412 CHSR_HABORT = (1 << 13),
413 CHSR_STOPS = (1 << 12),
414 CHSR_OPERR_mask = (3 << 10),
415 CHSR_OPERR_NOERROR = (0 << 10),
416 CHSR_OPERR_FIFOERROR = (1 << 10),
417 CHSR_OPERR_LINKERROR = (1 << 10),
418 CHSR_XFERR = (1 << 9),
419 CHSR_END = (1 << 8),
420 CHSR_DRQ1 = (1 << 7),
421 CHSR_DRQ0 = (1 << 6),
422 CHSR_LxERR_mask = (3 << 4),
423 CHSR_LBERR = (1 << 4),
424 CHSR_LRERR = (2 << 4),
425 CHSR_LOERR = (3 << 4),
426 CHSR_MxERR_mask = (3 << 2),
427 CHSR_MBERR = (1 << 2),
428 CHSR_MRERR = (2 << 2),
429 CHSR_MOERR = (3 << 2),
430 CHSR_DxERR_mask = (3 << 0),
431 CHSR_DBERR = (1 << 0),
432 CHSR_DRERR = (2 << 0),
433 CHSR_DOERR = (3 << 0),
434};
435
436static inline void mite_dma_reset(struct mite_channel *mite_chan)
437{
438 writel(CHOR_DMARESET | CHOR_FRESET,
439 mite_chan->mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
440};
441
442#endif
443