LXR linux/drivers/staging/cxt1e1/comet.c

   1/* Copyright (C) 2003-2005  SBE, Inc.
   2 *
   3 *   This program is free software; you can redistribute it and/or modify
   4 *   it under the terms of the GNU General Public License as published by
   5 *   the Free Software Foundation; either version 2 of the License, or
   6 *   (at your option) any later version.
   7 *
   8 *   This program is distributed in the hope that it will be useful,
   9 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  10 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11 *   GNU General Public License for more details.
  12 */
  13
  14#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  15
  16#include <linux/io.h>
  17#include <linux/hdlc.h>
  18#include "pmcc4_sysdep.h"
  19#include "sbecom_inline_linux.h"
  20#include "libsbew.h"
  21#include "pmcc4.h"
  22#include "comet.h"
  23#include "comet_tables.h"
  24
  25extern int  cxt1e1_log_level;
  26
  27#define COMET_NUM_SAMPLES   24  /* Number of entries in the waveform table */
  28#define COMET_NUM_UNITS     5   /* Number of points per entry in table */
  29
  30/* forward references */
  31static void SetPwrLevel(comet_t *comet);
  32static void WrtRcvEqualizerTbl(ci_t *ci, comet_t *comet, u_int32_t *table);
  33static void WrtXmtWaveformTbl(ci_t *ci, comet_t *comet, u_int8_t table[COMET_NUM_SAMPLES][COMET_NUM_UNITS]);
  34
  35
  36void       *TWV_table[12] = {
  37        TWVLongHaul0DB, TWVLongHaul7_5DB, TWVLongHaul15DB, TWVLongHaul22_5DB,
  38        TWVShortHaul0, TWVShortHaul1, TWVShortHaul2, TWVShortHaul3,
  39        TWVShortHaul4, TWVShortHaul5,
  40        /** PORT POINT - 75 Ohm not supported **/
  41        TWV_E1_75Ohm,
  42        TWV_E1_120Ohm
  43};
  44
  45
  46static int
  47lbo_tbl_lkup(int t1, int lbo) {
  48        /* error switches to default */
  49        if ((lbo < CFG_LBO_LH0) || (lbo > CFG_LBO_E120)) {
  50                if (t1)
  51                        /* default T1 waveform table */
  52                        lbo = CFG_LBO_LH0;
  53                else
  54                        /* default E1 waveform table */
  55                        lbo = CFG_LBO_E120;
  56        }
  57        /* make index ZERO relative */
  58        return lbo - 1;
  59}
  60
  61void init_comet(void *ci, comet_t *comet, u_int32_t port_mode, int clockmaster,
  62                u_int8_t moreParams)
  63{
  64        u_int8_t isT1mode;
  65        /* T1 default */
  66        u_int8_t    tix = CFG_LBO_LH0;
  67        isT1mode = IS_FRAME_ANY_T1(port_mode);
  68        /* T1 or E1 */
  69        if (isT1mode) {
  70                /* Select T1 Mode & PIO output enabled */
  71                pci_write_32((u_int32_t *) &comet->gbl_cfg, 0xa0);
  72                /* default T1 waveform table */
  73                tix = lbo_tbl_lkup(isT1mode, CFG_LBO_LH0);
  74        } else {
  75                /* Select E1 Mode & PIO output enabled */
  76                pci_write_32((u_int32_t *) &comet->gbl_cfg, 0x81);
  77                /* default E1 waveform table */
  78                tix = lbo_tbl_lkup(isT1mode, CFG_LBO_E120);
  79        }
  80
  81        if (moreParams & CFG_LBO_MASK)
  82                /* dial-in requested waveform table */
  83                tix = lbo_tbl_lkup(isT1mode, moreParams & CFG_LBO_MASK);
  84        /* Tx line Intfc cfg Set for analog & no special patterns */
  85        /* Transmit Line Interface Config. */
  86        pci_write_32((u_int32_t *) &comet->tx_line_cfg, 0x00);
  87        /* master test Ignore Test settings for now */
  88        /* making sure it's Default value */
  89        pci_write_32((u_int32_t *) &comet->mtest, 0x00);
  90        /* Turn on Center (CENT) and everything else off */
  91        /* RJAT cfg */
  92        pci_write_32((u_int32_t *) &comet->rjat_cfg, 0x10);
  93        /* Set Jitter Attenuation to recommend T1 values */
  94        if (isT1mode) {
  95                /* RJAT Divider N1 Control */
  96                pci_write_32((u_int32_t *) &comet->rjat_n1clk, 0x2F);
  97                /* RJAT Divider N2 Control */
  98                pci_write_32((u_int32_t *) &comet->rjat_n2clk, 0x2F);
  99        } else {
 100                /* RJAT Divider N1 Control */
 101                pci_write_32((u_int32_t *) &comet->rjat_n1clk, 0xFF);
 102                /* RJAT Divider N2 Control */
 103                pci_write_32((u_int32_t *) &comet->rjat_n2clk, 0xFF);
 104        }
 105
 106        /* Turn on Center (CENT) and everything else off */
 107        /* TJAT Config. */
 108        pci_write_32((u_int32_t *) &comet->tjat_cfg, 0x10);
 109
 110        /* Do not bypass jitter attenuation and bypass elastic store */
 111        /* rx opts */
 112        pci_write_32((u_int32_t *) &comet->rx_opt, 0x00);
 113
 114        /* TJAT ctrl & TJAT divider ctrl */
 115        /* Set Jitter Attenuation to recommended T1 values */
 116        if (isT1mode) {
 117                /* TJAT Divider N1 Control */
 118                pci_write_32((u_int32_t *) &comet->tjat_n1clk, 0x2F);
 119                /* TJAT Divider N2  Control */
 120                pci_write_32((u_int32_t *) &comet->tjat_n2clk, 0x2F);
 121        } else {
 122                /* TJAT Divider N1 Control */
 123                pci_write_32((u_int32_t *) &comet->tjat_n1clk, 0xFF);
 124                /* TJAT Divider N2 Control */
 125                pci_write_32((u_int32_t *) &comet->tjat_n2clk, 0xFF);
 126        }
 127
 128        /* 1c: rx ELST cfg   20: tx ELST cfg  28&38: rx&tx data link ctrl */
 129
 130        /* Select 193-bit frame format */
 131        if (isT1mode) {
 132                pci_write_32((u_int32_t *) &comet->rx_elst_cfg, 0x00);
 133                pci_write_32((u_int32_t *) &comet->tx_elst_cfg, 0x00);
 134        } else {
 135                /* Select 256-bit frame format */
 136                pci_write_32((u_int32_t *) &comet->rx_elst_cfg, 0x03);
 137                pci_write_32((u_int32_t *) &comet->tx_elst_cfg, 0x03);
 138                /* disable T1 data link receive */
 139                pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x00);
 140                /* disable T1 data link transmit */
 141                pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x00);
 142        }
 143
 144    /* the following is a default value */
 145    /* Enable 8 out of 10 validation */
 146         /* t1RBOC enable(BOC:BitOriented Code) */
 147        pci_write_32((u_int32_t *) &comet->t1_rboc_ena, 0x00);
 148        if (isT1mode)
 149        {
 150
 151        /* IBCD cfg: aka Inband Code Detection ** loopback code length set to */
 152                /* 6 bit down, 5 bit up (assert) */
 153                pci_write_32((u_int32_t *) &comet->ibcd_cfg, 0x04);
 154                /* line loopback activate pattern */
 155                pci_write_32((u_int32_t *) &comet->ibcd_act, 0x08);
 156                /* deactivate code pattern (i.e.001) */
 157                pci_write_32((u_int32_t *) &comet->ibcd_deact, 0x24);
 158        }
 159    /* 10: CDRC cfg 28&38: rx&tx data link 1 ctrl 48: t1 frmr cfg  */
 160    /* 50: SIGX cfg, COSS (change of signaling state) 54: XBAS cfg  */
 161    /* 60: t1 ALMI cfg */
 162    /* Configure Line Coding */
 163
 164        switch (port_mode)
 165        {
 166        /* 1 - T1 B8ZS */
 167        case CFG_FRAME_SF:
 168                pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
 169                pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0);
 170                pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 171                /* 5:B8ZS */
 172                pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x20);
 173                pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0);
 174                break;
 175        /* 2 - T1 B8ZS */
 176        case CFG_FRAME_ESF:
 177                pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
 178                /* Bit 5: T1 DataLink Enable */
 179                pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x20);
 180                /* 5: T1 DataLink Enable */
 181                pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x20);
 182                /* 4:ESF  5:ESFFA */
 183                pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0x30);
 184                /* 2:ESF */
 185                pci_write_32((u_int32_t *) &comet->sigx_cfg, 0x04);
 186                /* 4:ESF  5:B8ZS */
 187                pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x30);
 188                /* 4:ESF */
 189                pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0x10);
 190                break;
 191        /* 3 - HDB3 */
 192        case CFG_FRAME_E1PLAIN:
 193                pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
 194                pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 195                pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0);
 196                pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x40);
 197                break;
 198        /* 4 - HDB3 */
 199        case CFG_FRAME_E1CAS:
 200                pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
 201                pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 202                pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x60);
 203                pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0);
 204                break;
 205        /* 5 - HDB3 */
 206        case CFG_FRAME_E1CRC:
 207                pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
 208                pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 209                pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x10);
 210                pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0xc2);
 211                break;
 212        /* 6 - HDB3 */
 213        case CFG_FRAME_E1CRC_CAS:
 214                pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
 215                pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 216                pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x70);
 217                pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x82);
 218                break;
 219        /* 7 - T1 AMI */
 220        case CFG_FRAME_SF_AMI:
 221                /* Enable AMI Line Decoding */
 222                pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
 223                pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0);
 224                pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0);
 225                pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0);
 226                pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 227                break;
 228        /* 8 - T1 AMI */
 229        case CFG_FRAME_ESF_AMI:
 230                /* Enable AMI Line Decoding */
 231                pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
 232                /* 5: T1 DataLink Enable */
 233                pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x20);
 234                /* 5: T1 DataLink Enable */
 235                pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x20);
 236                /* Bit 4:ESF  5:ESFFA */
 237                pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0x30);
 238                /* 2:ESF */
 239                pci_write_32((u_int32_t *) &comet->sigx_cfg, 0x04);
 240                /* 4:ESF */
 241                pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x10);
 242                /* 4:ESF */
 243                pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0x10);
 244                break;
 245        /* 9 - AMI */
 246        case CFG_FRAME_E1PLAIN_AMI:
 247                /* Enable AMI Line Decoding */
 248                pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
 249                pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 250                pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x80);
 251                pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x40);
 252                break;
 253        /* 10 - AMI */
 254        case CFG_FRAME_E1CAS_AMI:
 255                /* Enable AMI Line Decoding */
 256                pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
 257                pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 258                pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0xe0);
 259                pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0);
 260                break;
 261        /* 11 - AMI */
 262        case CFG_FRAME_E1CRC_AMI:
 263                /* Enable AMI Line Decoding */
 264                pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
 265                pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 266                pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x90);
 267                pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0xc2);
 268                break;
 269        /* 12 - AMI */
 270        case CFG_FRAME_E1CRC_CAS_AMI:
 271                /* Enable AMI Line Decoding */
 272                pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
 273                pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 274                pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0xf0);
 275                pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x82);
 276                break;
 277        }       /* end switch */
 278
 279    /***
 280     * Set Full Frame mode (NXDSO[1] = 0, NXDSO[0] = 0)
 281     * CMODE=1: Clock slave mode with BRCLK as an input,
 282     * DE=0: Use falling edge of BRCLK for data,
 283     * FE=0: Use falling edge of BRCLK for frame,
 284     * CMS=0: Use backplane freq,
 285     * RATE[1:0]=0,0: T1
 286     ***/
 287
 288
 289    /* 0x30: "BRIF cfg"; 0x20 is 'CMODE', 0x03 is (bit) rate */
 290    /* note "rate bits can only be set once after reset" */
 291        if (clockmaster)
 292                {
 293                /* CMODE == clockMode, 0=clock master (so all 3 others should be slave) */
 294                /* rate = 1.544 Mb/s */
 295                if (isT1mode)
 296                        /* Comet 0 Master Mode(CMODE=0) */
 297                        pci_write_32((u_int32_t *) &comet->brif_cfg, 0x00);
 298                /* rate = 2.048 Mb/s */
 299                else
 300                        /* Comet 0 Master Mode(CMODE=0) */
 301                        pci_write_32((u_int32_t *) &comet->brif_cfg, 0x01);
 302
 303                /* 31: BRIF frame pulse cfg  06: tx timing options */
 304
 305                /* Master Mode i.e.FPMODE=0 (@0x20) */
 306                pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x00);
 307                if ((moreParams & CFG_CLK_PORT_MASK) == CFG_CLK_PORT_INTERNAL)
 308                        {
 309                        if (cxt1e1_log_level >= LOG_SBEBUG12)
 310                                pr_info(">> %s: clockmaster internal clock\n", __func__);
 311                        /* internal oscillator */
 312                        pci_write_32((u_int32_t *) &comet->tx_time, 0x0d);
 313                } else {
 314                        /* external clock source */
 315                        if (cxt1e1_log_level >= LOG_SBEBUG12)
 316                                pr_info(">> %s: clockmaster external clock\n", __func__);
 317                        /* loop timing(external) */
 318                        pci_write_32((u_int32_t *) &comet->tx_time, 0x09);
 319                }
 320
 321        } else  {
 322                /* slave */
 323                if (isT1mode)
 324                        /* Slave Mode(CMODE=1, see above) */
 325                        pci_write_32((u_int32_t *) &comet->brif_cfg, 0x20);
 326                else
 327                        /* Slave Mode(CMODE=1)*/
 328                        pci_write_32((u_int32_t *) &comet->brif_cfg, 0x21);
 329                /* Slave Mode i.e. FPMODE=1 (@0x20) */
 330                pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x20);
 331        if (cxt1e1_log_level >= LOG_SBEBUG12)
 332                pr_info(">> %s: clockslave internal clock\n", __func__);
 333        /* oscillator timing */
 334        pci_write_32((u_int32_t *) &comet->tx_time, 0x0d);
 335        }
 336
 337        /* 32: BRIF parity F-bit cfg */
 338        /* Totem-pole operation */
 339        /* Receive Backplane Parity/F-bit */
 340        pci_write_32((u_int32_t *) &comet->brif_pfcfg, 0x01);
 341
 342    /* dc: RLPS equalizer V ref */
 343    /* Configuration */
 344        if (isT1mode)
 345                /* RLPS Equalizer Voltage  */
 346                pci_write_32((u_int32_t *) &comet->rlps_eqvr, 0x2c);
 347        else
 348                /* RLPS Equalizer Voltage  */
 349                pci_write_32((u_int32_t *) &comet->rlps_eqvr, 0x34);
 350
 351    /* Reserved bit set and SQUELCH enabled */
 352    /* f8: RLPS cfg & status  f9: RLPS ALOS detect/clear threshold */
 353        /* RLPS Configuration Status */
 354        pci_write_32((u_int32_t *) &comet->rlps_cfgsts, 0x11);
 355        if (isT1mode)
 356                 /* ? */
 357                pci_write_32((u_int32_t *) &comet->rlps_alos_thresh, 0x55);
 358        else
 359                /* ? */
 360                pci_write_32((u_int32_t *) &comet->rlps_alos_thresh, 0x22);
 361
 362
 363    /* Set Full Frame mode (NXDSO[1] = 0, NXDSO[0] = 0) */
 364    /* CMODE=0: Clock slave mode with BTCLK as an input, DE=1: Use rising */
 365    /* edge of BTCLK for data, FE=1: Use rising edge of BTCLK for frame, */
 366    /* CMS=0: Use backplane freq, RATE[1:0]=0,0: T1 */
 367    /***    Transmit side is always an Input, Slave Clock*/
 368    /* 40: BTIF cfg  41: loop timing(external) */
 369        /*BTIF frame pulse cfg */
 370        if (isT1mode)
 371                /* BTIF Configuration  Reg. */
 372                pci_write_32((u_int32_t *) &comet->btif_cfg, 0x38);
 373        else
 374                /* BTIF Configuration  Reg. */
 375                pci_write_32((u_int32_t *) &comet->btif_cfg, 0x39);
 376        /* BTIF Frame Pulse Config. */
 377        pci_write_32((u_int32_t *) &comet->btif_fpcfg, 0x01);
 378
 379    /* 0a: master diag  06: tx timing options */
 380    /* if set Comet to loop back */
 381
 382    /* Comets set to normal */
 383        pci_write_32((u_int32_t *) &comet->mdiag, 0x00);
 384
 385    /* BTCLK driven by TCLKI internally (crystal driven) and Xmt Elasted  */
 386    /* Store is enabled. */
 387
 388        WrtXmtWaveformTbl(ci, comet, TWV_table[tix]);
 389        if (isT1mode)
 390                WrtRcvEqualizerTbl((ci_t *) ci, comet, &T1_Equalizer[0]);
 391        else
 392                WrtRcvEqualizerTbl((ci_t *) ci, comet, &E1_Equalizer[0]);
 393        SetPwrLevel(comet);
 394}
 395
 396/*
 397** Name:        WrtXmtWaveform
 398** Description: Formulate the Data for the Pulse Waveform Storage
 399**                Write register, (F2), from the sample and unit inputs.
 400**                Write the data to the Pulse Waveform Storage Data register.
 401** Returns:     Nothing
 402*/
 403static void
 404WrtXmtWaveform(ci_t *ci, comet_t *comet, u_int32_t sample, u_int32_t unit, u_int8_t data)
 405{
 406        u_int8_t    WaveformAddr;
 407
 408        WaveformAddr = (sample << 3) + (unit & 7);
 409        pci_write_32((u_int32_t *) &comet->xlpg_pwave_addr, WaveformAddr);
 410        /* for write order preservation when Optimizing driver */
 411        pci_flush_write(ci);
 412        pci_write_32((u_int32_t *) &comet->xlpg_pwave_data, 0x7F & data);
 413}
 414
 415/*
 416** Name:        WrtXmtWaveformTbl
 417** Description: Fill in the Transmit Waveform Values
 418**                for driving the transmitter DAC.
 419** Returns:     Nothing
 420*/
 421static void
 422WrtXmtWaveformTbl(ci_t *ci, comet_t *comet,
 423                  u_int8_t table[COMET_NUM_SAMPLES][COMET_NUM_UNITS])
 424{
 425        u_int32_t sample, unit;
 426
 427        for (sample = 0; sample < COMET_NUM_SAMPLES; sample++)
 428                {
 429                for (unit = 0; unit < COMET_NUM_UNITS; unit++)
 430                        WrtXmtWaveform(ci, comet, sample, unit, table[sample][unit]);
 431                }
 432
 433    /* Enable transmitter and set output amplitude */
 434        pci_write_32((u_int32_t *) &comet->xlpg_cfg, table[COMET_NUM_SAMPLES][0]);
 435}
 436
 437
 438/*
 439** Name:        WrtXmtWaveform
 440** Description: Fill in the Receive Equalizer RAM from the desired
 441**                table.
 442** Returns:     Nothing
 443**
 444** Remarks:  Per PM4351 Device Errata, Receive Equalizer RAM Initialization
 445**           is coded with early setup of indirect address.
 446*/
 447
 448static void
 449WrtRcvEqualizerTbl(ci_t *ci, comet_t *comet, u_int32_t *table)
 450{
 451        u_int32_t   ramaddr;
 452        volatile u_int32_t value;
 453
 454        for (ramaddr = 0; ramaddr < 256; ramaddr++) {
 455        /*** the following lines are per Errata 7, 2.5 ***/
 456                {
 457                /* Set up for a read operation */
 458                pci_write_32((u_int32_t *) &comet->rlps_eq_rwsel, 0x80);
 459                /* for write order preservation when Optimizing driver */
 460                pci_flush_write(ci);
 461                /* write the addr, initiate a read */
 462                pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr, (u_int8_t) ramaddr);
 463                /* for write order preservation when Optimizing driver */
 464                pci_flush_write(ci);
 465                /*
 466                * wait 3 line rate clock cycles to ensure address bits are
 467                * captured by T1/E1 clock
 468                */
 469
 470                /* 683ns * 3 = 1366 ns, approx 2us (but use 4us) */
 471                OS_uwait(4, "wret");
 472        }
 473
 474        value = *table++;
 475        pci_write_32((u_int32_t *) &comet->rlps_idata3, (u_int8_t) (value >> 24));
 476        pci_write_32((u_int32_t *) &comet->rlps_idata2, (u_int8_t) (value >> 16));
 477        pci_write_32((u_int32_t *) &comet->rlps_idata1, (u_int8_t) (value >> 8));
 478        pci_write_32((u_int32_t *) &comet->rlps_idata0, (u_int8_t) value);
 479         /* for write order preservation when Optimizing driver */
 480        pci_flush_write(ci);
 481
 482        /* Storing RAM address, causes RAM to be updated */
 483
 484                /* Set up for a write operation */
 485                pci_write_32((u_int32_t *) &comet->rlps_eq_rwsel, 0);
 486                /* for write order preservation when optimizing driver */
 487                pci_flush_write(ci);
 488                /* write the addr, initiate a read */
 489                pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr, (u_int8_t) ramaddr);
 490                 /* for write order preservation when optimizing driver */
 491                pci_flush_write(ci);
 492
 493        /*
 494        * wait 3 line rate clock cycles to ensure address bits are captured
 495        * by T1/E1 clock
 496        */
 497                /* 683ns * 3 = 1366 ns, approx 2us (but use 4us) */
 498                OS_uwait(4, "wret");
 499        }
 500
 501        /* Enable Equalizer & set it to use 256 periods */
 502        pci_write_32((u_int32_t *) &comet->rlps_eq_cfg, 0xCB);
 503}
 504
 505
 506/*
 507** Name:        SetPwrLevel
 508** Description: Implement power level setting algorithm described below
 509** Returns:     Nothing
 510*/
 511
 512static void
 513SetPwrLevel(comet_t *comet)
 514{
 515        volatile u_int32_t temp;
 516
 517/*
 518**    Algorithm to Balance the Power Distribution of Ttip Tring
 519**
 520**    Zero register F6
 521**    Write 0x01 to register F4
 522**    Write another 0x01 to register F4
 523**    Read register F4
 524**    Remove the 0x01 bit by Anding register F4 with 0xFE
 525**    Write the resultant value to register F4
 526**    Repeat these steps for register F5
 527**    Write 0x01 to register F6
 528*/
 529        /* XLPG Fuse Data Select */
 530        pci_write_32((u_int32_t *) &comet->xlpg_fdata_sel, 0x00);
 531        /* XLPG Analog Test Positive control */
 532        pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, 0x01);
 533        pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, 0x01);
 534        temp = pci_read_32((u_int32_t *) &comet->xlpg_atest_pctl) & 0xfe;
 535        pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, temp);
 536        pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, 0x01);
 537        pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, 0x01);
 538        /* XLPG Analog Test Negative control */
 539        temp = pci_read_32((u_int32_t *) &comet->xlpg_atest_nctl) & 0xfe;
 540        pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, temp);
 541        /* XLPG */
 542        pci_write_32((u_int32_t *) &comet->xlpg_fdata_sel, 0x01);
 543}
 544
 545
 546/*
 547** Name:        SetCometOps
 548** Description: Set up the selected Comet's clock edge drive for both
 549**                the transmit out the analog side and receive to the
 550**                backplane side.
 551** Returns:     Nothing
 552*/
 553#if 0
 554static void
 555SetCometOps(comet_t *comet)
 556{
 557        volatile u_int8_t rd_value;
 558
 559        if (comet == mConfig.C4Func1Base + (COMET0_OFFSET >> 2))
 560        {
 561                /* read the BRIF Configuration */
 562                rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_cfg);
 563                rd_value &= ~0x20;
 564                pci_write_32((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value);
 565                /* read the BRIF Frame Pulse Configuration */
 566                rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_fpcfg);
 567                rd_value &= ~0x20;
 568                pci_write_32((u_int32_t *) &comet->brif_fpcfg, (u_int8_t) rd_value);
 569        } else {
 570        /* read the BRIF Configuration */
 571        rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_cfg);
 572        rd_value |= 0x20;
 573        pci_write_32((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value);
 574        /* read the BRIF Frame Pulse Configuration */
 575        rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_fpcfg);
 576        rd_value |= 0x20;
 577        pci_write_32(u_int32_t *) & comet->brif_fpcfg, (u_int8_t) rd_value);
 578        }
 579}
 580#endif
 581
 582/***  End-of-File  ***/
 583