1#ifndef _INC_MUSYCC_H_ 2#define _INC_MUSYCC_H_ 3 4/*----------------------------------------------------------------------------- 5 * musycc.h - Multichannel Synchronous Communications Controller 6 * CN8778/8474A/8472A/8471A 7 * 8 * Copyright (C) 2002-2005 SBE, Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * For further information, contact via email: support@sbei.com 21 * SBE, Inc. San Ramon, California U.S.A. 22 *----------------------------------------------------------------------------- 23 */ 24 25#include <linux/types.h> 26 27#define VINT8 volatile u_int8_t 28#define VINT32 volatile u_int32_t 29 30#include "pmcc4_defs.h" 31 32 33/*------------------------------------------------------------------------ 34// Vendor, Board Identification definitions 35//------------------------------------------------------------------------ 36*/ 37 38#define PCI_VENDOR_ID_CONEXANT 0x14f1 39#define PCI_DEVICE_ID_CN8471 0x8471 40#define PCI_DEVICE_ID_CN8472 0x8472 41#define PCI_DEVICE_ID_CN8474 0x8474 42#define PCI_DEVICE_ID_CN8478 0x8478 43#define PCI_DEVICE_ID_CN8500 0x8500 44#define PCI_DEVICE_ID_CN8501 0x8501 45#define PCI_DEVICE_ID_CN8502 0x8502 46#define PCI_DEVICE_ID_CN8503 0x8503 47 48#define INT_QUEUE_SIZE MUSYCC_NIQD 49 50/* RAM image of MUSYCC registers laid out as a C structure */ 51struct musycc_groupr { 52 VINT32 thp[32]; /* Transmit Head Pointer [5-29] */ 53 VINT32 tmp[32]; /* Transmit Message Pointer [5-30] */ 54 VINT32 rhp[32]; /* Receive Head Pointer [5-29] */ 55 VINT32 rmp[32]; /* Receive Message Pointer [5-30] */ 56 VINT8 ttsm[128]; /* Time Slot Map [5-22] */ 57 VINT8 tscm[256]; /* Subchannel Map [5-24] */ 58 VINT32 tcct[32]; /* Channel Configuration [5-26] */ 59 VINT8 rtsm[128]; /* Time Slot Map [5-22] */ 60 VINT8 rscm[256]; /* Subchannel Map [5-24] */ 61 VINT32 rcct[32]; /* Channel Configuration [5-26] */ 62 VINT32 __glcd; /* Global Configuration Descriptor [5-10] */ 63 VINT32 __iqp; /* Interrupt Queue Pointer [5-36] */ 64 VINT32 __iql; /* Interrupt Queue Length [5-36] */ 65 VINT32 grcd; /* Group Configuration Descriptor [5-16] */ 66 VINT32 mpd; /* Memory Protection Descriptor [5-18] */ 67 VINT32 mld; /* Message Length Descriptor [5-20] */ 68 VINT32 pcd; /* Port Configuration Descriptor [5-19] */ 69}; 70 71/* hardware MUSYCC registers laid out as a C structure */ 72struct musycc_globalr { 73 VINT32 gbp; /* Group Base Pointer */ 74 VINT32 dacbp; /* Dual Address Cycle Base Pointer */ 75 VINT32 srd; /* Service Request Descriptor */ 76 VINT32 isd; /* Interrupt Service Descriptor */ 77 /* 78 * adjust __thp due to above 4 registers, which are not contained 79 * within musycc_groupr[]. All __XXX[] are just place holders, 80 * anyhow. 81 */ 82 VINT32 __thp[32 - 4]; /* Transmit Head Pointer [5-29] */ 83 VINT32 __tmp[32]; /* Transmit Message Pointer [5-30] */ 84 VINT32 __rhp[32]; /* Receive Head Pointer [5-29] */ 85 VINT32 __rmp[32]; /* Receive Message Pointer [5-30] */ 86 VINT8 ttsm[128]; /* Time Slot Map [5-22] */ 87 VINT8 tscm[256]; /* Subchannel Map [5-24] */ 88 VINT32 tcct[32]; /* Channel Configuration [5-26] */ 89 VINT8 rtsm[128]; /* Time Slot Map [5-22] */ 90 VINT8 rscm[256]; /* Subchannel Map [5-24] */ 91 VINT32 rcct[32]; /* Channel Configuration [5-26] */ 92 VINT32 glcd; /* Global Configuration Descriptor [5-10] */ 93 VINT32 iqp; /* Interrupt Queue Pointer [5-36] */ 94 VINT32 iql; /* Interrupt Queue Length [5-36] */ 95 VINT32 grcd; /* Group Configuration Descriptor [5-16] */ 96 VINT32 mpd; /* Memory Protection Descriptor [5-18] */ 97 VINT32 mld; /* Message Length Descriptor [5-20] */ 98 VINT32 pcd; /* Port Configuration Descriptor [5-19] */ 99 VINT32 rbist; /* Receive BIST status [5-4] */ 100 VINT32 tbist; /* Receive BIST status [5-4] */ 101}; 102 103/* Global Config Descriptor bit macros */ 104#define MUSYCC_GCD_ECLK_ENABLE 0x00000800 /* EBUS clock enable */ 105#define MUSYCC_GCD_INTEL_SELECT 0x00000400 /* MPU type select */ 106#define MUSYCC_GCD_INTA_DISABLE 0x00000008 /* PCI INTA disable */ 107#define MUSYCC_GCD_INTB_DISABLE 0x00000004 /* PCI INTB disable */ 108#define MUSYCC_GCD_BLAPSE 12 /* Position index for BLAPSE bit 109 * field */ 110#define MUSYCC_GCD_ALAPSE 8 /* Position index for ALAPSE bit 111 * field */ 112#define MUSYCC_GCD_ELAPSE 4 /* Position index for ELAPSE bit 113 * field */ 114#define MUSYCC_GCD_PORTMAP_3 3 /* Reserved */ 115#define MUSYCC_GCD_PORTMAP_2 2 /* Port 0=>Grp 0,1,2,3; Port 1=>Grp 116 * 4,5,6,7 */ 117#define MUSYCC_GCD_PORTMAP_1 1 /* Port 0=>Grp 0,1; Port 1=>Grp 2,3, 118 * etc... */ 119#define MUSYCC_GCD_PORTMAP_0 0 /* Port 0=>Grp 0; Port 1=>Grp 2, 120 * etc... */ 121 122/* and board specific assignments... */ 123#ifdef SBE_WAN256T3_ENABLE 124#define BLAPSE_VAL 0 125#define ALAPSE_VAL 0 126#define ELAPSE_VAL 7 127#define PORTMAP_VAL MUSYCC_GCD_PORTMAP_2 128#endif 129 130#ifdef SBE_PMCC4_ENABLE 131#define BLAPSE_VAL 7 132#define ALAPSE_VAL 3 133#define ELAPSE_VAL 7 134#define PORTMAP_VAL MUSYCC_GCD_PORTMAP_0 135#endif 136 137#define GCD_MAGIC (((BLAPSE_VAL)<<(MUSYCC_GCD_BLAPSE)) | \ 138 ((ALAPSE_VAL)<<(MUSYCC_GCD_ALAPSE)) | \ 139 ((ELAPSE_VAL)<<(MUSYCC_GCD_ELAPSE)) | \ 140 (MUSYCC_GCD_ECLK_ENABLE) | PORTMAP_VAL) 141 142/* Group Config Descriptor bit macros */ 143#define MUSYCC_GRCD_RX_ENABLE 0x00000001 /* Enable receive processing */ 144#define MUSYCC_GRCD_TX_ENABLE 0x00000002 /* Enable transmit processing */ 145#define MUSYCC_GRCD_SUBCHAN_DISABLE 0x00000004 /* Master disable for 146 * subchanneling */ 147#define MUSYCC_GRCD_OOFMP_DISABLE 0x00000008 /* Out of Frame message 148 * processing disabled all 149 * channels */ 150#define MUSYCC_GRCD_OOFIRQ_DISABLE 0x00000010 /* Out of Frame/In Frame irqs 151 * disabled */ 152#define MUSYCC_GRCD_COFAIRQ_DISABLE 0x00000020 /* Change of Frame Alignment 153 * irq disabled */ 154#define MUSYCC_GRCD_INHRBSD 0x00000100 /* Receive Buffer Status 155 * overwrite disabled */ 156#define MUSYCC_GRCD_INHTBSD 0x00000200 /* Transmit Buffer Status 157 * overwrite disabled */ 158#define MUSYCC_GRCD_SF_ALIGN 0x00008000 /* External frame sync */ 159#define MUSYCC_GRCD_MC_ENABLE 0x00000040 /* Message configuration bits 160 * copy enable. Conexant sez 161 * turn this on */ 162#define MUSYCC_GRCD_POLLTH_16 0x00000001 /* Poll every 16th frame */ 163#define MUSYCC_GRCD_POLLTH_32 0x00000002 /* Poll every 32nd frame */ 164#define MUSYCC_GRCD_POLLTH_64 0x00000003 /* Poll every 64th frame */ 165#define MUSYCC_GRCD_POLLTH_SHIFT 10 /* Position index for poll throttle 166 * bit field */ 167#define MUSYCC_GRCD_SUERM_THRESH_SHIFT 16 /* Position index for SUERM 168 * count threshold */ 169 170/* Port Config Descriptor bit macros */ 171#define MUSYCC_PCD_E1X2_MODE 2 /* Port mode in bits 0-2. T1 and E1 */ 172#define MUSYCC_PCD_E1X4_MODE 3 /* are defined in cn847x.h */ 173#define MUSYCC_PCD_NX64_MODE 4 174#define MUSYCC_PCD_TXDATA_RISING 0x00000010 /* Sample Tx data on TCLK 175 * rising edge */ 176#define MUSYCC_PCD_TXSYNC_RISING 0x00000020 /* Sample Tx frame sync on 177 * TCLK rising edge */ 178#define MUSYCC_PCD_RXDATA_RISING 0x00000040 /* Sample Rx data on RCLK 179 * rising edge */ 180#define MUSYCC_PCD_RXSYNC_RISING 0x00000080 /* Sample Rx frame sync on 181 * RCLK rising edge */ 182#define MUSYCC_PCD_ROOF_RISING 0x00000100 /* Sample Rx Out Of Frame 183 * signal on RCLK rising edge */ 184#define MUSYCC_PCD_TX_DRIVEN 0x00000200 /* No mapped timeslots causes 185 * logic 1 on output, else 186 * tristate */ 187#define MUSYCC_PCD_PORTMODE_MASK 0xfffffff8 /* For changing the port mode 188 * between E1 and T1 */ 189 190/* Time Slot Descriptor bit macros */ 191#define MUSYCC_TSD_MODE_64KBPS 4 192#define MUSYCC_TSD_MODE_56KBPS 5 193#define MUSYCC_TSD_SUBCHANNEL_WO_FIRST 6 194#define MUSYCC_TSD_SUBCHANNEL_WITH_FIRST 7 195 196/* Message Descriptor bit macros */ 197#define MUSYCC_MDT_BASE03_ADDR 0x00006000 198 199/* Channel Config Descriptor bit macros */ 200#define MUSYCC_CCD_BUFIRQ_DISABLE 0x00000002 /* BUFF and ONR irqs disabled */ 201#define MUSYCC_CCD_EOMIRQ_DISABLE 0x00000004 /* EOM irq disabled */ 202#define MUSYCC_CCD_MSGIRQ_DISABLE 0x00000008 /* LNG, FCS, ALIGN, and ABT 203 * irqs disabled */ 204#define MUSYCC_CCD_IDLEIRQ_DISABLE 0x00000010 /* CHABT, CHIC, and SHT irqs 205 * disabled */ 206#define MUSYCC_CCD_FILTIRQ_DISABLE 0x00000020 /* SFILT irq disabled */ 207#define MUSYCC_CCD_SDECIRQ_DISABLE 0x00000040 /* SDEC irq disabled */ 208#define MUSYCC_CCD_SINCIRQ_DISABLE 0x00000080 /* SINC irq disabled */ 209#define MUSYCC_CCD_SUERIRQ_DISABLE 0x00000100 /* SUERR irq disabled */ 210#define MUSYCC_CCD_FCS_XFER 0x00000200 /* Propagate FCS along with 211 * received data */ 212#define MUSYCC_CCD_PROTO_SHIFT 12 /* Position index for protocol bit 213 * field */ 214#define MUSYCC_CCD_TRANS 0 /* Protocol mode in bits 12-14 */ 215#define MUSYCC_CCD_SS7 1 216#define MUSYCC_CCD_HDLC_FCS16 2 217#define MUSYCC_CCD_HDLC_FCS32 3 218#define MUSYCC_CCD_EOPIRQ_DISABLE 0x00008000 /* EOP irq disabled */ 219#define MUSYCC_CCD_INVERT_DATA 0x00800000 /* Invert data */ 220#define MUSYCC_CCD_MAX_LENGTH 10 /* Position index for max length bit 221 * field */ 222#define MUSYCC_CCD_BUFFER_LENGTH 16 /* Position index for internal data 223 * buffer length */ 224#define MUSYCC_CCD_BUFFER_LOC 24 /* Position index for internal data 225 * buffer starting location */ 226 227/**************************************************************************** 228 * Interrupt Descriptor Information */ 229 230#define INT_EMPTY_ENTRY 0xfeedface 231#define INT_EMPTY_ENTRY2 0xdeadface 232 233/**************************************************************************** 234 * Interrupt Status Descriptor 235 * 236 * NOTE: One must first fetch the value of the interrupt status descriptor 237 * into a local variable, then pass that value into the read macros. This 238 * is required to avoid race conditions. 239 ***/ 240 241#define INTRPTS_NEXTINT_M 0x7FFF0000 242#define INTRPTS_NEXTINT_S 16 243#define INTRPTS_NEXTINT(x) ((x & INTRPTS_NEXTINT_M) >> INTRPTS_NEXTINT_S) 244 245#define INTRPTS_INTFULL_M 0x00008000 246#define INTRPTS_INTFULL_S 15 247#define INTRPTS_INTFULL(x) ((x & INTRPTS_INTFULL_M) >> INTRPTS_INTFULL_S) 248 249#define INTRPTS_INTCNT_M 0x00007FFF 250#define INTRPTS_INTCNT_S 0 251#define INTRPTS_INTCNT(x) ((x & INTRPTS_INTCNT_M) >> INTRPTS_INTCNT_S) 252 253 254/**************************************************************************** 255 * Interrupt Descriptor 256 ***/ 257 258#define INTRPT_DIR_M 0x80000000 259#define INTRPT_DIR_S 31 260#define INTRPT_DIR(x) ((x & INTRPT_DIR_M) >> INTRPT_DIR_S) 261 262#define INTRPT_GRP_M 0x60000000 263#define INTRPT_GRP_MSB_M 0x00004000 264#define INTRPT_GRP_S 29 265#define INTRPT_GRP_MSB_S 12 266#define INTRPT_GRP(x) (((x & INTRPT_GRP_M) >> INTRPT_GRP_S) | \ 267 ((x & INTRPT_GRP_MSB_M) >> INTRPT_GRP_MSB_S)) 268 269#define INTRPT_CH_M 0x1F000000 270#define INTRPT_CH_S 24 271#define INTRPT_CH(x) ((x & INTRPT_CH_M) >> INTRPT_CH_S) 272 273#define INTRPT_EVENT_M 0x00F00000 274#define INTRPT_EVENT_S 20 275#define INTRPT_EVENT(x) ((x & INTRPT_EVENT_M) >> INTRPT_EVENT_S) 276 277#define INTRPT_ERROR_M 0x000F0000 278#define INTRPT_ERROR_S 16 279#define INTRPT_ERROR(x) ((x & INTRPT_ERROR_M) >> INTRPT_ERROR_S) 280 281#define INTRPT_ILOST_M 0x00008000 282#define INTRPT_ILOST_S 15 283#define INTRPT_ILOST(x) ((x & INTRPT_ILOST_M) >> INTRPT_ILOST_S) 284 285#define INTRPT_PERR_M 0x00004000 286#define INTRPT_PERR_S 14 287#define INTRPT_PERR(x) ((x & INTRPT_PERR_M) >> INTRPT_PERR_S) 288 289#define INTRPT_BLEN_M 0x00003FFF 290#define INTRPT_BLEN_S 0 291#define INTRPT_BLEN(x) ((x & INTRPT_BLEN_M) >> INTRPT_BLEN_S) 292 293 294/* Buffer Descriptor bit macros */ 295#define OWNER_BIT 0x80000000 /* Set for MUSYCC owner on xmit, host 296 * owner on receive */ 297#define HOST_TX_OWNED 0x00000000 /* Host owns descriptor */ 298#define MUSYCC_TX_OWNED 0x80000000 /* MUSYCC owns descriptor */ 299#define HOST_RX_OWNED 0x80000000 /* Host owns descriptor */ 300#define MUSYCC_RX_OWNED 0x00000000 /* MUSYCC owns descriptor */ 301 302#define POLL_DISABLED 0x40000000 /* MUSYCC not allowed to poll buffer 303 * for ownership */ 304#define EOMIRQ_ENABLE 0x20000000 /* This buffer contains the end of 305 * the message */ 306#define EOBIRQ_ENABLE 0x10000000 /* EOB irq enabled */ 307#define PADFILL_ENABLE 0x01000000 /* Enable padfill */ 308#define REPEAT_BIT 0x00008000 /* Bit on for FISU descriptor */ 309#define LENGTH_MASK 0X3fff /* This part of status descriptor is 310 * length */ 311#define IDLE_CODE 25 /* Position index for idle code (2 312 * bits) */ 313#define EXTRA_FLAGS 16 /* Position index for minimum flags 314 * between messages (8 bits) */ 315#define IDLE_CODE_MASK 0x03 /* Gets rid of garbage before the 316 * pattern is OR'd in */ 317#define EXTRA_FLAGS_MASK 0xff /* Gets rid of garbage before the 318 * pattern is OR'd in */ 319#define PCI_PERMUTED_OWNER_BIT 0x00000080 /* For flipping the bit on 320 * the polled mode descriptor */ 321 322/* Service Request Descriptor bit macros */ 323#define SREQ 8 /* Position index for service request bit 324 * field */ 325#define SR_NOOP (0<<(SREQ)) /* No Operation. Generates SACK */ 326#define SR_CHIP_RESET (1<<(SREQ)) /* Soft chip reset */ 327#define SR_GROUP_RESET (2<<(SREQ)) /* Group reset */ 328#define SR_GLOBAL_INIT (4<<(SREQ)) /* Global init: read global 329 * config deswc and interrupt 330 * queue desc */ 331#define SR_GROUP_INIT (5<<(SREQ)) /* Group init: read Timeslot 332 * and Subchannel maps, 333 * Channel Config, */ 334 /* 335 * Group Config, Memory Protect, Message Length, and Port Config 336 * Descriptors 337 */ 338#define SR_CHANNEL_ACTIVATE (8<<(SREQ)) /* Init channel, read Head 339 * Pointer, process first 340 * Message Descriptor */ 341#define SR_GCHANNEL_MASK 0x001F /* channel portion (gchan) */ 342#define SR_CHANNEL_DEACTIVATE (9<<(SREQ)) /* Stop channel processing */ 343#define SR_JUMP (10<<(SREQ)) /* a: Process new Message 344 * List */ 345#define SR_CHANNEL_CONFIG (11<<(SREQ)) /* b: Read channel 346 * Configuration Descriptor */ 347#define SR_GLOBAL_CONFIG (16<<(SREQ)) /* 10: Read Global 348 * Configuration Descriptor */ 349#define SR_INTERRUPT_Q (17<<(SREQ)) /* 11: Read Interrupt Queue 350 * Descriptor */ 351#define SR_GROUP_CONFIG (18<<(SREQ)) /* 12: Read Group 352 * Configuration Descriptor */ 353#define SR_MEMORY_PROTECT (19<<(SREQ)) /* 13: Read Memory Protection 354 * Descriptor */ 355#define SR_MESSAGE_LENGTH (20<<(SREQ)) /* 14: Read Message Length 356 * Descriptor */ 357#define SR_PORT_CONFIG (21<<(SREQ)) /* 15: Read Port 358 * Configuration Descriptor */ 359#define SR_TIMESLOT_MAP (24<<(SREQ)) /* 18: Read Timeslot Map */ 360#define SR_SUBCHANNEL_MAP (25<<(SREQ)) /* 19: Read Subchannel Map */ 361#define SR_CHAN_CONFIG_TABLE (26<<(SREQ)) /* 20: Read Channel 362 * Configuration Table for 363 * the group */ 364#define SR_TX_DIRECTION 0x00000020 /* Transmit direction bit. 365 * Bit off indicates receive 366 * direction */ 367#define SR_RX_DIRECTION 0x00000000 368 369/* Interrupt Descriptor bit macros */ 370#define GROUP10 29 /* Position index for the 2 LS group 371 * bits */ 372#define CHANNEL 24 /* Position index for channel bits */ 373#define INT_IQD_TX 0x80000000 374#define INT_IQD_GRP 0x60000000 375#define INT_IQD_CHAN 0x1f000000 376#define INT_IQD_EVENT 0x00f00000 377#define INT_IQD_ERROR 0x000f0000 378#define INT_IQD_ILOST 0x00008000 379#define INT_IQD_PERR 0x00004000 380#define INT_IQD_BLEN 0x00003fff 381 382/* Interrupt Descriptor Events */ 383#define EVE_EVENT 20 /* Position index for event bits */ 384#define EVE_NONE 0 /* No event to report in this 385 * interrupt */ 386#define EVE_SACK 1 /* Service Request acknowledge */ 387#define EVE_EOB 2 /* End of Buffer */ 388#define EVE_EOM 3 /* End of Message */ 389#define EVE_EOP 4 /* End of Padfill */ 390#define EVE_CHABT 5 /* Change to Abort Code */ 391#define EVE_CHIC 6 /* Change to Idle Code */ 392#define EVE_FREC 7 /* Frame Recovery */ 393#define EVE_SINC 8 /* MTP2 SUERM Increment */ 394#define EVE_SDEC 9 /* MTP2 SUERM Decrement */ 395#define EVE_SFILT 10 /* MTP2 SUERM Filtered Message */ 396/* Interrupt Descriptor Errors */ 397#define ERR_ERRORS 16 /* Position index for error bits */ 398#define ERR_BUF 1 /* Buffer Error */ 399#define ERR_COFA 2 /* Change of Frame Alignment Error */ 400#define ERR_ONR 3 /* Owner Bit Error */ 401#define ERR_PROT 4 /* Memory Protection Error */ 402#define ERR_OOF 8 /* Out of Frame Error */ 403#define ERR_FCS 9 /* FCS Error */ 404#define ERR_ALIGN 10 /* Octet Alignment Error */ 405#define ERR_ABT 11 /* Abort Termination */ 406#define ERR_LNG 12 /* Long Message Error */ 407#define ERR_SHT 13 /* Short Message Error */ 408#define ERR_SUERR 14 /* SUERM threshold exceeded */ 409#define ERR_PERR 15 /* PCI Parity Error */ 410/* Other Stuff */ 411#define TRANSMIT_DIRECTION 0x80000000 /* Transmit direction bit. Bit off 412 * indicates receive direction */ 413#define ILOST 0x00008000 /* Interrupt Lost */ 414#define GROUPMSB 0x00004000 /* Group number MSB */ 415#define SACK_IMAGE 0x00100000 /* Used in IRQ for semaphore test */ 416#define INITIAL_STATUS 0x10000 /* IRQ status should be this after 417 * reset */ 418 419/* This must be defined on an entire channel group (Port) basis */ 420#define SUERM_THRESHOLD 0x1f 421 422#undef VINT32 423#undef VINT8 424 425#endif /*** _INC_MUSYCC_H_ ***/ 426 427/*** End-of-File ***/ 428