1/* 2 * Common structures and definitions for FT1000 Flarion Flash OFDM PCMCIA and USB devices 3 * 4 * Originally copyright (c) 2002 Flarion Technologies 5 * 6 */ 7 8#define DSPVERSZ 4 9#define HWSERNUMSZ 16 10#define SKUSZ 20 11#define EUISZ 8 12#define MODESZ 2 13#define CALVERSZ 2 14#define CALDATESZ 6 15 16#define ELECTRABUZZ_ID 0 /* ASIC ID for Electrabuzz */ 17#define MAGNEMITE_ID 0x1a01 /* ASIC ID for Magnemite */ 18 19/* MEMORY MAP common to both ELECTRABUZZ and MAGNEMITE */ 20#define FT1000_REG_DPRAM_ADDR 0x000E /* DPADR - Dual Port Ram Indirect Address Register */ 21#define FT1000_REG_SUP_CTRL 0x0020 /* HCTR - Host Control Register */ 22#define FT1000_REG_SUP_STAT 0x0022 /* HSTAT - Host Status Register */ 23#define FT1000_REG_RESET 0x0024 /* HCTR - Host Control Register */ 24#define FT1000_REG_SUP_ISR 0x0026 /* HISR - Host Interrupt Status Register */ 25#define FT1000_REG_SUP_IMASK 0x0028 /* HIMASK - Host Interrupt Mask */ 26#define FT1000_REG_DOORBELL 0x002a /* DBELL - Door Bell Register */ 27#define FT1000_REG_ASIC_ID 0x002e /* ASICID - ASIC Identification Number */ 28 29/* MEMORY MAP FOR ELECTRABUZZ ASIC */ 30#define FT1000_REG_UFIFO_STAT 0x0000 /* UFSR - Uplink FIFO status register */ 31#define FT1000_REG_UFIFO_BEG 0x0002 /* UFBR - Uplink FIFO beginning register */ 32#define FT1000_REG_UFIFO_MID 0x0004 /* UFMR - Uplink FIFO middle register */ 33#define FT1000_REG_UFIFO_END 0x0006 /* UFER - Uplink FIFO end register */ 34#define FT1000_REG_DFIFO_STAT 0x0008 /* DFSR - Downlink FIFO status register */ 35#define FT1000_REG_DFIFO 0x000A /* DFR - Downlink FIFO Register */ 36#define FT1000_REG_DPRAM_DATA 0x000C /* DPRAM - Dual Port Indirect Data Register */ 37#define FT1000_REG_WATERMARK 0x0010 /* WMARK - Watermark Register */ 38 39/* MEMORY MAP FOR MAGNEMITE */ 40#define FT1000_REG_MAG_UFDR 0x0000 /* UFDR - Uplink FIFO Data Register (32-bits) */ 41#define FT1000_REG_MAG_UFDRL 0x0000 /* UFDRL - Uplink FIFO Data Register low-word (16-bits) */ 42#define FT1000_REG_MAG_UFDRH 0x0002 /* UFDRH - Uplink FIFO Data Register high-word (16-bits) */ 43#define FT1000_REG_MAG_UFER 0x0004 /* UFER - Uplink FIFO End Register */ 44#define FT1000_REG_MAG_UFSR 0x0006 /* UFSR - Uplink FIFO Status Register */ 45#define FT1000_REG_MAG_DFR 0x0008 /* DFR - Downlink FIFO Register (32-bits) */ 46#define FT1000_REG_MAG_DFRL 0x0008 /* DFRL - Downlink FIFO Register low-word (16-bits) */ 47#define FT1000_REG_MAG_DFRH 0x000a /* DFRH - Downlink FIFO Register high-word (16-bits) */ 48#define FT1000_REG_MAG_DFSR 0x000c /* DFSR - Downlink FIFO Status Register */ 49#define FT1000_REG_MAG_DPDATA 0x0010 /* DPDATA - Dual Port RAM Indirect Data Register (32-bits) */ 50#define FT1000_REG_MAG_DPDATAL 0x0010 /* DPDATAL - Dual Port RAM Indirect Data Register low-word (16-bits) */ 51#define FT1000_REG_MAG_DPDATAH 0x0012 /* DPDATAH - Dual Port RAM Indirect Data Register high-word (16-bits) */ 52#define FT1000_REG_MAG_WATERMARK 0x002c /* WMARK - Watermark Register */ 53#define FT1000_REG_MAG_VERSION 0x0030 /* LLC Version */ 54 55/* Reserved Dual Port RAM offsets for Electrabuzz */ 56#define FT1000_DPRAM_TX_BASE 0x0002 /* Host to PC Card Messaging Area */ 57#define FT1000_DPRAM_RX_BASE 0x0800 /* PC Card to Host Messaging Area */ 58#define FT1000_FIFO_LEN 0x07FC /* total length for DSP FIFO tracking */ 59#define FT1000_HI_HO 0x07FE /* heartbeat with HI/HO */ 60#define FT1000_DSP_STATUS 0x0FFE /* dsp status - non-zero is a request to reset dsp */ 61#define FT1000_DSP_LED 0x0FFA /* dsp led status for PAD device */ 62#define FT1000_DSP_CON_STATE 0x0FF8 /* DSP Connection Status Info */ 63#define FT1000_DPRAM_FEFE 0x0002 /* location for dsp ready indicator */ 64#define FT1000_DSP_TIMER0 0x1FF0 /* Timer Field from Basestation */ 65#define FT1000_DSP_TIMER1 0x1FF2 /* Timer Field from Basestation */ 66#define FT1000_DSP_TIMER2 0x1FF4 /* Timer Field from Basestation */ 67#define FT1000_DSP_TIMER3 0x1FF6 /* Timer Field from Basestation */ 68 69/* Reserved Dual Port RAM offsets for Magnemite */ 70#define FT1000_DPRAM_MAG_TX_BASE 0x0000 /* Host to PC Card Messaging Area */ 71#define FT1000_DPRAM_MAG_RX_BASE 0x0200 /* PC Card to Host Messaging Area */ 72 73#define FT1000_MAG_FIFO_LEN 0x1FF /* total length for DSP FIFO tracking */ 74#define FT1000_MAG_FIFO_LEN_INDX 0x1 /* low-word index */ 75#define FT1000_MAG_HI_HO 0x1FF /* heartbeat with HI/HO */ 76#define FT1000_MAG_HI_HO_INDX 0x0 /* high-word index */ 77#define FT1000_MAG_DSP_LED 0x3FE /* dsp led status for PAD device */ 78#define FT1000_MAG_DSP_LED_INDX 0x0 /* dsp led status for PAD device */ 79#define FT1000_MAG_DSP_CON_STATE 0x3FE /* DSP Connection Status Info */ 80#define FT1000_MAG_DSP_CON_STATE_INDX 0x1 /* DSP Connection Status Info */ 81#define FT1000_MAG_DPRAM_FEFE 0x000 /* location for dsp ready indicator */ 82#define FT1000_MAG_DPRAM_FEFE_INDX 0x0 /* location for dsp ready indicator */ 83#define FT1000_MAG_DSP_TIMER0 0x3FC /* Timer Field from Basestation */ 84#define FT1000_MAG_DSP_TIMER0_INDX 0x1 85#define FT1000_MAG_DSP_TIMER1 0x3FC /* Timer Field from Basestation */ 86#define FT1000_MAG_DSP_TIMER1_INDX 0x0 87#define FT1000_MAG_DSP_TIMER2 0x3FD /* Timer Field from Basestation */ 88#define FT1000_MAG_DSP_TIMER2_INDX 0x1 89#define FT1000_MAG_DSP_TIMER3 0x3FD /* Timer Field from Basestation */ 90#define FT1000_MAG_DSP_TIMER3_INDX 0x0 91#define FT1000_MAG_TOTAL_LEN 0x200 92#define FT1000_MAG_TOTAL_LEN_INDX 0x1 93#define FT1000_MAG_PH_LEN 0x200 94#define FT1000_MAG_PH_LEN_INDX 0x0 95#define FT1000_MAG_PORT_ID 0x201 96#define FT1000_MAG_PORT_ID_INDX 0x0 97 98#define HOST_INTF_LE 0x0 /* Host interface little endian mode */ 99#define HOST_INTF_BE 0x1 /* Host interface big endian mode */ 100 101/* FT1000 to Host Doorbell assignments */ 102#define FT1000_DB_DPRAM_RX 0x0001 /* this value indicates that DSP has data for host in DPRAM */ 103#define FT1000_DB_DNLD_RX 0x0002 /* Downloader handshake doorbell */ 104#define FT1000_ASIC_RESET_REQ 0x0004 /* DSP requesting host to reset the ASIC */ 105#define FT1000_DSP_ASIC_RESET 0x0008 /* DSP indicating host that it will reset the ASIC */ 106#define FT1000_DB_COND_RESET 0x0010 /* DSP request for a card reset. */ 107 108/* Host to FT1000 Doorbell assignments */ 109#define FT1000_DB_DPRAM_TX 0x0100 /* this value indicates that host has data for DSP in DPRAM. */ 110#define FT1000_DB_DNLD_TX 0x0200 /* Downloader handshake doorbell */ 111#define FT1000_ASIC_RESET_DSP 0x0400 /* Responds to FT1000_ASIC_RESET_REQ */ 112#define FT1000_DB_HB 0x1000 /* Indicates that supervisor has a heartbeat message for DSP. */ 113 114#define hi 0x6869 /* PC Card heartbeat values */ 115#define ho 0x686f /* PC Card heartbeat values */ 116 117/* Magnemite specific defines */ 118#define hi_mag 0x6968 /* Byte swap hi to avoid additional system call */ 119#define ho_mag 0x6f68 /* Byte swap ho to avoid additional system call */ 120 121/* Bit field definitions for Host Interrupt Status Register */ 122/* Indicate the cause of an interrupt. */ 123#define ISR_EMPTY 0x00 /* no bits set */ 124#define ISR_DOORBELL_ACK 0x01 /* Doorbell acknowledge from DSP */ 125#define ISR_DOORBELL_PEND 0x02 /* Doorbell pending from DSP */ 126#define ISR_RCV 0x04 /* Packet available in Downlink FIFO */ 127#define ISR_WATERMARK 0x08 /* Watermark requirements satisfied */ 128 129/* Bit field definition for Host Interrupt Mask */ 130#define ISR_MASK_NONE 0x0000 /* no bits set */ 131#define ISR_MASK_DOORBELL_ACK 0x0001 /* Doorbell acknowledge mask */ 132#define ISR_MASK_DOORBELL_PEND 0x0002 /* Doorbell pending mask */ 133#define ISR_MASK_RCV 0x0004 /* Downlink Packet available mask */ 134#define ISR_MASK_WATERMARK 0x0008 /* Watermark interrupt mask */ 135#define ISR_MASK_ALL 0xffff /* Mask all interrupts */ 136/* Default interrupt mask (Enable Doorbell pending and Packet available interrupts) */ 137#define ISR_DEFAULT_MASK 0x7ff9 138 139/* Bit field definition for Host Control Register */ 140#define DSP_RESET_BIT 0x0001 /* Bit field to control dsp reset state */ 141 /* (0 = out of reset 1 = reset) */ 142#define ASIC_RESET_BIT 0x0002 /* Bit field to control ASIC reset state */ 143 /* (0 = out of reset 1 = reset) */ 144#define DSP_UNENCRYPTED 0x0004 145#define DSP_ENCRYPTED 0x0008 146#define EFUSE_MEM_DISABLE 0x0040 147 148/* Application specific IDs */ 149#define DSPID 0x20 150#define HOSTID 0x10 151#define DSPAIRID 0x90 152#define DRIVERID 0x00 153#define NETWORKID 0x20 154 155/* Size of DPRAM Message */ 156#define MAX_CMD_SQSIZE 1780 157 158#define ENET_MAX_SIZE 1514 159#define ENET_HEADER_SIZE 14 160 161#define SLOWQ_TYPE 0 162#define FASTQ_TYPE 1 163 164#define MAX_DSP_SESS_REC 1024 165 166#define DSP_QID_OFFSET 4 167 168/* Driver message types */ 169#define MEDIA_STATE 0x0010 170#define TIME_UPDATE 0x0020 171#define DSP_PROVISION 0x0030 172#define DSP_INIT_MSG 0x0050 173#define DSP_HIBERNATE 0x0060 174#define DSP_STORE_INFO 0x0070 175#define DSP_GET_INFO 0x0071 176#define GET_DRV_ERR_RPT_MSG 0x0073 177#define RSP_DRV_ERR_RPT_MSG 0x0074 178 179/* Driver Error Messages for DSP */ 180#define DSP_HB_INFO 0x7ef0 181#define DSP_FIFO_INFO 0x7ef1 182#define DSP_CONDRESET_INFO 0x7ef2 183#define DSP_CMDLEN_INFO 0x7ef3 184#define DSP_CMDPHCKSUM_INFO 0x7ef4 185#define DSP_PKTPHCKSUM_INFO 0x7ef5 186#define DSP_PKTLEN_INFO 0x7ef6 187#define DSP_USER_RESET 0x7ef7 188#define FIFO_FLUSH_MAXLIMIT 0x7ef8 189#define FIFO_FLUSH_BADCNT 0x7ef9 190#define FIFO_ZERO_LEN 0x7efa 191 192/* Pseudo Header structure */ 193struct pseudo_hdr { 194 unsigned short length; /* length of msg body */ 195 unsigned char source; /* hardware source id */ 196 /* Host = 0x10 */ 197 /* Dsp = 0x20 */ 198 unsigned char destination; /* hardware destination id (refer to source) */ 199 unsigned char portdest; /* software destination port id */ 200 /* Host = 0x00 */ 201 /* Applicaton Broadcast = 0x10 */ 202 /* Network Stack = 0x20 */ 203 /* Dsp OAM = 0x80 */ 204 /* Dsp Airlink = 0x90 */ 205 /* Dsp Loader = 0xa0 */ 206 /* Dsp MIP = 0xb0 */ 207 unsigned char portsrc; /* software source port id (refer to portdest) */ 208 unsigned short sh_str_id; /* not used */ 209 unsigned char control; /* not used */ 210 unsigned char rsvd1; 211 unsigned char seq_num; /* message sequence number */ 212 unsigned char rsvd2; 213 unsigned short qos_class; /* not used */ 214 unsigned short checksum; /* pseudo header checksum */ 215} __packed; 216 217struct drv_msg { 218 struct pseudo_hdr pseudo; 219 u16 type; 220 u16 length; 221 u8 data[0]; 222} __packed; 223 224struct media_msg { 225 struct pseudo_hdr pseudo; 226 u16 type; 227 u16 length; 228 u16 state; 229 u32 ip_addr; 230 u32 net_mask; 231 u32 gateway; 232 u32 dns_1; 233 u32 dns_2; 234} __packed; 235 236struct dsp_init_msg { 237 struct pseudo_hdr pseudo; 238 u16 type; 239 u16 length; 240 u8 DspVer[DSPVERSZ]; /* DSP version number */ 241 u8 HwSerNum[HWSERNUMSZ]; /* Hardware Serial Number */ 242 u8 Sku[SKUSZ]; /* SKU */ 243 u8 eui64[EUISZ]; /* EUI64 */ 244 u8 ProductMode[MODESZ]; /* Product Mode (Market/Production) */ 245 u8 RfCalVer[CALVERSZ]; /* Rf Calibration version */ 246 u8 RfCalDate[CALDATESZ]; /* Rf Calibration date */ 247} __packed; 248 249struct prov_record { 250 struct list_head list; 251 u8 *pprov_data; 252}; 253 254struct ft1000_info { 255 void *priv; 256 struct net_device_stats stats; 257 u16 DrvErrNum; 258 u16 AsicID; 259 int CardReady; 260 int registered; 261 int mediastate; 262 u8 squeseqnum; /* sequence number on slow queue */ 263 spinlock_t dpram_lock; 264 u16 fifo_cnt; 265 u8 DspVer[DSPVERSZ]; /* DSP version number */ 266 u8 HwSerNum[HWSERNUMSZ]; /* Hardware Serial Number */ 267 u8 Sku[SKUSZ]; /* SKU */ 268 u8 eui64[EUISZ]; /* EUI64 */ 269 time_t ConTm; /* Connection Time */ 270 u8 ProductMode[MODESZ]; 271 u8 RfCalVer[CALVERSZ]; 272 u8 RfCalDate[CALDATESZ]; 273 u16 DSP_TIME[4]; 274 u16 LedStat; 275 u16 ConStat; 276 u16 ProgConStat; 277 struct list_head prov_list; 278 u16 DSPInfoBlklen; 279 int (*ft1000_reset)(void *); 280 u16 DSPInfoBlk[MAX_DSP_SESS_REC]; 281 union { 282 u16 Rec[MAX_DSP_SESS_REC]; 283 u32 MagRec[MAX_DSP_SESS_REC/2]; 284 } DSPSess; 285 struct proc_dir_entry *ft1000_proc_dir; 286 char netdevname[IFNAMSIZ]; 287}; 288