1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export 24 * control laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION 32 * OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-usbnx-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon usbnx. 46 * 47 */ 48#ifndef __CVMX_USBNX_TYPEDEFS_H__ 49#define __CVMX_USBNX_TYPEDEFS_H__ 50 51#define CVMX_USBNXBID1(bid) (((bid) & 1) * 0x10000000ull) 52#define CVMX_USBNXBID2(bid) (((bid) & 1) * 0x100000000000ull) 53 54#define CVMX_USBNXREG1(reg, bid) \ 55 (CVMX_ADD_IO_SEG(0x0001180068000000ull | reg) + CVMX_USBNXBID1(bid)) 56#define CVMX_USBNXREG2(reg, bid) \ 57 (CVMX_ADD_IO_SEG(0x00016F0000000000ull | reg) + CVMX_USBNXBID2(bid)) 58 59#define CVMX_USBNX_CLK_CTL(bid) CVMX_USBNXREG1(0x10, bid) 60#define CVMX_USBNX_DMA0_INB_CHN0(bid) CVMX_USBNXREG2(0x818, bid) 61#define CVMX_USBNX_DMA0_OUTB_CHN0(bid) CVMX_USBNXREG2(0x858, bid) 62#define CVMX_USBNX_USBP_CTL_STATUS(bid) CVMX_USBNXREG1(0x18, bid) 63 64/** 65 * cvmx_usbn#_clk_ctl 66 * 67 * USBN_CLK_CTL = USBN's Clock Control 68 * 69 * This register is used to control the frequency of the hclk and the 70 * hreset and phy_rst signals. 71 */ 72union cvmx_usbnx_clk_ctl { 73 uint64_t u64; 74 /** 75 * struct cvmx_usbnx_clk_ctl_s 76 * @divide2: The 'hclk' used by the USB subsystem is derived 77 * from the eclk. 78 * Also see the field DIVIDE. DIVIDE2<1> must currently 79 * be zero because it is not implemented, so the maximum 80 * ratio of eclk/hclk is currently 16. 81 * The actual divide number for hclk is: 82 * (DIVIDE2 + 1) * (DIVIDE + 1) 83 * @hclk_rst: When this field is '0' the HCLK-DIVIDER used to 84 * generate the hclk in the USB Subsystem is held 85 * in reset. This bit must be set to '0' before 86 * changing the value os DIVIDE in this register. 87 * The reset to the HCLK_DIVIDERis also asserted 88 * when core reset is asserted. 89 * @p_x_on: Force USB-PHY on during suspend. 90 * '1' USB-PHY XO block is powered-down during 91 * suspend. 92 * '0' USB-PHY XO block is powered-up during 93 * suspend. 94 * The value of this field must be set while POR is 95 * active. 96 * @p_com_on: '0' Force USB-PHY XO Bias, Bandgap and PLL to 97 * remain powered in Suspend Mode. 98 * '1' The USB-PHY XO Bias, Bandgap and PLL are 99 * powered down in suspend mode. 100 * The value of this field must be set while POR is 101 * active. 102 * @p_c_sel: Phy clock speed select. 103 * Selects the reference clock / crystal frequency. 104 * '11': Reserved 105 * '10': 48 MHz (reserved when a crystal is used) 106 * '01': 24 MHz (reserved when a crystal is used) 107 * '00': 12 MHz 108 * The value of this field must be set while POR is 109 * active. 110 * NOTE: if a crystal is used as a reference clock, 111 * this field must be set to 12 MHz. 112 * @cdiv_byp: Used to enable the bypass input to the USB_CLK_DIV. 113 * @sd_mode: Scaledown mode for the USBC. Control timing events 114 * in the USBC, for normal operation this must be '0'. 115 * @s_bist: Starts bist on the hclk memories, during the '0' 116 * to '1' transition. 117 * @por: Power On Reset for the PHY. 118 * Resets all the PHYS registers and state machines. 119 * @enable: When '1' allows the generation of the hclk. When 120 * '0' the hclk will not be generated. SEE DIVIDE 121 * field of this register. 122 * @prst: When this field is '0' the reset associated with 123 * the phy_clk functionality in the USB Subsystem is 124 * help in reset. This bit should not be set to '1' 125 * until the time it takes 6 clocks (hclk or phy_clk, 126 * whichever is slower) has passed. Under normal 127 * operation once this bit is set to '1' it should not 128 * be set to '0'. 129 * @hrst: When this field is '0' the reset associated with 130 * the hclk functioanlity in the USB Subsystem is 131 * held in reset.This bit should not be set to '1' 132 * until 12ms after phy_clk is stable. Under normal 133 * operation, once this bit is set to '1' it should 134 * not be set to '0'. 135 * @divide: The frequency of 'hclk' used by the USB subsystem 136 * is the eclk frequency divided by the value of 137 * (DIVIDE2 + 1) * (DIVIDE + 1), also see the field 138 * DIVIDE2 of this register. 139 * The hclk frequency should be less than 125Mhz. 140 * After writing a value to this field the SW should 141 * read the field for the value written. 142 * The ENABLE field of this register should not be set 143 * until AFTER this field is set and then read. 144 */ 145 struct cvmx_usbnx_clk_ctl_s { 146 uint64_t reserved_20_63 : 44; 147 uint64_t divide2 : 2; 148 uint64_t hclk_rst : 1; 149 uint64_t p_x_on : 1; 150 uint64_t reserved_14_15 : 2; 151 uint64_t p_com_on : 1; 152 uint64_t p_c_sel : 2; 153 uint64_t cdiv_byp : 1; 154 uint64_t sd_mode : 2; 155 uint64_t s_bist : 1; 156 uint64_t por : 1; 157 uint64_t enable : 1; 158 uint64_t prst : 1; 159 uint64_t hrst : 1; 160 uint64_t divide : 3; 161 } s; 162 /** 163 * struct cvmx_usbnx_clk_ctl_cn30xx 164 * @hclk_rst: When this field is '0' the HCLK-DIVIDER used to 165 * generate the hclk in the USB Subsystem is held 166 * in reset. This bit must be set to '0' before 167 * changing the value os DIVIDE in this register. 168 * The reset to the HCLK_DIVIDERis also asserted 169 * when core reset is asserted. 170 * @p_x_on: Force USB-PHY on during suspend. 171 * '1' USB-PHY XO block is powered-down during 172 * suspend. 173 * '0' USB-PHY XO block is powered-up during 174 * suspend. 175 * The value of this field must be set while POR is 176 * active. 177 * @p_rclk: Phy refrence clock enable. 178 * '1' The PHY PLL uses the XO block output as a 179 * reference. 180 * '0' Reserved. 181 * @p_xenbn: Phy external clock enable. 182 * '1' The XO block uses the clock from a crystal. 183 * '0' The XO block uses an external clock supplied 184 * on the XO pin. USB_XI should be tied to 185 * ground for this usage. 186 * @p_com_on: '0' Force USB-PHY XO Bias, Bandgap and PLL to 187 * remain powered in Suspend Mode. 188 * '1' The USB-PHY XO Bias, Bandgap and PLL are 189 * powered down in suspend mode. 190 * The value of this field must be set while POR is 191 * active. 192 * @p_c_sel: Phy clock speed select. 193 * Selects the reference clock / crystal frequency. 194 * '11': Reserved 195 * '10': 48 MHz 196 * '01': 24 MHz 197 * '00': 12 MHz 198 * The value of this field must be set while POR is 199 * active. 200 * @cdiv_byp: Used to enable the bypass input to the USB_CLK_DIV. 201 * @sd_mode: Scaledown mode for the USBC. Control timing events 202 * in the USBC, for normal operation this must be '0'. 203 * @s_bist: Starts bist on the hclk memories, during the '0' 204 * to '1' transition. 205 * @por: Power On Reset for the PHY. 206 * Resets all the PHYS registers and state machines. 207 * @enable: When '1' allows the generation of the hclk. When 208 * '0' the hclk will not be generated. 209 * @prst: When this field is '0' the reset associated with 210 * the phy_clk functionality in the USB Subsystem is 211 * help in reset. This bit should not be set to '1' 212 * until the time it takes 6 clocks (hclk or phy_clk, 213 * whichever is slower) has passed. Under normal 214 * operation once this bit is set to '1' it should not 215 * be set to '0'. 216 * @hrst: When this field is '0' the reset associated with 217 * the hclk functioanlity in the USB Subsystem is 218 * held in reset.This bit should not be set to '1' 219 * until 12ms after phy_clk is stable. Under normal 220 * operation, once this bit is set to '1' it should 221 * not be set to '0'. 222 * @divide: The 'hclk' used by the USB subsystem is derived 223 * from the eclk. The eclk will be divided by the 224 * value of this field +1 to determine the hclk 225 * frequency. (Also see HRST of this register). 226 * The hclk frequency must be less than 125 MHz. 227 */ 228 struct cvmx_usbnx_clk_ctl_cn30xx { 229 uint64_t reserved_18_63 : 46; 230 uint64_t hclk_rst : 1; 231 uint64_t p_x_on : 1; 232 uint64_t p_rclk : 1; 233 uint64_t p_xenbn : 1; 234 uint64_t p_com_on : 1; 235 uint64_t p_c_sel : 2; 236 uint64_t cdiv_byp : 1; 237 uint64_t sd_mode : 2; 238 uint64_t s_bist : 1; 239 uint64_t por : 1; 240 uint64_t enable : 1; 241 uint64_t prst : 1; 242 uint64_t hrst : 1; 243 uint64_t divide : 3; 244 } cn30xx; 245 struct cvmx_usbnx_clk_ctl_cn30xx cn31xx; 246 /** 247 * struct cvmx_usbnx_clk_ctl_cn50xx 248 * @divide2: The 'hclk' used by the USB subsystem is derived 249 * from the eclk. 250 * Also see the field DIVIDE. DIVIDE2<1> must currently 251 * be zero because it is not implemented, so the maximum 252 * ratio of eclk/hclk is currently 16. 253 * The actual divide number for hclk is: 254 * (DIVIDE2 + 1) * (DIVIDE + 1) 255 * @hclk_rst: When this field is '0' the HCLK-DIVIDER used to 256 * generate the hclk in the USB Subsystem is held 257 * in reset. This bit must be set to '0' before 258 * changing the value os DIVIDE in this register. 259 * The reset to the HCLK_DIVIDERis also asserted 260 * when core reset is asserted. 261 * @p_rtype: PHY reference clock type 262 * '0' The USB-PHY uses a 12MHz crystal as a clock 263 * source at the USB_XO and USB_XI pins 264 * '1' Reserved 265 * '2' The USB_PHY uses 12/24/48MHz 2.5V board clock 266 * at the USB_XO pin. USB_XI should be tied to 267 * ground in this case. 268 * '3' Reserved 269 * (bit 14 was P_XENBN on 3xxx) 270 * (bit 15 was P_RCLK on 3xxx) 271 * @p_com_on: '0' Force USB-PHY XO Bias, Bandgap and PLL to 272 * remain powered in Suspend Mode. 273 * '1' The USB-PHY XO Bias, Bandgap and PLL are 274 * powered down in suspend mode. 275 * The value of this field must be set while POR is 276 * active. 277 * @p_c_sel: Phy clock speed select. 278 * Selects the reference clock / crystal frequency. 279 * '11': Reserved 280 * '10': 48 MHz (reserved when a crystal is used) 281 * '01': 24 MHz (reserved when a crystal is used) 282 * '00': 12 MHz 283 * The value of this field must be set while POR is 284 * active. 285 * NOTE: if a crystal is used as a reference clock, 286 * this field must be set to 12 MHz. 287 * @cdiv_byp: Used to enable the bypass input to the USB_CLK_DIV. 288 * @sd_mode: Scaledown mode for the USBC. Control timing events 289 * in the USBC, for normal operation this must be '0'. 290 * @s_bist: Starts bist on the hclk memories, during the '0' 291 * to '1' transition. 292 * @por: Power On Reset for the PHY. 293 * Resets all the PHYS registers and state machines. 294 * @enable: When '1' allows the generation of the hclk. When 295 * '0' the hclk will not be generated. SEE DIVIDE 296 * field of this register. 297 * @prst: When this field is '0' the reset associated with 298 * the phy_clk functionality in the USB Subsystem is 299 * help in reset. This bit should not be set to '1' 300 * until the time it takes 6 clocks (hclk or phy_clk, 301 * whichever is slower) has passed. Under normal 302 * operation once this bit is set to '1' it should not 303 * be set to '0'. 304 * @hrst: When this field is '0' the reset associated with 305 * the hclk functioanlity in the USB Subsystem is 306 * held in reset.This bit should not be set to '1' 307 * until 12ms after phy_clk is stable. Under normal 308 * operation, once this bit is set to '1' it should 309 * not be set to '0'. 310 * @divide: The frequency of 'hclk' used by the USB subsystem 311 * is the eclk frequency divided by the value of 312 * (DIVIDE2 + 1) * (DIVIDE + 1), also see the field 313 * DIVIDE2 of this register. 314 * The hclk frequency should be less than 125Mhz. 315 * After writing a value to this field the SW should 316 * read the field for the value written. 317 * The ENABLE field of this register should not be set 318 * until AFTER this field is set and then read. 319 */ 320 struct cvmx_usbnx_clk_ctl_cn50xx { 321 uint64_t reserved_20_63 : 44; 322 uint64_t divide2 : 2; 323 uint64_t hclk_rst : 1; 324 uint64_t reserved_16_16 : 1; 325 uint64_t p_rtype : 2; 326 uint64_t p_com_on : 1; 327 uint64_t p_c_sel : 2; 328 uint64_t cdiv_byp : 1; 329 uint64_t sd_mode : 2; 330 uint64_t s_bist : 1; 331 uint64_t por : 1; 332 uint64_t enable : 1; 333 uint64_t prst : 1; 334 uint64_t hrst : 1; 335 uint64_t divide : 3; 336 } cn50xx; 337 struct cvmx_usbnx_clk_ctl_cn50xx cn52xx; 338 struct cvmx_usbnx_clk_ctl_cn50xx cn56xx; 339}; 340 341/** 342 * cvmx_usbn#_usbp_ctl_status 343 * 344 * USBN_USBP_CTL_STATUS = USBP Control And Status Register 345 * 346 * Contains general control and status information for the USBN block. 347 */ 348union cvmx_usbnx_usbp_ctl_status { 349 uint64_t u64; 350 /** 351 * struct cvmx_usbnx_usbp_ctl_status_s 352 * @txrisetune: HS Transmitter Rise/Fall Time Adjustment 353 * @txvreftune: HS DC Voltage Level Adjustment 354 * @txfslstune: FS/LS Source Impedence Adjustment 355 * @txhsxvtune: Transmitter High-Speed Crossover Adjustment 356 * @sqrxtune: Squelch Threshold Adjustment 357 * @compdistune: Disconnect Threshold Adjustment 358 * @otgtune: VBUS Valid Threshold Adjustment 359 * @otgdisable: OTG Block Disable 360 * @portreset: Per_Port Reset 361 * @drvvbus: Drive VBUS 362 * @lsbist: Low-Speed BIST Enable. 363 * @fsbist: Full-Speed BIST Enable. 364 * @hsbist: High-Speed BIST Enable. 365 * @bist_done: PHY Bist Done. 366 * Asserted at the end of the PHY BIST sequence. 367 * @bist_err: PHY Bist Error. 368 * Indicates an internal error was detected during 369 * the BIST sequence. 370 * @tdata_out: PHY Test Data Out. 371 * Presents either internaly generated signals or 372 * test register contents, based upon the value of 373 * test_data_out_sel. 374 * @siddq: Drives the USBP (USB-PHY) SIDDQ input. 375 * Normally should be set to zero. 376 * When customers have no intent to use USB PHY 377 * interface, they should: 378 * - still provide 3.3V to USB_VDD33, and 379 * - tie USB_REXT to 3.3V supply, and 380 * - set USBN*_USBP_CTL_STATUS[SIDDQ]=1 381 * @txpreemphasistune: HS Transmitter Pre-Emphasis Enable 382 * @dma_bmode: When set to 1 the L2C DMA address will be updated 383 * with byte-counts between packets. When set to 0 384 * the L2C DMA address is incremented to the next 385 * 4-byte aligned address after adding byte-count. 386 * @usbc_end: Bigendian input to the USB Core. This should be 387 * set to '0' for operation. 388 * @usbp_bist: PHY, This is cleared '0' to run BIST on the USBP. 389 * @tclk: PHY Test Clock, used to load TDATA_IN to the USBP. 390 * @dp_pulld: PHY DP_PULLDOWN input to the USB-PHY. 391 * This signal enables the pull-down resistance on 392 * the D+ line. '1' pull down-resistance is connected 393 * to D+/ '0' pull down resistance is not connected 394 * to D+. When an A/B device is acting as a host 395 * (downstream-facing port), dp_pulldown and 396 * dm_pulldown are enabled. This must not toggle 397 * during normal opeartion. 398 * @dm_pulld: PHY DM_PULLDOWN input to the USB-PHY. 399 * This signal enables the pull-down resistance on 400 * the D- line. '1' pull down-resistance is connected 401 * to D-. '0' pull down resistance is not connected 402 * to D-. When an A/B device is acting as a host 403 * (downstream-facing port), dp_pulldown and 404 * dm_pulldown are enabled. This must not toggle 405 * during normal opeartion. 406 * @hst_mode: When '0' the USB is acting as HOST, when '1' 407 * USB is acting as device. This field needs to be 408 * set while the USB is in reset. 409 * @tuning: Transmitter Tuning for High-Speed Operation. 410 * Tunes the current supply and rise/fall output 411 * times for high-speed operation. 412 * [20:19] == 11: Current supply increased 413 * approximately 9% 414 * [20:19] == 10: Current supply increased 415 * approximately 4.5% 416 * [20:19] == 01: Design default. 417 * [20:19] == 00: Current supply decreased 418 * approximately 4.5% 419 * [22:21] == 11: Rise and fall times are increased. 420 * [22:21] == 10: Design default. 421 * [22:21] == 01: Rise and fall times are decreased. 422 * [22:21] == 00: Rise and fall times are decreased 423 * further as compared to the 01 setting. 424 * @tx_bs_enh: Transmit Bit Stuffing on [15:8]. 425 * Enables or disables bit stuffing on data[15:8] 426 * when bit-stuffing is enabled. 427 * @tx_bs_en: Transmit Bit Stuffing on [7:0]. 428 * Enables or disables bit stuffing on data[7:0] 429 * when bit-stuffing is enabled. 430 * @loop_enb: PHY Loopback Test Enable. 431 * '1': During data transmission the receive is 432 * enabled. 433 * '0': During data transmission the receive is 434 * disabled. 435 * Must be '0' for normal operation. 436 * @vtest_enb: Analog Test Pin Enable. 437 * '1' The PHY's analog_test pin is enabled for the 438 * input and output of applicable analog test signals. 439 * '0' THe analog_test pin is disabled. 440 * @bist_enb: Built-In Self Test Enable. 441 * Used to activate BIST in the PHY. 442 * @tdata_sel: Test Data Out Select. 443 * '1' test_data_out[3:0] (PHY) register contents 444 * are output. '0' internaly generated signals are 445 * output. 446 * @taddr_in: Mode Address for Test Interface. 447 * Specifies the register address for writing to or 448 * reading from the PHY test interface register. 449 * @tdata_in: Internal Testing Register Input Data and Select 450 * This is a test bus. Data is present on [3:0], 451 * and its corresponding select (enable) is present 452 * on bits [7:4]. 453 * @ate_reset: Reset input from automatic test equipment. 454 * This is a test signal. When the USB Core is 455 * powered up (not in Susned Mode), an automatic 456 * tester can use this to disable phy_clock and 457 * free_clk, then re-eanable them with an aligned 458 * phase. 459 * '1': The phy_clk and free_clk outputs are 460 * disabled. "0": The phy_clock and free_clk outputs 461 * are available within a specific period after the 462 * de-assertion. 463 */ 464 struct cvmx_usbnx_usbp_ctl_status_s { 465 uint64_t txrisetune : 1; 466 uint64_t txvreftune : 4; 467 uint64_t txfslstune : 4; 468 uint64_t txhsxvtune : 2; 469 uint64_t sqrxtune : 3; 470 uint64_t compdistune : 3; 471 uint64_t otgtune : 3; 472 uint64_t otgdisable : 1; 473 uint64_t portreset : 1; 474 uint64_t drvvbus : 1; 475 uint64_t lsbist : 1; 476 uint64_t fsbist : 1; 477 uint64_t hsbist : 1; 478 uint64_t bist_done : 1; 479 uint64_t bist_err : 1; 480 uint64_t tdata_out : 4; 481 uint64_t siddq : 1; 482 uint64_t txpreemphasistune : 1; 483 uint64_t dma_bmode : 1; 484 uint64_t usbc_end : 1; 485 uint64_t usbp_bist : 1; 486 uint64_t tclk : 1; 487 uint64_t dp_pulld : 1; 488 uint64_t dm_pulld : 1; 489 uint64_t hst_mode : 1; 490 uint64_t tuning : 4; 491 uint64_t tx_bs_enh : 1; 492 uint64_t tx_bs_en : 1; 493 uint64_t loop_enb : 1; 494 uint64_t vtest_enb : 1; 495 uint64_t bist_enb : 1; 496 uint64_t tdata_sel : 1; 497 uint64_t taddr_in : 4; 498 uint64_t tdata_in : 8; 499 uint64_t ate_reset : 1; 500 } s; 501 /** 502 * struct cvmx_usbnx_usbp_ctl_status_cn30xx 503 * @bist_done: PHY Bist Done. 504 * Asserted at the end of the PHY BIST sequence. 505 * @bist_err: PHY Bist Error. 506 * Indicates an internal error was detected during 507 * the BIST sequence. 508 * @tdata_out: PHY Test Data Out. 509 * Presents either internaly generated signals or 510 * test register contents, based upon the value of 511 * test_data_out_sel. 512 * @dma_bmode: When set to 1 the L2C DMA address will be updated 513 * with byte-counts between packets. When set to 0 514 * the L2C DMA address is incremented to the next 515 * 4-byte aligned address after adding byte-count. 516 * @usbc_end: Bigendian input to the USB Core. This should be 517 * set to '0' for operation. 518 * @usbp_bist: PHY, This is cleared '0' to run BIST on the USBP. 519 * @tclk: PHY Test Clock, used to load TDATA_IN to the USBP. 520 * @dp_pulld: PHY DP_PULLDOWN input to the USB-PHY. 521 * This signal enables the pull-down resistance on 522 * the D+ line. '1' pull down-resistance is connected 523 * to D+/ '0' pull down resistance is not connected 524 * to D+. When an A/B device is acting as a host 525 * (downstream-facing port), dp_pulldown and 526 * dm_pulldown are enabled. This must not toggle 527 * during normal opeartion. 528 * @dm_pulld: PHY DM_PULLDOWN input to the USB-PHY. 529 * This signal enables the pull-down resistance on 530 * the D- line. '1' pull down-resistance is connected 531 * to D-. '0' pull down resistance is not connected 532 * to D-. When an A/B device is acting as a host 533 * (downstream-facing port), dp_pulldown and 534 * dm_pulldown are enabled. This must not toggle 535 * during normal opeartion. 536 * @hst_mode: When '0' the USB is acting as HOST, when '1' 537 * USB is acting as device. This field needs to be 538 * set while the USB is in reset. 539 * @tuning: Transmitter Tuning for High-Speed Operation. 540 * Tunes the current supply and rise/fall output 541 * times for high-speed operation. 542 * [20:19] == 11: Current supply increased 543 * approximately 9% 544 * [20:19] == 10: Current supply increased 545 * approximately 4.5% 546 * [20:19] == 01: Design default. 547 * [20:19] == 00: Current supply decreased 548 * approximately 4.5% 549 * [22:21] == 11: Rise and fall times are increased. 550 * [22:21] == 10: Design default. 551 * [22:21] == 01: Rise and fall times are decreased. 552 * [22:21] == 00: Rise and fall times are decreased 553 * further as compared to the 01 setting. 554 * @tx_bs_enh: Transmit Bit Stuffing on [15:8]. 555 * Enables or disables bit stuffing on data[15:8] 556 * when bit-stuffing is enabled. 557 * @tx_bs_en: Transmit Bit Stuffing on [7:0]. 558 * Enables or disables bit stuffing on data[7:0] 559 * when bit-stuffing is enabled. 560 * @loop_enb: PHY Loopback Test Enable. 561 * '1': During data transmission the receive is 562 * enabled. 563 * '0': During data transmission the receive is 564 * disabled. 565 * Must be '0' for normal operation. 566 * @vtest_enb: Analog Test Pin Enable. 567 * '1' The PHY's analog_test pin is enabled for the 568 * input and output of applicable analog test signals. 569 * '0' THe analog_test pin is disabled. 570 * @bist_enb: Built-In Self Test Enable. 571 * Used to activate BIST in the PHY. 572 * @tdata_sel: Test Data Out Select. 573 * '1' test_data_out[3:0] (PHY) register contents 574 * are output. '0' internaly generated signals are 575 * output. 576 * @taddr_in: Mode Address for Test Interface. 577 * Specifies the register address for writing to or 578 * reading from the PHY test interface register. 579 * @tdata_in: Internal Testing Register Input Data and Select 580 * This is a test bus. Data is present on [3:0], 581 * and its corresponding select (enable) is present 582 * on bits [7:4]. 583 * @ate_reset: Reset input from automatic test equipment. 584 * This is a test signal. When the USB Core is 585 * powered up (not in Susned Mode), an automatic 586 * tester can use this to disable phy_clock and 587 * free_clk, then re-eanable them with an aligned 588 * phase. 589 * '1': The phy_clk and free_clk outputs are 590 * disabled. "0": The phy_clock and free_clk outputs 591 * are available within a specific period after the 592 * de-assertion. 593 */ 594 struct cvmx_usbnx_usbp_ctl_status_cn30xx { 595 uint64_t reserved_38_63 : 26; 596 uint64_t bist_done : 1; 597 uint64_t bist_err : 1; 598 uint64_t tdata_out : 4; 599 uint64_t reserved_30_31 : 2; 600 uint64_t dma_bmode : 1; 601 uint64_t usbc_end : 1; 602 uint64_t usbp_bist : 1; 603 uint64_t tclk : 1; 604 uint64_t dp_pulld : 1; 605 uint64_t dm_pulld : 1; 606 uint64_t hst_mode : 1; 607 uint64_t tuning : 4; 608 uint64_t tx_bs_enh : 1; 609 uint64_t tx_bs_en : 1; 610 uint64_t loop_enb : 1; 611 uint64_t vtest_enb : 1; 612 uint64_t bist_enb : 1; 613 uint64_t tdata_sel : 1; 614 uint64_t taddr_in : 4; 615 uint64_t tdata_in : 8; 616 uint64_t ate_reset : 1; 617 } cn30xx; 618 /** 619 * struct cvmx_usbnx_usbp_ctl_status_cn50xx 620 * @txrisetune: HS Transmitter Rise/Fall Time Adjustment 621 * @txvreftune: HS DC Voltage Level Adjustment 622 * @txfslstune: FS/LS Source Impedence Adjustment 623 * @txhsxvtune: Transmitter High-Speed Crossover Adjustment 624 * @sqrxtune: Squelch Threshold Adjustment 625 * @compdistune: Disconnect Threshold Adjustment 626 * @otgtune: VBUS Valid Threshold Adjustment 627 * @otgdisable: OTG Block Disable 628 * @portreset: Per_Port Reset 629 * @drvvbus: Drive VBUS 630 * @lsbist: Low-Speed BIST Enable. 631 * @fsbist: Full-Speed BIST Enable. 632 * @hsbist: High-Speed BIST Enable. 633 * @bist_done: PHY Bist Done. 634 * Asserted at the end of the PHY BIST sequence. 635 * @bist_err: PHY Bist Error. 636 * Indicates an internal error was detected during 637 * the BIST sequence. 638 * @tdata_out: PHY Test Data Out. 639 * Presents either internaly generated signals or 640 * test register contents, based upon the value of 641 * test_data_out_sel. 642 * @txpreemphasistune: HS Transmitter Pre-Emphasis Enable 643 * @dma_bmode: When set to 1 the L2C DMA address will be updated 644 * with byte-counts between packets. When set to 0 645 * the L2C DMA address is incremented to the next 646 * 4-byte aligned address after adding byte-count. 647 * @usbc_end: Bigendian input to the USB Core. This should be 648 * set to '0' for operation. 649 * @usbp_bist: PHY, This is cleared '0' to run BIST on the USBP. 650 * @tclk: PHY Test Clock, used to load TDATA_IN to the USBP. 651 * @dp_pulld: PHY DP_PULLDOWN input to the USB-PHY. 652 * This signal enables the pull-down resistance on 653 * the D+ line. '1' pull down-resistance is connected 654 * to D+/ '0' pull down resistance is not connected 655 * to D+. When an A/B device is acting as a host 656 * (downstream-facing port), dp_pulldown and 657 * dm_pulldown are enabled. This must not toggle 658 * during normal opeartion. 659 * @dm_pulld: PHY DM_PULLDOWN input to the USB-PHY. 660 * This signal enables the pull-down resistance on 661 * the D- line. '1' pull down-resistance is connected 662 * to D-. '0' pull down resistance is not connected 663 * to D-. When an A/B device is acting as a host 664 * (downstream-facing port), dp_pulldown and 665 * dm_pulldown are enabled. This must not toggle 666 * during normal opeartion. 667 * @hst_mode: When '0' the USB is acting as HOST, when '1' 668 * USB is acting as device. This field needs to be 669 * set while the USB is in reset. 670 * @tx_bs_enh: Transmit Bit Stuffing on [15:8]. 671 * Enables or disables bit stuffing on data[15:8] 672 * when bit-stuffing is enabled. 673 * @tx_bs_en: Transmit Bit Stuffing on [7:0]. 674 * Enables or disables bit stuffing on data[7:0] 675 * when bit-stuffing is enabled. 676 * @loop_enb: PHY Loopback Test Enable. 677 * '1': During data transmission the receive is 678 * enabled. 679 * '0': During data transmission the receive is 680 * disabled. 681 * Must be '0' for normal operation. 682 * @vtest_enb: Analog Test Pin Enable. 683 * '1' The PHY's analog_test pin is enabled for the 684 * input and output of applicable analog test signals. 685 * '0' THe analog_test pin is disabled. 686 * @bist_enb: Built-In Self Test Enable. 687 * Used to activate BIST in the PHY. 688 * @tdata_sel: Test Data Out Select. 689 * '1' test_data_out[3:0] (PHY) register contents 690 * are output. '0' internaly generated signals are 691 * output. 692 * @taddr_in: Mode Address for Test Interface. 693 * Specifies the register address for writing to or 694 * reading from the PHY test interface register. 695 * @tdata_in: Internal Testing Register Input Data and Select 696 * This is a test bus. Data is present on [3:0], 697 * and its corresponding select (enable) is present 698 * on bits [7:4]. 699 * @ate_reset: Reset input from automatic test equipment. 700 * This is a test signal. When the USB Core is 701 * powered up (not in Susned Mode), an automatic 702 * tester can use this to disable phy_clock and 703 * free_clk, then re-eanable them with an aligned 704 * phase. 705 * '1': The phy_clk and free_clk outputs are 706 * disabled. "0": The phy_clock and free_clk outputs 707 * are available within a specific period after the 708 * de-assertion. 709 */ 710 struct cvmx_usbnx_usbp_ctl_status_cn50xx { 711 uint64_t txrisetune : 1; 712 uint64_t txvreftune : 4; 713 uint64_t txfslstune : 4; 714 uint64_t txhsxvtune : 2; 715 uint64_t sqrxtune : 3; 716 uint64_t compdistune : 3; 717 uint64_t otgtune : 3; 718 uint64_t otgdisable : 1; 719 uint64_t portreset : 1; 720 uint64_t drvvbus : 1; 721 uint64_t lsbist : 1; 722 uint64_t fsbist : 1; 723 uint64_t hsbist : 1; 724 uint64_t bist_done : 1; 725 uint64_t bist_err : 1; 726 uint64_t tdata_out : 4; 727 uint64_t reserved_31_31 : 1; 728 uint64_t txpreemphasistune : 1; 729 uint64_t dma_bmode : 1; 730 uint64_t usbc_end : 1; 731 uint64_t usbp_bist : 1; 732 uint64_t tclk : 1; 733 uint64_t dp_pulld : 1; 734 uint64_t dm_pulld : 1; 735 uint64_t hst_mode : 1; 736 uint64_t reserved_19_22 : 4; 737 uint64_t tx_bs_enh : 1; 738 uint64_t tx_bs_en : 1; 739 uint64_t loop_enb : 1; 740 uint64_t vtest_enb : 1; 741 uint64_t bist_enb : 1; 742 uint64_t tdata_sel : 1; 743 uint64_t taddr_in : 4; 744 uint64_t tdata_in : 8; 745 uint64_t ate_reset : 1; 746 } cn50xx; 747 /** 748 * struct cvmx_usbnx_usbp_ctl_status_cn52xx 749 * @txrisetune: HS Transmitter Rise/Fall Time Adjustment 750 * @txvreftune: HS DC Voltage Level Adjustment 751 * @txfslstune: FS/LS Source Impedence Adjustment 752 * @txhsxvtune: Transmitter High-Speed Crossover Adjustment 753 * @sqrxtune: Squelch Threshold Adjustment 754 * @compdistune: Disconnect Threshold Adjustment 755 * @otgtune: VBUS Valid Threshold Adjustment 756 * @otgdisable: OTG Block Disable 757 * @portreset: Per_Port Reset 758 * @drvvbus: Drive VBUS 759 * @lsbist: Low-Speed BIST Enable. 760 * @fsbist: Full-Speed BIST Enable. 761 * @hsbist: High-Speed BIST Enable. 762 * @bist_done: PHY Bist Done. 763 * Asserted at the end of the PHY BIST sequence. 764 * @bist_err: PHY Bist Error. 765 * Indicates an internal error was detected during 766 * the BIST sequence. 767 * @tdata_out: PHY Test Data Out. 768 * Presents either internaly generated signals or 769 * test register contents, based upon the value of 770 * test_data_out_sel. 771 * @siddq: Drives the USBP (USB-PHY) SIDDQ input. 772 * Normally should be set to zero. 773 * When customers have no intent to use USB PHY 774 * interface, they should: 775 * - still provide 3.3V to USB_VDD33, and 776 * - tie USB_REXT to 3.3V supply, and 777 * - set USBN*_USBP_CTL_STATUS[SIDDQ]=1 778 * @txpreemphasistune: HS Transmitter Pre-Emphasis Enable 779 * @dma_bmode: When set to 1 the L2C DMA address will be updated 780 * with byte-counts between packets. When set to 0 781 * the L2C DMA address is incremented to the next 782 * 4-byte aligned address after adding byte-count. 783 * @usbc_end: Bigendian input to the USB Core. This should be 784 * set to '0' for operation. 785 * @usbp_bist: PHY, This is cleared '0' to run BIST on the USBP. 786 * @tclk: PHY Test Clock, used to load TDATA_IN to the USBP. 787 * @dp_pulld: PHY DP_PULLDOWN input to the USB-PHY. 788 * This signal enables the pull-down resistance on 789 * the D+ line. '1' pull down-resistance is connected 790 * to D+/ '0' pull down resistance is not connected 791 * to D+. When an A/B device is acting as a host 792 * (downstream-facing port), dp_pulldown and 793 * dm_pulldown are enabled. This must not toggle 794 * during normal opeartion. 795 * @dm_pulld: PHY DM_PULLDOWN input to the USB-PHY. 796 * This signal enables the pull-down resistance on 797 * the D- line. '1' pull down-resistance is connected 798 * to D-. '0' pull down resistance is not connected 799 * to D-. When an A/B device is acting as a host 800 * (downstream-facing port), dp_pulldown and 801 * dm_pulldown are enabled. This must not toggle 802 * during normal opeartion. 803 * @hst_mode: When '0' the USB is acting as HOST, when '1' 804 * USB is acting as device. This field needs to be 805 * set while the USB is in reset. 806 * @tx_bs_enh: Transmit Bit Stuffing on [15:8]. 807 * Enables or disables bit stuffing on data[15:8] 808 * when bit-stuffing is enabled. 809 * @tx_bs_en: Transmit Bit Stuffing on [7:0]. 810 * Enables or disables bit stuffing on data[7:0] 811 * when bit-stuffing is enabled. 812 * @loop_enb: PHY Loopback Test Enable. 813 * '1': During data transmission the receive is 814 * enabled. 815 * '0': During data transmission the receive is 816 * disabled. 817 * Must be '0' for normal operation. 818 * @vtest_enb: Analog Test Pin Enable. 819 * '1' The PHY's analog_test pin is enabled for the 820 * input and output of applicable analog test signals. 821 * '0' THe analog_test pin is disabled. 822 * @bist_enb: Built-In Self Test Enable. 823 * Used to activate BIST in the PHY. 824 * @tdata_sel: Test Data Out Select. 825 * '1' test_data_out[3:0] (PHY) register contents 826 * are output. '0' internaly generated signals are 827 * output. 828 * @taddr_in: Mode Address for Test Interface. 829 * Specifies the register address for writing to or 830 * reading from the PHY test interface register. 831 * @tdata_in: Internal Testing Register Input Data and Select 832 * This is a test bus. Data is present on [3:0], 833 * and its corresponding select (enable) is present 834 * on bits [7:4]. 835 * @ate_reset: Reset input from automatic test equipment. 836 * This is a test signal. When the USB Core is 837 * powered up (not in Susned Mode), an automatic 838 * tester can use this to disable phy_clock and 839 * free_clk, then re-eanable them with an aligned 840 * phase. 841 * '1': The phy_clk and free_clk outputs are 842 * disabled. "0": The phy_clock and free_clk outputs 843 * are available within a specific period after the 844 * de-assertion. 845 */ 846 struct cvmx_usbnx_usbp_ctl_status_cn52xx { 847 uint64_t txrisetune : 1; 848 uint64_t txvreftune : 4; 849 uint64_t txfslstune : 4; 850 uint64_t txhsxvtune : 2; 851 uint64_t sqrxtune : 3; 852 uint64_t compdistune : 3; 853 uint64_t otgtune : 3; 854 uint64_t otgdisable : 1; 855 uint64_t portreset : 1; 856 uint64_t drvvbus : 1; 857 uint64_t lsbist : 1; 858 uint64_t fsbist : 1; 859 uint64_t hsbist : 1; 860 uint64_t bist_done : 1; 861 uint64_t bist_err : 1; 862 uint64_t tdata_out : 4; 863 uint64_t siddq : 1; 864 uint64_t txpreemphasistune : 1; 865 uint64_t dma_bmode : 1; 866 uint64_t usbc_end : 1; 867 uint64_t usbp_bist : 1; 868 uint64_t tclk : 1; 869 uint64_t dp_pulld : 1; 870 uint64_t dm_pulld : 1; 871 uint64_t hst_mode : 1; 872 uint64_t reserved_19_22 : 4; 873 uint64_t tx_bs_enh : 1; 874 uint64_t tx_bs_en : 1; 875 uint64_t loop_enb : 1; 876 uint64_t vtest_enb : 1; 877 uint64_t bist_enb : 1; 878 uint64_t tdata_sel : 1; 879 uint64_t taddr_in : 4; 880 uint64_t tdata_in : 8; 881 uint64_t ate_reset : 1; 882 } cn52xx; 883}; 884 885#endif 886