LXR linux/drivers/staging/rtl8188eu/include/odm.h

   1/******************************************************************************
   2 *
   3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of version 2 of the GNU General Public License as
   7 * published by the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12 * more details.
  13 *
  14 * You should have received a copy of the GNU General Public License along with
  15 * this program; if not, write to the Free Software Foundation, Inc.,
  16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17 *
  18 *
  19 ******************************************************************************/
  20
  21
  22#ifndef __HALDMOUTSRC_H__
  23#define __HALDMOUTSRC_H__
  24
  25/*  Definition */
  26/*  Define all team support ability. */
  27
  28/*  Define for all teams. Please Define the constant in your precomp header. */
  29
  30/* define               DM_ODM_SUPPORT_AP                       0 */
  31/* define               DM_ODM_SUPPORT_ADSL                     0 */
  32/* define               DM_ODM_SUPPORT_CE                       0 */
  33/* define               DM_ODM_SUPPORT_MP                       1 */
  34
  35/*  Define ODM SW team support flag. */
  36
  37/*  Antenna Switch Relative Definition. */
  38
  39/*  Add new function SwAntDivCheck8192C(). */
  40/*  This is the main function of Antenna diversity function before link. */
  41/*  Mainly, it just retains last scan result and scan again. */
  42/*  After that, it compares the scan result to see which one gets better
  43 *  RSSI. It selects antenna with better receiving power and returns better
  44 *  scan result. */
  45
  46#define TP_MODE                 0
  47#define RSSI_MODE               1
  48#define TRAFFIC_LOW             0
  49#define TRAFFIC_HIGH            1
  50
  51/* 3 Tx Power Tracking */
  52/* 3============================================================ */
  53#define         DPK_DELTA_MAPPING_NUM   13
  54#define         index_mapping_HP_NUM    15
  55
  56
  57/*  */
  58/* 3 PSD Handler */
  59/* 3============================================================ */
  60
  61#define AFH_PSD         1       /* 0:normal PSD scan, 1: only do 20 pts PSD */
  62#define MODE_40M        0       /* 0:20M, 1:40M */
  63#define PSD_TH2         3
  64#define PSD_CHM         20   /*  Minimum channel number for BT AFH */
  65#define SIR_STEP_SIZE   3
  66#define Smooth_Size_1   5
  67#define Smooth_TH_1     3
  68#define Smooth_Size_2   10
  69#define Smooth_TH_2     4
  70#define Smooth_Size_3   20
  71#define Smooth_TH_3     4
  72#define Smooth_Step_Size 5
  73#define Adaptive_SIR    1
  74#define PSD_RESCAN      4
  75#define PSD_SCAN_INTERVAL       700 /* ms */
  76
  77/* 8723A High Power IGI Setting */
  78#define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22
  79#define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28
  80#define DM_DIG_HIGH_PWR_THRESHOLD       0x3a
  81
  82/*  LPS define */
  83#define DM_DIG_FA_TH0_LPS               4 /*  4 in lps */
  84#define DM_DIG_FA_TH1_LPS               15 /*  15 lps */
  85#define DM_DIG_FA_TH2_LPS               30 /*  30 lps */
  86#define RSSI_OFFSET_DIG                 0x05;
  87
  88/* ANT Test */
  89#define ANTTESTALL              0x00    /* Ant A or B will be Testing */
  90#define ANTTESTA                0x01    /* Ant A will be Testing */
  91#define ANTTESTB                0x02    /* Ant B will be testing */
  92
  93/*  structure and define */
  94
  95/*  Add for AP/ADSLpseudo DM structuer requirement. */
  96/*  We need to remove to other position??? */
  97struct rtl8192cd_priv {
  98        u8              temp;
  99};
 100
 101struct rtw_dig {
 102        u8              Dig_Enable_Flag;
 103        u8              Dig_Ext_Port_Stage;
 104
 105        int             RssiLowThresh;
 106        int             RssiHighThresh;
 107
 108        u32             FALowThresh;
 109        u32             FAHighThresh;
 110
 111        u8              CurSTAConnectState;
 112        u8              PreSTAConnectState;
 113        u8              CurMultiSTAConnectState;
 114
 115        u8              PreIGValue;
 116        u8              CurIGValue;
 117        u8              BackupIGValue;
 118
 119        s8              BackoffVal;
 120        s8              BackoffVal_range_max;
 121        s8              BackoffVal_range_min;
 122        u8              rx_gain_range_max;
 123        u8              rx_gain_range_min;
 124        u8              Rssi_val_min;
 125
 126        u8              PreCCK_CCAThres;
 127        u8              CurCCK_CCAThres;
 128        u8              PreCCKPDState;
 129        u8              CurCCKPDState;
 130
 131        u8              LargeFAHit;
 132        u8              ForbiddenIGI;
 133        u32             Recover_cnt;
 134
 135        u8              DIG_Dynamic_MIN_0;
 136        u8              DIG_Dynamic_MIN_1;
 137        bool            bMediaConnect_0;
 138        bool            bMediaConnect_1;
 139
 140        u32             AntDiv_RSSI_max;
 141        u32             RSSI_max;
 142};
 143
 144struct rtl_ps {
 145        u8              PreCCAState;
 146        u8              CurCCAState;
 147
 148        u8              PreRFState;
 149        u8              CurRFState;
 150
 151        int                 Rssi_val_min;
 152
 153        u8              initialize;
 154        u32             Reg874,RegC70,Reg85C,RegA74;
 155
 156};
 157
 158struct false_alarm_stats {
 159        u32     Cnt_Parity_Fail;
 160        u32     Cnt_Rate_Illegal;
 161        u32     Cnt_Crc8_fail;
 162        u32     Cnt_Mcs_fail;
 163        u32     Cnt_Ofdm_fail;
 164        u32     Cnt_Cck_fail;
 165        u32     Cnt_all;
 166        u32     Cnt_Fast_Fsync;
 167        u32     Cnt_SB_Search_fail;
 168        u32     Cnt_OFDM_CCA;
 169        u32     Cnt_CCK_CCA;
 170        u32     Cnt_CCA_all;
 171        u32     Cnt_BW_USC;     /* Gary */
 172        u32     Cnt_BW_LSC;     /* Gary */
 173};
 174
 175struct dyn_primary_cca {
 176        u8              PriCCA_flag;
 177        u8              intf_flag;
 178        u8              intf_type;
 179        u8              DupRTS_flag;
 180        u8              Monitor_flag;
 181};
 182
 183struct rx_hpc {
 184        u8              RXHP_flag;
 185        u8              PSD_func_trigger;
 186        u8              PSD_bitmap_RXHP[80];
 187        u8              Pre_IGI;
 188        u8              Cur_IGI;
 189        u8              Pre_pw_th;
 190        u8              Cur_pw_th;
 191        bool            First_time_enter;
 192        bool            RXHP_enable;
 193        u8              TP_Mode;
 194        struct timer_list PSDTimer;
 195};
 196
 197#define ASSOCIATE_ENTRY_NUM     32 /*  Max size of AsocEntry[]. */
 198#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
 199
 200/*  This indicates two different steps. */
 201/*  In SWAW_STEP_PEAK, driver needs to switch antenna and listen to
 202 *  the signal on the air. */
 203/*  In SWAW_STEP_DETERMINE, driver just compares the signal captured in
 204 *  SWAW_STEP_PEAK with original RSSI to determine if it is necessary to
 205 *  switch antenna. */
 206
 207#define SWAW_STEP_PEAK          0
 208#define SWAW_STEP_DETERMINE     1
 209
 210#define TP_MODE                 0
 211#define RSSI_MODE               1
 212#define TRAFFIC_LOW             0
 213#define TRAFFIC_HIGH            1
 214
 215struct sw_ant_switch {
 216        u8      try_flag;
 217        s32     PreRSSI;
 218        u8      CurAntenna;
 219        u8      PreAntenna;
 220        u8      RSSI_Trying;
 221        u8      TestMode;
 222        u8      bTriggerAntennaSwitch;
 223        u8      SelectAntennaMap;
 224        u8      RSSI_target;
 225
 226        /*  Before link Antenna Switch check */
 227        u8      SWAS_NoLink_State;
 228        u32     SWAS_NoLink_BK_Reg860;
 229        bool    ANTA_ON;        /* To indicate Ant A is or not */
 230        bool    ANTB_ON;        /* To indicate Ant B is on or not */
 231
 232        s32     RSSI_sum_A;
 233        s32     RSSI_sum_B;
 234        s32     RSSI_cnt_A;
 235        s32     RSSI_cnt_B;
 236        u64     lastTxOkCnt;
 237        u64     lastRxOkCnt;
 238        u64     TXByteCnt_A;
 239        u64     TXByteCnt_B;
 240        u64     RXByteCnt_A;
 241        u64     RXByteCnt_B;
 242        u8      TrafficLoad;
 243        struct timer_list SwAntennaSwitchTimer;
 244        /* Hybrid Antenna Diversity */
 245        u32     CCK_Ant1_Cnt[ASSOCIATE_ENTRY_NUM];
 246        u32     CCK_Ant2_Cnt[ASSOCIATE_ENTRY_NUM];
 247        u32     OFDM_Ant1_Cnt[ASSOCIATE_ENTRY_NUM];
 248        u32     OFDM_Ant2_Cnt[ASSOCIATE_ENTRY_NUM];
 249        u32     RSSI_Ant1_Sum[ASSOCIATE_ENTRY_NUM];
 250        u32     RSSI_Ant2_Sum[ASSOCIATE_ENTRY_NUM];
 251        u8      TxAnt[ASSOCIATE_ENTRY_NUM];
 252        u8      TargetSTA;
 253        u8      antsel;
 254        u8      RxIdleAnt;
 255};
 256
 257struct edca_turbo {
 258        bool bCurrentTurboEDCA;
 259        bool bIsCurRDLState;
 260        u32     prv_traffic_idx; /*  edca turbo */
 261};
 262
 263struct odm_rate_adapt {
 264        u8      Type;           /*  DM_Type_ByFW/DM_Type_ByDriver */
 265        u8      HighRSSIThresh; /*  if RSSI > HighRSSIThresh    => RATRState is DM_RATR_STA_HIGH */
 266        u8      LowRSSIThresh;  /*  if RSSI <= LowRSSIThresh    => RATRState is DM_RATR_STA_LOW */
 267        u8      RATRState;      /*  Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */
 268        u32     LastRATR;       /*  RATR Register Content */
 269};
 270
 271#define IQK_MAC_REG_NUM         4
 272#define IQK_ADDA_REG_NUM        16
 273#define IQK_BB_REG_NUM_MAX      10
 274#define IQK_BB_REG_NUM          9
 275#define HP_THERMAL_NUM          8
 276
 277#define AVG_THERMAL_NUM         8
 278#define IQK_Matrix_REG_NUM      8
 279#define IQK_Matrix_Settings_NUM 1+24+21
 280
 281#define DM_Type_ByFWi           0
 282#define DM_Type_ByDriver        1
 283
 284/*  Declare for common info */
 285
 286#define MAX_PATH_NUM_92CS       2
 287
 288struct odm_phy_status_info {
 289        u8      RxPWDBAll;
 290        u8      SignalQuality;   /*  in 0-100 index. */
 291        u8      RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; /* EVM */
 292        u8      RxMIMOSignalStrength[MAX_PATH_NUM_92CS];/*  in 0~100 index */
 293        s8      RxPower; /*  in dBm Translate from PWdB */
 294        s8      RecvSignalPower;/*  Real power in dBm for this packet, no
 295                                 * beautification and aggregation. Keep this raw
 296                                 * info to be used for the other procedures. */
 297        u8      BTRxRSSIPercentage;
 298        u8      SignalStrength; /*  in 0-100 index. */
 299        u8      RxPwr[MAX_PATH_NUM_92CS];/* per-path's pwdb */
 300        u8      RxSNR[MAX_PATH_NUM_92CS];/* per-path's SNR */
 301};
 302
 303struct odm_phy_dbg_info {
 304        /* ODM Write,debug info */
 305        s8      RxSNRdB[MAX_PATH_NUM_92CS];
 306        u64     NumQryPhyStatus;
 307        u64     NumQryPhyStatusCCK;
 308        u64     NumQryPhyStatusOFDM;
 309        /* Others */
 310        s32     RxEVM[MAX_PATH_NUM_92CS];
 311};
 312
 313struct odm_per_pkt_info {
 314        s8      Rate;
 315        u8      StationID;
 316        bool    bPacketMatchBSSID;
 317        bool    bPacketToSelf;
 318        bool    bPacketBeacon;
 319};
 320
 321struct odm_mac_status_info {
 322        u8      test;
 323};
 324
 325enum odm_ability {
 326        /*  BB Team */
 327        ODM_DIG                 = 0x00000001,
 328        ODM_HIGH_POWER          = 0x00000002,
 329        ODM_CCK_CCA_TH          = 0x00000004,
 330        ODM_FA_STATISTICS       = 0x00000008,
 331        ODM_RAMASK              = 0x00000010,
 332        ODM_RSSI_MONITOR        = 0x00000020,
 333        ODM_SW_ANTDIV           = 0x00000040,
 334        ODM_HW_ANTDIV           = 0x00000080,
 335        ODM_BB_PWRSV            = 0x00000100,
 336        ODM_2TPATHDIV           = 0x00000200,
 337        ODM_1TPATHDIV           = 0x00000400,
 338        ODM_PSD2AFH             = 0x00000800
 339};
 340
 341/*  2011/20/20 MH For MP driver RT_WLAN_STA =  struct sta_info */
 342/*  Please declare below ODM relative info in your STA info structure. */
 343
 344struct odm_sta_info {
 345        /*  Driver Write */
 346        bool    bUsed;          /*  record the sta status link or not? */
 347        u8      IOTPeer;        /*  Enum value. HT_IOT_PEER_E */
 348
 349        /*  ODM Write */
 350        /* 1 PHY_STATUS_INFO */
 351        u8      RSSI_Path[4];           /*  */
 352        u8      RSSI_Ave;
 353        u8      RXEVM[4];
 354        u8      RXSNR[4];
 355};
 356
 357/*  2011/10/20 MH Define Common info enum for all team. */
 358
 359enum odm_common_info_def {
 360        /*  Fixed value: */
 361
 362        /* HOOK BEFORE REG INIT----------- */
 363        ODM_CMNINFO_PLATFORM = 0,
 364        ODM_CMNINFO_ABILITY,            /* ODM_ABILITY_E */
 365        ODM_CMNINFO_INTERFACE,          /* ODM_INTERFACE_E */
 366        ODM_CMNINFO_MP_TEST_CHIP,
 367        ODM_CMNINFO_IC_TYPE,            /* ODM_IC_TYPE_E */
 368        ODM_CMNINFO_CUT_VER,            /* ODM_CUT_VERSION_E */
 369        ODM_CMNINFO_FAB_VER,            /* ODM_FAB_E */
 370        ODM_CMNINFO_RF_TYPE,            /* ODM_RF_PATH_E or ODM_RF_TYPE_E? */
 371        ODM_CMNINFO_BOARD_TYPE,         /* ODM_BOARD_TYPE_E */
 372        ODM_CMNINFO_EXT_LNA,            /* true */
 373        ODM_CMNINFO_EXT_PA,
 374        ODM_CMNINFO_EXT_TRSW,
 375        ODM_CMNINFO_PATCH_ID,           /* CUSTOMER ID */
 376        ODM_CMNINFO_BINHCT_TEST,
 377        ODM_CMNINFO_BWIFI_TEST,
 378        ODM_CMNINFO_SMART_CONCURRENT,
 379        /* HOOK BEFORE REG INIT-----------  */
 380
 381        /*  Dynamic value: */
 382/*  POINTER REFERENCE-----------  */
 383        ODM_CMNINFO_MAC_PHY_MODE,       /*  ODM_MAC_PHY_MODE_E */
 384        ODM_CMNINFO_TX_UNI,
 385        ODM_CMNINFO_RX_UNI,
 386        ODM_CMNINFO_WM_MODE,            /*  ODM_WIRELESS_MODE_E */
 387        ODM_CMNINFO_BAND,               /*  ODM_BAND_TYPE_E */
 388        ODM_CMNINFO_SEC_CHNL_OFFSET,    /*  ODM_SEC_CHNL_OFFSET_E */
 389        ODM_CMNINFO_SEC_MODE,           /*  ODM_SECURITY_E */
 390        ODM_CMNINFO_BW,                 /*  ODM_BW_E */
 391        ODM_CMNINFO_CHNL,
 392
 393        ODM_CMNINFO_DMSP_GET_VALUE,
 394        ODM_CMNINFO_BUDDY_ADAPTOR,
 395        ODM_CMNINFO_DMSP_IS_MASTER,
 396        ODM_CMNINFO_SCAN,
 397        ODM_CMNINFO_POWER_SAVING,
 398        ODM_CMNINFO_ONE_PATH_CCA,       /*  ODM_CCA_PATH_E */
 399        ODM_CMNINFO_DRV_STOP,
 400        ODM_CMNINFO_PNP_IN,
 401        ODM_CMNINFO_INIT_ON,
 402        ODM_CMNINFO_ANT_TEST,
 403        ODM_CMNINFO_NET_CLOSED,
 404        ODM_CMNINFO_MP_MODE,
 405/*  POINTER REFERENCE----------- */
 406
 407/* CALL BY VALUE------------- */
 408        ODM_CMNINFO_WIFI_DIRECT,
 409        ODM_CMNINFO_WIFI_DISPLAY,
 410        ODM_CMNINFO_LINK,
 411        ODM_CMNINFO_RSSI_MIN,
 412        ODM_CMNINFO_DBG_COMP,                   /*  u64 */
 413        ODM_CMNINFO_DBG_LEVEL,                  /*  u32 */
 414        ODM_CMNINFO_RA_THRESHOLD_HIGH,          /*  u8 */
 415        ODM_CMNINFO_RA_THRESHOLD_LOW,           /*  u8 */
 416        ODM_CMNINFO_RF_ANTENNA_TYPE,            /*  u8 */
 417        ODM_CMNINFO_BT_DISABLED,
 418        ODM_CMNINFO_BT_OPERATION,
 419        ODM_CMNINFO_BT_DIG,
 420        ODM_CMNINFO_BT_BUSY,                    /* Check Bt is using or not */
 421        ODM_CMNINFO_BT_DISABLE_EDCA,
 422/* CALL BY VALUE-------------*/
 423
 424        /*  Dynamic ptr array hook itms. */
 425        ODM_CMNINFO_STA_STATUS,
 426        ODM_CMNINFO_PHY_STATUS,
 427        ODM_CMNINFO_MAC_STATUS,
 428        ODM_CMNINFO_MAX,
 429};
 430
 431/*  2011/10/20 MH Define ODM support ability.  ODM_CMNINFO_ABILITY */
 432
 433enum odm_ability_def {
 434        /*  BB ODM section BIT 0-15 */
 435        ODM_BB_DIG                      = BIT0,
 436        ODM_BB_RA_MASK                  = BIT1,
 437        ODM_BB_DYNAMIC_TXPWR            = BIT2,
 438        ODM_BB_FA_CNT                   = BIT3,
 439        ODM_BB_RSSI_MONITOR             = BIT4,
 440        ODM_BB_CCK_PD                   = BIT5,
 441        ODM_BB_ANT_DIV                  = BIT6,
 442        ODM_BB_PWR_SAVE                 = BIT7,
 443        ODM_BB_PWR_TRA                  = BIT8,
 444        ODM_BB_RATE_ADAPTIVE            = BIT9,
 445        ODM_BB_PATH_DIV                 = BIT10,
 446        ODM_BB_PSD                      = BIT11,
 447        ODM_BB_RXHP                     = BIT12,
 448
 449        /*  MAC DM section BIT 16-23 */
 450        ODM_MAC_EDCA_TURBO              = BIT16,
 451        ODM_MAC_EARLY_MODE              = BIT17,
 452
 453        /*  RF ODM section BIT 24-31 */
 454        ODM_RF_TX_PWR_TRACK             = BIT24,
 455        ODM_RF_RX_GAIN_TRACK            = BIT25,
 456        ODM_RF_CALIBRATION              = BIT26,
 457};
 458
 459/*      ODM_CMNINFO_INTERFACE */
 460enum odm_interface_def {
 461        ODM_ITRF_PCIE   =       0x1,
 462        ODM_ITRF_USB    =       0x2,
 463        ODM_ITRF_SDIO   =       0x4,
 464        ODM_ITRF_ALL    =       0x7,
 465};
 466
 467/*  ODM_CMNINFO_IC_TYPE */
 468enum odm_ic_type {
 469        ODM_RTL8192S    =       BIT0,
 470        ODM_RTL8192C    =       BIT1,
 471        ODM_RTL8192D    =       BIT2,
 472        ODM_RTL8723A    =       BIT3,
 473        ODM_RTL8188E    =       BIT4,
 474        ODM_RTL8812     =       BIT5,
 475        ODM_RTL8821     =       BIT6,
 476};
 477
 478#define ODM_IC_11N_SERIES                                               \
 479        (ODM_RTL8192S | ODM_RTL8192C | ODM_RTL8192D |                   \
 480         ODM_RTL8723A | ODM_RTL8188E)
 481#define ODM_IC_11AC_SERIES              (ODM_RTL8812)
 482
 483/* ODM_CMNINFO_CUT_VER */
 484enum odm_cut_version {
 485        ODM_CUT_A       =       1,
 486        ODM_CUT_B       =       2,
 487        ODM_CUT_C       =       3,
 488        ODM_CUT_D       =       4,
 489        ODM_CUT_E       =       5,
 490        ODM_CUT_F       =       6,
 491        ODM_CUT_TEST    =       7,
 492};
 493
 494/*  ODM_CMNINFO_FAB_VER */
 495enum odm_fab_Version {
 496        ODM_TSMC        =       0,
 497        ODM_UMC         =       1,
 498};
 499
 500/*  ODM_CMNINFO_RF_TYPE */
 501/*  For example 1T2R (A+AB = BIT0|BIT4|BIT5) */
 502enum odm_rf_path {
 503        ODM_RF_TX_A     =       BIT0,
 504        ODM_RF_TX_B     =       BIT1,
 505        ODM_RF_TX_C     =       BIT2,
 506        ODM_RF_TX_D     =       BIT3,
 507        ODM_RF_RX_A     =       BIT4,
 508        ODM_RF_RX_B     =       BIT5,
 509        ODM_RF_RX_C     =       BIT6,
 510        ODM_RF_RX_D     =       BIT7,
 511};
 512
 513enum odm_rf_type {
 514        ODM_1T1R        =       0,
 515        ODM_1T2R        =       1,
 516        ODM_2T2R        =       2,
 517        ODM_2T3R        =       3,
 518        ODM_2T4R        =       4,
 519        ODM_3T3R        =       5,
 520        ODM_3T4R        =       6,
 521        ODM_4T4R        =       7,
 522};
 523
 524/*  ODM Dynamic common info value definition */
 525
 526enum odm_mac_phy_mode {
 527        ODM_SMSP        = 0,
 528        ODM_DMSP        = 1,
 529        ODM_DMDP        = 2,
 530};
 531
 532enum odm_bt_coexist {
 533        ODM_BT_BUSY             = 1,
 534        ODM_BT_ON               = 2,
 535        ODM_BT_OFF              = 3,
 536        ODM_BT_NONE             = 4,
 537};
 538
 539/*  ODM_CMNINFO_OP_MODE */
 540enum odm_operation_mode {
 541        ODM_NO_LINK             = BIT0,
 542        ODM_LINK                = BIT1,
 543        ODM_SCAN                = BIT2,
 544        ODM_POWERSAVE           = BIT3,
 545        ODM_AP_MODE             = BIT4,
 546        ODM_CLIENT_MODE         = BIT5,
 547        ODM_AD_HOC              = BIT6,
 548        ODM_WIFI_DIRECT         = BIT7,
 549        ODM_WIFI_DISPLAY        = BIT8,
 550};
 551
 552/*  ODM_CMNINFO_WM_MODE */
 553enum odm_wireless_mode {
 554        ODM_WM_UNKNOW   = 0x0,
 555        ODM_WM_B        = BIT0,
 556        ODM_WM_G        = BIT1,
 557        ODM_WM_A        = BIT2,
 558        ODM_WM_N24G     = BIT3,
 559        ODM_WM_N5G      = BIT4,
 560        ODM_WM_AUTO     = BIT5,
 561        ODM_WM_AC       = BIT6,
 562};
 563
 564/*  ODM_CMNINFO_BAND */
 565enum odm_band_type {
 566        ODM_BAND_2_4G   = BIT0,
 567        ODM_BAND_5G     = BIT1,
 568};
 569
 570/*  ODM_CMNINFO_SEC_CHNL_OFFSET */
 571enum odm_sec_chnl_offset {
 572        ODM_DONT_CARE   = 0,
 573        ODM_BELOW       = 1,
 574        ODM_ABOVE       = 2
 575};
 576
 577/*  ODM_CMNINFO_SEC_MODE */
 578enum odm_security {
 579        ODM_SEC_OPEN            = 0,
 580        ODM_SEC_WEP40           = 1,
 581        ODM_SEC_TKIP            = 2,
 582        ODM_SEC_RESERVE         = 3,
 583        ODM_SEC_AESCCMP         = 4,
 584        ODM_SEC_WEP104          = 5,
 585        ODM_WEP_WPA_MIXED       = 6, /*  WEP + WPA */
 586        ODM_SEC_SMS4            = 7,
 587};
 588
 589/*  ODM_CMNINFO_BW */
 590enum odm_bw {
 591        ODM_BW20M               = 0,
 592        ODM_BW40M               = 1,
 593        ODM_BW80M               = 2,
 594        ODM_BW160M              = 3,
 595        ODM_BW10M               = 4,
 596};
 597
 598/*  ODM_CMNINFO_BOARD_TYPE */
 599enum odm_board_type {
 600        ODM_BOARD_NORMAL        = 0,
 601        ODM_BOARD_HIGHPWR       = 1,
 602        ODM_BOARD_MINICARD      = 2,
 603        ODM_BOARD_SLIM          = 3,
 604        ODM_BOARD_COMBO         = 4,
 605};
 606
 607/*  ODM_CMNINFO_ONE_PATH_CCA */
 608enum odm_cca_path {
 609        ODM_CCA_2R              = 0,
 610        ODM_CCA_1R_A            = 1,
 611        ODM_CCA_1R_B            = 2,
 612};
 613
 614struct odm_ra_info {
 615        u8 RateID;
 616        u32 RateMask;
 617        u32 RAUseRate;
 618        u8 RateSGI;
 619        u8 RssiStaRA;
 620        u8 PreRssiStaRA;
 621        u8 SGIEnable;
 622        u8 DecisionRate;
 623        u8 PreRate;
 624        u8 HighestRate;
 625        u8 LowestRate;
 626        u32 NscUp;
 627        u32 NscDown;
 628        u16 RTY[5];
 629        u32 TOTAL;
 630        u16 DROP;
 631        u8 Active;
 632        u16 RptTime;
 633        u8 RAWaitingCounter;
 634        u8 RAPendingCounter;
 635        u8 PTActive;    /*  on or off */
 636        u8 PTTryState;  /*  0 trying state, 1 for decision state */
 637        u8 PTStage;     /*  0~6 */
 638        u8 PTStopCount; /* Stop PT counter */
 639        u8 PTPreRate;   /*  if rate change do PT */
 640        u8 PTPreRssi;   /*  if RSSI change 5% do PT */
 641        u8 PTModeSS;    /*  decide whitch rate should do PT */
 642        u8 RAstage;     /*  StageRA, decide how many times RA will be done
 643                         * between PT */
 644        u8 PTSmoothFactor;
 645};
 646
 647struct ijk_matrix_regs_set {
 648        bool    bIQKDone;
 649        s32     Value[1][IQK_Matrix_REG_NUM];
 650};
 651
 652struct odm_rf_cal {
 653        /* for tx power tracking */
 654        u32     RegA24; /*  for TempCCK */
 655        s32     RegE94;
 656        s32     RegE9C;
 657        s32     RegEB4;
 658        s32     RegEBC;
 659
 660        u8      TXPowercount;
 661        bool    bTXPowerTrackingInit;
 662        bool    bTXPowerTracking;
 663        u8      TxPowerTrackControl; /* for mp mode, turn off txpwrtracking
 664                                      * as default */
 665        u8      TM_Trigger;
 666        u8      InternalPA5G[2];        /* pathA / pathB */
 667
 668        u8      ThermalMeter[2];    /* ThermalMeter, index 0 for RFIC0,
 669                                     * and 1 for RFIC1 */
 670        u8      ThermalValue;
 671        u8      ThermalValue_LCK;
 672        u8      ThermalValue_IQK;
 673        u8      ThermalValue_DPK;
 674        u8      ThermalValue_AVG[AVG_THERMAL_NUM];
 675        u8      ThermalValue_AVG_index;
 676        u8      ThermalValue_RxGain;
 677        u8      ThermalValue_Crystal;
 678        u8      ThermalValue_DPKstore;
 679        u8      ThermalValue_DPKtrack;
 680        bool    TxPowerTrackingInProgress;
 681        bool    bDPKenable;
 682
 683        bool    bReloadtxpowerindex;
 684        u8      bRfPiEnable;
 685        u32     TXPowerTrackingCallbackCnt; /* cosa add for debug */
 686
 687        u8      bCCKinCH14;
 688        u8      CCK_index;
 689        u8      OFDM_index[2];
 690        bool bDoneTxpower;
 691
 692        u8      ThermalValue_HP[HP_THERMAL_NUM];
 693        u8      ThermalValue_HP_index;
 694        struct ijk_matrix_regs_set IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
 695
 696        u8      Delta_IQK;
 697        u8      Delta_LCK;
 698
 699        /* for IQK */
 700        u32     RegC04;
 701        u32     Reg874;
 702        u32     RegC08;
 703        u32     RegB68;
 704        u32     RegB6C;
 705        u32     Reg870;
 706        u32     Reg860;
 707        u32     Reg864;
 708
 709        bool    bIQKInitialized;
 710        bool    bLCKInProgress;
 711        bool    bAntennaDetected;
 712        u32     ADDA_backup[IQK_ADDA_REG_NUM];
 713        u32     IQK_MAC_backup[IQK_MAC_REG_NUM];
 714        u32     IQK_BB_backup_recover[9];
 715        u32     IQK_BB_backup[IQK_BB_REG_NUM];
 716
 717        /* for APK */
 718        u32     APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */
 719        u8      bAPKdone;
 720        u8      bAPKThermalMeterIgnore;
 721        u8      bDPdone;
 722        u8      bDPPathAOK;
 723        u8      bDPPathBOK;
 724};
 725
 726/*  ODM Dynamic common info value definition */
 727
 728struct fast_ant_train {
 729        u8      Bssid[6];
 730        u8      antsel_rx_keep_0;
 731        u8      antsel_rx_keep_1;
 732        u8      antsel_rx_keep_2;
 733        u32     antSumRSSI[7];
 734        u32     antRSSIcnt[7];
 735        u32     antAveRSSI[7];
 736        u8      FAT_State;
 737        u32     TrainIdx;
 738        u8      antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
 739        u8      antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
 740        u8      antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
 741        u32     MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
 742        u32     AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
 743        u32     MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
 744        u32     AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
 745        u8      RxIdleAnt;
 746        bool    bBecomeLinked;
 747};
 748
 749enum fat_state {
 750        FAT_NORMAL_STATE                = 0,
 751        FAT_TRAINING_STATE              = 1,
 752};
 753
 754enum ant_div_type {
 755        NO_ANTDIV                       = 0xFF,
 756        CG_TRX_HW_ANTDIV                = 0x01,
 757        CGCS_RX_HW_ANTDIV               = 0x02,
 758        FIXED_HW_ANTDIV                 = 0x03,
 759        CG_TRX_SMART_ANTDIV             = 0x04,
 760        CGCS_RX_SW_ANTDIV               = 0x05,
 761};
 762
 763/* Copy from SD4 defined structure. We use to support PHY DM integration. */
 764struct odm_dm_struct {
 765        /*      Add for different team use temporarily */
 766        struct adapter *Adapter;        /*  For CE/NIC team */
 767        struct rtl8192cd_priv *priv;    /*  For AP/ADSL team */
 768        /*  WHen you use above pointers, they must be initialized. */
 769        bool    odm_ready;
 770
 771        struct rtl8192cd_priv *fake_priv;
 772        u64     DebugComponents;
 773        u32     DebugLevel;
 774
 775/*  ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
 776        bool    bCckHighPower;
 777        u8      RFPathRxEnable;         /*  ODM_CMNINFO_RFPATH_ENABLE */
 778        u8      ControlChannel;
 779/*  ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
 780
 781/* 1  COMMON INFORMATION */
 782        /*  Init Value */
 783/* HOOK BEFORE REG INIT----------- */
 784        /*  ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 */
 785        u8      SupportPlatform;
 786        /*  ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K */
 787        u32     SupportAbility;
 788        /*  ODM PCIE/USB/SDIO/GSPI = 0/1/2/3 */
 789        u8      SupportInterface;
 790        /*  ODM composite or independent. Bit oriented/ 92C+92D+ .... or any
 791         *  other type = 1/2/3/... */
 792        u32     SupportICType;
 793        /*  Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */
 794        u8      CutVersion;
 795        /*  Fab Version TSMC/UMC = 0/1 */
 796        u8      FabVersion;
 797        /*  RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */
 798        u8      RFType;
 799        /*  Board Type Normal/HighPower/MiniCard/SLIM/Combo/. = 0/1/2/3/4/. */
 800        u8      BoardType;
 801        /*  with external LNA  NO/Yes = 0/1 */
 802        u8      ExtLNA;
 803        /*  with external PA  NO/Yes = 0/1 */
 804        u8      ExtPA;
 805        /*  with external TRSW  NO/Yes = 0/1 */
 806        u8      ExtTRSW;
 807        u8      PatchID; /* Customer ID */
 808        bool    bInHctTest;
 809        bool    bWIFITest;
 810
 811        bool    bDualMacSmartConcurrent;
 812        u32     BK_SupportAbility;
 813        u8      AntDivType;
 814/* HOOK BEFORE REG INIT----------- */
 815
 816        /*  Dynamic Value */
 817/*  POINTER REFERENCE----------- */
 818
 819        u8      u8_temp;
 820        bool    bool_temp;
 821        struct adapter *adapter_temp;
 822
 823        /*  MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */
 824        u8      *pMacPhyMode;
 825        /* TX Unicast byte count */
 826        u64     *pNumTxBytesUnicast;
 827        /* RX Unicast byte count */
 828        u64     *pNumRxBytesUnicast;
 829        /*  Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */
 830        u8      *pWirelessMode; /* ODM_WIRELESS_MODE_E */
 831        /*  Frequence band 2.4G/5G = 0/1 */
 832        u8      *pBandType;
 833        /*  Secondary channel offset don't_care/below/above = 0/1/2 */
 834        u8      *pSecChOffset;
 835        /*  Security mode Open/WEP/AES/TKIP = 0/1/2/3 */
 836        u8      *pSecurity;
 837        /*  BW info 20M/40M/80M = 0/1/2 */
 838        u8      *pBandWidth;
 839        /*  Central channel location Ch1/Ch2/.... */
 840        u8      *pChannel;      /* central channel number */
 841        /*  Common info for 92D DMSP */
 842
 843        bool    *pbGetValueFromOtherMac;
 844        struct adapter **pBuddyAdapter;
 845        bool    *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */
 846        /*  Common info for Status */
 847        bool    *pbScanInProcess;
 848        bool    *pbPowerSaving;
 849        /*  CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */
 850        u8      *pOnePathCCA;
 851        /* pMgntInfo->AntennaTest */
 852        u8      *pAntennaTest;
 853        bool    *pbNet_closed;
 854/*  POINTER REFERENCE----------- */
 855        /*  */
 856/* CALL BY VALUE------------- */
 857        bool    bWIFI_Direct;
 858        bool    bWIFI_Display;
 859        bool    bLinked;
 860        u8      RSSI_Min;
 861        u8      InterfaceIndex; /*  Add for 92D  dual MAC: 0--Mac0 1--Mac1 */
 862        bool    bIsMPChip;
 863        bool    bOneEntryOnly;
 864        /*  Common info for BTDM */
 865        bool    bBtDisabled;    /*  BT is disabled */
 866        bool    bBtHsOperation; /*  BT HS mode is under progress */
 867        u8      btHsDigVal;     /*  use BT rssi to decide the DIG value */
 868        bool    bBtDisableEdcaTurbo;/* Under some condition, don't enable the
 869                                     * EDCA Turbo */
 870        bool    bBtBusy;                        /*  BT is busy. */
 871/* CALL BY VALUE------------- */
 872
 873        /* 2 Define STA info. */
 874        /*  _ODM_STA_INFO */
 875        /*  For MP, we need to reduce one array pointer for default port.?? */
 876        struct sta_info *pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM];
 877
 878        u16     CurrminRptTime;
 879        struct odm_ra_info RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; /* Use MacID as
 880                        * array index. STA MacID=0,
 881                        * VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} */
 882        /*  */
 883        /*  2012/02/14 MH Add to share 88E ra with other SW team. */
 884        /*  We need to colelct all support abilit to a proper area. */
 885        /*  */
 886        bool    RaSupport88E;
 887
 888        /*  Define ........... */
 889
 890        /*  Latest packet phy info (ODM write) */
 891        struct odm_phy_dbg_info PhyDbgInfo;
 892
 893        /*  Latest packet phy info (ODM write) */
 894        struct odm_mac_status_info *pMacInfo;
 895
 896        /*  Different Team independt structure?? */
 897
 898        /* ODM Structure */
 899        struct fast_ant_train DM_FatTable;
 900        struct rtw_dig  DM_DigTable;
 901        struct rtl_ps   DM_PSTable;
 902        struct dyn_primary_cca DM_PriCCA;
 903        struct rx_hpc   DM_RXHP_Table;
 904        struct false_alarm_stats FalseAlmCnt;
 905        struct false_alarm_stats FlaseAlmCntBuddyAdapter;
 906        struct sw_ant_switch DM_SWAT_Table;
 907        bool            RSSI_test;
 908
 909        struct edca_turbo DM_EDCA_Table;
 910        u32             WMMEDCA_BE;
 911        /*  Copy from SD4 structure */
 912        /*  */
 913        /*  ================================================== */
 914        /*  */
 915
 916        bool    *pbDriverStopped;
 917        bool    *pbDriverIsGoingToPnpSetPowerSleep;
 918        bool    *pinit_adpt_in_progress;
 919
 920        /* PSD */
 921        bool    bUserAssignLevel;
 922        struct timer_list PSDTimer;
 923        u8      RSSI_BT;                        /* come from BT */
 924        bool    bPSDinProcess;
 925        bool    bDMInitialGainEnable;
 926
 927        /* for rate adaptive, in fact,  88c/92c fw will handle this */
 928        u8      bUseRAMask;
 929
 930        struct odm_rate_adapt RateAdaptive;
 931
 932        struct odm_rf_cal RFCalibrateInfo;
 933
 934        /*  TX power tracking */
 935        u8      BbSwingIdxOfdm;
 936        u8      BbSwingIdxOfdmCurrent;
 937        u8      BbSwingIdxOfdmBase;
 938        bool    BbSwingFlagOfdm;
 939        u8      BbSwingIdxCck;
 940        u8      BbSwingIdxCckCurrent;
 941        u8      BbSwingIdxCckBase;
 942        bool    BbSwingFlagCck;
 943        u8      *mp_mode;
 944        /*  ODM system resource. */
 945
 946        /*  ODM relative time. */
 947        struct timer_list PathDivSwitchTimer;
 948        /* 2011.09.27 add for Path Diversity */
 949        struct timer_list CCKPathDiversityTimer;
 950        struct timer_list FastAntTrainingTimer;
 951};              /*  DM_Dynamic_Mechanism_Structure */
 952
 953#define ODM_RF_PATH_MAX 2
 954
 955enum ODM_RF_RADIO_PATH {
 956        ODM_RF_PATH_A = 0,   /* Radio Path A */
 957        ODM_RF_PATH_B = 1,   /* Radio Path B */
 958        ODM_RF_PATH_C = 2,   /* Radio Path C */
 959        ODM_RF_PATH_D = 3,   /* Radio Path D */
 960};
 961
 962enum ODM_RF_CONTENT {
 963        odm_radioa_txt = 0x1000,
 964        odm_radiob_txt = 0x1001,
 965        odm_radioc_txt = 0x1002,
 966        odm_radiod_txt = 0x1003
 967};
 968
 969enum odm_bb_config_type {
 970    CONFIG_BB_PHY_REG,
 971    CONFIG_BB_AGC_TAB,
 972    CONFIG_BB_AGC_TAB_2G,
 973    CONFIG_BB_AGC_TAB_5G,
 974    CONFIG_BB_PHY_REG_PG,
 975};
 976
 977/*  Status code */
 978enum rt_status {
 979        RT_STATUS_SUCCESS,
 980        RT_STATUS_FAILURE,
 981        RT_STATUS_PENDING,
 982        RT_STATUS_RESOURCE,
 983        RT_STATUS_INVALID_CONTEXT,
 984        RT_STATUS_INVALID_PARAMETER,
 985        RT_STATUS_NOT_SUPPORT,
 986        RT_STATUS_OS_API_FAILED,
 987};
 988
 989/* 3=========================================================== */
 990/* 3 DIG */
 991/* 3=========================================================== */
 992
 993enum dm_dig_op {
 994        RT_TYPE_THRESH_HIGH     = 0,
 995        RT_TYPE_THRESH_LOW      = 1,
 996        RT_TYPE_BACKOFF         = 2,
 997        RT_TYPE_RX_GAIN_MIN     = 3,
 998        RT_TYPE_RX_GAIN_MAX     = 4,
 999        RT_TYPE_ENABLE          = 5,
1000        RT_TYPE_DISABLE         = 6,

1001        DIG_OP_TYPE_MAX
1002};
1003
1004#define         DM_DIG_THRESH_HIGH      40
1005#define         DM_DIG_THRESH_LOW       35
1006
1007#define         DM_SCAN_RSSI_TH         0x14 /* scan return issue for LC */
1008
1009
1010#define         DM_false_ALARM_THRESH_LOW       400
1011#define         DM_false_ALARM_THRESH_HIGH      1000
1012
1013#define         DM_DIG_MAX_NIC                  0x4e
1014#define         DM_DIG_MIN_NIC                  0x1e /* 0x22/0x1c */
1015
1016#define         DM_DIG_MAX_AP                   0x32
1017#define         DM_DIG_MIN_AP                   0x20
1018
1019#define         DM_DIG_MAX_NIC_HP               0x46
1020#define         DM_DIG_MIN_NIC_HP               0x2e
1021
1022#define         DM_DIG_MAX_AP_HP                0x42
1023#define         DM_DIG_MIN_AP_HP                0x30
1024
1025/* vivi 92c&92d has different definition, 20110504 */
1026/* this is for 92c */
1027#define         DM_DIG_FA_TH0                   0x200/* 0x20 */
1028#define         DM_DIG_FA_TH1                   0x300/* 0x100 */
1029#define         DM_DIG_FA_TH2                   0x400/* 0x200 */
1030/* this is for 92d */
1031#define         DM_DIG_FA_TH0_92D               0x100
1032#define         DM_DIG_FA_TH1_92D               0x400
1033#define         DM_DIG_FA_TH2_92D               0x600
1034
1035#define         DM_DIG_BACKOFF_MAX              12
1036#define         DM_DIG_BACKOFF_MIN              -4
1037#define         DM_DIG_BACKOFF_DEFAULT          10
1038
1039/* 3=========================================================== */
1040/* 3 AGC RX High Power Mode */
1041/* 3=========================================================== */
1042#define   LNA_Low_Gain_1                0x64
1043#define   LNA_Low_Gain_2                0x5A
1044#define   LNA_Low_Gain_3                0x58
1045
1046#define   FA_RXHP_TH1                   5000
1047#define   FA_RXHP_TH2                   1500
1048#define   FA_RXHP_TH3                   800
1049#define   FA_RXHP_TH4                   600
1050#define   FA_RXHP_TH5                   500
1051
1052/* 3=========================================================== */
1053/* 3 EDCA */
1054/* 3=========================================================== */
1055
1056/* 3=========================================================== */
1057/* 3 Dynamic Tx Power */
1058/* 3=========================================================== */
1059/* Dynamic Tx Power Control Threshold */
1060#define         TX_POWER_NEAR_FIELD_THRESH_LVL2 74
1061#define         TX_POWER_NEAR_FIELD_THRESH_LVL1 67
1062#define         TX_POWER_NEAR_FIELD_THRESH_AP           0x3F
1063
1064#define         TxHighPwrLevel_Normal           0
1065#define         TxHighPwrLevel_Level1           1
1066#define         TxHighPwrLevel_Level2           2
1067#define         TxHighPwrLevel_BT1              3
1068#define         TxHighPwrLevel_BT2              4
1069#define         TxHighPwrLevel_15               5
1070#define         TxHighPwrLevel_35               6
1071#define         TxHighPwrLevel_50               7
1072#define         TxHighPwrLevel_70               8
1073#define         TxHighPwrLevel_100              9
1074
1075/* 3=========================================================== */
1076/* 3 Rate Adaptive */
1077/* 3=========================================================== */
1078#define         DM_RATR_STA_INIT                0
1079#define         DM_RATR_STA_HIGH                1
1080#define         DM_RATR_STA_MIDDLE              2
1081#define         DM_RATR_STA_LOW                 3
1082
1083/* 3=========================================================== */
1084/* 3 BB Power Save */
1085/* 3=========================================================== */
1086
1087
1088enum dm_1r_cca {
1089        CCA_1R = 0,
1090        CCA_2R = 1,
1091        CCA_MAX = 2,
1092};
1093
1094enum dm_rf {
1095        RF_Save = 0,
1096        RF_Normal = 1,
1097        RF_MAX = 2,
1098};
1099
1100/* 3=========================================================== */
1101/* 3 Antenna Diversity */
1102/* 3=========================================================== */
1103enum dm_swas {
1104        Antenna_A = 1,
1105        Antenna_B = 2,
1106        Antenna_MAX = 3,
1107};
1108
1109/*  Maximal number of antenna detection mechanism needs to perform. */
1110#define MAX_ANTENNA_DETECTION_CNT       10
1111
1112/*  Extern Global Variables. */
1113#define OFDM_TABLE_SIZE_92C     37
1114#define OFDM_TABLE_SIZE_92D     43
1115#define CCK_TABLE_SIZE          33
1116
1117extern  u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D];
1118extern  u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
1119extern  u8 CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8];
1120
1121/*  check Sta pointer valid or not */
1122#define IS_STA_VALID(pSta)              (pSta)
1123/*  20100514 Joseph: Add definition for antenna switching test after link. */
1124/*  This indicates two different the steps. */
1125/*  In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the
1126 *  signal on the air. */
1127/*  In SWAW_STEP_DETERMINE, driver just compares the signal captured in
1128 *  SWAW_STEP_PEAK */
1129/*  with original RSSI to determine if it is necessary to switch antenna. */
1130#define SWAW_STEP_PEAK          0
1131#define SWAW_STEP_DETERMINE     1
1132
1133void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI);
1134void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres);
1135
1136void ODM_SetAntenna(struct odm_dm_struct *pDM_Odm, u8 Antenna);
1137
1138
1139#define dm_RF_Saving    ODM_RF_Saving
1140void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal);
1141
1142#define SwAntDivRestAfterLink   ODM_SwAntDivRestAfterLink
1143void ODM_SwAntDivRestAfterLink(struct odm_dm_struct *pDM_Odm);
1144
1145#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck
1146void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm);
1147
1148bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI,
1149                      bool bForceUpdate, u8 *pRATRState);
1150
1151#define dm_SWAW_RSSI_Check      ODM_SwAntDivChkPerPktRssi
1152void ODM_SwAntDivChkPerPktRssi(struct odm_dm_struct *pDM_Odm, u8 StationID,
1153                               struct odm_phy_status_info *pPhyInfo);
1154
1155u32 ConvertTo_dB(u32 Value);
1156
1157u32 GetPSDData(struct odm_dm_struct *pDM_Odm, unsigned int point,
1158               u8 initial_gain_psd);
1159
1160void odm_DIGbyRSSI_LPS(struct odm_dm_struct *pDM_Odm);
1161
1162u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid,
1163                        u32 ra_mask, u8 rssi_level);
1164
1165void ODM_DMInit(struct odm_dm_struct *pDM_Odm);
1166
1167void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm);
1168
1169void ODM_CmnInfoInit(struct odm_dm_struct *pDM_Odm,
1170                     enum odm_common_info_def CmnInfo, u32 Value);
1171
1172void ODM_CmnInfoHook(struct odm_dm_struct *pDM_Odm,
1173                     enum odm_common_info_def CmnInfo, void *pValue);
1174
1175void ODM_CmnInfoPtrArrayHook(struct odm_dm_struct *pDM_Odm,
1176                             enum odm_common_info_def CmnInfo,
1177                             u16 Index, void *pValue);
1178
1179void ODM_CmnInfoUpdate(struct odm_dm_struct *pDM_Odm, u32 CmnInfo, u64 Value);
1180
1181void ODM_InitAllTimers(struct odm_dm_struct *pDM_Odm);
1182
1183void ODM_CancelAllTimers(struct odm_dm_struct *pDM_Odm);
1184
1185void ODM_ReleaseAllTimers(struct odm_dm_struct *pDM_Odm);
1186
1187void ODM_ResetIQKResult(struct odm_dm_struct *pDM_Odm);
1188
1189void ODM_AntselStatistics_88C(struct odm_dm_struct *pDM_Odm, u8 MacId,
1190                              u32 PWDBAll, bool isCCKrate);
1191
1192void ODM_SingleDualAntennaDefaultSetting(struct odm_dm_struct *pDM_Odm);
1193
1194bool ODM_SingleDualAntennaDetection(struct odm_dm_struct *pDM_Odm, u8 mode);
1195
1196void odm_dtc(struct odm_dm_struct *pDM_Odm);
1197
1198#endif
1199