1
2
3
4
5
6
7
8
9
10
11
12
13#ifndef __DRIVERS_USB_CHIPIDEA_CI_H
14#define __DRIVERS_USB_CHIPIDEA_CI_H
15
16#include <linux/list.h>
17#include <linux/irqreturn.h>
18#include <linux/usb.h>
19#include <linux/usb/gadget.h>
20
21
22
23
24#define TD_PAGE_COUNT 5
25#define CI_HDRC_PAGE_SIZE 4096ul
26#define ENDPT_MAX 32
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44struct ci_hw_ep {
45 struct usb_ep ep;
46 u8 dir;
47 u8 num;
48 u8 type;
49 char name[16];
50 struct {
51 struct list_head queue;
52 struct ci_hw_qh *ptr;
53 dma_addr_t dma;
54 } qh;
55 int wedge;
56
57
58 struct ci_hdrc *ci;
59 spinlock_t *lock;
60 struct dma_pool *td_pool;
61 struct td_node *pending_td;
62};
63
64enum ci_role {
65 CI_ROLE_HOST = 0,
66 CI_ROLE_GADGET,
67 CI_ROLE_END,
68};
69
70
71
72
73
74
75
76
77struct ci_role_driver {
78 int (*start)(struct ci_hdrc *);
79 void (*stop)(struct ci_hdrc *);
80 irqreturn_t (*irq)(struct ci_hdrc *);
81 const char *name;
82};
83
84
85
86
87
88
89
90
91
92
93
94struct hw_bank {
95 unsigned lpm;
96 resource_size_t phys;
97 void __iomem *abs;
98 void __iomem *cap;
99 void __iomem *op;
100 size_t size;
101 void __iomem **regmap;
102};
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139struct ci_hdrc {
140 struct device *dev;
141 spinlock_t lock;
142 struct hw_bank hw_bank;
143 int irq;
144 struct ci_role_driver *roles[CI_ROLE_END];
145 enum ci_role role;
146 bool is_otg;
147 struct work_struct work;
148 struct workqueue_struct *wq;
149
150 struct dma_pool *qh_pool;
151 struct dma_pool *td_pool;
152
153 struct usb_gadget gadget;
154 struct usb_gadget_driver *driver;
155 unsigned hw_ep_max;
156 struct ci_hw_ep ci_hw_ep[ENDPT_MAX];
157 u32 ep0_dir;
158 struct ci_hw_ep *ep0out, *ep0in;
159
160 struct usb_request *status;
161 bool setaddr;
162 u8 address;
163 u8 remote_wakeup;
164 u8 suspended;
165 u8 test_mode;
166
167 struct ci_hdrc_platform_data *platdata;
168 int vbus_active;
169
170 bool global_phy;
171 struct usb_phy *transceiver;
172 struct usb_hcd *hcd;
173 struct dentry *debugfs;
174 bool id_event;
175 bool b_sess_valid_event;
176};
177
178static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
179{
180 BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
181 return ci->roles[ci->role];
182}
183
184static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
185{
186 int ret;
187
188 if (role >= CI_ROLE_END)
189 return -EINVAL;
190
191 if (!ci->roles[role])
192 return -ENXIO;
193
194 ret = ci->roles[role]->start(ci);
195 if (!ret)
196 ci->role = role;
197 return ret;
198}
199
200static inline void ci_role_stop(struct ci_hdrc *ci)
201{
202 enum ci_role role = ci->role;
203
204 if (role == CI_ROLE_END)
205 return;
206
207 ci->role = CI_ROLE_END;
208
209 ci->roles[role]->stop(ci);
210}
211
212
213
214
215
216#define REG_BITS (32)
217
218
219enum ci_hw_regs {
220 CAP_CAPLENGTH,
221 CAP_HCCPARAMS,
222 CAP_DCCPARAMS,
223 CAP_TESTMODE,
224 CAP_LAST = CAP_TESTMODE,
225 OP_USBCMD,
226 OP_USBSTS,
227 OP_USBINTR,
228 OP_DEVICEADDR,
229 OP_ENDPTLISTADDR,
230 OP_PORTSC,
231 OP_DEVLC,
232 OP_OTGSC,
233 OP_USBMODE,
234 OP_ENDPTSETUPSTAT,
235 OP_ENDPTPRIME,
236 OP_ENDPTFLUSH,
237 OP_ENDPTSTAT,
238 OP_ENDPTCOMPLETE,
239 OP_ENDPTCTRL,
240
241 OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
242};
243
244
245
246
247
248
249
250
251static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
252{
253 return ioread32(ci->hw_bank.regmap[reg]) & mask;
254}
255
256
257
258
259
260
261
262static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
263 u32 mask, u32 data)
264{
265 if (~mask)
266 data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
267 | (data & mask);
268
269 iowrite32(data, ci->hw_bank.regmap[reg]);
270}
271
272
273
274
275
276
277
278
279static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
280 u32 mask)
281{
282 u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
283
284 iowrite32(val, ci->hw_bank.regmap[reg]);
285 return val;
286}
287
288
289
290
291
292
293
294
295
296static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
297 u32 mask, u32 data)
298{
299 u32 val = hw_read(ci, reg, ~0);
300
301 hw_write(ci, reg, mask, data);
302 return (val & mask) >> __ffs(mask);
303}
304
305int hw_device_reset(struct ci_hdrc *ci, u32 mode);
306
307int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
308
309u8 hw_port_test_get(struct ci_hdrc *ci);
310
311int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
312 u32 value, unsigned int timeout_ms);
313
314#endif
315