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19#ifndef __DRIVERS_USB_DWC3_CORE_H
20#define __DRIVERS_USB_DWC3_CORE_H
21
22#include <linux/device.h>
23#include <linux/spinlock.h>
24#include <linux/ioport.h>
25#include <linux/list.h>
26#include <linux/dma-mapping.h>
27#include <linux/mm.h>
28#include <linux/debugfs.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32#include <linux/usb/otg.h>
33
34
35#define DWC3_EP0_BOUNCE_SIZE 512
36#define DWC3_ENDPOINTS_NUM 32
37#define DWC3_XHCI_RESOURCES_NUM 2
38
39#define DWC3_EVENT_SIZE 4
40#define DWC3_EVENT_MAX_NUM 64
41#define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM)
42#define DWC3_EVENT_TYPE_MASK 0xfe
43
44#define DWC3_EVENT_TYPE_DEV 0
45#define DWC3_EVENT_TYPE_CARKIT 3
46#define DWC3_EVENT_TYPE_I2C 4
47
48#define DWC3_DEVICE_EVENT_DISCONNECT 0
49#define DWC3_DEVICE_EVENT_RESET 1
50#define DWC3_DEVICE_EVENT_CONNECT_DONE 2
51#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
52#define DWC3_DEVICE_EVENT_WAKEUP 4
53#define DWC3_DEVICE_EVENT_HIBER_REQ 5
54#define DWC3_DEVICE_EVENT_EOPF 6
55#define DWC3_DEVICE_EVENT_SOF 7
56#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
57#define DWC3_DEVICE_EVENT_CMD_CMPL 10
58#define DWC3_DEVICE_EVENT_OVERFLOW 11
59
60#define DWC3_GEVNTCOUNT_MASK 0xfffc
61#define DWC3_GSNPSID_MASK 0xffff0000
62#define DWC3_GSNPSREV_MASK 0xffff
63
64
65#define DWC3_XHCI_REGS_START 0x0
66#define DWC3_XHCI_REGS_END 0x7fff
67#define DWC3_GLOBALS_REGS_START 0xc100
68#define DWC3_GLOBALS_REGS_END 0xc6ff
69#define DWC3_DEVICE_REGS_START 0xc700
70#define DWC3_DEVICE_REGS_END 0xcbff
71#define DWC3_OTG_REGS_START 0xcc00
72#define DWC3_OTG_REGS_END 0xccff
73
74
75#define DWC3_GSBUSCFG0 0xc100
76#define DWC3_GSBUSCFG1 0xc104
77#define DWC3_GTXTHRCFG 0xc108
78#define DWC3_GRXTHRCFG 0xc10c
79#define DWC3_GCTL 0xc110
80#define DWC3_GEVTEN 0xc114
81#define DWC3_GSTS 0xc118
82#define DWC3_GSNPSID 0xc120
83#define DWC3_GGPIO 0xc124
84#define DWC3_GUID 0xc128
85#define DWC3_GUCTL 0xc12c
86#define DWC3_GBUSERRADDR0 0xc130
87#define DWC3_GBUSERRADDR1 0xc134
88#define DWC3_GPRTBIMAP0 0xc138
89#define DWC3_GPRTBIMAP1 0xc13c
90#define DWC3_GHWPARAMS0 0xc140
91#define DWC3_GHWPARAMS1 0xc144
92#define DWC3_GHWPARAMS2 0xc148
93#define DWC3_GHWPARAMS3 0xc14c
94#define DWC3_GHWPARAMS4 0xc150
95#define DWC3_GHWPARAMS5 0xc154
96#define DWC3_GHWPARAMS6 0xc158
97#define DWC3_GHWPARAMS7 0xc15c
98#define DWC3_GDBGFIFOSPACE 0xc160
99#define DWC3_GDBGLTSSM 0xc164
100#define DWC3_GPRTBIMAP_HS0 0xc180
101#define DWC3_GPRTBIMAP_HS1 0xc184
102#define DWC3_GPRTBIMAP_FS0 0xc188
103#define DWC3_GPRTBIMAP_FS1 0xc18c
104
105#define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
106#define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04))
107
108#define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04))
109
110#define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))
111
112#define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04))
113#define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04))
114
115#define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10))
116#define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10))
117#define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10))
118#define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10))
119
120#define DWC3_GHWPARAMS8 0xc600
121
122
123#define DWC3_DCFG 0xc700
124#define DWC3_DCTL 0xc704
125#define DWC3_DEVTEN 0xc708
126#define DWC3_DSTS 0xc70c
127#define DWC3_DGCMDPAR 0xc710
128#define DWC3_DGCMD 0xc714
129#define DWC3_DALEPENA 0xc720
130#define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10))
131#define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10))
132#define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10))
133#define DWC3_DEPCMD(n) (0xc80c + (n * 0x10))
134
135
136#define DWC3_OCFG 0xcc00
137#define DWC3_OCTL 0xcc04
138#define DWC3_OEVT 0xcc08
139#define DWC3_OEVTEN 0xcc0C
140#define DWC3_OSTS 0xcc10
141
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143
144
145#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
146#define DWC3_GCTL_U2RSTECN (1 << 16)
147#define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
148#define DWC3_GCTL_CLK_BUS (0)
149#define DWC3_GCTL_CLK_PIPE (1)
150#define DWC3_GCTL_CLK_PIPEHALF (2)
151#define DWC3_GCTL_CLK_MASK (3)
152
153#define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
154#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
155#define DWC3_GCTL_PRTCAP_HOST 1
156#define DWC3_GCTL_PRTCAP_DEVICE 2
157#define DWC3_GCTL_PRTCAP_OTG 3
158
159#define DWC3_GCTL_CORESOFTRESET (1 << 11)
160#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
161#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
162#define DWC3_GCTL_DISSCRAMBLE (1 << 3)
163#define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1)
164#define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
165
166
167#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
168#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
169
170
171#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
172#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
173
174
175#define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
176#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
177
178
179#define DWC3_GEVNTSIZ_INTMASK (1 << 31)
180#define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
181
182
183#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
184#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
185#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
186#define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
187#define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
188#define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
189
190
191#define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
192#define DWC3_MAX_HIBER_SCRATCHBUFS 15
193
194
195#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
196#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
197
198#define DWC3_DCFG_SPEED_MASK (7 << 0)
199#define DWC3_DCFG_SUPERSPEED (4 << 0)
200#define DWC3_DCFG_HIGHSPEED (0 << 0)
201#define DWC3_DCFG_FULLSPEED2 (1 << 0)
202#define DWC3_DCFG_LOWSPEED (2 << 0)
203#define DWC3_DCFG_FULLSPEED1 (3 << 0)
204
205#define DWC3_DCFG_LPM_CAP (1 << 22)
206
207
208#define DWC3_DCTL_RUN_STOP (1 << 31)
209#define DWC3_DCTL_CSFTRST (1 << 30)
210#define DWC3_DCTL_LSFTRST (1 << 29)
211
212#define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
213#define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
214
215#define DWC3_DCTL_APPL1RES (1 << 23)
216
217
218#define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
219#define DWC3_DCTL_TRGTULST(n) ((n) << 17)
220#define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
221#define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
222#define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
223#define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
224#define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
225
226
227#define DWC3_DCTL_KEEP_CONNECT (1 << 19)
228#define DWC3_DCTL_L1_HIBER_EN (1 << 18)
229#define DWC3_DCTL_CRS (1 << 17)
230#define DWC3_DCTL_CSS (1 << 16)
231
232#define DWC3_DCTL_INITU2ENA (1 << 12)
233#define DWC3_DCTL_ACCEPTU2ENA (1 << 11)
234#define DWC3_DCTL_INITU1ENA (1 << 10)
235#define DWC3_DCTL_ACCEPTU1ENA (1 << 9)
236#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
237
238#define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
239#define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
240
241#define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
242#define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
243#define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
244#define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
245#define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
246#define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
247#define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
248
249
250#define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12)
251#define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11)
252#define DWC3_DEVTEN_CMDCMPLTEN (1 << 10)
253#define DWC3_DEVTEN_ERRTICERREN (1 << 9)
254#define DWC3_DEVTEN_SOFEN (1 << 7)
255#define DWC3_DEVTEN_EOPFEN (1 << 6)
256#define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5)
257#define DWC3_DEVTEN_WKUPEVTEN (1 << 4)
258#define DWC3_DEVTEN_ULSTCNGEN (1 << 3)
259#define DWC3_DEVTEN_CONNECTDONEEN (1 << 2)
260#define DWC3_DEVTEN_USBRSTEN (1 << 1)
261#define DWC3_DEVTEN_DISCONNEVTEN (1 << 0)
262
263
264#define DWC3_DSTS_DCNRD (1 << 29)
265
266
267#define DWC3_DSTS_PWRUPREQ (1 << 24)
268
269
270#define DWC3_DSTS_RSS (1 << 25)
271#define DWC3_DSTS_SSS (1 << 24)
272
273#define DWC3_DSTS_COREIDLE (1 << 23)
274#define DWC3_DSTS_DEVCTRLHLT (1 << 22)
275
276#define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
277#define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
278
279#define DWC3_DSTS_RXFIFOEMPTY (1 << 17)
280
281#define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
282#define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
283
284#define DWC3_DSTS_CONNECTSPD (7 << 0)
285
286#define DWC3_DSTS_SUPERSPEED (4 << 0)
287#define DWC3_DSTS_HIGHSPEED (0 << 0)
288#define DWC3_DSTS_FULLSPEED2 (1 << 0)
289#define DWC3_DSTS_LOWSPEED (2 << 0)
290#define DWC3_DSTS_FULLSPEED1 (3 << 0)
291
292
293#define DWC3_DGCMD_SET_LMP 0x01
294#define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
295#define DWC3_DGCMD_XMIT_FUNCTION 0x03
296
297
298#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
299#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
300
301#define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
302#define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
303#define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
304#define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
305
306#define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1)
307#define DWC3_DGCMD_CMDACT (1 << 10)
308#define DWC3_DGCMD_CMDIOC (1 << 8)
309
310
311#define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0)
312#define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
313#define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
314#define DWC3_DGCMDPAR_TX_FIFO (1 << 5)
315#define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
316#define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0)
317
318
319#define DWC3_DEPCMD_PARAM_SHIFT 16
320#define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
321#define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
322#define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1)
323#define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11)
324#define DWC3_DEPCMD_CMDACT (1 << 10)
325#define DWC3_DEPCMD_CMDIOC (1 << 8)
326
327#define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
328#define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
329#define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
330#define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
331#define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
332#define DWC3_DEPCMD_SETSTALL (0x04 << 0)
333
334#define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
335
336#define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
337#define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
338#define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
339
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341#define DWC3_DALEPENA_EP(n) (1 << n)
342
343#define DWC3_DEPCMD_TYPE_CONTROL 0
344#define DWC3_DEPCMD_TYPE_ISOC 1
345#define DWC3_DEPCMD_TYPE_BULK 2
346#define DWC3_DEPCMD_TYPE_INTR 3
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350struct dwc3_trb;
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362struct dwc3_event_buffer {
363 void *buf;
364 unsigned length;
365 unsigned int lpos;
366 unsigned int count;
367 unsigned int flags;
368
369#define DWC3_EVENT_PENDING BIT(0)
370
371 dma_addr_t dma;
372
373 struct dwc3 *dwc;
374};
375
376#define DWC3_EP_FLAG_STALLED (1 << 0)
377#define DWC3_EP_FLAG_WEDGED (1 << 1)
378
379#define DWC3_EP_DIRECTION_TX true
380#define DWC3_EP_DIRECTION_RX false
381
382#define DWC3_TRB_NUM 32
383#define DWC3_TRB_MASK (DWC3_TRB_NUM - 1)
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406struct dwc3_ep {
407 struct usb_ep endpoint;
408 struct list_head request_list;
409 struct list_head req_queued;
410
411 struct dwc3_trb *trb_pool;
412 dma_addr_t trb_pool_dma;
413 u32 free_slot;
414 u32 busy_slot;
415 const struct usb_ss_ep_comp_descriptor *comp_desc;
416 struct dwc3 *dwc;
417
418 unsigned flags;
419#define DWC3_EP_ENABLED (1 << 0)
420#define DWC3_EP_STALL (1 << 1)
421#define DWC3_EP_WEDGE (1 << 2)
422#define DWC3_EP_BUSY (1 << 4)
423#define DWC3_EP_PENDING_REQUEST (1 << 5)
424#define DWC3_EP_MISSED_ISOC (1 << 6)
425
426
427#define DWC3_EP0_DIR_IN (1 << 31)
428
429 unsigned current_trb;
430
431 u8 number;
432 u8 type;
433 u8 resource_index;
434 u32 interval;
435
436 char name[20];
437
438 unsigned direction:1;
439 unsigned stream_capable:1;
440};
441
442enum dwc3_phy {
443 DWC3_PHY_UNKNOWN = 0,
444 DWC3_PHY_USB3,
445 DWC3_PHY_USB2,
446};
447
448enum dwc3_ep0_next {
449 DWC3_EP0_UNKNOWN = 0,
450 DWC3_EP0_COMPLETE,
451 DWC3_EP0_NRDY_DATA,
452 DWC3_EP0_NRDY_STATUS,
453};
454
455enum dwc3_ep0_state {
456 EP0_UNCONNECTED = 0,
457 EP0_SETUP_PHASE,
458 EP0_DATA_PHASE,
459 EP0_STATUS_PHASE,
460};
461
462enum dwc3_link_state {
463
464 DWC3_LINK_STATE_U0 = 0x00,
465 DWC3_LINK_STATE_U1 = 0x01,
466 DWC3_LINK_STATE_U2 = 0x02,
467 DWC3_LINK_STATE_U3 = 0x03,
468 DWC3_LINK_STATE_SS_DIS = 0x04,
469 DWC3_LINK_STATE_RX_DET = 0x05,
470 DWC3_LINK_STATE_SS_INACT = 0x06,
471 DWC3_LINK_STATE_POLL = 0x07,
472 DWC3_LINK_STATE_RECOV = 0x08,
473 DWC3_LINK_STATE_HRESET = 0x09,
474 DWC3_LINK_STATE_CMPLY = 0x0a,
475 DWC3_LINK_STATE_LPBK = 0x0b,
476 DWC3_LINK_STATE_RESET = 0x0e,
477 DWC3_LINK_STATE_RESUME = 0x0f,
478 DWC3_LINK_STATE_MASK = 0x0f,
479};
480
481
482#define DWC3_TRB_SIZE_MASK (0x00ffffff)
483#define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
484#define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
485#define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
486
487#define DWC3_TRBSTS_OK 0
488#define DWC3_TRBSTS_MISSED_ISOC 1
489#define DWC3_TRBSTS_SETUP_PENDING 2
490#define DWC3_TRB_STS_XFER_IN_PROG 4
491
492
493#define DWC3_TRB_CTRL_HWO (1 << 0)
494#define DWC3_TRB_CTRL_LST (1 << 1)
495#define DWC3_TRB_CTRL_CHN (1 << 2)
496#define DWC3_TRB_CTRL_CSP (1 << 3)
497#define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
498#define DWC3_TRB_CTRL_ISP_IMI (1 << 10)
499#define DWC3_TRB_CTRL_IOC (1 << 11)
500#define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
501
502#define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
503#define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
504#define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
505#define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
506#define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
507#define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
508#define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
509#define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
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518struct dwc3_trb {
519 u32 bpl;
520 u32 bph;
521 u32 size;
522 u32 ctrl;
523} __packed;
524
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537struct dwc3_hwparams {
538 u32 hwparams0;
539 u32 hwparams1;
540 u32 hwparams2;
541 u32 hwparams3;
542 u32 hwparams4;
543 u32 hwparams5;
544 u32 hwparams6;
545 u32 hwparams7;
546 u32 hwparams8;
547};
548
549
550#define DWC3_MODE(n) ((n) & 0x7)
551
552#define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
553
554
555#define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
556
557
558#define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
559#define DWC3_NUM_EPS_MASK (0x3f << 12)
560#define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
561 (DWC3_NUM_EPS_MASK)) >> 12)
562#define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
563 (DWC3_NUM_IN_EPS_MASK)) >> 18)
564
565
566#define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
567
568struct dwc3_request {
569 struct usb_request request;
570 struct list_head list;
571 struct dwc3_ep *dep;
572 u32 start_slot;
573
574 u8 epnum;
575 struct dwc3_trb *trb;
576 dma_addr_t trb_dma;
577
578 unsigned direction:1;
579 unsigned mapped:1;
580 unsigned queued:1;
581};
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586
587struct dwc3_scratchpad_array {
588 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
589};
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641struct dwc3 {
642 struct usb_ctrlrequest *ctrl_req;
643 struct dwc3_trb *ep0_trb;
644 void *ep0_bounce;
645 u8 *setup_buf;
646 dma_addr_t ctrl_req_addr;
647 dma_addr_t ep0_trb_addr;
648 dma_addr_t ep0_bounce_addr;
649 struct dwc3_request ep0_usb_req;
650
651
652 spinlock_t lock;
653
654 struct device *dev;
655
656 struct platform_device *xhci;
657 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
658
659 struct dwc3_event_buffer **ev_buffs;
660 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
661
662 struct usb_gadget gadget;
663 struct usb_gadget_driver *gadget_driver;
664
665 struct usb_phy *usb2_phy;
666 struct usb_phy *usb3_phy;
667
668 void __iomem *regs;
669 size_t regs_size;
670
671 enum usb_dr_mode dr_mode;
672
673
674 u32 dcfg;
675 u32 gctl;
676
677 u32 num_event_buffers;
678 u32 u1u2;
679 u32 maximum_speed;
680 u32 revision;
681
682#define DWC3_REVISION_173A 0x5533173a
683#define DWC3_REVISION_175A 0x5533175a
684#define DWC3_REVISION_180A 0x5533180a
685#define DWC3_REVISION_183A 0x5533183a
686#define DWC3_REVISION_185A 0x5533185a
687#define DWC3_REVISION_187A 0x5533187a
688#define DWC3_REVISION_188A 0x5533188a
689#define DWC3_REVISION_190A 0x5533190a
690#define DWC3_REVISION_194A 0x5533194a
691#define DWC3_REVISION_200A 0x5533200a
692#define DWC3_REVISION_202A 0x5533202a
693#define DWC3_REVISION_210A 0x5533210a
694#define DWC3_REVISION_220A 0x5533220a
695#define DWC3_REVISION_230A 0x5533230a
696#define DWC3_REVISION_240A 0x5533240a
697#define DWC3_REVISION_250A 0x5533250a
698
699 unsigned is_selfpowered:1;
700 unsigned three_stage_setup:1;
701 unsigned ep0_bounced:1;
702 unsigned ep0_expect_in:1;
703 unsigned start_config_issued:1;
704 unsigned setup_packet_pending:1;
705 unsigned delayed_status:1;
706 unsigned needs_fifo_resize:1;
707 unsigned resize_fifos:1;
708 unsigned pullups_connected:1;
709
710 enum dwc3_ep0_next ep0_next_event;
711 enum dwc3_ep0_state ep0state;
712 enum dwc3_link_state link_state;
713
714 u16 isoch_delay;
715 u16 u2sel;
716 u16 u2pel;
717 u8 u1sel;
718 u8 u1pel;
719
720 u8 speed;
721
722 u8 num_out_eps;
723 u8 num_in_eps;
724
725 void *mem;
726
727 struct dwc3_hwparams hwparams;
728 struct dentry *root;
729 struct debugfs_regset32 *regset;
730
731 u8 test_mode;
732 u8 test_mode_nr;
733};
734
735
736
737
738
739struct dwc3_event_type {
740 u32 is_devspec:1;
741 u32 type:7;
742 u32 reserved8_31:24;
743} __packed;
744
745#define DWC3_DEPEVT_XFERCOMPLETE 0x01
746#define DWC3_DEPEVT_XFERINPROGRESS 0x02
747#define DWC3_DEPEVT_XFERNOTREADY 0x03
748#define DWC3_DEPEVT_RXTXFIFOEVT 0x04
749#define DWC3_DEPEVT_STREAMEVT 0x06
750#define DWC3_DEPEVT_EPCMDCMPLT 0x07
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771struct dwc3_event_depevt {
772 u32 one_bit:1;
773 u32 endpoint_number:5;
774 u32 endpoint_event:4;
775 u32 reserved11_10:2;
776 u32 status:4;
777
778
779#define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3)
780
781
782#define DEPEVT_STATUS_BUSERR (1 << 0)
783#define DEPEVT_STATUS_SHORT (1 << 1)
784#define DEPEVT_STATUS_IOC (1 << 2)
785#define DEPEVT_STATUS_LST (1 << 3)
786
787
788#define DEPEVT_STREAMEVT_FOUND 1
789#define DEPEVT_STREAMEVT_NOTFOUND 2
790
791
792#define DEPEVT_STATUS_CONTROL_DATA 1
793#define DEPEVT_STATUS_CONTROL_STATUS 2
794
795 u32 parameters:16;
796} __packed;
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820struct dwc3_event_devt {
821 u32 one_bit:1;
822 u32 device_event:7;
823 u32 type:4;
824 u32 reserved15_12:4;
825 u32 event_info:8;
826 u32 reserved31_24:8;
827} __packed;
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835
836struct dwc3_event_gevt {
837 u32 one_bit:1;
838 u32 device_event:7;
839 u32 phy_port_number:4;
840 u32 reserved31_12:20;
841} __packed;
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851union dwc3_event {
852 u32 raw;
853 struct dwc3_event_type type;
854 struct dwc3_event_depevt depevt;
855 struct dwc3_event_devt devt;
856 struct dwc3_event_gevt gevt;
857};
858
859
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861
862
863#define DWC3_HAS_PERIPHERAL BIT(0)
864#define DWC3_HAS_XHCI BIT(1)
865#define DWC3_HAS_OTG BIT(3)
866
867
868void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
869int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc);
870
871#if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
872int dwc3_host_init(struct dwc3 *dwc);
873void dwc3_host_exit(struct dwc3 *dwc);
874#else
875static inline int dwc3_host_init(struct dwc3 *dwc)
876{ return 0; }
877static inline void dwc3_host_exit(struct dwc3 *dwc)
878{ }
879#endif
880
881#if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
882int dwc3_gadget_init(struct dwc3 *dwc);
883void dwc3_gadget_exit(struct dwc3 *dwc);
884#else
885static inline int dwc3_gadget_init(struct dwc3 *dwc)
886{ return 0; }
887static inline void dwc3_gadget_exit(struct dwc3 *dwc)
888{ }
889#endif
890
891
892#if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
893int dwc3_gadget_prepare(struct dwc3 *dwc);
894void dwc3_gadget_complete(struct dwc3 *dwc);
895int dwc3_gadget_suspend(struct dwc3 *dwc);
896int dwc3_gadget_resume(struct dwc3 *dwc);
897#else
898static inline int dwc3_gadget_prepare(struct dwc3 *dwc)
899{
900 return 0;
901}
902
903static inline void dwc3_gadget_complete(struct dwc3 *dwc)
904{
905}
906
907static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
908{
909 return 0;
910}
911
912static inline int dwc3_gadget_resume(struct dwc3 *dwc)
913{
914 return 0;
915}
916#endif
917
918#endif
919