1
2
3
4
5
6
7
8
9
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/sched.h>
14#include <linux/init.h>
15#include <linux/list.h>
16#include <linux/gpio.h>
17#include <linux/io.h>
18#include <linux/err.h>
19#include <linux/platform_device.h>
20#include <linux/dma-mapping.h>
21#include <linux/prefetch.h>
22#include <linux/usb/usb_phy_gen_xceiv.h>
23
24#include <asm/cacheflush.h>
25
26#include "musb_core.h"
27#include "musbhsdma.h"
28#include "blackfin.h"
29
30struct bfin_glue {
31 struct device *dev;
32 struct platform_device *musb;
33};
34#define glue_to_musb(g) platform_get_drvdata(g->musb)
35
36
37
38
39void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
40{
41 struct musb *musb = hw_ep->musb;
42 void __iomem *fifo = hw_ep->fifo;
43 void __iomem *epio = hw_ep->regs;
44 u8 epnum = hw_ep->epnum;
45
46 prefetch((u8 *)src);
47
48 musb_writew(epio, MUSB_TXCOUNT, len);
49
50 dev_dbg(musb->controller, "TX ep%d fifo %p count %d buf %p, epio %p\n",
51 hw_ep->epnum, fifo, len, src, epio);
52
53 dump_fifo_data(src, len);
54
55 if (!ANOMALY_05000380 && epnum != 0) {
56 u16 dma_reg;
57
58 flush_dcache_range((unsigned long)src,
59 (unsigned long)(src + len));
60
61
62 dma_reg = (u32)src;
63 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
64 SSYNC();
65
66 dma_reg = (u32)src >> 16;
67 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
68 SSYNC();
69
70
71 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
72 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
73 SSYNC();
74
75
76 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA | DIRECTION;
77 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
78 SSYNC();
79
80
81 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
82 cpu_relax();
83
84
85 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
86 SSYNC();
87
88
89 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
90 SSYNC();
91 } else {
92 SSYNC();
93
94 if (unlikely((unsigned long)src & 0x01))
95 outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
96 else
97 outsw((unsigned long)fifo, src, (len + 1) >> 1);
98 }
99}
100
101
102
103void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
104{
105 struct musb *musb = hw_ep->musb;
106 void __iomem *fifo = hw_ep->fifo;
107 u8 epnum = hw_ep->epnum;
108
109 if (ANOMALY_05000467 && epnum != 0) {
110 u16 dma_reg;
111
112 invalidate_dcache_range((unsigned long)dst,
113 (unsigned long)(dst + len));
114
115
116 dma_reg = (u32)dst;
117 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
118 SSYNC();
119
120 dma_reg = (u32)dst >> 16;
121 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
122 SSYNC();
123
124
125 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
126 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
127 SSYNC();
128
129
130 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA;
131 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
132 SSYNC();
133
134
135 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
136 cpu_relax();
137
138
139 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
140 SSYNC();
141
142
143 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
144 SSYNC();
145 } else {
146 SSYNC();
147
148
149
150 if (len == 1)
151 *dst = (u8)inw((unsigned long)fifo + 4);
152 else {
153 if (unlikely((unsigned long)dst & 0x01))
154 insw_8((unsigned long)fifo, dst, len >> 1);
155 else
156 insw((unsigned long)fifo, dst, len >> 1);
157
158 if (len & 0x01)
159 *(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
160 }
161 }
162 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
163 'R', hw_ep->epnum, fifo, len, dst);
164
165 dump_fifo_data(dst, len);
166}
167
168static irqreturn_t blackfin_interrupt(int irq, void *__hci)
169{
170 unsigned long flags;
171 irqreturn_t retval = IRQ_NONE;
172 struct musb *musb = __hci;
173
174 spin_lock_irqsave(&musb->lock, flags);
175
176 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
177 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
178 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
179
180 if (musb->int_usb || musb->int_tx || musb->int_rx) {
181 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
182 musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
183 musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
184 retval = musb_interrupt(musb);
185 }
186
187
188 if ((musb->xceiv->state == OTG_STATE_B_IDLE
189 || musb->xceiv->state == OTG_STATE_A_WAIT_BCON) ||
190 (musb->int_usb & MUSB_INTR_DISCONNECT && is_host_active(musb))) {
191 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
192 musb->a_wait_bcon = TIMER_DELAY;
193 }
194
195 spin_unlock_irqrestore(&musb->lock, flags);
196
197 return retval;
198}
199
200static void musb_conn_timer_handler(unsigned long _musb)
201{
202 struct musb *musb = (void *)_musb;
203 unsigned long flags;
204 u16 val;
205 static u8 toggle;
206
207 spin_lock_irqsave(&musb->lock, flags);
208 switch (musb->xceiv->state) {
209 case OTG_STATE_A_IDLE:
210 case OTG_STATE_A_WAIT_BCON:
211
212 val = musb_readw(musb->mregs, MUSB_DEVCTL);
213 val &= ~MUSB_DEVCTL_SESSION;
214 musb_writew(musb->mregs, MUSB_DEVCTL, val);
215 val |= MUSB_DEVCTL_SESSION;
216 musb_writew(musb->mregs, MUSB_DEVCTL, val);
217
218 val = musb_readw(musb->mregs, MUSB_DEVCTL);
219
220 if (!(val & MUSB_DEVCTL_BDEVICE)) {
221 gpio_set_value(musb->config->gpio_vrsel, 1);
222 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
223 } else {
224 gpio_set_value(musb->config->gpio_vrsel, 0);
225
226 val = musb_readb(musb->mregs, MUSB_INTRUSBE);
227 val &= ~MUSB_INTR_VBUSERROR;
228 musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
229
230 val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
231 musb_writeb(musb->mregs, MUSB_INTRUSB, val);
232 musb->xceiv->state = OTG_STATE_B_IDLE;
233 }
234 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
235 break;
236 case OTG_STATE_B_IDLE:
237
238
239
240
241 val = musb_readw(musb->mregs, MUSB_DEVCTL);
242 val |= MUSB_DEVCTL_SESSION;
243 musb_writew(musb->mregs, MUSB_DEVCTL, val);
244 val = musb_readw(musb->mregs, MUSB_DEVCTL);
245
246 if (!(val & MUSB_DEVCTL_BDEVICE)) {
247 gpio_set_value(musb->config->gpio_vrsel, 1);
248 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
249 } else {
250 gpio_set_value(musb->config->gpio_vrsel, 0);
251
252
253 val = musb_readb(musb->mregs, MUSB_INTRUSBE);
254 val &= ~MUSB_INTR_VBUSERROR;
255 musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
256
257 val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
258 musb_writeb(musb->mregs, MUSB_INTRUSB, val);
259
260
261
262
263 if (toggle) {
264 val = musb_readb(musb->mregs, MUSB_POWER);
265 val &= ~MUSB_POWER_SOFTCONN;
266 musb_writeb(musb->mregs, MUSB_POWER, val);
267 toggle = 0;
268 } else {
269 val = musb_readb(musb->mregs, MUSB_POWER);
270 val |= MUSB_POWER_SOFTCONN;
271 musb_writeb(musb->mregs, MUSB_POWER, val);
272 toggle = 1;
273 }
274
275
276
277
278 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY / 4);
279 }
280 break;
281 default:
282 dev_dbg(musb->controller, "%s state not handled\n",
283 usb_otg_state_string(musb->xceiv->state));
284 break;
285 }
286 spin_unlock_irqrestore(&musb->lock, flags);
287
288 dev_dbg(musb->controller, "state is %s\n",
289 usb_otg_state_string(musb->xceiv->state));
290}
291
292static void bfin_musb_enable(struct musb *musb)
293{
294
295}
296
297static void bfin_musb_disable(struct musb *musb)
298{
299}
300
301static void bfin_musb_set_vbus(struct musb *musb, int is_on)
302{
303 int value = musb->config->gpio_vrsel_active;
304 if (!is_on)
305 value = !value;
306 gpio_set_value(musb->config->gpio_vrsel, value);
307
308 dev_dbg(musb->controller, "VBUS %s, devctl %02x "
309 "\n",
310 usb_otg_state_string(musb->xceiv->state),
311 musb_readb(musb->mregs, MUSB_DEVCTL));
312}
313
314static int bfin_musb_set_power(struct usb_phy *x, unsigned mA)
315{
316 return 0;
317}
318
319static int bfin_musb_vbus_status(struct musb *musb)
320{
321 return 0;
322}
323
324static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode)
325{
326 return -EIO;
327}
328
329static int bfin_musb_adjust_channel_params(struct dma_channel *channel,
330 u16 packet_sz, u8 *mode,
331 dma_addr_t *dma_addr, u32 *len)
332{
333 struct musb_dma_channel *musb_channel = channel->private_data;
334
335
336
337
338
339
340
341
342 if (ANOMALY_05000450) {
343 if (musb_channel->transmit && *mode == 1)
344 *len = *len - (*len % packet_sz);
345 }
346
347 return 0;
348}
349
350static void bfin_musb_reg_init(struct musb *musb)
351{
352 if (ANOMALY_05000346) {
353 bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
354 SSYNC();
355 }
356
357 if (ANOMALY_05000347) {
358 bfin_write_USB_APHY_CNTRL(0x0);
359 SSYNC();
360 }
361
362
363 bfin_write_USB_PLLOSC_CTRL(0x3080 |
364 ((480/musb->config->clkin) << 1));
365 SSYNC();
366
367 bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
368 SSYNC();
369
370 bfin_write_USB_EP_NI0_RXMAXP(64);
371 SSYNC();
372
373 bfin_write_USB_EP_NI0_TXMAXP(64);
374 SSYNC();
375
376
377 bfin_write_USB_GLOBINTR(0x7);
378 SSYNC();
379
380 bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
381 EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
382 EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
383 EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
384 EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
385 SSYNC();
386}
387
388static int bfin_musb_init(struct musb *musb)
389{
390
391
392
393
394
395
396
397
398 if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
399 printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d\n",
400 musb->config->gpio_vrsel);
401 return -ENODEV;
402 }
403 gpio_direction_output(musb->config->gpio_vrsel, 0);
404
405 usb_nop_xceiv_register();
406 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
407 if (IS_ERR_OR_NULL(musb->xceiv)) {
408 gpio_free(musb->config->gpio_vrsel);
409 return -EPROBE_DEFER;
410 }
411
412 bfin_musb_reg_init(musb);
413
414 setup_timer(&musb_conn_timer, musb_conn_timer_handler,
415 (unsigned long) musb);
416
417 musb->xceiv->set_power = bfin_musb_set_power;
418
419 musb->isr = blackfin_interrupt;
420 musb->double_buffer_not_ok = true;
421
422 return 0;
423}
424
425static int bfin_musb_exit(struct musb *musb)
426{
427 gpio_free(musb->config->gpio_vrsel);
428
429 usb_put_phy(musb->xceiv);
430 usb_nop_xceiv_unregister();
431 return 0;
432}
433
434static const struct musb_platform_ops bfin_ops = {
435 .init = bfin_musb_init,
436 .exit = bfin_musb_exit,
437
438 .enable = bfin_musb_enable,
439 .disable = bfin_musb_disable,
440
441 .set_mode = bfin_musb_set_mode,
442
443 .vbus_status = bfin_musb_vbus_status,
444 .set_vbus = bfin_musb_set_vbus,
445
446 .adjust_channel_params = bfin_musb_adjust_channel_params,
447};
448
449static u64 bfin_dmamask = DMA_BIT_MASK(32);
450
451static int bfin_probe(struct platform_device *pdev)
452{
453 struct resource musb_resources[2];
454 struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
455 struct platform_device *musb;
456 struct bfin_glue *glue;
457
458 int ret = -ENOMEM;
459
460 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
461 if (!glue) {
462 dev_err(&pdev->dev, "failed to allocate glue context\n");
463 goto err0;
464 }
465
466 musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO);
467 if (!musb) {
468 dev_err(&pdev->dev, "failed to allocate musb device\n");
469 goto err1;
470 }
471
472 musb->dev.parent = &pdev->dev;
473 musb->dev.dma_mask = &bfin_dmamask;
474 musb->dev.coherent_dma_mask = bfin_dmamask;
475
476 glue->dev = &pdev->dev;
477 glue->musb = musb;
478
479 pdata->platform_ops = &bfin_ops;
480
481 platform_set_drvdata(pdev, glue);
482
483 memset(musb_resources, 0x00, sizeof(*musb_resources) *
484 ARRAY_SIZE(musb_resources));
485
486 musb_resources[0].name = pdev->resource[0].name;
487 musb_resources[0].start = pdev->resource[0].start;
488 musb_resources[0].end = pdev->resource[0].end;
489 musb_resources[0].flags = pdev->resource[0].flags;
490
491 musb_resources[1].name = pdev->resource[1].name;
492 musb_resources[1].start = pdev->resource[1].start;
493 musb_resources[1].end = pdev->resource[1].end;
494 musb_resources[1].flags = pdev->resource[1].flags;
495
496 ret = platform_device_add_resources(musb, musb_resources,
497 ARRAY_SIZE(musb_resources));
498 if (ret) {
499 dev_err(&pdev->dev, "failed to add resources\n");
500 goto err3;
501 }
502
503 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
504 if (ret) {
505 dev_err(&pdev->dev, "failed to add platform_data\n");
506 goto err3;
507 }
508
509 ret = platform_device_add(musb);
510 if (ret) {
511 dev_err(&pdev->dev, "failed to register musb device\n");
512 goto err3;
513 }
514
515 return 0;
516
517err3:
518 platform_device_put(musb);
519
520err1:
521 kfree(glue);
522
523err0:
524 return ret;
525}
526
527static int bfin_remove(struct platform_device *pdev)
528{
529 struct bfin_glue *glue = platform_get_drvdata(pdev);
530
531 platform_device_unregister(glue->musb);
532 kfree(glue);
533
534 return 0;
535}
536
537#ifdef CONFIG_PM
538static int bfin_suspend(struct device *dev)
539{
540 struct bfin_glue *glue = dev_get_drvdata(dev);
541 struct musb *musb = glue_to_musb(glue);
542
543 if (is_host_active(musb))
544
545
546
547
548
549
550 gpio_set_value(musb->config->gpio_vrsel, 0);
551
552 return 0;
553}
554
555static int bfin_resume(struct device *dev)
556{
557 struct bfin_glue *glue = dev_get_drvdata(dev);
558 struct musb *musb = glue_to_musb(glue);
559
560 bfin_musb_reg_init(musb);
561
562 return 0;
563}
564
565static struct dev_pm_ops bfin_pm_ops = {
566 .suspend = bfin_suspend,
567 .resume = bfin_resume,
568};
569
570#define DEV_PM_OPS &bfin_pm_ops
571#else
572#define DEV_PM_OPS NULL
573#endif
574
575static struct platform_driver bfin_driver = {
576 .probe = bfin_probe,
577 .remove = __exit_p(bfin_remove),
578 .driver = {
579 .name = "musb-blackfin",
580 .pm = DEV_PM_OPS,
581 },
582};
583
584MODULE_DESCRIPTION("Blackfin MUSB Glue Layer");
585MODULE_AUTHOR("Bryan Wy <cooloney@kernel.org>");
586MODULE_LICENSE("GPL v2");
587module_platform_driver(bfin_driver);
588
