LXR linux/include/linux/mtd/nand.h

   1/*
   2 *  linux/include/linux/mtd/nand.h
   3 *
   4 *  Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
   5 *                        Steven J. Hill <sjhill@realitydiluted.com>
   6 *                        Thomas Gleixner <tglx@linutronix.de>
   7 *
   8 * This program is free software; you can redistribute it and/or modify
   9 * it under the terms of the GNU General Public License version 2 as
  10 * published by the Free Software Foundation.
  11 *
  12 * Info:
  13 *      Contains standard defines and IDs for NAND flash devices
  14 *
  15 * Changelog:
  16 *      See git changelog.
  17 */
  18#ifndef __LINUX_MTD_NAND_H
  19#define __LINUX_MTD_NAND_H
  20
  21#include <linux/wait.h>
  22#include <linux/spinlock.h>
  23#include <linux/mtd/mtd.h>
  24#include <linux/mtd/flashchip.h>
  25#include <linux/mtd/bbm.h>
  26
  27struct mtd_info;
  28struct nand_flash_dev;
  29/* Scan and identify a NAND device */
  30extern int nand_scan(struct mtd_info *mtd, int max_chips);
  31/*
  32 * Separate phases of nand_scan(), allowing board driver to intervene
  33 * and override command or ECC setup according to flash type.
  34 */
  35extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
  36                           struct nand_flash_dev *table);
  37extern int nand_scan_tail(struct mtd_info *mtd);
  38
  39/* Free resources held by the NAND device */
  40extern void nand_release(struct mtd_info *mtd);
  41
  42/* Internal helper for board drivers which need to override command function */
  43extern void nand_wait_ready(struct mtd_info *mtd);
  44
  45/* locks all blocks present in the device */
  46extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
  47
  48/* unlocks specified locked blocks */
  49extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
  50
  51/* The maximum number of NAND chips in an array */
  52#define NAND_MAX_CHIPS          8
  53
  54/*
  55 * This constant declares the max. oobsize / page, which
  56 * is supported now. If you add a chip with bigger oobsize/page
  57 * adjust this accordingly.
  58 */
  59#define NAND_MAX_OOBSIZE        744
  60#define NAND_MAX_PAGESIZE       8192
  61
  62/*
  63 * Constants for hardware specific CLE/ALE/NCE function
  64 *
  65 * These are bits which can be or'ed to set/clear multiple
  66 * bits in one go.
  67 */
  68/* Select the chip by setting nCE to low */
  69#define NAND_NCE                0x01
  70/* Select the command latch by setting CLE to high */
  71#define NAND_CLE                0x02
  72/* Select the address latch by setting ALE to high */
  73#define NAND_ALE                0x04
  74
  75#define NAND_CTRL_CLE           (NAND_NCE | NAND_CLE)
  76#define NAND_CTRL_ALE           (NAND_NCE | NAND_ALE)
  77#define NAND_CTRL_CHANGE        0x80
  78
  79/*
  80 * Standard NAND flash commands
  81 */
  82#define NAND_CMD_READ0          0
  83#define NAND_CMD_READ1          1
  84#define NAND_CMD_RNDOUT         5
  85#define NAND_CMD_PAGEPROG       0x10
  86#define NAND_CMD_READOOB        0x50
  87#define NAND_CMD_ERASE1         0x60
  88#define NAND_CMD_STATUS         0x70
  89#define NAND_CMD_SEQIN          0x80
  90#define NAND_CMD_RNDIN          0x85
  91#define NAND_CMD_READID         0x90
  92#define NAND_CMD_ERASE2         0xd0
  93#define NAND_CMD_PARAM          0xec
  94#define NAND_CMD_GET_FEATURES   0xee
  95#define NAND_CMD_SET_FEATURES   0xef
  96#define NAND_CMD_RESET          0xff
  97
  98#define NAND_CMD_LOCK           0x2a
  99#define NAND_CMD_UNLOCK1        0x23
 100#define NAND_CMD_UNLOCK2        0x24
 101
 102/* Extended commands for large page devices */
 103#define NAND_CMD_READSTART      0x30
 104#define NAND_CMD_RNDOUTSTART    0xE0
 105#define NAND_CMD_CACHEDPROG     0x15
 106
 107#define NAND_CMD_NONE           -1
 108
 109/* Status bits */
 110#define NAND_STATUS_FAIL        0x01
 111#define NAND_STATUS_FAIL_N1     0x02
 112#define NAND_STATUS_TRUE_READY  0x20
 113#define NAND_STATUS_READY       0x40
 114#define NAND_STATUS_WP          0x80
 115
 116/*
 117 * Constants for ECC_MODES
 118 */
 119typedef enum {
 120        NAND_ECC_NONE,
 121        NAND_ECC_SOFT,
 122        NAND_ECC_HW,
 123        NAND_ECC_HW_SYNDROME,
 124        NAND_ECC_HW_OOB_FIRST,
 125        NAND_ECC_SOFT_BCH,
 126} nand_ecc_modes_t;
 127
 128/*
 129 * Constants for Hardware ECC
 130 */
 131/* Reset Hardware ECC for read */
 132#define NAND_ECC_READ           0
 133/* Reset Hardware ECC for write */
 134#define NAND_ECC_WRITE          1
 135/* Enable Hardware ECC before syndrome is read back from flash */
 136#define NAND_ECC_READSYN        2
 137
 138/* Bit mask for flags passed to do_nand_read_ecc */
 139#define NAND_GET_DEVICE         0x80
 140
 141
 142/*
 143 * Option constants for bizarre disfunctionality and real
 144 * features.
 145 */
 146/* Buswidth is 16 bit */
 147#define NAND_BUSWIDTH_16        0x00000002
 148/* Chip has cache program function */
 149#define NAND_CACHEPRG           0x00000008
 150/*
 151 * Chip requires ready check on read (for auto-incremented sequential read).
 152 * True only for small page devices; large page devices do not support
 153 * autoincrement.
 154 */
 155#define NAND_NEED_READRDY       0x00000100
 156
 157/* Chip does not allow subpage writes */
 158#define NAND_NO_SUBPAGE_WRITE   0x00000200
 159
 160/* Device is one of 'new' xD cards that expose fake nand command set */
 161#define NAND_BROKEN_XD          0x00000400
 162
 163/* Device behaves just like nand, but is readonly */
 164#define NAND_ROM                0x00000800
 165
 166/* Device supports subpage reads */
 167#define NAND_SUBPAGE_READ       0x00001000
 168
 169/* Options valid for Samsung large page devices */
 170#define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
 171
 172/* Macros to identify the above */
 173#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
 174#define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
 175
 176/* Non chip related options */
 177/* This option skips the bbt scan during initialization. */
 178#define NAND_SKIP_BBTSCAN       0x00010000
 179/*
 180 * This option is defined if the board driver allocates its own buffers
 181 * (e.g. because it needs them DMA-coherent).
 182 */
 183#define NAND_OWN_BUFFERS        0x00020000
 184/* Chip may not exist, so silence any errors in scan */
 185#define NAND_SCAN_SILENT_NODEV  0x00040000
 186/*
 187 * Autodetect nand buswidth with readid/onfi.
 188 * This suppose the driver will configure the hardware in 8 bits mode
 189 * when calling nand_scan_ident, and update its configuration
 190 * before calling nand_scan_tail.
 191 */
 192#define NAND_BUSWIDTH_AUTO      0x00080000
 193
 194/* Options set by nand scan */
 195/* Nand scan has allocated controller struct */
 196#define NAND_CONTROLLER_ALLOC   0x80000000
 197
 198/* Cell info constants */
 199#define NAND_CI_CHIPNR_MSK      0x03
 200#define NAND_CI_CELLTYPE_MSK    0x0C
 201
 202/* Keep gcc happy */
 203struct nand_chip;
 204
 205/* ONFI features */
 206#define ONFI_FEATURE_16_BIT_BUS         (1 << 0)
 207#define ONFI_FEATURE_EXT_PARAM_PAGE     (1 << 7)
 208
 209/* ONFI timing mode, used in both asynchronous and synchronous mode */
 210#define ONFI_TIMING_MODE_0              (1 << 0)
 211#define ONFI_TIMING_MODE_1              (1 << 1)
 212#define ONFI_TIMING_MODE_2              (1 << 2)
 213#define ONFI_TIMING_MODE_3              (1 << 3)
 214#define ONFI_TIMING_MODE_4              (1 << 4)
 215#define ONFI_TIMING_MODE_5              (1 << 5)
 216#define ONFI_TIMING_MODE_UNKNOWN        (1 << 6)
 217
 218/* ONFI feature address */
 219#define ONFI_FEATURE_ADDR_TIMING_MODE   0x1
 220
 221/* ONFI subfeature parameters length */
 222#define ONFI_SUBFEATURE_PARAM_LEN       4
 223
 224/* ONFI optional commands SET/GET FEATURES supported? */
 225#define ONFI_OPT_CMD_SET_GET_FEATURES   (1 << 2)
 226
 227struct nand_onfi_params {
 228        /* rev info and features block */
 229        /* 'O' 'N' 'F' 'I'  */
 230        u8 sig[4];
 231        __le16 revision;
 232        __le16 features;
 233        __le16 opt_cmd;
 234        u8 reserved0[2];
 235        __le16 ext_param_page_length; /* since ONFI 2.1 */
 236        u8 num_of_param_pages;        /* since ONFI 2.1 */
 237        u8 reserved1[17];
 238
 239        /* manufacturer information block */
 240        char manufacturer[12];
 241        char model[20];
 242        u8 jedec_id;
 243        __le16 date_code;
 244        u8 reserved2[13];
 245
 246        /* memory organization block */
 247        __le32 byte_per_page;
 248        __le16 spare_bytes_per_page;
 249        __le32 data_bytes_per_ppage;
 250        __le16 spare_bytes_per_ppage;
 251        __le32 pages_per_block;
 252        __le32 blocks_per_lun;
 253        u8 lun_count;
 254        u8 addr_cycles;
 255        u8 bits_per_cell;
 256        __le16 bb_per_lun;
 257        __le16 block_endurance;
 258        u8 guaranteed_good_blocks;
 259        __le16 guaranteed_block_endurance;
 260        u8 programs_per_page;
 261        u8 ppage_attr;
 262        u8 ecc_bits;
 263        u8 interleaved_bits;
 264        u8 interleaved_ops;
 265        u8 reserved3[13];
 266
 267        /* electrical parameter block */
 268        u8 io_pin_capacitance_max;
 269        __le16 async_timing_mode;
 270        __le16 program_cache_timing_mode;
 271        __le16 t_prog;
 272        __le16 t_bers;
 273        __le16 t_r;
 274        __le16 t_ccs;
 275        __le16 src_sync_timing_mode;
 276        __le16 src_ssync_features;
 277        __le16 clk_pin_capacitance_typ;
 278        __le16 io_pin_capacitance_typ;
 279        __le16 input_pin_capacitance_typ;
 280        u8 input_pin_capacitance_max;
 281        u8 driver_strenght_support;
 282        __le16 t_int_r;
 283        __le16 t_ald;
 284        u8 reserved4[7];
 285
 286        /* vendor */
 287        u8 reserved5[90];
 288
 289        __le16 crc;
 290} __attribute__((packed));
 291
 292#define ONFI_CRC_BASE   0x4F4E
 293
 294/* Extended ECC information Block Definition (since ONFI 2.1) */
 295struct onfi_ext_ecc_info {
 296        u8 ecc_bits;
 297        u8 codeword_size;
 298        __le16 bb_per_lun;
 299        __le16 block_endurance;
 300        u8 reserved[2];
 301} __packed;
 302
 303#define ONFI_SECTION_TYPE_0     0       /* Unused section. */
 304#define ONFI_SECTION_TYPE_1     1       /* for additional sections. */
 305#define ONFI_SECTION_TYPE_2     2       /* for ECC information. */
 306struct onfi_ext_section {
 307        u8 type;
 308        u8 length;
 309} __packed;
 310
 311#define ONFI_EXT_SECTION_MAX 8
 312
 313/* Extended Parameter Page Definition (since ONFI 2.1) */
 314struct onfi_ext_param_page {
 315        __le16 crc;
 316        u8 sig[4];             /* 'E' 'P' 'P' 'S' */
 317        u8 reserved0[10];
 318        struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
 319
 320        /*
 321         * The actual size of the Extended Parameter Page is in
 322         * @ext_param_page_length of nand_onfi_params{}.
 323         * The following are the variable length sections.
 324         * So we do not add any fields below. Please see the ONFI spec.
 325         */
 326} __packed;
 327
 328/**
 329 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
 330 * @lock:               protection lock
 331 * @active:             the mtd device which holds the controller currently
 332 * @wq:                 wait queue to sleep on if a NAND operation is in
 333 *                      progress used instead of the per chip wait queue
 334 *                      when a hw controller is available.
 335 */
 336struct nand_hw_control {
 337        spinlock_t lock;
 338        struct nand_chip *active;
 339        wait_queue_head_t wq;
 340};
 341
 342/**
 343 * struct nand_ecc_ctrl - Control structure for ECC
 344 * @mode:       ECC mode
 345 * @steps:      number of ECC steps per page
 346 * @size:       data bytes per ECC step
 347 * @bytes:      ECC bytes per step
 348 * @strength:   max number of correctible bits per ECC step
 349 * @total:      total number of ECC bytes per page
 350 * @prepad:     padding information for syndrome based ECC generators
 351 * @postpad:    padding information for syndrome based ECC generators
 352 * @layout:     ECC layout control struct pointer
 353 * @priv:       pointer to private ECC control data
 354 * @hwctl:      function to control hardware ECC generator. Must only
 355 *              be provided if an hardware ECC is available
 356 * @calculate:  function for ECC calculation or readback from ECC hardware
 357 * @correct:    function for ECC correction, matching to ECC generator (sw/hw)
 358 * @read_page_raw:      function to read a raw page without ECC
 359 * @write_page_raw:     function to write a raw page without ECC
 360 * @read_page:  function to read a page according to the ECC generator
 361 *              requirements; returns maximum number of bitflips corrected in
 362 *              any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
 363 * @read_subpage:       function to read parts of the page covered by ECC;
 364 *                      returns same as read_page()
 365 * @write_subpage:      function to write parts of the page covered by ECC.
 366 * @write_page: function to write a page according to the ECC generator
 367 *              requirements.
 368 * @write_oob_raw:      function to write chip OOB data without ECC
 369 * @read_oob_raw:       function to read chip OOB data without ECC
 370 * @read_oob:   function to read chip OOB data
 371 * @write_oob:  function to write chip OOB data
 372 */
 373struct nand_ecc_ctrl {
 374        nand_ecc_modes_t mode;
 375        int steps;
 376        int size;
 377        int bytes;
 378        int total;
 379        int strength;
 380        int prepad;
 381        int postpad;
 382        struct nand_ecclayout   *layout;
 383        void *priv;
 384        void (*hwctl)(struct mtd_info *mtd, int mode);
 385        int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
 386                        uint8_t *ecc_code);
 387        int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
 388                        uint8_t *calc_ecc);
 389        int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 390                        uint8_t *buf, int oob_required, int page);
 391        int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 392                        const uint8_t *buf, int oob_required);
 393        int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
 394                        uint8_t *buf, int oob_required, int page);
 395        int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
 396                        uint32_t offs, uint32_t len, uint8_t *buf);
 397        int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
 398                        uint32_t offset, uint32_t data_len,
 399                        const uint8_t *data_buf, int oob_required);
 400        int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
 401                        const uint8_t *buf, int oob_required);
 402        int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 403                        int page);
 404        int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 405                        int page);
 406        int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
 407        int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
 408                        int page);
 409};
 410
 411/**
 412 * struct nand_buffers - buffer structure for read/write
 413 * @ecccalc:    buffer for calculated ECC
 414 * @ecccode:    buffer for ECC read from flash
 415 * @databuf:    buffer for data - dynamically sized
 416 *
 417 * Do not change the order of buffers. databuf and oobrbuf must be in
 418 * consecutive order.
 419 */
 420struct nand_buffers {
 421        uint8_t ecccalc[NAND_MAX_OOBSIZE];
 422        uint8_t ecccode[NAND_MAX_OOBSIZE];
 423        uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
 424};
 425
 426/**
 427 * struct nand_chip - NAND Private Flash Chip Data
 428 * @IO_ADDR_R:          [BOARDSPECIFIC] address to read the 8 I/O lines of the
 429 *                      flash device
 430 * @IO_ADDR_W:          [BOARDSPECIFIC] address to write the 8 I/O lines of the
 431 *                      flash device.
 432 * @read_byte:          [REPLACEABLE] read one byte from the chip
 433 * @read_word:          [REPLACEABLE] read one word from the chip
 434 * @write_buf:          [REPLACEABLE] write data from the buffer to the chip
 435 * @read_buf:           [REPLACEABLE] read data from the chip into the buffer
 436 * @select_chip:        [REPLACEABLE] select chip nr
 437 * @block_bad:          [REPLACEABLE] check if a block is bad, using OOB markers
 438 * @block_markbad:      [REPLACEABLE] mark a block bad
 439 * @cmd_ctrl:           [BOARDSPECIFIC] hardwarespecific function for controlling
 440 *                      ALE/CLE/nCE. Also used to write command and address
 441 * @init_size:          [BOARDSPECIFIC] hardwarespecific function for setting
 442 *                      mtd->oobsize, mtd->writesize and so on.
 443 *                      @id_data contains the 8 bytes values of NAND_CMD_READID.
 444 *                      Return with the bus width.
 445 * @dev_ready:          [BOARDSPECIFIC] hardwarespecific function for accessing
 446 *                      device ready/busy line. If set to NULL no access to
 447 *                      ready/busy is available and the ready/busy information
 448 *                      is read from the chip status register.
 449 * @cmdfunc:            [REPLACEABLE] hardwarespecific function for writing
 450 *                      commands to the chip.
 451 * @waitfunc:           [REPLACEABLE] hardwarespecific function for wait on
 452 *                      ready.
 453 * @ecc:                [BOARDSPECIFIC] ECC control structure
 454 * @buffers:            buffer structure for read/write
 455 * @hwcontrol:          platform-specific hardware control structure
 456 * @erase_cmd:          [INTERN] erase command write function, selectable due
 457 *                      to AND support.
 458 * @scan_bbt:           [REPLACEABLE] function to scan bad block table
 459 * @chip_delay:         [BOARDSPECIFIC] chip dependent delay for transferring
 460 *                      data from array to read regs (tR).
 461 * @state:              [INTERN] the current state of the NAND device
 462 * @oob_poi:            "poison value buffer," used for laying out OOB data
 463 *                      before writing
 464 * @page_shift:         [INTERN] number of address bits in a page (column
 465 *                      address bits).
 466 * @phys_erase_shift:   [INTERN] number of address bits in a physical eraseblock
 467 * @bbt_erase_shift:    [INTERN] number of address bits in a bbt entry
 468 * @chip_shift:         [INTERN] number of address bits in one chip
 469 * @options:            [BOARDSPECIFIC] various chip options. They can partly
 470 *                      be set to inform nand_scan about special functionality.
 471 *                      See the defines for further explanation.
 472 * @bbt_options:        [INTERN] bad block specific options. All options used
 473 *                      here must come from bbm.h. By default, these options
 474 *                      will be copied to the appropriate nand_bbt_descr's.
 475 * @badblockpos:        [INTERN] position of the bad block marker in the oob
 476 *                      area.
 477 * @badblockbits:       [INTERN] minimum number of set bits in a good block's
 478 *                      bad block marker position; i.e., BBM == 11110111b is
 479 *                      not bad when badblockbits == 7
 480 * @cellinfo:           [INTERN] MLC/multichip data from chip ident
 481 * @ecc_strength_ds:    [INTERN] ECC correctability from the datasheet.
 482 *                      Minimum amount of bit errors per @ecc_step_ds guaranteed
 483 *                      to be correctable. If unknown, set to zero.
 484 * @ecc_step_ds:        [INTERN] ECC step required by the @ecc_strength_ds,
 485 *                      also from the datasheet. It is the recommended ECC step
 486 *                      size, if known; if unknown, set to zero.
 487 * @numchips:           [INTERN] number of physical chips
 488 * @chipsize:           [INTERN] the size of one chip for multichip arrays
 489 * @pagemask:           [INTERN] page number mask = number of (pages / chip) - 1
 490 * @pagebuf:            [INTERN] holds the pagenumber which is currently in
 491 *                      data_buf.
 492 * @pagebuf_bitflips:   [INTERN] holds the bitflip count for the page which is
 493 *                      currently in data_buf.
 494 * @subpagesize:        [INTERN] holds the subpagesize
 495 * @onfi_version:       [INTERN] holds the chip ONFI version (BCD encoded),
 496 *                      non 0 if ONFI supported.
 497 * @onfi_params:        [INTERN] holds the ONFI page parameter when ONFI is
 498 *                      supported, 0 otherwise.
 499 * @onfi_set_features:  [REPLACEABLE] set the features for ONFI nand
 500 * @onfi_get_features:  [REPLACEABLE] get the features for ONFI nand
 501 * @ecclayout:          [REPLACEABLE] the default ECC placement scheme
 502 * @bbt:                [INTERN] bad block table pointer
 503 * @bbt_td:             [REPLACEABLE] bad block table descriptor for flash
 504 *                      lookup.
 505 * @bbt_md:             [REPLACEABLE] bad block table mirror descriptor
 506 * @badblock_pattern:   [REPLACEABLE] bad block scan pattern used for initial
 507 *                      bad block scan.
 508 * @controller:         [REPLACEABLE] a pointer to a hardware controller
 509 *                      structure which is shared among multiple independent
 510 *                      devices.
 511 * @priv:               [OPTIONAL] pointer to private chip data
 512 * @errstat:            [OPTIONAL] hardware specific function to perform
 513 *                      additional error status checks (determine if errors are
 514 *                      correctable).
 515 * @write_page:         [REPLACEABLE] High-level page write function
 516 */
 517
 518struct nand_chip {
 519        void __iomem *IO_ADDR_R;
 520        void __iomem *IO_ADDR_W;
 521
 522        uint8_t (*read_byte)(struct mtd_info *mtd);
 523        u16 (*read_word)(struct mtd_info *mtd);
 524        void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 525        void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
 526        void (*select_chip)(struct mtd_info *mtd, int chip);
 527        int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
 528        int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
 529        void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
 530        int (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
 531                        u8 *id_data);
 532        int (*dev_ready)(struct mtd_info *mtd);
 533        void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
 534                        int page_addr);
 535        int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
 536        void (*erase_cmd)(struct mtd_info *mtd, int page);
 537        int (*scan_bbt)(struct mtd_info *mtd);
 538        int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
 539                        int status, int page);
 540        int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
 541                        uint32_t offset, int data_len, const uint8_t *buf,
 542                        int oob_required, int page, int cached, int raw);
 543        int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
 544                        int feature_addr, uint8_t *subfeature_para);
 545        int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
 546                        int feature_addr, uint8_t *subfeature_para);
 547
 548        int chip_delay;
 549        unsigned int options;
 550        unsigned int bbt_options;
 551
 552        int page_shift;
 553        int phys_erase_shift;
 554        int bbt_erase_shift;
 555        int chip_shift;
 556        int numchips;
 557        uint64_t chipsize;
 558        int pagemask;
 559        int pagebuf;
 560        unsigned int pagebuf_bitflips;
 561        int subpagesize;
 562        uint8_t cellinfo;
 563        uint16_t ecc_strength_ds;
 564        uint16_t ecc_step_ds;
 565        int badblockpos;
 566        int badblockbits;
 567
 568        int onfi_version;
 569        struct nand_onfi_params onfi_params;
 570
 571        flstate_t state;
 572
 573        uint8_t *oob_poi;
 574        struct nand_hw_control *controller;
 575        struct nand_ecclayout *ecclayout;
 576
 577        struct nand_ecc_ctrl ecc;
 578        struct nand_buffers *buffers;
 579        struct nand_hw_control hwcontrol;
 580
 581        uint8_t *bbt;
 582        struct nand_bbt_descr *bbt_td;
 583        struct nand_bbt_descr *bbt_md;
 584
 585        struct nand_bbt_descr *badblock_pattern;
 586
 587        void *priv;
 588};
 589
 590/*
 591 * NAND Flash Manufacturer ID Codes
 592 */
 593#define NAND_MFR_TOSHIBA        0x98
 594#define NAND_MFR_SAMSUNG        0xec
 595#define NAND_MFR_FUJITSU        0x04
 596#define NAND_MFR_NATIONAL       0x8f
 597#define NAND_MFR_RENESAS        0x07
 598#define NAND_MFR_STMICRO        0x20
 599#define NAND_MFR_HYNIX          0xad
 600#define NAND_MFR_MICRON         0x2c
 601#define NAND_MFR_AMD            0x01
 602#define NAND_MFR_MACRONIX       0xc2
 603#define NAND_MFR_EON            0x92
 604
 605/* The maximum expected count of bytes in the NAND ID sequence */
 606#define NAND_MAX_ID_LEN 8
 607
 608/*
 609 * A helper for defining older NAND chips where the second ID byte fully
 610 * defined the chip, including the geometry (chip size, eraseblock size, page
 611 * size). All these chips have 512 bytes NAND page size.
 612 */
 613#define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts)          \
 614        { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
 615          .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
 616
 617/*
 618 * A helper for defining newer chips which report their page size and
 619 * eraseblock size via the extended ID bytes.
 620 *
 621 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
 622 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
 623 * device ID now only represented a particular total chip size (and voltage,
 624 * buswidth), and the page size, eraseblock size, and OOB size could vary while
 625 * using the same device ID.
 626 */
 627#define EXTENDED_ID_NAND(nm, devid, chipsz, opts)                      \
 628        { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
 629          .options = (opts) }
 630
 631#define NAND_ECC_INFO(_strength, _step) \
 632                        { .strength_ds = (_strength), .step_ds = (_step) }
 633#define NAND_ECC_STRENGTH(type)         ((type)->ecc.strength_ds)
 634#define NAND_ECC_STEP(type)             ((type)->ecc.step_ds)
 635
 636/**
 637 * struct nand_flash_dev - NAND Flash Device ID Structure
 638 * @name: a human-readable name of the NAND chip
 639 * @dev_id: the device ID (the second byte of the full chip ID array)
 640 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
 641 *          memory address as @id[0])
 642 * @dev_id: device ID part of the full chip ID array (refers the same memory
 643 *          address as @id[1])
 644 * @id: full device ID array
 645 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
 646 *            well as the eraseblock size) is determined from the extended NAND
 647 *            chip ID array)
 648 * @chipsize: total chip size in MiB
 649 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
 650 * @options: stores various chip bit options
 651 * @id_len: The valid length of the @id.
 652 * @oobsize: OOB size
 653 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
 654 *                   @ecc_strength_ds in nand_chip{}.
 655 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
 656 *               @ecc_step_ds in nand_chip{}, also from the datasheet.
 657 *               For example, the "4bit ECC for each 512Byte" can be set with
 658 *               NAND_ECC_INFO(4, 512).
 659 */
 660struct nand_flash_dev {
 661        char *name;
 662        union {
 663                struct {
 664                        uint8_t mfr_id;
 665                        uint8_t dev_id;
 666                };
 667                uint8_t id[NAND_MAX_ID_LEN];
 668        };
 669        unsigned int pagesize;
 670        unsigned int chipsize;
 671        unsigned int erasesize;
 672        unsigned int options;
 673        uint16_t id_len;
 674        uint16_t oobsize;
 675        struct {
 676                uint16_t strength_ds;
 677                uint16_t step_ds;
 678        } ecc;
 679};
 680
 681/**
 682 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
 683 * @name:       Manufacturer name
 684 * @id:         manufacturer ID code of device.
 685*/
 686struct nand_manufacturers {
 687        int id;
 688        char *name;
 689};
 690
 691extern struct nand_flash_dev nand_flash_ids[];
 692extern struct nand_manufacturers nand_manuf_ids[];
 693
 694extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
 695extern int nand_default_bbt(struct mtd_info *mtd);
 696extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
 697extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
 698extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 699                           int allowbbt);
 700extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
 701                        size_t *retlen, uint8_t *buf);
 702
 703/**
 704 * struct platform_nand_chip - chip level device structure
 705 * @nr_chips:           max. number of chips to scan for
 706 * @chip_offset:        chip number offset
 707 * @nr_partitions:      number of partitions pointed to by partitions (or zero)
 708 * @partitions:         mtd partition list
 709 * @chip_delay:         R/B delay value in us
 710 * @options:            Option flags, e.g. 16bit buswidth
 711 * @bbt_options:        BBT option flags, e.g. NAND_BBT_USE_FLASH
 712 * @ecclayout:          ECC layout info structure
 713 * @part_probe_types:   NULL-terminated array of probe types
 714 */
 715struct platform_nand_chip {
 716        int nr_chips;
 717        int chip_offset;
 718        int nr_partitions;
 719        struct mtd_partition *partitions;
 720        struct nand_ecclayout *ecclayout;
 721        int chip_delay;
 722        unsigned int options;
 723        unsigned int bbt_options;
 724        const char **part_probe_types;
 725};
 726
 727/* Keep gcc happy */
 728struct platform_device;
 729
 730/**
 731 * struct platform_nand_ctrl - controller level device structure
 732 * @probe:              platform specific function to probe/setup hardware
 733 * @remove:             platform specific function to remove/teardown hardware
 734 * @hwcontrol:          platform specific hardware control structure
 735 * @dev_ready:          platform specific function to read ready/busy pin
 736 * @select_chip:        platform specific chip select function
 737 * @cmd_ctrl:           platform specific function for controlling
 738 *                      ALE/CLE/nCE. Also used to write command and address
 739 * @write_buf:          platform specific function for write buffer
 740 * @read_buf:           platform specific function for read buffer
 741 * @read_byte:          platform specific function to read one byte from chip
 742 * @priv:               private data to transport driver specific settings
 743 *
 744 * All fields are optional and depend on the hardware driver requirements
 745 */
 746struct platform_nand_ctrl {
 747        int (*probe)(struct platform_device *pdev);
 748        void (*remove)(struct platform_device *pdev);
 749        void (*hwcontrol)(struct mtd_info *mtd, int cmd);
 750        int (*dev_ready)(struct mtd_info *mtd);
 751        void (*select_chip)(struct mtd_info *mtd, int chip);
 752        void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
 753        void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 754        void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
 755        unsigned char (*read_byte)(struct mtd_info *mtd);
 756        void *priv;
 757};
 758
 759/**
 760 * struct platform_nand_data - container structure for platform-specific data
 761 * @chip:               chip level chip structure
 762 * @ctrl:               controller level device structure
 763 */
 764struct platform_nand_data {
 765        struct platform_nand_chip chip;
 766        struct platform_nand_ctrl ctrl;
 767};
 768
 769/* Some helpers to access the data structures */
 770static inline
 771struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
 772{
 773        struct nand_chip *chip = mtd->priv;
 774
 775        return chip->priv;
 776}
 777
 778/* return the supported features. */
 779static inline int onfi_feature(struct nand_chip *chip)
 780{
 781        return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
 782}
 783
 784/* return the supported asynchronous timing mode. */
 785static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
 786{
 787        if (!chip->onfi_version)
 788                return ONFI_TIMING_MODE_UNKNOWN;
 789        return le16_to_cpu(chip->onfi_params.async_timing_mode);
 790}
 791
 792/* return the supported synchronous timing mode. */
 793static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
 794{
 795        if (!chip->onfi_version)
 796                return ONFI_TIMING_MODE_UNKNOWN;
 797        return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
 798}
 799
 800#endif /* __LINUX_MTD_NAND_H */
 801